LM96194 TruTherm™ Hardware Monitor with PI Fan Control for Workstation Management 1.0 General Description The LM96194 hardware monitor has a two wire digital interface compatible with SMBus 2.0. Using a ΣΔ ADC, the LM96194 measures the temperature of four remote diode connected transistors as well as its own die and 9 power supply voltages. The LM96194 has new TruTherm technology that supports precision thermal diode measurements of processors on sub-micron processes. To set fan speed, the LM96194 has two PWM outputs that are each controlled by up to six temperature zones. The fancontrol algorithm can be based on a lookup table, PI (proportional/integral) control loop, or a combination of both. The LM96194 includes digital filters that can be invoked to smooth temperature readings for better control of fan speed such that acoustical noise is minimized. The LM96194 has four tachometer inputs to measure fan speed. Limit and status registers for all measured values are included. The LM96194 includes most of the features of the LM94, dual CPU motherboard server management ASIC, such as measurement and control support for dynamic Vccp monitoring for VRD10/11 and PROCHOT but is targeted for single processor systems. 2.0 Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 2 PWM fan speed control outputs 4 fan tachometer inputs Processor thermal throttling (PROCHOT) monitoring Dynamic VID monitoring (6/7 VIDs per processor) supports VRD10.2/11 8 general purpose I/Os: — 4 can be configured as fan tachometer inputs — 2 can be configured to connect to processor THERMTRIP — 2 are standard GPIOs that could be used to monitor IERR signal A general purpose inputs that can be used to monitor the 7th VID signal for VRD11 Limit register comparisons of all monitored values 2-wire serial digital interface, SMBus 2.0 compliant Supports byte/block read and write Selectable slave address (tri-level pin selects 1 of 3 possible addresses) ALERT output supports interrupt or comparator modes LLP-48 package XOR-tree test mode 3.0 Key Specifications ΣΔ ADC architecture Monitors 9 power supplies Monitors 4 remote thermal diodes and 2 LM60 New TruTherm technology support for precision thermal diode measurements Internal ambient temperature sensing Programmable autonomous fan control based on temperature readings with fan boost support Fan boost support on tachometer limit error event Fan control based on 13-step lookup table or PI Control Loop or combination of both PI fan control loop supports Tcontrol Temperature reading digital filters 0.5°C digital temperature sensor resolution 0.0625°C filtered temperature resolution for fan control ■ ■ ■ ■ ■ Voltage Measurement Accuracy Temperature Resolution Temperature Sensor Accuracy Temperature Range: LM96194 Operational Remote Temp Accuracy ■ Power Supply Voltage ■ Power Supply Current ±2% FS (max) 9-bits, 0.5°C ±2.5 °C (max) -40°C to +85°C -40°C to +125°C +3.0V to +3.6V 1.6 mA 4.0 Applications ■ Servers ■ Workstations ■ Processor based equipment TruTherm™ is a trademark of National Semiconductor Corporation. © 2007 National Semiconductor Corporation 201944 www.national.com LM96194 TruTherm™ Hardware Monitor with PI Fan Control for Workstation Management March 2007 LM96194 5.0 Ordering Information Order Number NS Package Number Transport media LM96194CISQ SQA48A 250 units in rail LM96194CISQX SQA48A 2500 units in tapeand-reel 6.0 Block Diagram The block diagram of LM96194 hardware is illustrated below. The hardware implementation is a single chip ASIC solution. 20194401 www.national.com 2 LM96194 7.0 Application The system diagram show in Figure 1 is a single processor workstation example. 20194405 FIGURE 1. Workstation Management 3 www.national.com LM96194 8.0 Connection Diagram 56 Pin TSSOP 20194402 NS Package NSQ48A Top View NS Order Numbers: LM96194CISQ (250 units per rail), or LM96194CISQX (2500 units per tape-and-reel) www.national.com 4 LM96194 9.0 Pin Descriptions Symbol Pin # Type Function PROCHOT 1 Digital I/O (OpenDrain) Connected to CPU1 PROCHOT (processor hot) signal through a bidirectional level shifter. Supports TTL input logic levels and AGTL compatible input logic levels. GND 2 Ground All grounds need to be tied together at the chip then taken to a low noise system ground. A voltage difference between grounds may cause erroneous results. GND 3 Ground All grounds need to be tied together at the chip then taken to a low noise system ground. A voltage difference between grounds may cause erroneous results. GND 4 Ground All grounds need to be tied together at the chip then taken to a low noise system ground. A voltage difference between grounds may cause erroneous results. GND 5 Ground All grounds need to be tied together at the chip then taken to a low noise system ground. A voltage difference between grounds may cause erroneous results. GND 6 Ground All grounds need to be tied together at the chip then taken to a low noise system ground. A voltage difference between grounds may cause erroneous results. GPIO_0/TACH1 7 Digital I/O (OpenDrain) Can be configured as fan tach input or a general purpose open-drain digital I/O. GPIO_1/TACH2 8 Digital I/O (OpenDrain) Can be configured as fan tach input or a general purpose open-drain digital I/O. GPIO_2/TACH3 9 Digital I/O (OpenDrain) Can be configured as fan tach input or a general purpose open-drain digital I/O. GPIO_3/TACH4 10 Digital I/O (OpenDrain) Can be configured as fan tach input or a general purpose open-drain digital I/O.. GPIO_4 / THERMTRIP 11 Digital I/O (OpenDrain) A general purpose open-drain digital I/O. Can be configured to monitor a CPU's THERMTRIP signal to mask other errors. Supports TTL input logic levels and AGTL compatible input logic levels. GPIO_5 12 Digital I/O (OpenDrain) A general purpose open-drain digital I/O. Supports TTL input logic levels and AGTL compatible input logic levels. GPIO_6 13 Digital I/O (OpenDrain) Can be used to detect the state of CPU's IERR or a general purpose opendrain digital I/O. Supports TTL input logic levels and AGTL compatible input logic levels. GPIO_7 14 Digital I/O (OpenDrain) A general purpose open-drain digital I/O. Supports TTL input logic levels and AGTL compatible input logic levels. VRD1_HOT 15 Digital Input CPU1 voltage regulator HOT. Supports TTL input logic levels and AGTL compatible input logic levels. GND 16 Ground Input All grounds need to be tied together at the chip then taken to a low noise system ground. A voltage difference between grounds may cause erroneous results. VID6/GPI9 17 Digital Input CPU VID6 input. Could also be used as a general purpose input to trigger an error event. Supports TTL input logic levels and AGTL compatible input logic levels. SMBDAT 18 Digital I/O (OpenDrain) Bidirectional System Management Bus Data. Output configured as 5V tolerant open-drain. SMBus 2.0 compliant. SMBCLK 19 Digital Input System Management Bus Clock. Driven by an open-drain output, and is 5V tolerant. SMBus 2.0 Compliant. ALERT/XtestOut 20 Digital Output (OpenDrain) Open-drain ALERT output used in an interrupt driven system to signal that an error event has occurred. Masked error events do not activate the ALERT output. When in XOR tree test mode, functions as XOR Tree output. 5 www.national.com LM96194 Symbol Pin # Type Function RESET 21 Digital I/O (OpenDrain) Open-drain reset output when power is first applied to the LM96194. Used as a reset for devices powered by 3.3V stand-by. After reset, this pin becomes a reset input. See Section (TBD) for more information. If this pin is not used, connection to an external resistive pull-up is required to prevent LM96194 malfunction. AGND 22 GROUND Input Analog Ground. All grounds need to be tied together at the chip then taken to a low noise system ground. A voltage difference between grounds may cause erroneous results. REMOTE1− 23 Remote Thermal Diode_1- Input (CPU THERMDC) This is the negative input (current sink) from both of the CPU thermal diodes. Connected to THERMDC pin of Pentium processor or the emitter of a diode connected MMBT3904 NPN transistor. Serves as the negative input into the A/D for thermal diode voltage measurements. A 100 pF capacitor is optional and can be connected between REMOTE1− and REMOTE1+. REMOTE1a+ 24 Remote Thermal Diode_1a+ I/O (CPU THERMDA1) This is a positive connection to the first CPU thermal diode. Serves as the positive input into the A/D for thermal diode voltage measurements. It also serves as a current source output that forward biases the thermal diode. Connected to THERMDA pin of Pentium processor or the base of a diode connected MMBT3904 NPN transistor. A 100 pF capacitor is optional and can be connected between REMOTE1− and each REMOTE1+. REMOTE2− 25 Remote Thermal Diode_2 - Input This is the negative input (current sink) from both of the CPU2 thermal diodes. Connected to THERMDC pins of Pentium processor or the emitter of a diode connected MMBT3904 NPN transistor. Serves as the negative input into the A/D for thermal diode voltage measurements. A 100 pF capacitor is optional and can be connected between REMOTE2− and each REMOTE2+. REMOTE2a+ 26 Remote Thermal Diode_2a + I/O This is a positive connection to the third thermal diode. Serves as the positive input into the A/D for thermal diode voltage measurements. It also serves as a current source output that forward biases the thermal diode. Connected to THERMDA pin of Pentium processor or the base of a diode connected MMBT3904 NPN transistor. A 100 pF capacitor is optional and can be connected between REMOTE2− and REMOTE2+. AD_IN1/REMOTE1b+ 27 Analog Input (+12V1 or Analog Input for +12V Rail 1 monitoring, for CPU1 voltage regulator. CPU1 THERMDA2) External attenuation resistors required such that 12V is attenuated to 0.927V for nominal ¾ scale reading. This pin may also serve as the second positive thermal diode input for the CPU. AD_IN2/REMOTE2b+ 28 Analog Input or Remote Thermal Diode_2b + I/O Analog Input for +12V Rail 2 monitoring. External attenuation resistors required such that 12V is attenuated to 0.927V for nominal ¾ scale reading. This pin may also serve as the fourth positive thermal diode input. AD_IN3 29 Analog Input (+12V3) Analog Input for +12V Rail 3, for Memory/3GIO slots. External attenuation resistors required such that 12V is attenuated to 0.927V for nominal ¾ scale reading. AD_IN4 (Vccp) 30 Analog Input (CPU1_Vccp) Analog input for +Vccp (processor voltage) monitoring. AD_IN5 31 Analog Input (+3.3V) Analog input for +3.3V monitoring, nominal ¾ scale reading GND 32 Ground All grounds need to be tied together at the chip then taken to a low noise system ground. A voltage difference between grounds may cause erroneous results. GND 33 Ground All grounds need to be tied together at the chip then taken to a low noise system ground. A voltage difference between grounds may cause erroneous results. GND 34 Ground All grounds need to be tied together at the chip then taken to a low noise system ground. A voltage difference between grounds may cause erroneous results. www.national.com 6 Pin # Type Function AD_IN6 35 Analog Input (Mem_Vtt) Analog input for +0.984V monitoring, nominal ¾ scale reading. AD_IN7 36 Analog Input (Gbit_Core) Analog input for +0.984V S/B monitoring, nominal ¾ scale reading. AD_IN8 37 Analog Input (-12V) Analog input for -12V monitoring. External resistors required to scale to positive level. Full scale reading at 1.236V, , nominal ¾ scale reading. This pin may also be used to monitor an analog temperature sensor such as the LM60, since readings from this input can be routed to the fan control logic. Address Select 38 3 level analog input This input selects the lower two bits of the LM96194 SMBus slave address. 3.3V SB (AD_IN8) 39 POWER (VDD) +3.3V standby power VDD power input for LM96194. Generally this is connected to +3.3V standby power. The LM96194 can be powered by +3.3V if monitoring in low power states is not required, but power should be applied to this input before any other pins. This pin also serves as the analog input to monitor the 3.3V stand-by (SB) voltage. It is necessary to bypass this pin with a 0.1 µF in parallel with 100 pF. A bulk capacitance of 10 µF should be in the near vicinity. The 100 pF should be closest to the power pin. GND 40 Ground Digital Ground. All grounds need to be tied together at the chip then taken to a low noise system ground. A voltage difference between grounds may cause erroneous results. PWM1 41 Digital Output (OpenDrain) Fan control output 1. PWM2 42 Digital Output (OpenDrain) Fan control output 2 VID0/VID7 43 Digital Input Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. VID1 44 Digital Input Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. VID2 45 Digital Input Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. VID3 46 Digital Input Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. VID4 47 Digital Input Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. VID5 48 Digital Input Voltage Identification signal from the processor. Supports TTL input logic levels and AGTL compatible input logic levels. The over-score indicates the signal is active low (“Not”). 10.0 Server Terminology A/D Analog to Digital Converter FSB Front side bus ACPI Advanced Configuration and Power Interface FW Firmware Gb Gigabit ALERT SMBus signal to bus master that an event occurred that has been flagged for attention. GB Gigabyte Gbe Gigabit Ethernet ASF Alert Standard Format GPI General purpose input BMC Baseboard Management Controller GPIO General purpose I/O BW Bandwidth HW Hardware DIMM Dual in line memory module I2C Inter integrated circuit (bus) DP Dual-processor LAN Local area network ECC Error checking and correcting LSb Least Significant Bit FRU Field replaceable unit LSB Least Significant Byte 7 www.national.com LM96194 Symbol LM96194 LVDS Low-Voltage Differential Signaling P/S Power Supply LUT Look-Up Table PCI PCI Local Bus Mb Megabit PDB Power Distribution Board MB Megabyte POR Power On Reset MP Multi-processor PS Power Supply MSb Most Significant Bit MSB Most Significant Byte MTBF Mean time between failures SMBCLK and These signals comprise the SMBus SMBDAT interface (data and clock) See the SMBus Interface section for more information. MTTR Mean time to repair VRD NIC Network Interface Card (Ethernet Card) OS Operating system Voltage Regulator Down - regulates Vccp voltage for a CPU 11.0 Recommended Implementation 20194406 Recommended implementation without thermal diode connections www.national.com 8 LM96194 20194407 Note: 100 pF cap across each thermal diode is optional and should be placed close to the LM96194, if used. The maximum capacitance between thermal diode pins is 300 pF. Thermal diode recommended implementation 9 www.national.com LM96194 All of the analog inputs include internal scaling resistors, exept for AD_IN1, AD_IN2, AD_IN3 and AD_IN8. External scaling resistors are required for measuring ±12V. The inputs are converted to 8-bit digital values such that a nominal voltage appears at ¾ scale for positive voltages and ¼ scale for negative voltages. The analog inputs are intended to be connected to both baseboard resident VRDs and to standard voltage rails supplied by a SSI compliant power supply. The LM96194 has logic that ties a set of dynamically moving VID inputs to their associated Vccp analog input for real time window comparison fault determination. Voltage mapping for VRD10, VRD10 extended and VRD11are supported by the LM96194. When VRD10 mode is selected GPI8 and GPI9 can be used to detect external error flags whose state is reflected in the status registers. Error events are captured in two sets of mirrored status registers (BMC Error Status Registers and Host Status Registers) allowing two controllers access to the status information without any interference. The LM96194's ALERT output supports interrupt mode or comparator mode of operation. The comparator mode is only functional for thermal monitoring. The LM96194 provides a number of internal registers, which are detailed in the register section of this document. 12.0 Functional Description The LM96194 provides 9 channels of voltage monitoring, 4 remote thermal diode monitors, an internal/local ambient temperature sensor, a PROCHOT monitor, 4 fan tachometers, 8 GPIOs, THERMTRIP monitor for masking error events, 1 sets of 7 VID inputs, an ALERT output and all the associated limit registers on a single chip, and communicates to the rest of the baseboard over the System Management Bus (SMBus). The LM96194 also provides 2 PWM outputs and associated fan control logic for controlling the speed of system fans. There are two sets of fan control logic, a lookup table and a PI (proportional/integral) loop controller. The lookup table and PI controller are interactive, such that the fans run at the fastest required speed. Upon a temperature or fan tach error event, the PWM outputs may be programmed such that they automatically boost to 100% duty cycle. A timer is included that sets the minimum time that the fans are in the boost condition when activated by a fan tach error. The LM96194 incorporates National Semiconductor's TruTherm technology for precision “Remote Diode” readings of processors on 90nm process geometry or smaller. Readings from the external thermal diodes and the internal temperature sensor are made available as an 9-bit two'scomplement digital value with the LSb representing 0.5°C. Filtered temperature readings are available as a 12-bit two'scomplement digital value with the LSb representing 0.0625° C. 12.1 Please contact your local sales office for complete LM96194 applications information. 13.0 Registers 13.1 REGISTER WARNINGS In most cases, reserved registers and register bits return zero when read. This should not be relied upon, since reserved registers can be used for future expansion of the LM96194 functions. Some registers have “N/D” for their default value. This means that the power-up default of the register is not defined. In the case of value registers, care should be taken to ensure that software does not read a value register until the associated measurement function has acquired a measurement. This applies to temperatures, voltages, fan RPM, and PROCHOT monitoring. 13.2 REGISTER SUMMARY TABLE Register Key Term Loc k Register Name Description N/D Not Defined N/A Not Applicable R Read Only R/W Read or Write RWC Read or Write to Clear Address Description FACTORY REGISTERS x XOR Test 00h Used to set the XOR test tree mode SMBus Test 01h SMBus read/write test register Reserved 02h-04h “REMOTE DIODE” MODE SELECT x Transistor Mode Select 05h Selects Diode Mode (default) or Transistor Mode for “Remote Diode” measurements 06h Measured value of remote thermal diode temperature channel 1b VALUE REGISTER SECTION 1 Zone 1b (CPU Diode b) Temp www.national.com 10 Register Name Address Description Zone 2b (MMBT3904 Diode b) Temp 07h Measured value of remote thermal diode temperature channel 2b Zone 1b (CPU Diode b) Filtered Temp 08h Filtered value of remote thermal diode temperature channel 1b Zone 2b (MMBT3904 Diode b) Fitlered Temp 09h Filtered value of remote thermal diode temperature channel 2b PWM1 8-bit Duty Cycle Value 0Ah 8- bit value of the PWM1 duty cycle. PWM2 8-bit Duty Cycle Value 0Bh 8-bit value of the PWM2 duty cycle HIGH RESOLUTION PWM OVERIDE REGISTERS x PWM1 Duty Cycle Override (low byte) 0Ch Lower byte of the high resolution PWM1 duty cycle register x PWM1 Duty Cycle Override (high byte) 0Dh Upper byte of the high resolution PWM1 duty cycle register x PWM2 Duty Cycle Override (low byte) 0Eh Lower byte of the high resolution PWM2 duty cycle register x PWM2 Duty Cycle Override (high byte) 0Fh Upper byte of the high resolution PWM2 duty cycle register EXTENDED RESOLUTION TEMPERATURE VALUE REGISTERS Z1a_LSB 10h Zone 1a (CPU) extended resolution unfiltered temperature value register, least-significant byte Z1a_MSB 11h Zone 1a (CPU) extended resolution unfiltered temperature value register, most-significant byte Z1b_LSB 12h Zone 1b (CPU) extended resolution unfiltered temperature value register, least-significant-byte Z1b_MSB 13h Zone 1b (CPU) extended resolution unfiltered temperature value register, most-significant byte Z2a_LSB 14h Zone 2a (MMBT2904) extended resolution unfiltered temperature value register, least-significant-byte Z2a_MSB 15h Zone 2a (MMBT3904) extended resolution unfiltered temperature value register, most-significant byte Z2b_LSB 16h Zone 2b (MMBT3904) extended resolution unfiltered temperature value register, least-significant-byte Z2b_MSB 17h Zone 2b (MMBT3904) extended resolution unfiltered temperature value register, most-significant byte Z1a_F_LSB 18h Zone 1a (CPU) extended resolution filtered temperature value register, least-significant byte Z1a_F_MSB 19h Zone 1a (CPU) extended resolution filtered temperature value register, most-significant byte Z1b_F_LSB 1Ah Zone 1b (CPU) extended resolution filtered temperature value register, least-significant-byte Z1b_F_MSB 1Bh Zone 1b (CPU) extended resolution filtered temperature value register, most-significant byte Z2a_F_LSB 1Ch Zone 2a (MMBT3904) extended resolution filtered temperature value register, least-significant-byte Z2a_F_MSB 1Dh Zone 2a (MMBT3904) extended resolution filtered temperature value register, most-significant byte Z2b_F_LSB 1Eh Zone 2b (MMBT3904) extended resolution filtered temperature value register, least-significant-byte Z2b_F_MSB 1Fh Zone 2b (MMBT3904) extended resolution filtered temperature value register, most-significant byte Z3_LSB 20h Zone 3 (Internal) extended resolution temperature value register, leastsignificant byte Z3_MSB 21h Zone 3 (Internal) extended resolution temperature value register, leastsignificant byte Z4_LSB 22h Zone 4 (External Digital) extended resolution temperature value register, most-significant byte Z4_MSB 23h Zone 4 (External Digital) extended resolution temperature value register, least-significant byte 11 www.national.com LM96194 Loc k LM96194 Loc k Register Name Reserved Address Description 24h-30h PI LOOP AND FAN CONTROL SETUP REGISTERS x Temperature Source Select 31h Selects the temperature source for some temperature zones. x PWM Filter Settings 32h Sets the IIR filter coefficients for the PWM outputs for low resolution sources x PWM1 Filter Shutoff Threshold 33h PWM1 Filter Shutoff Threshold x PWM2 Filter Shutoff Threshold 34h PWM2 Filter Shutoff Threshold x PI/LUT Fan Control Bindings 35h PI/LUT fan control binding configuration x PI Controller Minimum PWM and Hysteresis 36h PI Controller Minimum PWM and Hysteresis settings x Zone 1 Tcontrol 37h Zone 1 (CPU) PI Controller Target Temperature (Tcontrol) x Zone 2 Tcontrol 38h Zone 2 (MMBT3904) PI Controller Target Temperature (Tcontrol) x Zone 1 Toff 39h Zone 1 (CPU) PI Controller Off Temperature (Toff) x Zone 2 Toff 3Ah Zone 2 (MMBT3904) PI Controller Off Temperature (Toff) x P Coefficient 3Bh PI controller proportional coefficient x I Coefficient 3Ch PI controller integral coefficient x PI Exponents 3Dh PI controller coefficient exponents Manufacturer ID 3Eh Contains manufacturer ID code Version/Stepping 3Fh Contains code for major and minor revisions B_Error Status 1 40h BMC error status register 1 B_Error Status 2 41h BMC error register 2 B_Error Status 3 42h BMC error register 3 B_Error Status 4 43h BMC error register 4 B_PROCHOT Error Status 44h BMC error register for PROCHOT Reserved 45h B_GPI Error Status 46h BMC error register for GPIs B_Fan Error Status 47h BMC error register for Fans H_Error Status 1 48h HOST error status register 1 H_Error Status 2 49h HOST error register 2 H_Error Status 3 4Ah HOST error register 3 H_Error Status 4 4Bh HOST error register 4 H_PROCHOT Error Status 4Ch HOST error register for PROCHOT Reserved 4Dh H_GPI Error Status 4Eh HOST error register for GPIs H_Fan Error Status 4Fh HOST error register for Fans Zone 1a (CPU) Temp 50h Measured value of remote thermal diode temperature channel 1a Zone 2a (MMBT3904) Temp 51h Measured value of remote thermal diode temperature channel 2a Zone 3 (Internal) Temp 52h Measured temperature from on-chip sensor Zone 4 (External Digital) Temp 53h Measured temperature from external temperature sensor Zone 1a (CPU) Filtered Temp 54h Filtered value of remote thermal diode temperature channel 1a Zone 2a (MMBT3904) Filtered Temp 55h Filtered value of remote thermal diode temperature channel 2a AD_IN1 Voltage 56h Measured value of AD_IN1 AD_IN2 Voltage 57h Measured value of AD_IN2 DEVICE IDENTIFICATION REGISTERS BMC ERROR STATUS REGISTERS HOST ERROR STATUS REGISTERS VALUE REGISTERS SECTION 2 www.national.com 12 Register Name Address LM96194 Loc k Description AD_IN3 Voltage 58h Reserved 59h-5Bh Measured value of AD_IN3 AD_IN4 Voltage 5Ch Reserved 5Dh AD_IN5 Voltage 5Eh Reserved 5Fh-61h AD_IN6 Voltage 62h Measured value of AD_IN6 AD_IN7 Voltage 63h Measured value of AD_IN7 AD_IN8 Voltage 64h Measured value of AD_IN8 AD_IN9 Voltage 65h Measured value of AD_IN9 (VDD 3.3V S/B) Reserved 66h Current PROCHOT 67h Measured PPROCHOT throttle percentage Average PROCHOT 68h Average PPROCHOT throttle percentage Reserved 69h-6Ah GPI State 6Bh Current GPIO state P1_VID 6Ch Current Processor VID value Reserved 6Dh FAN Tach 1 LSB 6Eh Measured FAN Tach 1 LSB FAN Tach 1 MSB 6Fh Measured FAN Tach 1 MSB FAN Tach 2 LSB 70h Measured FAN Tach 2 LSB FAN Tach 2 MSB 71h Measured FAN Tach 2 MSB FAN Tach 3 LSB 72h Measured FAN Tach 3 LSB FAN Tach 3 MSB 73h Measured FAN Tach 3 MSB FAN Tach 4 LSB 74h Measured FAN Tach 4 LSB FAN Tach 4 MSB 75h Measured FAN Tach 4 MSB Reserved 76h-77h Measured value of AD_IN4 Measured value of AD_IN5 TEMPERATURE LIMIT REGISTERS Zone 1 (CPU) Low Temp 78h Low limit for external thermal diode temperature channel 1 (D1) measurement Zone 1 (CP1) High Temp 79h High limit for external thermal diode temperature channel 1 (D1) measurement Zone 2 (MMBT3904) Low Temp 7Ah Low limit for external thermal diode temperature channel 2 (D2) measurement Zone 2 (MMBT3904) High Temp 7Bh High limit for external thermal diode temperature channel 2 (D2) measurement Zone 3 (Internal) Low Temp 7Ch Low limit for local temperature measurement Zone 3 (Internal) High Temp 7Dh High limit for local temperature measurement Zone 4 (External Digital) Low Temp 7Eh Low limit for external digital temperature sensor Zone 4 (External Digital) High Temp 7Fh High limit for external digital temperature sensor x Fan Boost Temp Zone 1 80h Zone 1 (CPU) fan boost temperature x Fan Boost Temp Zone 2 81h Zone 2 (MMBT3904) fan boost temperature 13 www.national.com LM96194 Loc k Register Name Address Description x Fan Boost Temp Zone 3 82h Zone 3 (Internal) fan boost temperature x Fan Boost Temp Zone 4 83h Zone 4 (External Digital) fan boost temperature Zone1 and Zone 2 Hysteresis 84h Zone 1 and Zone 2 hysteresis for limit comparisons Zone 3 and Zone 4 Hysteresis 85h Zone 3 and Zone 4 hysteresis for limit comparisons Reserved 86h-8Dh ZONE 1b and 2b TEMPERATURE READING ADJUSTMENT REGISTERS Zone 1b Temp Adjust 8Eh Allows all Zone 1b temperature measurements to be adjusted by a programmable offset. Zone 2b Temp Adjust 8Fh Allows all Zone 2b temperature measurements to be adjusted by a programmable offset. AD_IN1 Low Limit 90h Low limit for analog input 1 measurement AD_IN1 High Limit 91h High limit for analog input 1 measurement AD_IN2 Low Limit 92h Low limit for analog input 2 measurement AD_IN2 High Limit 93h High limit for analog input 2 measurement AD_IN3 Low Limit 94h Low limit for analog input 3 measurement AD_IN3 High Limit 95h High limit for analog input 3 measurement Reserved 96h-9Dh AD_IN4 Low Limit 9Ch Low limit for analog input 4 measurement (Processor Vccp) AD_IN4 High Limit 9Dh High limit for analog input 4 measurement (Processor Vccp) Reserved 9Eh-9Fh AD_IN5 Low Limit A0h Low limit for analog input 5 measurement AD_IN5 High Limit A1h High limit for analog input 5 measurement Reserved A2h-A7h AD_IN6 Low Limit A8h Low limit for analog input 6 measurement AD_IN6 High Limit A9h High limit for analog input 6 measurement AD_IN7 Low Limit AAh Low limit for analog input 7 measurement AD_IN7 High Limit ABh High limit for analog input 7 measurement AD_IN8 Low Limit ACh Low limit for analog input 8 measurement AD_IN8 High Limit ADh High limit for analog input 8 measurement AD_IN9 Low Limit AEh Low limit for analog input 9 measurement AD_IN9 High Limit AFh High limit for analog input 9 measurement PROCHOT User Limit B0h User settable limit for PROCHOT Reserved B1h Vccp Limit Offsets B2h Reserved B3h FAN Tach 1 Limit LSB B4h FAN Tach 1 Limit LSB FAN Tach 1 Limit MSB B5h FAN Tach 1 Limit MSB FAN Tach 2 Limit LSB B6h FAN Tach 2 Limit LSB FAN Tach 2 Limit MSB B7h FAN Tach 2 Limit MSB FAN Tach 3 Limit LSB B8h FAN Tach 3 Limit LSB FAN Tach 3 Limit MSB B9h FAN Tach 3 Limit MSB FAN Tach 4 Limit LSB BAh FAN Tach 4 Limit LSB FAN Tach 4 Limit MSB BBh FAN Tach 4 Limit MSB OTHER LIMIT REGISTERS www.national.com VID offset values for window comparator for CPU Vccp (AD_IN4) 14 Register Name Address LM96194 Loc k Description SETUP REGISTERS Special Function Control 1 BCh Controls the hysteresis for voltage limit comparisons. Also selects filtered or unfiltered temperature usage for temperature limit comparisons and fan control. Special Function Control 2 BDh Enables smart tach detection. Also selects 0.5°C or 1.0°C resolution for fan control. x GPI / VID Level Control BEh Control the input threshold levels for the VIDx, and GPIO_x inputs. x PWM Ramp Control BFh Controls the ramp rate of the PWM duty cycle when VRD_HOT is asserted, as well as the ramp rate when PROCHOT exceeds the user threshold. x Fan Boost Hysteresis (Zones 1/2) C0h Fan Boost Hysteresis for zones 1 and 2 x Fan Boost Hysteresis (Zones 3/4) C1h Fan Boost Hysteresis for zones 3 and 4 x Zones 1/2 Spike Smoothing Control C2h Configures Spike Smoothing for zones 1 and 2 x LUT 1/2 MinPWM and Hysteresis C3h Controls MinPWM and hysteresis setting for LUT 1 and 2 auto-fan control x LUT 3/4 MinPWM and Hysteresis C4h Controls MinPWM and hysteresis setting for LUT 3 and 4 auto-fan control GPO C5h Controls the output state of the GPIO pins PROCHOT Control C6h Controls assertion PROCHOT PROCHOT Time Interval C7h Configures the time window over which the PROCHOT inputs are measured x PWM1 Control 1 C8h Controls PWM control source bindings. x PWM1 Control 2 C9h Controls PWM override and output polarity x PWM1 Control 3 CAh Controls PWM spin-up duration and duty cycle x PWM1 Control 4 CBh Frequency control for PWM1. x PWM2 Control 1 CCh Controls PWM control source bindings. x PWM2 Control 2 CDh Controls PWM override and output polarity x PWM2 Control 3 CEh Controls PWM spin-up duration and duty cycle x PWM2 Control 4 CFh Frequency control for PWM2 x LUT 1 Base Temperature D0h Base temperature to which look-up table offset is applied for LUT 1 x LUT 2 Base Temperature D1h Base temperature to which look-up table offset is applied for LUT 2 x LUT 3 Base Temperature D2h Base temperature to which look-up table offset is applied for LUT 3 x LUT 4 Base Temperature D3h Base temperature to which look-up table offset is applied for LUT 4 x Step 2 Temp Offset D4h Step 2 LUT 1/2 and LUT 3/4 Offset Temperatures x Step 3 Temp Offset D5h Step 3 LUT 1/2 and LUT 3/4 Offset Temperatures x Step 4 Temp Offset D6h Step 4 LUT 1/2 and LUT 3/4 Offset Temperatures x Step 5 Temp Offset D7h Step 5 LUT 1/2 and LUT 3/4 Offset Temperatures x Step 6 Temp Offset D8h Step 6 LUT 1/2 and LUT 3/4 Offset Temperatures x Step 7 Temp Offset D9h Step 7 LUT 1/2 and LUT 3/4 Offset Temperatures x Step 8 Temp Offset DAh Step 8 LUT 1/2 and LUT 3/4 Offset Temperatures x Step 9 Temp Offset DBh Step 9 LUT 1/2 and LUT 3/4 Offset Temperatures x Step 10 Temp Offset DCh Step 10 LUT 1/2 and LUT 3/4 Offset Temperatures x Step 11 Temp Offset DDh Step 11 LUT 1/2 and LUT 3/4 Offset Temperatures x Step 12 Temp Offset DEh Step 12 LUT 1/2 and LUT 3/4 Offset Temperatures x Step 13 Temp Offset DFh Step 13 LUT 1/2 and LUT 3/4 Offset Temperatures 15 www.national.com LM96194 Loc k Register Name Address Description TACH to PWM Binding E0h Controls the tachometer input to PWM output binding x Tach Boost Control E1h Controls the fan boost function upon a tach error x LM96194 Status/Control E2h Gives Master error status, ASF reset control and Max PWM control x LM96194 Configuration E3h Configures various outputs and provides START bit SLEEP STATE CONTROL AND MASK REGISTERS Sleep State Control E4h Used to communicate the system sleep state to the LM96194 S1 GPI Mask E5h Sleep state S1 GPI error mask register S1 Fan Mask E6h Sleep state S1 fan tach error mask register S3 GPI Mask E7h Sleep state S3 GPI error mask register S3 Fan Mask E8h Sleep state S3 fan tach error mask register S3 Temperature/Voltage Mask E9h Sleep state S3 temperature or voltage error mask register S4/5 GPI Mask EAh Sleep state S4/5 GPI error mask register S4/5 Temperature/Voltage Mask EBh Sleep state S4/5 temperature or voltage error mask register GPI Error Mask ECh Error mask register for GPI faults Miscellaneous Error Mask EDh Error mask register for VRD_HOT, GPI, and dynamic Vccp limit checking. OTHER MASK REGISTERS ZONE 1a AND 2a TEMPERATURE READING ADJUSTMENT REGISTERS Zone 1a Temp Adjust EEh Allows all Zone 1a temperature measurements to be adjusted by a programmable offset Zone 2a Temp Adjust EFh Allows all Zone 2a temperature measurements to be adjusted by a programmable offset Block Write Command F0h SMBus Block Write Command Code Block Read Command F1h SMBus Block Write/Read Process call Fixed Block 0 F2h Fixed block code address 40h, size 8 bytes Fixed Block 1 F3h Fixed block code address 48h, size 8 bytes Fixed Block 2 F4h Fixed block code address 50h, size 6 bytes Fixed Block 3 F5h Fixed block code address 56h, size 16 bytes Fixed Block 4 F6h Fixed block code address 67h, size 4 bytes Fixed Block 5 F7h Fixed block code address 6Eh, size 8 bytes Fixed Block 6 F8h Fixed block code address 78h, size 12 bytes Fixed Block 7 F9h Fixed block code address 90h, size 32 bytes Fixed Block 8 FAh Fixed block code address B4h, size 8 bytes Fixed Block 9 FBh Fixed block code address C8h, size 8 bytes Fixed Block 10 FCh Fixed block code address D0h, size 16 bytes Fixed Block 11 FDh Fixed block code address E5h, size 9 bytes Reserved FEh-FFh Reserved for future commands BLOCK COMMANDS Please contact your local sales office for complete LM96194 applications information. www.national.com 16 (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Positive Supply Voltage (VDD) Voltage on Any Digital Input or Output Pin Voltage on +5V Input Voltage at Positive Remote Diode Inputs, AD_IN1, AD_IN2, AD_IN3, and AD_IN15 Inputs Voltage at Other Analog Voltage Inputs Input Current at Thermal Diode Negative Inputs Input Current at any pin (Note 3) Package Input Current (Note 3) Maximum Junction Temperature (Note 9) (TJMAX) 6.0V −0.3V to 6.0V (Except Analog Inputs) −0.3V to +6.667V 15.0 Operating Ratings (Notes 1, 2) TMIN ≤ TA ≤ TMAX -40°C ≤ TA ≤ +85°C 3.3V +3.0V to +3.6V −0.05V to +5.5V −0.05V to (VDD + 0.05V) 79°C/W Operating Temperature Range −0.3V to (VDD + 0.05V) Nominal Supply Voltage Supply Voltage Range (VDD) VID0-VID5 Digital Input Voltage Range −0.3V to +6.0V ±1 mA ±10mA ±100 mA Package Thermal Resistance (Note 6) 150 °C DC Electrical Characteristics The following limits apply for +3.0 VDC to +3.6 VDC, unless otherwise noted. Bold face limits apply for TA = TJ over TMIN to TMAX of the operating range; all other limits TA = TJ = 25°C unless otherwise noted. TA is the ambient temperature of the LM96194; TJ is the junction temperature of the LM96194; TD is the junction temperature of the thermal diode. Symbol Parameter Conditions Typical (Note 9) Limits (Note 10) Units (Limits) 2 2.75 mA (max) POWER SUPPLY CHARACTERISTICS Power Supply Current Converting, Interface and Fans Inactive, Peak Current Converting, Interface and Fans Inactive, Average Current Power-On Reset Threshold Voltage 1.6 2 mA 1.6 V (min) 2.7 V (max) ±4 °C (max) TEMPERATURE-TO-DIGITAL CONVERTER CHARACTERISTICS Local Temperature Accuracy Over Full Range -40°C ≤ TA < 0°C ±2 0°C ≤ TA ≤ 85°C ±2 ±3 °C (max) TA = +55°C ±1 ±2.5 °C (max) Local Temperature Resolution 1 Remote Thermal Diode Temperature Accuracy(Note 0°C ≤ TA ≤ 85°C 8) and 0°C ≤ TD ≤ 100°C 0°C ≤ TA ≤ 85°C and TD =70°C -40°C ≤ TA < 0°C Remote Thermal Diode Temperature Accuracy Extended to Down to -40 for MMBT3904 Only and -40°C ≤ TD < 0°C Remote Thermal Diode Temperature Accuracy; 0°C ≤ TA ≤ 85°C targeted for a typical Pentium processor on 90nm or and 25°C ≤ T ≤ 70°C D 65nm process (Note 8) Remote Temperature Resolution °C ±3 °C (max) ±2.5 °C (max) ±4 °C (max) ±1 °C 1 Thermal Diode Source Current 17 High Level 172 Low Level 10.75 °C 230 µA (max) µA www.national.com LM96194 ESD Susceptibility (Note 4) Human Body Model 3 kV Machine Model 300V Charged Device Model 750V Storage Temperature −65°C to +150°C Soldering process must comply with National's reflow temperature profile specifications. Refer to www.national.com/packaging/. (Note 5) 14.0 Absolute Maximum Ratings LM96194 Symbol Parameter Conditions Thermal Diode Current Ratio TC Typical (Note 9) Limits (Note 10) Units (Limits) 100 ms (max) ±2 % of FS (max) 16 Total Monitoring Cycle Time ANALOG-TO-DIGITAL VOLTAGE MEASUREMENT CONVERTER CHARACTERISTICS TUE Total Unadjusted Error (Note 12) DNL Differential Non-Linearity PSS Power Supply (VDD) Sensitivity TC Total Monitoring Cycle Time Input Resistance for Inputs with Dividers ±1 LSB ±1 %/V (of FS) 200 AD_IN1- AD_IN3 and AD_IN8 Analog Input Leakage Current (No Dividers are present on these inputs.) (Note 13) 100 ms (max) 140 kΩ (min) 60 nA (max) DIGITAL OUTPUTS: PWM1, PWM2 IOL Maximum Current Sink VOL Output Low Voltage 8 mA (min) IOUT = 8.0 mA 0.4 V (max) Output Low Voltage (Note excessive current flow causes self-heating and degrades the internal temperature accuracy.) IOUT = 4.0 mA 0.4 V (min) IOUT = 6 mA 0.55 V (min) IOH High Level Output Leakage Current VOUT = VDD 10 µA (max) IOTMAX Maximum Total Sink Current for all Digital Outputs Combined 32 mA (max) CO Digital Output Capacitance DIGITAL OUTPUTS: ALL VOL 0.1 20 pF DIGITAL INPUTS: ALL VIH Input High Voltage Except Address Select 2.1 V (min) VIL Input Low Voltage Except Address Select 0.8 V (max) VIH Input High Voltage for Address Select 90% VDD V (min) VIM Input Mid Voltage for Address Select 43% VDD 57% VDD V (min) V (max) VIL Input Low Voltage for Address Select 10% VDD V (max) VHYST DC Hysteresis IIH Input High Current VIN = VDD −10 µA (min) IIL Input Low Current VIN = 0V 10 µA (max) CIN Digital Input Capacitance 0.3 V 20 pF DIGITAL INPUTS: P1_VIDx, P2_VIDx, GPI_9, GPI_8, GPIO_7, GPIO_6, GPIO_5, GPIO_4 (When respective bit set in Register BEh GPI/VID Level Control) VIH Alternate Input High Voltage (AGTL+ Compatible) 0.8 V (min) VIL Alternate Input Low Voltage (AGTL+ Compatible) 0.4 V (max) www.national.com 18 The following limits apply for +3.0 VDC to +3.6 VDC, unless otherwise noted. Bold face limits apply for TA = TJ = TMIN to TMAX of the operating range; all other limits TA = TJ = 25°C unless otherwise noted. Symbol Parameter Conditions Typical (Note 9) Limits (Note 10) Units (Limits) FAN RPM-TO-DIGITAL CHARACTERISTICS Counter Resolution 14 bits Number of fan tach pulses count is based on 2 pulses Counter Frequency 22.5 Accuracy kHz ±6 % (max) ±6 % (max) ±6 % (max) 250 330 ms (min) ms (max) PWM OUTPUT CHARACTERISTICS Frequency Tolerances Duty-Cycle Tolerance ±2 RESET INPUT/OUTPUT CHARACTERISTICS Output Pulse Width Upon Power Up Minimum Input Pulse Width Reset Output Fall Time 1.6V to 0.4V Logic Levels 10 µs (min) 1 µs (max) 10 100 kHz (min) kHz (max) SMBus TIMING CHARACTERISTICS fSMBCLK SMBCLK (Clock) Clock Frequency tBUF SMBus Free Time between Stop and Start Conditions 4.7 µs (min) tHD;STA Hold time after (Repeated) Start Condition. After this period, the first clock is generated. 4.0 µs (min) tSU;STA Repeated Start Condition Setup Time 4.7 µs (min) tSU;STO Stop Condition Setup Time 4.0 µs (min) tSU;DAT Data Input Setup Time to SMBCLK High 250 ns (min) tHD;DAT Data Output Hold Time after SMBCLK Low 300 1075 ns (min) ns (max) tLOW SMBCLK Low Period 4.7 50 µs (min) µs (max) tHIGH SMBCLK High Period 4.0 50 µs (min) µs (max) tR Rise Time 1 µs (max) tF Fall Time 300 ns (max) tTIMEOUT Timeout SMBDAT or SMBCLK low time required to reset the Serial Bus Interface to the Idle State 25 35 ms ms (min) ms (max) tPOR Time in which a device must be operational after power-on reset 500 ms (max) CL Capacitance Load on SMBCLK and SMBDAT 400 pF (max) 31 VDD > +2.8V 19 www.national.com LM96194 AC Electrical Characteristics LM96194 20194403 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND, unless otherwise noted. Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < (GND or AGND) or VIN > VDD, except for analog voltage inputs), the current at that pin should be limited to 10 mA. The 100 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to ten. Parasitic components and/or ESD protection circuitry are shown below for the LM96194’s pins. Care should be taken not to forward bias the parasitic diode, D1, present on pins D+ and D− as shown in circuits C and D. Doing so by more than 50 mV may corrupt temperature measurements. D1 and the ESD Clamp are connected between V+ (VDD, AD_IN16) and GND as shown in circuit B. SNP stands for snap-back device. Symbol Pin # Circuit All Input Circuits PROCHOT 1 A GND 2 A GND 3 A GND 4 A GND 5 A GND 6 A GPIO_0/TACH1 7 A GPIO_1/TACH2 8 A GPIO_2/TACH3 9 A GPIO_3/TACH4 10 A GPIO_4 /THERMTRIP 11 A GPIO_5 12 A GPIO_6 13 A GPIO_7 14 A VRD_HOT 15 A GND 16 A SCSI_TERM1 17 A SMBDAT 18 A SMBCLK 19 A ALERT/XtestOut 20 A RESET 21 A AGND 22 B (Internally shorted to GND pin.) REMOTE1– 23 C REMOTE1+ 24 D REMOTE2– 25 C REMOTE+ 26 D AD_IN1 27 D AD_IN2 28 D AD_IN3 29 D www.national.com Circuit A Circuit B Circuit C 20 Symbol Circuit 30 E AD_IN5 31 E GND 32 E GND 33 E GND 34 E AD_IN6 35 E AD_IN7 36 E AD_IN8 37 D ADDR_SEL 38 A AD_IN9/VDD (V+) 39 B GND 40 B (Internally shorted to AGND.) PWM1 41 A PWM2 42 A P1_VID0 43 A P1_VID1 44 A P1_VID2 45 A P1_VID3 46 A P1_VID4 47 A P1_VID5 48 A LM96194 Pin # AD_IN4 All Input Circuits Circuit D Circuit E Note 4: Human body model, 100 pF discharged through a 1.5 kΩ resistor. Machine model, 200 pF discharged directly into each pin. Charged device model (CDM) simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged. Note 5: Reflow temperature profiles are different for lead-free and non lead-free packages. Note 6: The maximum power dissipation must be de-rated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD MAX= (TJMAX − TA) / θJA. The θJAfor the LM96194 when mounted to 1 oz. copper foil PCB the θJA with different air flow is listed in the following table. Air Flow Junction to Ambient Thermal Resistance, θJA 0 m/s 28 °C/W 1.14 m/s (225 LFPM) 25 °C/W 2.54 m/s (500 LFPM) 22 °C/W Note 7: See the URL "http://www.national.com/packaging/" for other recommendations and methods of soldering surface mount devices. Note 8: At the time of first pubication of this specification (Jan 2006), this specification applies to either Pentium or Xeon Processors on 90nm or 65nm process when TruTherm is selected. When TruTherm is deselected this specification applies to an MMBT3904. This specification does include the error caused by the variability of the diode ideality and series resistance parameters. Note 9: Typical parameters are at TJ = TA = 25 °C and represent most likely parametric norm. Note 10: Limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 11: TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC. Note 12: Total Monitoring Cycle Time includes all temperature and voltage conversions. Note 13: Leakage current approximately doubles every 20 °C. Note 14: A total digital I/O current of 40 mA can cause 6 mV of offset in Vref. Note 15: Timing specifications are tested at the TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge. TRI-STATE output voltage is forced to 1.4V. 21 www.national.com LM96194 16.0 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Molded LLP Package, Order Number LM96194CISQ or LM96194CIAQX, NS Package Number SQA48A www.national.com 22 LM96194 Notes 23 www.national.com LM96194 TruTherm™ Hardware Monitor with PI Fan Control for Workstation Management Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS. 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