LM26484 Power Management Unit General Description The LM26484 is a multi-function, configurable Power Management Unit. This device integrates two highly efficient 2.0A Step-Down DC/DC converters, one LDO Controller, a POR (Power On Reset) circuit, and thermal overload protection circuitry. All regulator output voltages are externally adjustable. The LDO controller is a low-voltage NMOS voltage regulator. The LM26484 is offered in a 5 x 4 x 0.8 mm LLP-24 pin package. Key Specifications Applications STEP-DOWN DC/DC CONVERTER (BUCK) ■ 3.0–5.5V Input Range ■ Externally adjustable VOUT: — Buck1 : 0.8V–3.5V @ 2A — Buck2 : 0.8V–3.5V @ 2A ■ 180° Phase Shift between Bucks Clocks ■ 2 MHz PWM switching frequency ■ ±1% feedback voltage accuracy ■ Automatic soft start ■ Current overload protection ■ PWM/PFM efficiency modes available © 2009 National Semiconductor Corporation LINEAR REGULATOR (LDO) CONTROLLER ■ 3.0V–5.5V Input range ■ Externally adjustable VOUT ■ ±1.5% feedback voltage accuracy ■ Regulated to Low VIN - Low VOUT LI-LO (Low Input Low Output) NFET operation ■ Input to the LI-LO configuration, can be post regulated when supply is regulated by Buck2 ■ Up to 1000 mA output current by selection of external FET 300661 ■ ■ ■ ■ ■ ■ Digital Cores and I/Os (FPGAs, ASICs, DSPs) Automotive infotainment Set-top-box Cordless phone base station Networking router Printers www.national.com LM26484 Power Management Unit September 23, 2009 LM26484 Application Circuit 30066101 FIGURE 1. Application Circuit www.national.com 2 LM26484 Connection Diagram and Package Mark Information 30066102 24-Lead LLP Package (top view) Note: The physical placement of the package marking will vary from part to part. (*) UZXYTT format: ‘U’ – wafer fab code; ‘Z’ – assembly code; ’XY’ 2 digit date code; ‘TT” – die run code. See http://www.national.com/quality/marking_conventions.html for more information on marking information. Ordering Information Part Number Package Marking Ordering Spec Buck1 Buck2 LM26484SQE 26484SQ NOPB PWM PWM 250 units, tape-and-reel LM26484SQ 26484SQ NOPB PWM PWM 1000 units, tape-and-reel LM26484SQX 26484SQ NOPB PWM PWM 4500 units, tape-and-reel 3 Supplied As www.national.com LM26484 Pin Descriptions Pins Name I/O Type Description 1 VIN1 I PWR Power in DC source Buck1 PMOS 2 ENSW1 I D Enable for Buck1 switcher, a logic HIGH enables Buck1 3 FB1 I A Buck1 input feedback terminal 4 AVIN I PWR 5 FB2 I A Buck2 input feedback terminal 6 ENSW2 I D Enable for Buck2 switcher, a logic HIGH enables Buck2 7 VIN2 I PWR Power in DC source Buck2 PMOS 8 VIN2 I PWR Power in DC source Buck2 PMOS 9 SW2 O A Buck2 switcher output 10 SW2 O A Buck2 switcher output 11 PGND_SW2 G G Buck2 NMOS Power Ground 12 PGND_SW2 G G Buck2 NMOS Power Ground 13 ENLDO I D Enable for LDO, a logic HIGH enables LDO 14 LDOGATE O A LDO Controller output to NMOS power transistor Gate 15 LDOFB I A LDO Controller input to feedback terminal 16 AGND G G Analog GND 17 GND G G Ground 18 nPOR O D nPOR Active low Reset output. nPOR remains LOW while the input supply is below threshold, and goes HIGH after the threshold is reached and timed delay Analog power for internal circuits 19 AVDD I PWR 20 PGND_SW1 G G Buck1 NMOS Power Ground 21 PGND_SW1 G G Buck1 NMOS Power Ground 22 SW1 O A Buck1 switcher output 23 SW1 O A Buck1 switcher output 24 VIN1 I PWR Power in DC source Buck1 PMOS DAP DAP GND GND Connection isn't necessary for electrical performance, but it is recommended for better thermal dissipation. A: Analog Pin www.national.com D: Digital Pin Analog Power Pin G: Ground Pin 4 PWR: Power Pin Operating Ratings 2) VIN1, VIN2, AVDD, AVIN nPOR, ENSW1, ENSW2, ENLDO, LDO_GATE, SW1, SW2 FB1, FB2 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VIN1, VIN2, AVDD, AVIN −0.3V to +6V nPOR, ENSW1, FB1, ENSW2, FB2, ENLDO, LDO_FB −0.3 to VIN + 0.3V GND to GND SLUG ±0.3V Junction Temperature (TJ-MAX) 150°C Storage Temperature Range −65°C to +150°C Maximum Lead Temperature (Soldering) 260°C ESD Ratings Human Body Model (Note 4) Machine Model: VIN1,2; SW1,2 PGND1,2 All other pins 3.0V to 5.5V 0V to VIN + 0.3V 0v to VBuck1 and VBuck2 respectively 0v to VLDO 1.2W LDOFB Power Dissipation (PD-MAX) TA = 85°C, TMAX = 125°C Junction Temperature (TJ) Range (Note 3) Thermal Properties Junction-to-Ambient Thermal Resistance (θJA) 2 kV 150V 200V −40°C to +125°C (Note 5, Note 6) 33.1°C/W based on a 4-layer 1 oz. PCB Junction-to-Case Thermal Resistance (θJC) 4.3°C/W General Electrical Characteristics Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C. (Note 2, Note 7) Symbol Parameter Conditions Min Typ Max Units 3.0 3.3 5.5 V VIN Operational Voltage Range AVDD, AVIN TSD Thermal Shutdown (Note 3) 160 °C CIN Input Capacitor C9, Figure 1 10 µF Iq Quiescent Current “Off” VIN = 3.3V, ENSW1, ENSW2, ENLDO = 0 0.03 1 µA LDO Controller Unless otherwise noted, AVDD = AVIN 3.3V, PVIN = 1.8V. Typical values and limits appearing in normal type apply for TA = 25° C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C. (Note 2, Note 7) Min Typ Max Units VIN Symbol Operational Voltage Range Parameter AVIN LDO internal circuits Conditions 3.0 3.3 5.5 V VOUT NMOS configuration Externally configured 0.8 1.5 V VFB Feedback Voltage Accuracy 0.5 V −1.5 1.5 −2 2 % PSRR Power Supply Ripple Rejection F = 10 kHz, Load Current = IMAX −30 dB TON Turn On Time Start up from shut-down 500 µsec CFB Feedback Capacitor C11, Figure 1 12 pF Output Capacitor C10, (Note 1) Capacitance for stability: COUT −40°C ≤ TJ ≤ 125°C ESR (Equivalent Series Resistance) 5 10 22 0.5 µF Ω www.national.com LM26484 Absolute Maximum Ratings (Note 1, Note LM26484 Buck Converters SW1, SW2 Unless otherwise noted, AVDD=AVIN=VIN1=VIN2 = 3.3V, CIN = 10 µF, COUT = 22 µF, LOUT = 0.5 µH. Buck1 is configured to 1.8V. Buck2 is configured to 1.0V. Typical values and limits appearing in normal type apply for TA = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C. (Note 2, Note 7) Symbol Parameter VIN VIN Range VFB Feedback Voltage Accuracy Conditions AVDD=VIN1=VIN2 Min Typ Max Units 3.0 3.3 5.5 V +1.0 % 0.5 −1.0 −1.5 +1.5 DC Line Regulation 3.0 < VIN < 3.6 IO =1000 mA 0.174 %/V DC Load Regulation 100 mA < IO < IMAX 0.75 %/A 2.0 MHz ΔVOUT fOSC Oscillator Frequency IPEAK Peak Switching Current Limit 1.8 3.2 RDSON (P) Pin-Pin Resistance PFET 70 100 RDSON (N) Pin-Pin Resistance NFET 80 100 TON Turn On Time Start up from shut-down CIN Input Capacitor Capacitance for stability 10 CO Output Capacitor Capacitance for stability 10 A 500 mΩ mΩ µsec µF 22 µF I/O Electrical Characteristics Unless otherwise noted: AVDD=AVIN=VIN1=VIN2 = 3.3V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = -40 to +125°C (Note 2, Note 7) Symbol Parameter VIL Input Low Level, ENSW1, ENSW2, ENLDO VIH Input High Level, ENSW1, ENSW2, ENLDO IOH nPOR VOL nPOR TnPOR nPOR Delay Min Typ Max Units 0.4 V 0.01 2 µA 0.125 0.25 V 200 475 msec V 0.8*VIN 60 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pin. Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160°C (typ.) and disengages at TJ = 130°C (typ.) Note 4: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. (MILSTD - 883 3015.7) Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature, the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the package in the application (θJA), as given by the following equation: TA-MAX = TJMAX − (θJA × PD-MAX). Refer to dissipation rating table for PD-MAX values at different ambient temperatures. Note 6: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. More information is available in National Semiconductor Application Note AN1187. Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Note 8: This specification is guaranteed by design. www.national.com 6 Load Transient VOUT — 1.0V, IOUT = 200 mA-1A TA = 25°C unless otherwise noted. Load Transient VOUT — 1.0V, IOUT = 50 mA- 500 mA 30066108 30066139 Typical Performance Characteristics — Buck Startup of Buck1: VOUT = 1.8V; IOUT = 100 mA TA = 25°C unless otherwise noted. Startup of Buck1: VOUT = 1.8V; IOUT = 2A 30066140 30066141 Startup of Buck2: VOUT = 1.0V; IOUT = 100 mA Startup of Buck2: VOUT = 1.0V; IOUT = 2A 30066142 30066156 7 www.national.com LM26484 Typical Performance Characteristics — LDO LM26484 Line Transient: VIN = 3.0V - 3.6V; IOUT = 250 mA; VOUT = 1.8V Line Transient: VIN = 3.3V - 4.2V IOUT = 250 mA; VOUT = 1.0V 30066157 30066158 Buck1 Load Transient: VIN = 3.3V; VOUT = 1.8V; IOUT = 250 mA - 1.5A Buck1 Load Transient: VIN = 3.3V; VOUT = 1.8V; IOUT = 500 mA - 2A 30066159 30066160 Buck2 Load Transient: VIN = 3.3V; VOUT = 1.0V; IOUT = 250 mA - 1.5A Buck2 Load Transient: VIN = 3.3V; VOUT = 1.0V; IOUT = 500 mA - 2A 30066162 30066161 www.national.com 8 Efficiency of Buck2, VOUT = 1.0V, at Room Temp 30066137 30066138 Efficiency of Buck1, VOUT = 3.5V at Room Temp 30066115 Flexible Power Sequencing of Multiple Power Supplies Power-On Reset The LM26484 provides an active low reset output nPOR. Typical waveform is as shown in Figure 2 below: The two bucks and the LDO in the LM26484 can be individually controlled with ENSW1, ENSW2, and ENLDO, respectively. All the enable inputs need to be either grounded or tied to VIH. 30066103 FIGURE 2. Power-On Reset Waveform 9 www.national.com LM26484 Efficiency of Buck1, VOUT = 1.8V, at Room Temp LM26484 NO-LOAD STABILITY The LDO will remain stable and in regulation with no external load. This is an important consideration in some circuits, for example CMOS RAM keep-alive applications. LDO Functional Description The LDO is a linear regulator which targets analog loads characterized by low noise requirements. The LDO is enabled through the ENLDO pin. The output voltage is determined by the configuration of the external feedback resistors, as seen in the typical application circuit (Figure 1), R5 and R6. TABLE 1. LDO Configuration and Component Selection Guide Target Ideal Resistor Values Common R Values Actual VOUT with Com R (V) Feedback Capacitor VOUT(V) R5 (KΩ) R6 (KΩ) R5 (KΩ) R6 (KΩ) 0.8 120 200 120 200 0.8 15 0.9 160 200 162 200 0.905 15 1 200 200 200 200 1 15 1.1 240 200 240 200 1.1 15 1.2 280 200 280 200 1.2 12 1.3 320 200 324 200 1.31 12 1.4 360 200 357 200 1.393 10 1.5 400 200 402 200 1.505 10 RESISTOR SELECTION FOR LDO The output voltage of the LDO on the LM26484 is established by the feed back resistor divider R5 and R6 shown on the typical application circuit (Figure 1). The equation for determining VOUT is: VOUT = VFB*(R5+R6)/R6, where VFB is the voltage on the LDO_FB pin. The LDO control loop will force the voltage on VFB to be 0.50V. Table 1 shows ideal resistor values to establish LDO voltages from 0.8V to 1.5V along with common resistor values to establish these voltages. Common resistors do not always produce the target value. The resulting output voltage using common resistors is also found in Table 1. To keep the power consumed by the feedback network low it is recommended that R6 be established as about 200 kΩ. Lesser values of R6 are OK and can be used at the user’s discretion. FEEDBACK CAPACITOR A Feedback capacitor is required for stability; recommended values can be seen in Table 1. This capacitor must be located a distance of not more than 1 cm from the LDO_FB pin and LDO_OUT. Any good quality ceramic or film capacitor should be used. OUTPUT CAPACITOR The LDO on the LM26484 is designed specifically to work with very small ceramic output capacitors. A 10.0 µF ceramic capacitor, marked as C10 in Figure 1, temperature types Z5U, Y5V or X7R with ESR between 5 mΩ to 500 mΩ, is suitable for proper operation. It is also possible to use tantalum or film capacitors, but these are not as attractive for reasons of size and cost. The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR value that is within the range 50 mΩ to 500 mΩ for stability. NFET SELECTION There are a few major concerns when selecting an NFET for the LM26484 controller. The most important factor to consider is the maximum power rating. It is important for the NFET to have a maximum power rating larger than the application will need. The LM26484 has the ability to drive the gate voltage very close to VIN and down to approximately 1.5V. Selecting an NFET where the guaranteed operation of the VGS is ≥1.5V is important. CAPACITOR CHARACTERISTICS The LDO is designed to work with ceramic capacitors on the output to take advantage of the benefits they offer. For capacitance values in the range of 0.47 μF to 44 μF, ceramic capacitors are the smallest, least expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a typical 10 μF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for stability for the LDO. For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure correct device operation. The capacitor value can change greatly, depending on the operating conditions and capacitor type. In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the specification is met within the application. The capacitance can vary with DC bias conditions as well as temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging. The capacitor parameters are also dependent on the particular case size, with smaller sizes giving poorer performance figures in general. Recommended NFET Part Number Si1450DH Vendor Vishay VGS 1.5V PDISSIPATION 2.78W EXTERNAL CAPACITORS The LDO on the LM26484 requires external capacitors for regulator stability. These are specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. The tolerance and temperature coefficient must be considered when selecting the capacitor to ensure that the capacitance will remain close to ideal over the entire operating temperature range. www.national.com C11 (pF) 10 The LM26484 incorporates two high efficiency synchronous switching buck regulators which are 180° out of phase, SW1 and SW2 that deliver voltages from a single DC input voltage. Using a voltage mode architecture with synchronous rectification, both bucks have the ability to deliver up to 2A depending on the input voltage and output voltage (voltage head room), and the inductor chosen (maximum current capability). There are three modes of operation depending on the current required - PWM, PFM, and shutdown. PWM mode handles current loads of approximately 70 mA or higher, delivering voltage precision with high efficiency. Lighter output current loads cause the device to automatically switch into PFM for reduced current consumption (Iq = 15 µA typ.) and a longer battery life. The Standby operating mode turns off the device, offering the lowest current consumption. Forced PWM is factory programmed. For Auto PFM-PWM please contact National Semiconductor Sales. Both SW1 and SW2 can operate up to a 100% duty cycle (PMOS switch always on) for low drop out control of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage. Additional features include soft-start, under-voltage lockout, current overload protection, and thermal overload protection. During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output FETs such that the output voltage ramps between 0.8% and 1.6% (typ.) above the nominal PWM output voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on. It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the I PFM level set for PFM mode. The typical peak current in PFM mode is: PWM OPERATION During PWM operation the converter operates as a voltagemode controller with input voltage feed forward. This allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional to the input voltage. To eliminate this dependence, feed forward voltage inversely proportional to the input voltage is introduced. Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the ‘high’ PFM comparator threshold (see Figure 3), the PMOS switch is again turned on and the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this ‘sleep’ mode is less than 30 µA, which allows the part to achieve high efficiencies under extremely light load conditions. When the output drops below the ‘low’ PFM threshold, the cycle repeats to restore the output voltage to ~1.6% above the nominal PWM output voltage. If the load current should increase during PFM mode (see Figure 3) causing the output voltage to fall below the ‘low2’ PFM threshold, the part will automatically transition into fixedfrequency PWM mode. During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The NFET switch will be on in shutdown to discharge the output. When the converter is enabled, soft start is activated. It is recommended to disable the converter during the system power up and under voltage conditions when the supply is less than 3.0V. INTERNAL SYNCHRONOUS RECTIFICATION While in PWM mode, the buck uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier diode. CURRENT LIMITING A current limit feature allows the converter to protect the LM26484 and any external components during overload conditions. An internal comparator senses the voltage across an internal sense resistor and will turn on the NFET when the output current is sensed at 2.5A (min.) with 0.5 µH inductors. If the output is shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby preventing runaway. PFM OPERATION At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply current to maintain high efficiency. For the PFM mode to be enabled, please contact National Semiconductor Sales. 11 www.national.com LM26484 The part will automatically transition into PFM mode when either of two conditions occurs for a duration of 32 or more clock cycles: A. The inductor current becomes discontinuous or B. The peak PMOS switch current drops below the IMODE level Buck Regulator Functional Description LM26484 30066105 FIGURE 3. PFM vs PWM output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage. When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV. The minimum input voltage needed to support the output voltage is VIN, MIN = ILOAD * (RDSON, PFET + RINDUCTOR) + VOUT SOFT START The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus reducing start-up stresses and surges. The two LM26484 buck converters have a soft-start circuit that limits in-rush current during start-up or the one which ramps up output voltage linearly over about 500 µs. During start-up the switch current limit is ramped up (100 µs, typ.), depending on the kind of soft-start. Soft start is activated only if EN goes from logic low to logic high after VIN reaches 2.8V. — ILOAD — RDSON, PFET — RINDUCTOR LOW DROPOUT OPERATION The LM26484 can operate at 100% duty cycle (no switching; PMOS switch completely on) for low dropout support of the www.national.com 12 Load current Drain to source resistance of PFET switch in the triode region Inductor resistance LM26484 Component Selection SW1, SW2 OPERATION TABLE 2. Buck1/2 Configuration and Component Selection Guide Target Ideal Resistor Values Actual VOUT with Com/R (V) Common R Values Actual VOUT Delta from Target (V) Feedback Capacitors VOUT (V) R1/3 (KΩ) R2/4 (KΩ) R1/3 (KΩ) R2/4 (KΩ) (V) (V) C3/6 (pF) C4/8 (pF) 0.8 120 200 121 200 0.803 0.002 15 none 0.9 160 200 162 200 0.905 0.005 15 none 1 200 200 200 200 1 0 15 none 1.1 240 200 240 200 1.1 0 15 none 1.2 280 200 280 200 1.2 0 12 none 1.3 320 200 324 200 1.31 0.01 12 none 1.4 360 200 357 200 1.393 -0.008 10 none 1.5 400 200 402 200 1.505 0.005 10 none 1.6 440 200 442 200 1.605 0.005 8.2 none 1.7 427 178 432 178 1.713 0.013 8.2 none 1.8 463 178 464 178 1.803 0.003 8.2 none 1.9 498 178 499 178 1.902 0.002 8.2 none 2 450 150 453 150 2.01 0.01 8.2 none 2.1 480 150 475 150 2.083 -0.017 8.2 none 2.2 422 124 422 124 2.202 0.002 8.2 none 2.3 446 124 442 124 2.282 -0.018 8.2 none 2.4 471 124 475 124 2.415 0.015 8.2 none 2.5 400 100 402 100 2.51 0.01 8.2 none 2.6 420 100 422 100 2.61 0.01 8.2 none 2.7 440 100 442 100 2.71 0.01 8.2 33 2.8 460 100 464 100 2.82 0.02 8.2 33 2.9 480 100 475 100 2.875 -0.025 8.2 33 3 500 100 499 100 2.995 -0.005 6.8 33 3.1 520 100 523 100 3.115 0.015 6.8 33 3.2 540 100 536 100 3.18 -0.02 6.8 33 3.3 560 100 562 100 3.31 0.01 6.8 33 3.4 580 100 576 100 3.38 -0.02 6.8 33 3.5 600 100 604 100 3.52 0.02 6.8 33 The Buck control loop will force the voltage on VFB to be 0.50V. shows ideal resistor values to establish buck voltages from 0.8V to 3.5V along with common resistor values to establish these voltages. Common resistors do not always produce the target value, error is given in the delta column. In addition to the resistor feedback, feedback capacitors are also required. ( — C3/4/6/8) When choosing the output voltage for the two bucks, please take into account the fact that, the factory has optimized the accuracy of Buck1 at the top end of the VOUT range and Buck2 for the bottom end of the VOUT range. 13 www.national.com LM26484 30066104 FIGURE 4. Typical Variation in Capacitance vs. DC Bias As shown in , increasing the DC Bias condition can result in a capacitance value that falls below the minimum value given in the recommended capacitor specifications table. Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers’ specifications for the nominal value capacitor are consulted for all conditions, as some capacitor sizes (e.g. 0402) may not be suitable in the actual application. The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a temperature range of −55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R has a similar tolerance over a reduced temperature range of −55°C to +85°C. Many large value ceramic capacitors, larger than 1 μF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 0.47 µF to 44 µF range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed. www.national.com OUTPUT INDUCTORS & CAPACITORS FOR SW1 AND SW2 There are several design considerations related to the selection of output inductors and capacitors: • Load transient response; • Stability; • Efficiency; • Output ripple voltage; and • Over-current ruggedness. The LM26484 has been optimized for use with nominal values 0.5 µH and 22 µF. If other values are needed for the design, please contact National Semiconductor sales with any concerns. INDUCTOR SELECTION FOR SW1 AND SW2 A nominal inductor value of 0.5 µH is recommended. It is important to guarantee the inductor core does not saturate during any foreseeable operational situation. Care should be taken when reviewing the different saturation current ratings that are specified by different manufacturers. Saturation current ratings are typically specified at 25ºC, so ratings at maximum ambient temperature of the application should be requested from the manufacturer. There are two methods to choose the inductor saturation current rating: Recommended method: The best way to guarantee the inductor does not saturate is to choose an inductor that has saturation current rating greater than the maximum LM26484 current limit of 3.0A. In this case the device will prevent inductor saturation. Alternate method: If the recommended approach cannot be used, care must be taken to guarantee that the saturation current is greater than the peak inductor current: 14 30066106 ISAT: Maximum average inductor current Peak-to-Peak inductor current Output voltage Input voltage Inductor value in Henries at IOUTMAX Switching frequency, Hertz Estimated duty factor Estimated power supply efficiency ISAT may not be exceeded during any operation, including transients, startup, high temperature, worst case conditions, etc. Inductor saturation current at operating temperature Peak inductor current during worst case conditions ILPEAK: LM26484 IOUTMAX: IRIPPLE: VOUT: VIN: L: F: D: EFF: Inductor Value Unit Description Notes L1 and L2 0.5 µH SW1 and SW2 inductor D.C.R. 50 mΩ SUGGESTED INDUCTORS AND THEIR SUPPLIERS Output Voltage Range Vendor Part Number Value DCR (max) VOUT ≥ 2.0V Coilcraft LPS4012–222ML 2.2 µH 100 mΩ VOUT < 2.0V Coilcraft LPS4414–501ML 0.5 µH 50 mΩ OUTPUT CAPACITOR SELECTION FOR SW1 AND SW2 A ceramic output capacitor of 10 µF, 6.3V is recommended with an ESR of about 2 mΩ or less. Output ripple can be estimated from the vector sum of the reactive (Capacitor) voltage component and the real (ESR) voltage component of the output capacitor. VCOUT: VROUT: VPPOUT: INPUT CAPACITOR SELECTION FOR SW1 AND SW2 It is required to use a ceramic input capacitor of at least 10 μF and 6.3V with an ESR of under 10 mΩ. The input power source supplies average current continuously. During the PFET switch on-time, however, the demanded di/dt is higher than can be typically supplied by the input power source. This delta is supplied by the input capacitor. Estimated reactive output ripple Estimated real output ripple Estimated peak-to-peak output ripple The output capacitor needs to be mounted as close as possible to the output pin of the device. The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR to perform these functions. Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series resistance of the output capacitor (ESRCOUT). ESRCOUT is frequency dependent as well as temperature dependent. The RESR should be calculated with the applicable switching frequency and ambient temperature. 15 www.national.com LM26484 VPPIN: IOUT: CIN: ESRIN: A simplified “worst case” assumption is that all of the PFET current is supplied by the input capacitor. This will result in conservative estimates of input ripple voltage and capacitor RMS current. Input ripple voltage is estimated as follows: Estimated peak-to-peak input ripple voltage Output current, Amps Input capacitor value, Farads Input capacitor ESR, Ohms This capacitor is exposed to significant RMS current, so it is important to select a capacitor with an adequate RMS current rating. Capacitor RMS current estimated as follows: IRSCIN Model Type Estimated input capacitor RMS current Vendor Voltage Rating Case Size Inch (mm) 10 µF for CIN or COUT; C9, C2, C1, C5, C7, C10 GRM21BR60J106K Ceramic, X7R Murata 6.3V 0805, (2012) JMK212BJ106K Ceramic, X5R Taiyo-Yuden 6.3V 0805, (2012) LMK212C106KG-T Ceramic, X7R Taiyo-Yuden 10V 0805, (2012) C1608X5R0J106K Ceramic, X5R TDK 6.3V 0603, (1608) Model Type Vendor Voltage Rating Case Size Inch (mm) GRM31CR70J226KE23L Ceramic, X7R Murata 6.3V 1206, (3216) JMK316B7226ML-T Ceramic, X7R Taiyo-Yuden 6.3V 1206, (3216) 22 µF for COUT; C10, C2, C7 Capacitor Min Value Unit Description Recommended Type C10, 10.0 µF LDO1 output capacitor Ceramic, 6.3V, X5R C2, 10.0 µF SW1 output capacitor Ceramic, 6.3V, X5R C7, 10.0 µF SW2 output capacitor Ceramic, 6.3V, X5R www.national.com 16 LM26484 Physical Dimensions inches (millimeters) unless otherwise noted 5 X 4 X 0.8 mm 24-Pin LLP Package NSC Package SQA24B 17 www.national.com LM26484 Power Management Unit Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage Reference www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Solutions www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic Wireless (PLL/VCO) www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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