www.DataSheet4U.com LP3906 Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface General Description Features The LP3906 is a multi-function, programmable Power Management Unit, optimized for low power FPGAs, Microprocessors and DSPs. This device integrates two highly efficient 1.5A Step-Down DC/DC converters with dynamic voltage management (DVM), two 300mA Linear Regulators and a 400kHz I2C compatible interface to allow a host controller access to the internal control registers of the LP3906. The LP3906 additionally features programmable power-on sequencing and is offered in a tiny 5 x 4 x 0.8mm LLP-24 pin package. n Compatible with advanced applications processors and FPGAs n 2 LDOs for powering Internal processor functions and I/Os n High speed serial interface for independent control of device functions and settings n Precision internal reference n Thermal overload protection n Current overload protection n 24-lead 5 x 4 x 0.8 mm LLP package n Software Programmable Regulators Key Specifications Applications Step-Down DC/DC Converter (Buck) n 1.5A output current n Programmable Vout from: — Buck1 : 0.8V–2.0V — Buck2 : 1.0V–3.5V n Up to 96% efficiency n 2 MHz PWM switching frequency n ± 3% output voltage accuracy n Automatic soft start n FPGA, DSP core power n Applications processors n Peripheral I/O power Linear Regulators (LDO) n Programmable VOUT of 1.0V–3.5V n ± 3% output voltage accuracy n 300 mA output currents n 25 mV (typ) Dropout © 2006 National Semiconductor Corporation DS201978 www.national.com LP3906 Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface September 2006 LP3906 www.DataSheet4U.com Typical Application Circuit 20197801 FIGURE 1. Typical Application Circuit www.national.com 2 www.DataSheet4U.com LP3906 (Continued) 20197863 * For information about how schottky diodes can reduce noise in high load, high Vin applications, refer to "Buck Output Ripple Management" in the Application Notes section. FIGURE 2. Typical Application Circuit 3 www.national.com LP3906 www.DataSheet4U.com Connection Diagram 20197802 * Refer to Package Marking in Ordering Information Table Below FIGURE 3. 24-Lead LLP Package (Top View) Note: The physical placement of the package marking will vary from part to part. (*) UZXYTT format: ‘U’ – wafer fab code; ‘Z’ – assembly code; ’XY’ 2 digit date code; ‘TT” – die run code See http://www.national.com/quality/marking_conventions.html for more information on marking information. Ordering Information Voltage Option Order Number Package Type NSC Package Drawing Package Marking Supplied As Voltage JXXI LP3906SQ JXXI 24 lead LLP SQA024AG 06-JXXI 1000 tape & reel Voltage JXXI LP3906SQX JXXI 24 lead LLP SQA024AG 06-JXXI 4500 tape & reel Voltage DJXI LP3906SQ DJXI 24 lead LLP SQA024AG 06-DJXI 1000 tape & reel Voltage DJXI LP3906SQX DJXI 24 lead LLP SQA024AG 06-DJXI 4500 tape & reel Default Voltage Options Regulator www.national.com Version JXXI Version DJXI Default Voltages (V) Default Voltages (V) SW1 1.2 0.9 SW2 3.3 1.8 LDO1 3.3 3.3 LDO2 1.8 1.8 4 www.DataSheet4U.com LP3906 Pin Descriptions Pin Pin Name I/O Type 1 VIN2 I PWR Power in from either DC source or Battery to Buck 2 Functional Description 2 SW2 O PWR Buck2 switcher output pin 3 GND_SW2 G G Buck2 NMOS Power Ground 4 GND_C G G Non switching core ground pin 5 GND_SW1 G G 6 SW1 O PWR Buck1 switcher output pin 7 VIN1 I PWR Power in from either DC source or Battery to buck 1 8 SDA I/O D I2C Data (Bidirectional) 9 SCL I D I2C Clock 10 EN_T I D Enable for preset power on sequence. 11 FB1 I A 12 AVDD I PWR Analog Power for Buck converters. 13 VINLDO1 I PWR Power in from either DC source or Battery to input terminal of LDO1 14 LDO1 O PWR LDO1 Output 15 ENLDO1 I D 16 ENLDO2 I D LDO2 enable pin, a logic HIGH enables the LDO2 17 GND_L G G LDO Ground 18 LDO2 O PWR LDO2 Output 19 VINLDO2 I PWR Power in from either DC source or battery to input terminal to LDO2 20 VinLDO12 I PWR Analog Power for Internal Functions (VREF, BIAS, I2C, Logic) 21 FB2 I A 22 ENSW1 I D Enable Pin for Buck1 switcher, a logic HIGH enables Buck1 23 SYNC I D Frequency Synchronization pin which allows the user to connect an external clock signal PLL to synchronize the PMIC internal oscillator. 24 ENSW2 I D Enable Pin for Buck2 switcher, a logic HIGH enables Buck2 Buck1 NMOS Power Ground Buck1 input feedback terminal LDO1 enable pin, a logic HIGH enables the LDO1 Buck2 input feedback terminal A: Analog Pin D: Digital Pin G: Ground Pin PWR: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin 5 www.national.com LP3906 www.DataSheet4U.com Absolute Maximum Ratings (Notes 1, 2) Operating Ratings (Notes 1, 2, 7) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Bucks VIN, SDA, SCL VIN −0.3V to +6V ± 0.3V GND to GND SLUG Power Dissipation (PD_MAX) (TA=85˚C, TMAX=125˚C, (Note 5)) Storage Temperature Range −40˚C to +125˚C −40˚C to +85˚C Junction-to-Ambient Thermal Resistance (θJA)SQA024AG −65˚C to +150˚C ESD Ratings Human Body Model (Note 4) Junction Temperature (TJ) Range Thermal Properties (Notes 3, 5, 6) 150˚C Maximum Lead Temperature (Soldering) 0 to (VIN + 0.3V) Ambient Temperature (TA) Range (Note 6) 1.43 W Junction Temperature (TJ-MAX) 2.7V to 5.5V VEN 28˚C/W 260˚C 2 kV Electrical Characteristics General Electrical Characteristics (Notes 1, 2, 7, 13) Unless otherwise noted, VIN = 3.6V, Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C. Symbol Parameter VPOR Power-On Reset Threshold TSD TSDH Conditions Min VDD Falling Edge Typ Max Units 1.9 V Thermal Shutdown Threshold 160 ˚C Themal Shutdown Hysteresis 20 ˚C I2C Compatible Interface Electrical Specifications (Note 13) Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C Symbol Parameter FCLK Clock Frequency Conditions Min Typ Max Units 400 kHz tBF Bus-Free Time Between Start and Stop (Note 13) 1.3 µs tHOLD Hold Time Repeated Start Condition (Note 13) 0.6 µs tCLKLP CLK Low Period (Note 13) 1.3 µs tCLKHP CLK High Period (Note 13) 0.6 µs tSU Set Up Time Repeated Start Condition (Note 13) 0.6 µs tDATAHLD Data Hold time (Note 13) 0 µs tDATASU Data Set Up Time (Note 13) 100 ns TSU Set Up Time for Start Condition (Note 13) 0.6 µs TTRANS Maximum Pulse Width of Spikes that Must be Suppressed by the Input Filter of Both DATA & CLK Signals. (Note 13) www.national.com 50 6 ns www.DataSheet4U.com LP3906 Electrical Characteristics (Continued) Low Drop Out Regulators, LDO1 and LDO2 Unless otherwise noted, VIN = 3.6, CIN = 1.0 µF, COUT = 0.47 µF. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C. (Notes 2, 7, 8, 9, 10, 11, 12) Symbol Parameter Conditions Min VINLDO1 and VINLDO2 PMOS pins(Note 15) Max Units 1.74 5.5 V −3 3 % VIN = (VOUT + 0.3V) to 5.0V, (Note 12), Load Current = 1 mA 0.15 %/V Load Regulation VIN = 3.6V, Load Current = 1 mA to IMAX 0.011 %/mA ISC Short Circuit Current Limit LDO1-2, VOUT = 0V 500 VIN – VOUT Dropout Voltage Load Current = 50 mA (Note 10) 25 PSRR Power Supply Ripple Rejection F = 10 kHz, Load Current = IMAX 45 dB θn Supply Output Noise 10 Hz < F < 100 KHz 80 µVrms IQ (Notes 11, 14) Quiescent Current “On” IOUT = 0 mA 40 µA Quiescent Current “On” IOUT = IMAX 60 µA Quiescent Current “Off” EN is de-asserted(Note 16) 0.03 µA 300 µs µF VIN Operational Voltage Range VOUT Accuracy Output Voltage Accuracy (Default VOUT) Load current = 1 mA ∆VOUT Line Regulation Typ TON Turn On Time Start up from shut-down COUT Output Capacitor Capacitance for stability 0˚C ≤ TJ ≤ 125˚C 0.33 0.47 −40˚C ≤ TJ ≤ 125˚C 0.68 1.0 ESR 5 mA 200 mV µF 500 mΩ Buck Converters SW1, SW2 Unless otherwise noted, VIN = 3.6, CIN = 10 µF, COUT = 10 µF, LOUT = 2.2 µH ceramic. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C. (Notes 2, 7, 8, 9, 14) Symbol Parameter Conditions Min Typ −3 Max Default VOUT Line Regulation 2.7 < VIN < 5.5 IO =10 mA 0.089 %/V Load Regulation 100 mA < IO < IMAX 0.0013 %/mA Eff Efficiency Load Current = 250 mA 96 % ISHDN Shutdown Supply Current EN is de-asserted 0.01 µA fOSC Sync Mode Clock Frequency Synchronized from 13 MHz system clock 2.0 MHz Internal Oscillator Frequency 2.0 MHz IPEAK Peak Switching Current Limit 2.0 A IQ (Note 14) Quiescent Current “On” 33 µA RDSON (P) Pin-Pin Resistance PFET 200 mΩ RDSON (N) Pin-Pin Resistance NFET 180 mΩ TON Turn On Time Start up from shut-down CIN Input Capacitor Capacitance for stability 10 µF CO Output Capacitor Capacitance for stability 10 µF No load PFM Mode 7 +3 Units Output Voltage Accuracy VOUT 500 % µs www.national.com LP3906 www.DataSheet4U.com Electrical Characteristics (Continued) IO Electrical Characteristics Unless otherwise noted: Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = 0˚C to +125˚C. (Note 13) Symbol Parameter VIL Input Low Level VIH Input High Level Conditions Limit Min Max 0.4 1.2 Units V V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics. Note 2: All voltages are with respect to the potential at the GND pin. Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160˚C (typ.) and disengages at TJ = 140˚C (typ.) Note 4: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. (MILSTD - 883 3015.7) Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125˚C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP − (θJA x PD-MAX). See applications section. Note 6: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Note 8: CIN, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. Note 9: The device maintains a stable, regulated output voltage without a load. Note 10: Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value. Note 11: Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT. Note 12: VIN minimum for line regulation values is 1.8V. Note 13: This specification is guaranteed by design. Note 14: The Iq can be defined as the standing current of the LP3906 when the I2C bus is active and all other power blocks have been disabled via the I2C bus, or it can be defined as the I2C bus active, and the other power blocks are active under no load condition. These two values can be used by the system designer when the LP3906 is powered using a battery. If the user plans to use the HW enable pins to disable each block of the IC please contact the factory applications for IQ details. Note 15: Pins 13, 19 can operate from Vin min of 1.74 to a Vin max of 5.5V this rating is only for the series pass pmos power fet. It allows the system design to use a lower voltage rating if the input voltage comes from a buck output. Note 16: The Iq exhibits a higher current draw when the EN pin is de-asserted because the I2C buffer pins draw an additional 2µA www.national.com 8 www.DataSheet4U.com Output Voltage Change vs Temperature (LDO1) Vin = 4.3V, Vout = 3.3V, 100 mA load TA = 25˚C unless otherwise noted Output Voltage Change vs Temperature (LDO2) Vin = 4.3V, Vout = 1.8V, 100 mA load 20197835 20197836 Load Transient (LDO1) 3.6 Vin, 3.3 Vout, 0 – 100 mA load Load Transient (LDO2) 3.6 Vin, 1.8 Vout, 0 – 100 mA load 20197837 20197838 Line Transient (LDO1) 3.6 - 4.5 Vin, 3.3 Vout, 150 mA load Line Transient (LDO2) 3 – 4.2 Vin, 1.8 Vout, 150 mA load 20197839 20197840 9 www.national.com LP3906 Typical Performance Characteristics — LDO LP3906 www.DataSheet4U.com Typical Performance Characteristics — LDO TA = 25˚C unless otherwise noted Enable Start-up time (LDO1) ) 0-3.6 Vin, 3.3 Vout, 1mA load Enable Start-up time (LDO2) 0 – 3.6 Vin, 1.8 Vout, 1 mA load 20197841 www.national.com (Continued) 20197842 10 www.DataSheet4U.com LP3906 Typical Performance Characteristics — Buck TA = 25˚C unless otherwise noted Output Voltage vs. Supply Voltage (Vout = 1.0 V) Shutdown Current vs. Temp 20197844 20197843 Output Voltage vs. Supply Voltage (Vout = 1.8V) Output Voltage vs. Supply Voltage (Vout = 3.5V) 20197845 20197846 Buck 1 Efficiency vs Output Current (Forced PWM Mode, Vout =1.2V, L= 2.2µH) Buck 1 Efficiency vs Output Current (Forced PWM Mode, Vout =2.0V, L= 2.2µH) 20197847 20197848 11 www.national.com LP3906 www.DataSheet4U.com Typical Performance Characteristics — Buck TA = 25˚C unless otherwise noted Buck 1 Efficiency vs Output Current (PFM to PWM mode, Vout =1.2V, L= 2.2µH) Buck 1 Efficiency vs Output Current (PFM to PWM mode, Vout =2.0V, L= 2.2µH) 20197849 20197850 Buck 2 Efficiency vs Output Current (Forced PWM Mode, Vout =1.8V, L= 2.2µH) Buck 2 Efficiency vs Output Current (Forced PWM Mode, Vout =3.3V, L= 2.2µH) 20197851 www.national.com (Continued) 20197852 12 www.DataSheet4U.com Buck 2 Efficiency vs Output Current (PFM to PWM Mode, Vout =1.8V, L= 2.2µH) (Continued) Buck 2 Efficiency vs Output Current (PFM to PWM Mode, Vout =3.3V, L= 2.2µH) 20197853 20197854 Load Transient Response Vout = 1.2 (PWM Mode) Mode Change by Load Transient Vout = 1.2V (PWM to PFM) 20197855 20197856 Line Transient Response Vin = 3 – 3.6 V, Vout = 1.2 V, 250 mA load Line Transient Response Vin = 3 – 3.6 V, Vout = 3.3 V, 250 mA load 20197858 20197857 13 www.national.com LP3906 Typical Performance Characteristics — Buck TA = 25˚C unless otherwise noted LP3906 www.DataSheet4U.com Typical Performance Characteristics — Buck TA = 25˚C unless otherwise noted Start up into PWM Mode Vout = 1.8 V, 1.2 A load Start up into PWM Mode Vout = 3.3 V, 1.2 A load 20197859 20197860 Start up into PFM Mode Vout = 1.8 V, 30 mA load Start up into PFM Mode Vout = 3.3 V, 30 mA load 20197861 www.national.com (Continued) 20197862 14 www.DataSheet4U.com LP3906 DC/DC Converters OVERVIEW The LP3906 supplies the various power needs of the application by means of two Linear Low Drop Regulators LDO1 and LDO2 and two Buck converters SW1 and SW2. The table here under lists the output characteristics of the various regulators. SUPPLY SPECIFICATION Output VOUT Range(V) Resolution (mV) IMAX Maximum Output Current (mA) analog 1.0 to 3.5 100 300 analog 1.0 to 3.5 100 300 SW1 digital 0.8 to 2.0 50 1500 SW2 digital 1.0 to 3.5 100 1500 Supply Load LDO1 LDO2 *For default values of the regulators, please consult Default Voltage Options Table page 3 LINEAR LOW DROP-OUT REGULATORS (LDOS) The output voltages of both LDOs are register programmable. The default output voltages are factory programmed during Final Test, which can be tailored to the specific needs of the system designer. LDO1 and LDO2 are identical linear regulators targeting analog loads characterized by low noise requirements. LDO1 and LDO2 are enabled through the ENLDO pin or through the corresponding LDO1 or LDO2 control register. 20197822 NO-LOAD STABILITY The LDOs will remain stable and in regulation with no external load. This is an important consideration in some circuits, for example CMOS RAM keep-alive applications. mable in steps of 100mV from 1.0V to 3.5V by programming bits D4-0 in the LDO Control registers. Both LDO1 and LDO2 are enabled by applying a logic 1 to the ENLDO1 and ENLDO2 pin. Enable/disable control is also provided through enable bit of the LDO1 and LDO2 control registers. The value of the enable LDO bit in the register is logic 1 by default. The output voltage can be altered while the LDO is enabled. LDO1 AND LDO2 CONTROL REGISTERS LDO1 and LDO2 can be configured by means of the LDO1 and LDO2 control registers. The output voltage is program- 15 www.national.com LP3906 www.DataSheet4U.com SW1, SW2: Synchronous Step Down Magnetic DC/DC Converters The DC gain of the power stage is proportional to the input voltage. To eliminate this dependence, feed forward voltage inversely proportional to the input voltage is introduced. FUNCTIONAL DESCRIPTION INTERNAL SYNCHRONOUS RECTIFICATION While in PWM mode, the buck uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier diode. The LP3906 incorporates two high efficiency synchronous switching buck regulators, SW1 and SW2 that deliver a constant voltage from a single Li-Ion battery to the portable system processors. Using a voltage mode architecture with synchronous rectification, both bucks have the ability to deliver up to 1500mA depending on the input voltage and output voltage (voltage head room), and the inductor chosen (maximum current capability). CURRENT LIMITING A current limit feature allows the converter to protect itself and external components during overload conditions. PWM mode implements current limiting using an internal comparator that trips at 2.0 A (typ). If the output is shorted to ground the device enters a timed current limit mode where the NFET is turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor current has more time to decay, thereby preventing runaway. There are three modes of operation depending on the current required - PWM, PFM, and shutdown. PWM mode handles current loads of approximately 70mA or higher, delivering voltage precision of +/-3% with 90% efficiency or better. Lighter output current loads cause the device to automatically switch into PFM for reduced current consumption (IQ = 15 µA typ.) and a longer battery life. The Standby operating mode turns off the device, offering the lowest current consumption. PWM or PFM mode is selected automatically or PWM mode can be forced through the setting of the buck control register. Both SW1 and SW2 can operate up to a 100% duty cycle (PMOS switch always on) for low drop out control of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage. Additional features include soft-start, under-voltage lock-out, current overload protection, and thermal overload protection. A current limit feature allows the buck to protect itself and external components during overload conditions PWM mode implements cycle-by-cycle current limiting using an internal comparator that trips at 2000mA (typical). PFM OPERATION At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply current to maintain high efficiency. The part will automatically transition into PFM mode when either of two conditions occurs for a duration of 32 or more clock cycles: A. The inductor current becomes discontinuous or B. The peak PMOS switch current drops below the IMODE level CIRCUIT OPERATION DESCRIPTION A buck converter contains a control block, a switching PFET connected between input and output, a synchronous rectifying NFET connected between the output and ground (BCKGND pin) and a feedback path. During the first portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output voltage. If the output voltage is below the ‘high’ PFM comparator threshold, the PMOS power switch is turned on. It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the IPFM level set for PFM mode. The typical peak current in PFM mode is: by storing energy in a magnetic field. During the second portion of each cycle, the control block turns the PFET switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor current down with a slope of The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage across the load. Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output voltage is below the ‘high’ PFM comparator threshold (see figure below), the PMOS switch is again turned on and the cycle is PWM OPERATION During PWM operation the converter operates as a voltagemode controller with input voltage feed forward. This allows the converter to achieve excellent load and line regulation. www.national.com 16 www.DataSheet4U.com the internal state machine of the LP3906 following a Power-On event that moves the operating mode to the Active state. (see Power On Sequence). The SW1 and SW2 output voltages revert to default values when the power on sequence has been completed. The default output voltage for each buck converter is factory programmable. (See Application Notes). SW1, SW2 can be enabled/disabled through the corresponding control register. The Modulation mode PWM/PFM is by default automatic and depends on the load as described above in the functional description. The modulation mode can be overridden by setting I2C bit to a logic 1 in the corresponding buck control register, forcing the buck to operate in PWM mode regardless of the load condition. (Continued) repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this ‘sleep’ mode is less than 30 µA, which allows the part to achieve high efficiencies under extremely light load conditions. When the output drops below the ‘low’ PFM threshold, the cycle repeats to restore the output voltage to ~1.6% above the nominal PWM output voltage. If the load current should increase during PFM mode (see figure below) causing the output voltage to fall below the ‘low2’ PFM threshold, the part will automatically transition into fixed-frequency PWM mode. SW1, SW2 OPERATION SW1 and SW2 have selectable output voltages ranging from 0.8V to 3.5V (typ.). Both SW1 and SW2 in the LP3906 are I2C register controlled and are enabled by default through 20197803 SHUTDOWN MODE During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The NFET switch will be on in shutdown to discharge the output. When the converter is enabled, soft start is activated. It is recommended to disable the converter during the system power up and under voltage conditions when the supply is less than 2.8V. to logic high after VIN reaches 2.8V. Soft start is implemented by increasing switch current limit in steps of 213 mA, 425 mA, 850 mA and 1700 mA (typ. Switch current limit). The start-up time thereby depends on the output capacitor and load current demanded at start-up. LOW DROPOUT OPERATION The LP3906 can operate at 100% duty cycle (noswitching; PMOS switch completely on) for low drop out support of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage. When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV. The minimum input voltage needed to support the output voltage is SOFT START The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus reducing start-up stresses and surges. The two LP3906 buck converters have a soft-start circuit that limits in-rush current during start-up. During start-up the switch current limit is increased in steps. Soft start is activated only if EN goes from logic low 17 www.national.com LP3906 SW1, SW2: Synchronous Step Down Magnetic DC/DC Converters LP3906 www.DataSheet4U.com SW1, SW2: Synchronous Step Down Magnetic DC/DC Converters EN_T is edge triggered with rising edge signaling the chip to power on. The EN_T input is deglitched and the default is set at 1 ms. As shown in the next 2 diagrams, a rising EN_T edge will start a power on sequence, while a falling EN_T edge will start a shutdown sequence. If EN_T is high, toggling the external enables of the regulators will have no effect on the chip. (Continued) VIN, MIN = ILOAD * (RDSON, PFET + RINDUCTOR) + VOUT • ILOAD Load current • RDSON, PFET Drain to source resistance of PFET switch in the triode region • RINDUCTOR Inductor resistance Default Power ON Sequence: FLEXIBLE POWER SEQUENCING OF MULTIPLE POWER SUPPLIES The LP3906 provides several options for power on sequencing. The two bucks can be individually controlled with ENSW1 and ENSW2. The two LDOs can also be individually controlled with ENLDO1 and ENLDO2. If the user desires a set power on sequence, all four enables should be tied LOW so that the regulators don’t automatically enable when power is supplied. The user can then program the chip through I2C and raise EN_T from LOW to HIGH to activate the power on sequencing. t2 (ms) t3 (ms) t4 (ms) 1.5 2.0 3 6 Note: LP3906 The default Power on delays can be reprogrammed at final test or by using I2C registers to 1, 1.5, 2, 3, 6, or 11 ms. The regulators can also be programmed through I2C to turn on and off. By default, the I2C enables for the regulators are ON. The regulators are on following the pattern below: Regulators on = (I2C enable) AND (External pin enable OR EN_T high). POWER ON EN_T assertion causes the LP3906 to emerge from Standby mode to Full Operation mode at a preset timing sequence. By default, the enables for the LDOs and Bucks are internally pulled up, which causes the part to turn ON automatically. If the user wishes to have a preset timing sequence to power on the regulators, the external regulator enables must be tied LOW. Otherwise, simply tie the enables of each specific regulator HIGH. www.national.com t1 (ms) 20197809 18 www.DataSheet4U.com LP3906 LP3906 Default Power-Up Sequence 20197810 Power-On Timing Specification Symbol Description Min Typ Max Units t1 Programmable Delay from EN_T assertion to VCC_Buck1 On 1.5 ms t2 Programmable Delay from EN_T assertion to VCC_Buck2 On 2 ms t3 Programmable Delay from EN_T assertion to VCC_LDO1 On 3 ms t4 Programmable Delay from EN_T assertion to VCC_LDO2 On 6 ms Note: LP3906 The default Power on delays can be reprogrammed at final test or I2C to 1, 1.5, 2, 3, 6, or 11 ms. 19 www.national.com LP3906 www.DataSheet4U.com LP3906 Default Power-Off Sequence 20197811 Symbol Description Min Typ Max Units t1 Programmable Delay from EN_T deassertion to VCC_Buck1 Off 1.5 ms t2 Programmable Delay from EN_T deassertion to VCC_Buck2 Off 2 ms t3 Programmable Delay from EN_T deassertion to VCC_LDO1 Off 3 ms t4 Programmable Delay from EN_T deassertion to VCC_LDO2 Off 6 ms Note: LP3906 The default Power on delays can be reprogrammed at final test to 0, .5, 1, 2, 5, or 10 ms. Default setting is the same as the on sequence. VDD rises above the minimum operating voltage of the Logic and the internal oscillator that clocks the Sequential Logic in the Control section. Power-On-Reset The LP3906 is equipped with an internal Power-On-Reset (“POR”) circuit that will reset the logic when VDD < VPOR. This guarantees that the logic is properly initialized when www.national.com 20 www.DataSheet4U.com Signal timing specifications are according to the I2C bus specification. The maximum bit rate is 400 kbit/s. See I2C specification from Philips for further details. I2C SIGNALS The LP3906 features an I2C compatible serial interface, using two dedicated pins: SCL and SDA for I2C clock and data respectively. Both signals need a pull-up resistor according to the I2C specification. The LP3906 interface is an I2C slave that is clocked by the incoming SCL clock. I2C DATA VALIDITY The data on the SDA line must be stable during the HIGH period of the clock signal (SCL), e.g.- the state of the data line can only be changed when CLK is LOW. 20197816 I2C Signals: Data Validity I2C START AND STOP CONDITIONS START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as the SDA signal transitioning from HIGH to LOW while the SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH while the SCL is HIGH. The I2C master always generates START and STOP bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data transmission, I2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise. 20197817 START and STOP Conditions TRANSFERRING DATA Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledged related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying acknowledgement. A receiver which has been addressed must generate an acknowledgement (“ACK”) after each byte has been received. After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). Please note that according to industry I2C standards for 7-bit addresses, the MSB of an 8-bit address is removed, and communication actually starts with the 7th most significant bit. For the eighth bit (LSB), a “0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register. LP3906 has a chip address of 60’h, which is factory programmed. 20197818 I2C Chip Address 21 www.national.com LP3906 I2C Compatible Serial Interface LP3906 www.DataSheet4U.com I2C Compatible Serial Interface (Continued) 20197819 w = write (SDA = “0”) r = read (SDA = “1”) ack = acknowledge (SDA pulled down by either master or slave) rs = repeated start id = LP3906 chip address : 0x60 I2C Write Cycle When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle waveform. 20197824 I2C Read Cycle www.national.com 22 www.DataSheet4U.com LP3906 LP3906 Control Registers Register Address Register Name Read/Write Register Description 0x02 ICRA R Interrupt Status Register A 0x07 SCR1 R/W System Control 1 Register 0x10 BKLDOEN R/W Buck and LDO Output Voltage Enable Register 0x11 BKLDOSR R 0x20 VCCR R/W Voltage Change Control Register 1 0x23 B1TV1 R/W Buck 1 Target Voltage 1 Register 0x24 B1TV2 R/W Buck 1 Target Voltage 2 Register 0x25 B1RC R/W Buck 1 Ramp Control 0x29 B2TV1 R/W Buck 2 Target Voltage 1 Register 0x2A B2TV2 R/W Buck 2 Target Voltage 2 Register 0x2B B2RC R/W Buck 2 Ramp Control 0x38 BFCR R/W Buck Function Register 0x39 LDO1VCR R/W LDO1 Voltage control Registers 0x3A LDO2VCR R/W LDO2 Voltage control Registers Buck and LDO Output Voltage Status Register 23 www.national.com LP3906 www.DataSheet4U.com LP3906 Control Registers (Continued) INTERRUPT STATUS REGISTER (ISRA) 0X02 This register informs the user of the temperature status of the chip. D7-2 D1 D0 Name — Temp 125˚C — Access — R — Data Reserved Status bit for thermal warning PMIC T > 125˚C 0 – PMIC Temp. < 125˚C 1 – PMIC Temp. > 125˚C Reserved Reset 0 0 0 CONTROL 1 REGISTER (SCR1) 0X07 This register allows the user to select the preset delay sequence for power-on timing, to switch between PFM and PWM mode for the bucks, and also to select between an internal and external clock for the bucks. The external LDO and SW enables should be pulled LOW to allow the blocks to sequence correctly through assertion of the EN_T pin. D7 D6-4 D3 D2 D1 D0 — EN_DLY — FPWM2 FPWM1 ECEN Access — R/W — R/W R/W R/W Data Reserved Selects the preset Reserved delay sequence from EN_T assertion (shown below) Buck 2 PWM /PFM Mode select 0 – Auto Switch PFM - PWM operation 1 – PWM Mode Only Buck 1 PWM /PFM Mode select 0 – Auto Switch PFM - PWM operation 1 – PWM Mode Only External Buck Clock Select 0 – Internal 2 MHz Oscillator clock 1 – External 13 MHz Oscillator clock Reset 0 010 0 0 0 Name 1 EN_DLY PRESET DELAY SEQUENCE AFTER EN_T ASSERTION EN_DLY < 2:0 > Buck2 LDO1 LDO2 1 1 1 1 001 1 1.5 2 2 010 1.5 2 3 6 011 1.5 2 1 1 100 1.5 2 3 6 101 1.5 1.5 2 2 110 3 2 1 1.5 111 2 3 6 11 000 www.national.com Delay (ms) Buck1 24 www.DataSheet4U.com LP3906 LP3906 Control Registers (Continued) BUCK AND LDO OUTPUT VOLTAGE ENABLE REGISTER (BKLDOEN) – 0X10 This register controls the enables for the Bucks and LDOs. D7 D6 D5 D4 D3 D2 D1 D0 Name — LDO2EN — LDO1EN — BK2EN — BK1EN Access — R/W — R/W — R/W — R/W Data Reserved 0 – Disable 1 – Enable Reserved 0 – Disable 1 – Enable Reserved 0 – Disable 1 – Enable Reserved 0 – Disable 1 – Enable Reset 0 1 1 1 0 1 0 1 BUCK AND LDO STATUS REGISTER (BKLDOSR) – 0X11 This register monitors whether the Bucks and LDOs meet the voltage output specifications. D7 D6 D5 D4 D3 D2 D1 D0 BKS_OK LDOS_OK LDO2_OK LDO1_OK — BK2_OK — BK1_OK Access R R R R — R — R Data 0 – Buck 1-2 Not Valid 1 – Bucks Valid 0 – LDO 1-2 Not Valid 1 – LDOs Valid 0 – LDO2 Not 0 – LDO1 Not Reserved 0 – Buck2 Not Reserved 0 – Buck1 Valid Valid Valid Not Valid 1 – LDO2 1 – LDO1 1 – Buck2 1 – Buck1 Valid Valid Valid Valid Reset 0 0 0 Name 0 0 0 0 0 BUCK VOLTAGE CHANGE CONTROL REGISTER 1 (VCCR) – 0X20 This register selects and controls the output target voltages for the buck regulators. D7-6 D5 D4 D3-2 D1 D0 Name — B2VS B2GO — B1VS B1GO Access — R/W R/W — R/W R/W Data Reserved Buck2 Target Voltage Buck2 Voltage Ramp Reserved Select CTRL 0 – B2VT1 0 – Hold 1 – B2VT2 1 – Ramp to B2VS selection Buck1 Target Voltage Buck1 Voltage Ramp Select CTRL 0 – B1VT1 0 – Hold 1 – B1VT2 1 – Ramp to B1VS selection Reset 00 0 0 0 00 25 0 www.national.com LP3906 www.DataSheet4U.com LP3906 Control Registers (Continued) BUCK 1 TARGET VOLTAGE 2 REGISTER (B1TV2) – 0X24 This register allows the user to program the output target voltage of Buck 1. BUCK1 TARGET VOLTAGE 1 REGISTER (B1TV1) – 0X23 This register allows the user to program the output target voltage of Buck 1. D7-5 D4-0 D7-5 D4-0 Name — BK1_VOUT1 Name — BK1_VOUT2 Access — R/W Access — R/W Reserved Buck1 Output Voltage (V) Reserved Buck1 Output Voltage (V) Data Reset www.national.com 000 Data 5’h00 Ext Ctrl 5’h00 Ext Ctrl 5’h01 0.80 5’h01 0.80 5’h02 0.85 5’h02 0.85 5’h03 0.90 5’h03 0.90 5’h04 0.95 5’h04 0.95 5’h05 1.00 5’h05 1.00 5’h06 1.05 5’h06 1.05 5’h07 1.10 5’h07 1.10 5’h08 1.15 5’h08 1.15 5’h09 1.20 5’h09 1.20 5’h0A 1.25 5’h0A 1.25 5’h0B 1.30 5’h0B 1.30 5’h0C 1.35 5’h0C 1.35 5’h0D 1.40 5’h0D 1.40 5’h0E 1.45 5’h0E 1.45 5’h0F 1.50 5’h0F 1.50 5’h10 1.55 5’h10 1.55 5’h11 1.60 5’h11 1.60 5’h12 1.65 5’h12 1.65 5’h13 1.70 5’h13 1.70 5’h14 1.75 5’h14 1.75 5’h15 1.80 5’h15 1.80 5’h16 1.85 5’h16 1.85 5’h17 1.90 5’h17 1.90 5’h18 1.95 5’h18 1.95 5’h19 2.00 5’h19 2.00 5’h1A–5’h1F 2.00 5’h1A–5’h1F 2.00 Reset Factory Programmed Default 26 000 Factory Programmed Default www.DataSheet4U.com LP3906 LP3906 Control Registers (Continued) BUCK 1 RAMP CONTROL REGISTER (B1RC) - 0x25 This register allows the user to program the rate of change between the target voltages of Buck 1. D7 D6-4 D3-0 Name ---- ---- B1RS Access ---- ---- R/W Reserved Reserved Data Data Code Ramp Rate mV/us 4h’0 Instant 4h’1 1 4h’2 2 4h’3 3 4h’4 4 4h’5 5 4h’6 6 4h’7 7 4h’8 8 4h’9 9 4h’A 10 4h’B - 4h’F Reset 0 010 27 10 1000 www.national.com LP3906 www.DataSheet4U.com LP3906 Control Registers (Continued) BUCK 2 TARGET VOLTAGE 2 REGISTER (B2TV2) – 0X2A This register allows the user to program the output target voltage of Buck 2. BUCK 2 TARGET VOLTAGE 1 REGISTER (B2TV1) – 0X29 This register allows the user to program the output target voltage of Buck 2. D7-5 D4-0 D7-5 D4-0 Name — BK2_VOUT1 Name — BK2_VOUT2 Access — R/W Access — R/W Reserved Buck2 Output Voltage (V) Reserved Buck2 Output Voltage (V) Data Reset www.national.com 000 Data 5’h00 Ext Ctrl 5’h00 Ext Ctrl 5’h01 1.0 5’h01 1.0 5’h02 1.1 5’h02 1.1 5’h03 1.2 5’h03 1.2 5’h04 1.3 5’h04 1.3 5’h05 1.4 5’h05 1.4 5’h06 1.5 5’h06 1.5 5’h07 1.6 5’h07 1.6 5’h08 1.7 5’h08 1.7 5’h09 1.8 5’h09 1.8 5’h0A 1.9 5’h0A 1.9 5’h0B 2.0 5’h0B 2.0 5’h0C 2.1 5’h0C 2.1 5’h0D 2.2 5’h0D 2.2 5’h0E 2.4 5’h0E 2.4 5’h0F 2.5 5’h0F 2.5 5’h10 2.6 5’h10 2.6 5’h11 2.7 5’h11 2.7 5’h12 2.8 5’h12 2.8 5’h13 2.9 5’h13 2.9 5’h14 3.0 5’h14 3.0 5’h15 3.1 5’h15 3.1 5’h16 3.2 5’h16 3.2 5’h17 3.3 5’h17 3.3 5’h18 3.4 5’h18 3.4 5’h19 3.5 5’h19 3.5 5’h1A–5’h1F 3.5 5’h1A–5’h1F 3.5 Reset Factory Programmed Default 28 000 Factory Programmed Default www.DataSheet4U.com LP3906 LP3906 Control Registers (Continued) BUCK 2 RAMP CONTROL REGISTER (B2RC) - 0x2B This register allows the user to program the rate of change between the target voltages of Buck 2 D7 D6-4 D3-0 Name ---- ---- B2RS Access ---- ---- R/W Reserved Reserved Data Data Code Ramp Rate mV/us 4h’0 Instant 4h’1 1 4h’2 2 4h’3 3 4h’4 4 4h’5 5 4h’6 6 4h’7 7 4h’8 8 4h’9 9 4h’A 10 4h’B - 4h’F Reset 0 010 29 10 1000 www.national.com LP3906 www.DataSheet4U.com LP3906 Control Registers (Continued) BUCK FUNCTION REGISTER (BFCR) – 0x38 This register allows the Buck switcher clock frequency to be spread across a wider range, allowing for less Electro-magnetic Interference (EMI). The spread spectrum modulation frequency refers to the rate at which the frequency ramps up and down, centered at 2 MHz. 20197825 D7-2 D1 D0 Name — BK_SLOMOD BK_SSEN Access — R/W R/W Buck Spread Spectrum Modulation 0 – 10 kHz triangular wave 1 – 2 kHz triangular wave Spread Spectrum Function Output 0 – Disabled 1 – Enabled 1 0 Data Reserved Reset 000010 www.national.com 30 www.DataSheet4U.com (Continued) LDO2 CONTROL REGISTER (LDO2VCR) – 0X3A This register allows the user to program the output target voltage of LDO 2. LDO1 CONTROL REGISTER (LDO1VCR) – 0X39 This register allows the user to program the output target voltage of LDO 1. D7-5 D4-0 Name — LDO1_OUT Access — R/W Reserved LDO1 Output voltage (V) Data 000 D4-0 Name — LDO2_OUT Access — R/W Reserved LDO2 Output voltage (V) Data 5’h00 1.0 5’h00 1.0 5’h01 1.1 5’h01 1.1 5’h02 1.2 5’h02 1.2 5’h03 1.3 5’h03 1.3 5’h04 1.4 5’h04 1.4 5’h05 1.5 5’h05 1.5 5’h06 1.6 5’h06 1.6 5’h07 1.7 5’h07 1.7 5’h08 1.8 5’h08 1.8 5’h09 1.9 5’h09 1.9 5’h0A 2.0 5’h0A 2.0 5’h0B 2.1 5’h0B 2.1 5’h0C 2.2 5’h0C 2.2 5’h0D 2.3 5’h0D 2.3 5’h0E 2.4 5’h0E 2.4 5’h0F 2.5 5’h0F 2.5 5’h10 2.6 5’h10 2.6 5’h11 2.7 5’h11 2.7 5’h12 2.8 5’h12 2.8 5’h13 2.9 5’h13 2.9 5’h14 3.0 5’h14 3.0 5’h15 3.1 5’h15 3.1 5’h16 3.2 5’h16 3.2 5’h17 3.3 5’h17 3.3 3.4 5’h18 3.4 5’h18 Reset D7-5 5’h19 3.5 5’h19 3.5 5’h1A–5’h1F 3.5 5’h1A–5’h1F 3.5 Reset Factory Programmed Default 31 000 Factory Programmed Default www.national.com LP3906 LP3906 Control Registers LP3906 www.DataSheet4U.com Application Notes Method 2: SYSTEM CLOCK INPUT (SYNC) PIN A more conservative and recommended approach is to choose an inductor that has saturation current rating greater than the maximum current limit of 2375 mA. Pin 23 of the chip allows for a system clock input in order to synchronize the buck converters in PWM mode. This is useful if the user wishes to force the bucks to work synchronously with the system. Otherwise, the user should tie the pin to GND and the bucks will operate on an internal 2 MHz clock. The signal applied to the SYNC pin must be 13 MHz as per application processor specifications, but we can be contacted to modify that specification if so desired. Upon inputting the 13 MHz clock signal, the bucks will scale it down and continue to run at 2 MHz based off the 13 MHz clock. Given a peak-to-peak current ripple (IPP) the inductor needs to be at least Inductor Value Unit Description LSW1,2 µH Notes SW1,2 inductor D.C.R. 70 mΩ External Capacitors The regulators on the LP3906 require external capacitors for regulator stability. These are specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. ANALOG POWER SIGNAL ROUTING All power inputs should be tied to the main VDD source (i.e. battery), unless the user wishes to power it from another source. (i.e. external LDO output). The analog VDD inputs power the internal bias and error amplifiers, so they should be tied to the main VDD. The analog VDD inputs must have an input voltage between 2.7 and 5.5 V, as specified on pg. 6 of the datasheet. The other VINs (VINLDO1, VINLDO2, VIN1, VIN2) can actually have inputs lower than 2.7V, as long as it’s higher than the programmed output (+0.3V, to be safe). The analog and digital grounds should be tied together outside of the chip to reduce noise coupling. LDO CAPACITOR SELECTION Input Capacitor An input capacitor is required for stability. It is recommended that a 1.0 µF capacitor be connected between the LDO input pin and ground (this capacitance value may be increased without limit). This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Important: Tantalum capacitors can suffer catastrophic failures due to surge currents when connected to a low impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be guaranteed by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain approximately 1.0 µF over the entire operating temperature range. COMPONENT SELECTION Inductors for SW1 and SW2 There are two main considerations when choosing an inductor; the inductor should not saturate and the inductor current ripple is small enough to achieve the desired output voltage ripple. Care should be taken when reviewing the different saturation current ratings that are specified by different manufacturers. Saturation current ratings are typically specified at 25oC, so ratings at maximum ambient temperature of the application should be requested from the manufacturer. There are two methods to choose the inductor saturation current rating: Method 1: The saturation current is greater than the sum of the maximum load current and the worst case average to peak inductor current. This can be written as follows: Output Capacitor The LDOs on the LP3906 are designed specifically to work with very small ceramic output capacitors. A 1.0 µF ceramic capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5 mΩ to 500 mΩ, are suitable in the application circuit. It is also possible to use tantalum or film capacitors at the device output, COUT (or VOUT), but these are not as attractive for reasons of size and cost. The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR value that is within the range 5 mΩ to 500 mΩ for stability. IRIPPLE: Average to peak inductor current IOUTMAX: Maximum load current VIN: Maximum input voltage to the buck L: Min inductor value including worse case tolerances (30% drop can be considered for method 1) f: Minimum switching frequency (1.6 MHz) Buck Output voltage VOUT: www.national.com 2.2 Capacitor Characteristics The LDOs are designed to work with ceramic capacitors on the output to take advantage of the benefits they offer. For capacitance values in the range of 0.47 µF to 4.7 µF, ceramic capacitors are the smallest, least expensive and have the lowest ESR values, thus making them best for eliminating 32 www.DataSheet4U.com Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25˚C down to −40˚C, so some guard band must be allowed. (Continued) high frequency noise. The ESR of a typical 1.0 µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for stability for the LDOs. For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure correct device operation. The capacitor value can change greatly, depending on the operating conditions and capacitor type. In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the specification is met within the application. The capacitance can vary with DC bias conditions as well as temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging. The capacitor parameters are also dependent on the particular case size, with smaller sizes giving poorer performance figures in general. As an example, the graph below shows a typical graph comparing different capacitor case sizes in a Capacitance vs. DC Bias plot. Input Capacitor Selection for SW1 and SW2 A ceramic input capacitor of 10 µF, 6.3V is sufficient for the magnetic dc/dc converters. Place the input capacitor as close as possible to the input of the device. A large value may be used for improved input voltage filtering. The recommended capacitor types are X7R or X5R. Y5V type capacitors should not be used. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. The input filter capacitor supplies current to the PFET switch of the dc/dc converter in the first half of each cycle and reduces voltage ripple imposed on the input power source. A ceramic capacitor’s low ESR (Equivalent Series Resistance) provides the best noise filtering of the input voltage spikes due to fast current transients. A capacitor with sufficient ripple current rating should be selected. The Input current ripple can be calculated as: The worse case is when VIN = 2VOUT 20197828 Graph Showing a Typical Variation in Capacitance vs. DC Bias Output Capacitor Selection for SW1, SW2 A 10 µF, 6.3V ceramic capacitor should be used on the output of the sw1 and sw2 magnetic dc/dc converters. The input capacitor needs to be mounted as close as possible to the input of the device. A large value may be used for improved input voltage filtering. The recommended capacitor types are X7R or X5R. Y5V type capacitors should not be used. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer and DC bias curves should be requested from them and analyzed as part of the capacitor selection process. The output filter capacitor of the magnetic dc/dc converter smoothes out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESD to perform these functions. The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its ESR and can be calculated as follows: As shown in the graph, increasing the DC Bias condition can result in the capacitance value that falls below the minimum value given in the recommended capacitor specifications table. Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers’ specifications for the nominal value capacitor are consulted for all conditions, as some capacitor sizes (e.g. 0402) may not be suitable in the actual application. The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a temperature range of −55˚C to +125˚C, will only vary the capacitance to within ± 15%. The capacitor type X5R has a similar tolerance over a reduced temperature range of −55˚C to +85˚C. Many large value ceramic capacitors, larger than 1 µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by more than 50% as the temperature varies from 25˚C to 85˚C. Therefore X7R is recommended over Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25˚C. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 0.47 µF to 4.7 µF range. 33 www.national.com LP3906 Application Notes LP3906 www.DataSheet4U.com Application Notes ∼1.8kΩ) are determined by the capacitance of the bus. Too large of a resistor combined with a given bus capacitance will result in a rise time that would violate the max. rise time specification. A too small resistor will result in a contention with the pull-down transistor on either slave(s) or master. (Continued) Voltage peak-to-peak ripple due to ESR can be expressed as follows: VPP–ESR = 2 x IRIPPLE x RESR Because the VPP-C and VPP-ESR are out of phase, the rms value can be used to get an approximate value of the peakto-peak ripple: Operation without I2C Interface Operation of the LP3906 without the I2C interface is possible if the system can operate with default values for the LDO and Buck regulators. (Read below: Factory programmable options). The I2C-less system must rely on the correct default output values of the LDO and Buck converters. Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series resistance of the output capacitor (RESR). The RESR is frequency dependent as well as temperature dependent. The RESR should be calculated with the applicable switching frequency and ambient temperature. Capacitor Min Unit Value CLDO1 0.47 µF CLDO2 0.47 µF Description Factory Programmable Options The following options are EPROM programmed during final test of the LP3906. The system designer that needs specific options is advised to contact the local National Semiconductor sales office. Recommended Type LDO1 output capacitor Ceramic, 6.3V, X5R LDO2 output capacitor Ceramic, 6.3V, X5R CSW1 10.0 µF SW1 output capacitor Ceramic, 6.3V, X5R CSW2 10.0 µF SW2 output capacitor Ceramic, 6.3V, X5R Current value Enable delay for power on code 010 (see Control 1 register section) SW1 ramp speed 8 mV/µs SW2 ramp speed 8 mV/µs 2 The I C Chip ID address is offered as a metal mask option. The current value equals 0x60. I2C Pullup Resistor Both I2C_SDA and I2C_SCL terminals need to have pullup resistors connected to VINLDO12 or to the power supply of the I2C master. The values of the pull-up resistors (typ. www.national.com Factory programmable options 34 www.DataSheet4U.com shows the operational area that may exhibit this increased output ripple. If the application is expected to be operated in the area of concern AND have a static load current of the transition current value, the user can avoid the possible noise increase by invoking the components’ “Force PWM mode”. (Continued) MODE BOUNCE PFM-PWM transition at low load current. To improve efficiency at lower load currents LP3906 buck converters employ an automatically invoked PFM mode for the low load operation. The PFM mode operates with a much lower value quiescent current (IQ) than the PWM mode of operation that is used in the higher load currents. LP3906 Buck Converter VOUT vs VIN Operating Range during PFM-PWM-PPM Transition As shown in the datasheet section about SW operation, there is a DC voltage difference between the two modes of operation, with Vout PFM being typically 1.2% higher than Vout PWM. So there is a DC voltage level transition and some associated dynamic perturbation at the mode transition point. The transition between the two modes of operation has an associated hysterisis in the transition current value, That is, the transition point for increasing current (PFM to PWM) is at a higher value that the decreasing current (PWM to PFM). This hysterisis is to ensure that in the event that the load current values equals the PFM PWM transition value, the device will not make multiple transitions between modes; this reduces the noise at this load by eliminating multiple transitions between modes (also known as mode bounce). Under some conditions of high Vin and Low Vout the hystersis value is reduced and some amount of mode bounce can occur. Under these conditions, the regulator still maintains DC regulation, however the output ripple is more pronounced. Refer to the attached Vout vs Vin chart below that 20197865 35 www.national.com LP3906 Application Notes LP3906 www.DataSheet4U.com Application Notes Power dissipation of Buck1 PBuck1 = PIN – POUT = (Continued) High Vin-High Load Operation VoutBuck1* IoutBuck1 * (1 -η1) / η1 [V*A] η1 = efficiency of buck 1 Additional information is provided when the IC is operated at extremes of Vin and regulator loads. These are described in terms of the Junction temperature and, Buck output ripple management. Power dissipation of Buck2 PBuck2 = PIN – POUT = VoutBuck2 * IoutBuck2 * (1 - η2) / η2 [V*A] η2 = efficiency of buck 2 Junction Temperature The maximum junction temperature TJ-MAX-OP of 125oC of the IC package. η is the efficiency for the specific condition taken from efficiency graphs. The following equations demonstrate junction temperature determination, ambient temperature TA-MAX and Total chip power must be controlled to keep TJ below this maximum: Buck Output Ripple Management If Vin and ILoad increase, the output ripple associated with the Buck Regulators also increases. The figure below shows the safe operating area. To ensure operation in the area of concern it is recommended that the system designer circumvents the output ripple issues to install schottky diodes on the Bucks(s) that are expected to perform under these extreme corner conditions. TJ-MAX-OP = TA-MAX + (θJA) [ ˚C/ Watt] * (PD-MAX) [Watts] Total IC power dissipation PD-MAX is the sum of the individual power dissipation of the four regulators plus a minor amount for chip overhead. Chip overhead is Bias, TSD & LDO analog. PD-MAX = PLDO1 + PLD02 + PBUCK1 + PBUCK2 + (0.0001A * Vin) [Watts]. (Schottky diodes are recommended to reduce the output ripple if the system requirements include this shaded area of operation. Vin > 5.2 V and Iload > 1.24 A) Power dissipation of LDO1 PLDO1 = (VinLDO1- VoutLDO1) * IoutLDO1 [V*A] Power dissipation of LDO2 PLDO2 = (VinLDO2 - VoutLDO2) * IoutLDO2 [V*A] LP3906 Buck Converter VIN vs ILOAD Operating Ranges 20197864 www.national.com 36 www.DataSheet4U.com The LP3906 is a monolithic device with integrated power FETs. For that reason, it is important to pay special attention to the thermal impedance of the LLP package and to the PCB layout rules in order to maximize power dissipation of the LLP package. The LLP package is designed for enhanced thermal performance and features an exposed die attach pad at the bottom center of the package that creates a direct path to the PCB for maximum power dissipation. Compared to the traditional leaded packages where the die attach pad is embedded inside the molding compound, the LLP reduces one layer in the thermal path. The thermal advantage of the LLP package is fully realized only when the exposed die attach pad is soldered down to a thermal land on the PCB board with thermal vias planted 37 www.national.com LP3906 underneath the thermal land. Based on thermal analysis of the LLP package, the junction-to-ambient thermal resistance (θJA) can be improved by a factor of two when the die attach pad of the LLP package is soldered directly onto the PCB with thermal land and thermal vias, as opposed to an alternative with no direct soldering to a thermal land. Typical pitch and outer diameter for thermal vias are 1.27mm and 0.33mm respectively. Typical copper via barrel plating is 1oz, although thicker copper may be used to further improve thermal performance. The LP3906 die attach pad is connected to the substrate of the IC and therefore, the thermal land and vias on the PCB board need to be connected to ground (GND pin). For more information on board layout techniques, refer to Application Note AN–1187 “Leadless Lead frame Package (LLP).” on http://www.national.com This application note also discusses package handling, solder stencil and the assembly process. Thermal Performance of the LLP Package LP3906 Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C Compatible Interface www.DataSheet4U.com Physical Dimensions inches (millimeters) unless otherwise noted 5 X 4 X 0.8 mm 24-Pin LLP Package National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C2) and Banned Substances and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at: www.national.com/quality/green. Lead free products are RoHS compliant. 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