W83C43 KEYBOARD CONTROLLER GENERAL DESCRIPTION The W83C43 is a keyboard controller designed to provide the functions needed to interface a CPU to a keyboard or to a PS/2 mouse. The W83C43 can be used with IBM-compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. The controller will interrupt the system when data are placed in its output buffer. The keyboard and PS/2 mouse are required to acknowledge all data transmissions. No transmission should be sent to the keyboard or PS/2 mouse until acknowledge is received for the previous byte sent. This fast keyboard controller can improve the performance of IBM PC/AT 386 DX/SX and 486 DX/SX machines and their compatibles. Hardwire methodology is used in this controller instead of software implementation, as in the traditional 8042 keyboard BIOS. With full hardware implementation, this enables the keyboard controller to respond instantly to all commands sent from the keyboard and PS/2 mouse to the CPU BIOS. The keyboard controller enables popular programs such as AutoCAD, Microsoft Windows 3.1, NOVELL , and other programs to run much faster. FEATURES • Supports IBM PC/AT 386 DX/SX and 486 DX/SX system designs • Full hardwire design based on advanced VLSI CMOS technology • Supports PS/2 Mouse • 6 MHz to 12 MHz operating frequency • Supports AT mode and PS/2 mode for different hardware configurations • Automatically detects PS/2 mode or AT mode • Much faster than traditional keyboard controller • Packaged in 40-pin DIP or 44-pin PLCC -1- Publication Release Date: January 1996 Revision A2 W83C43 PIN CONFIGURATIONS 40-pin DIP T0 X1 X2 1 2 3 4 5 6 RESET Vcc CS GND D2 D3 D4 D5 P11 P10 NC 25 24 18 19 20 GND P13 P12 29 28 27 26 15 16 17 D6 D7 P16 (DISP) P15 (JUMP) P14 (RAM) 31 30 12 13 14 D0 D1 P25 (IEMP/MINT) P24 (KINT) P17 (KINH) 34 33 32 9 10 11 NC T1 P27 (KDAT) P26 (KCLK) 37 36 35 7 8 RD A2 WR Vcc 40 39 38 Vcc P23 (NC/MCLK) P22 (NC/MDAT) P21 (GA20) 23 22 21 P20 (RC) 44-pin PLCC CS GND RD A2 WR NC NC D0 D1 D2 D3 7 8 9 / R E V S c E X c T 2 X T 1 0 6 3 5 10 11 12 4 2 V N c T C c 1 P 2 7 P 2 6 P 2 5 1 44 43 42 41 40 39 38 37 36 35 34 33 13 14 15 32 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 D 4 D 5 -2- D D G N P P 6 7 N C 2 2 D 0 1 P 2 2 P 2 3 V c c P24 P17 P16 P15 P14 NC P13 P12 P11 P10 NC W83C43 PIN DESCRIPTION PIN NO. I/O NAME FUNCTION (40-pin DIP) (44-pin PLCC) 1 2 I T0 K/B Clock Input K/B Clock Input 2 3 I X1 Crystal Clock I/P Crystal Clock I/P 3 4 I X2 Crystal Clock I/P Crystal Clock I/P 4 5 I RESET Chip Reset Chip Reset 5 6 - VCC Optional +5V Power Supply Optional + 5V Power Supply 6 7 I CS Chip Select Chip Select 7 8 - GND Optional Ground Power Optional Ground Power 8 9 I RD I/O Read I/O Read 9 10 I A2 Connect to Address A2 Connect to Address A2 10 11 I WR I/O Write I/O Write Reserved Reserved Data Bus D0−D7 Data Bus D0−D7 AT MODE PS/2 MODE 11, 26 1, 12, 13, 23, 29, 34 - NC 12, 13, 14, 15, 16, 17, 18, 19 14, 15, 16, 17, 18, 19, 20, 21 I/O D0−D7 20 22 - GND Ground Power Supply Ground Power Supply 21 24 O P20 Bit 0 of Port2 Bit 0 of Port2 ( RC : System Reset) ( RC : System Reset) Bit 1 of Port2 Bit 1 of Port2 ( GA20 : GATE A20) ( GA20 : GATE A20) Bit 2 of Port2 Bit 2 of Port2 (NC: User-defined I/O) (MDAT: Mouse Data Output) Bit 3 of Port2 Bit 3 of Port2 (NC: User-defined I/O) (MCLK: Mouse Clock Output) Optional +5V Power Supply Optional + 5V Power Supply 22 23 24 25 25 26 27 28 O I/O I/O - P21 P22 P23 VCC -3- Publication Release Date: January 1996 Revision A2 W83C43 Pin Description, continued PIN NO. I/O (40-pin DIP) (44-pin PLCC) 27 30 NAME AT MODE I/O P10 31 I/O Bit 0 of Port1 (User-defined I/O) (K/B Data Input) Bit 1 of Port1 Bit 1 of Port1 (User-defined I/O) (Mouse Data Input) Bit 2 of Port2 Bit 2 of Port2 (User-defined I/O) (User-defined I/O) Bit 3 of Port1 Bit 3 of Port1 (User-defined I/O) (User-defined I/O) Bit 4 of Port1 Bit 4 of Port1 (RAM: RAM Jumper Select) (RAM: RAM Jumper Select) P15 Bit 5 of Port1 (JUMP: Jumper) Bit 5 of Port1 (JUMP: Jumper) P16 Bit 6 of Port1 (DISP: Display Select) Bit 6 of Port1 (DISP: Display Select) P17 Bit 7 of Port1 (KINH: K/B Inhibit Switch) Bit 7 of Port1 (KINH: K/B Inhibit Switch) P24 Bit 4 of Port2 Bit 4 of Port2 (KINT: K/B OBF O/P Interrupt) (KINT: K/B OBF O/P Interrupt) Bit 5 of Port2 Bit 5 of Port2 (IEMP: I/P Buffer Empty) (MINT: Mouse OBF O/P Interrupt) Bit 6 of Port2 Bit 6 of Port2 (KCLK: K/B Clock Output) (KCLK: K/B Clock Output) Bit 7 of Port2 Bit 7 of Port2 (KDAT: K/B Data Output) (KDAT: K/B Data Output) P11 PU* 29 30 31 32 33 35 I/O I/O I P12 P13 P14 PU* 32 36 I PU* 33 37 I PU* 34 38 I PU* 35 36 37 38 39 40 41 42 O O O O PS/2 MODE Bit 0 of Port1 PU* 28 FUNCTION P25 P26 P27 39 43 I T1 K/B Data Input Mouse Clock Input 40 44 - Vcc +5V Power Supply +5V Power Supply * Internal pull-up resistor -4- W83C43 BLOCK DIAGRAM T0 T1 x1 x2 HARDWIRE CONTROL & SELECT LOGIC WR RD CS A2 RESET R64 D0~D7 SCAN CODE ROM RECEIVE CONTROL DATA BUFFER REGISTER W60 W64 R60 TRANSMIT CONTRROL TRANSMIT REGISTER STATUS REGISTER STATUS BUFFER REGISTER INPUT & OUTPUT PORT INPUT BUFFER REGISTER INTERFACE OUTPUT BUFFER REGISTER OUTPUT PORT INTERFACE P10 P11 P12 P13 P14 (RAM) P15 (JUMP) P16 (DISP) P17 (KINH) P20 (RC) P21 (GA20) P22 (NC/MDAT) P23 (NC/MCLK) P24 (KINT) P25 (IEMP/MINT) P26 (KCLK) P27 (KDAT) ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNIT Ambient Operating Temperature -0 to + 85 °C Storage Temperature -65 to + 150 °C Supply Voltage to Ground Potential -0.3 to + 7.0 V Applied Input/Output Voltage -0.3 to + 7.0 V 50 mW Power Dissipation Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. -5- Publication Release Date: January 1996 Revision A2 W83C43 ELECTRICAL CHARACTERISTICS & CAPACITANCE (Ta = 0° C to + 70° C, VDD = +5V ± 5%) SYMBOL DESCRIPTION MIN. TYP. MAX. UNIT 4.75 5.0 5.25 V NOTE VDD Power Supply VIL Input Low Voltage (except RESET, T0, T1) 0.8 V VIL1 Input Low Voltage (RESET, T0, T1) 0.6 V VIH1 Input High Voltage (except RESET, T0, T1, P10, P11) 2.0 V VIH2 Input High Voltage (P10, P11) 3.0 V VIH3 Input High Voltage (T0, T1, RESET) 3.5 V VOH1 Output High Voltage (P10−P13, P20−P27) 2.4 V IOH = -2 mA VOH2 Output High Voltage (D0−D7) 2.4 V IOH = -4 mA VOL1 Output Low Voltage (P10−P13, P20−P27) 0.4 V IOL = 2 mA VOL2 Output Low Voltage (D0−D7) 0.4 V IOL = 4 mA RIP Min. I/P Resist 10K Ω IOFL O/P Leakage Current (D0−D7, High Z State) -10 10 µA IIH I/P Leakage Current -10 10 µA VDD = 5.5V, VIN = VDD IIL I/P Leakage Current (Except P10, P11, P14, P15, P16, P17) -10 10 µA VDD = 5.5V, VIN = VSS IIL1 I/P Leakage Current (P10, P11, P14, P15, P16, P17) -10 550 µA VDD = 5.5V, VIN = VSS CL O/P Load Capacity 15 50 pF STATUS REGISTER (AT MODE) The status register is an 8-bit read-only register at I/O address hex 64 that holds information about the status of the keyboard controller and interface. It may be read at any time. BIT 0 BIT FUNCTION DESCRIPTION Output Buffer Full 0: Output buffer empty 1: Output buffer full 1 Input Buffer Full 0: Input buffer empty 1: Input buffer full -6- W83C43 Status Register (AT Mode), continued BIT BIT FUNCTION DESCRIPTION 2 System Flag This bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller. It is set to 0 after a power-on reset 3 Command/data 0: Data byte 1: Command byte 4 Inhibit Switch 0: Keyboard is inhibited 1: Keyboard is not inhibited 5 Transmit Time-out 0: No transmit time-out error 1: Transmit time-out error 6 Receive Time-out 0: No receive time-out error 1: Receive time-out error 7 Parity Error 0: Odd parity (no error) 1: Even parity (error) OUTPUT BUFFER The output buffer is an 8-bit read-only register at I/O address hex 60. The keyboard controller uses the output buffer to send the scan code received from the keyboard and data bytes required by commands to the system. The output buffer should be read only when the output buffer full bit in the register is 1. ONPUT BUFFER The input buffer is an 8-bit write-only register at I/O address hex 60 or 64. Writing to address hex 60 sets a flag that indicates a data write; writing to address hex 64 sets a flag that indicates a command write. Data written to I/O address hex 60 are sent to the keyboard (unless the keyboard controller is expecting a data byte) following the controller's input buffer only if the input buffer full bit in the status register is set to 0. (A) Input Port Definition (AT Mode) BIT FUNCTION 0 Undefined 1 Undefined 2 Undefined 3 Undefined 4 RAM on System Board 0: Disable second 256 KB of system board RAM 1: Enable second 256 KB of system board RAM -7- Publication Release Date: January 1996 Revision A2 W83C43 (A) Input Port Definition (AT Mode), continued BIT FUNCTION 5 Manufacturing Jumper Installed 0: Manufacturing jumper 1: Jumper not installed 6 Display Type Switch 0: Primary display attached to color/graphics 1: Primary display attached to monochrome 7 Keyboard Inhibit Switch 0: Keyboard inhibited 1: Keyboard not inhibited (B) Output Port Definition (AT Mode) BIT FUNCTION 0 System Reset 1 Gate A20 2 Undefined 3 Undefined 4 Output Buffer Full 5 Input Buffer Empty 6 Keyboard Clock (Output) 7 Keyboard Data (Output) (C) Test-input Port Definition (AT Mode) BIT FUNCTION 0 Keyboard Clock (Input) 1 Keyboard Data (Input) Status Register (PS/2 Mode) BIT BIT FUNCTION DESCRIPTION 0 Output Buffer Full 0: Output buffer empty 1: Output buffer full 1 Input Buffer Full 0: Input buffer empty 1: Input buffer full 2 System Flag This bit may be set to 0 or 1 by writting to the system flag bit in the command byte of the keyboard controller. It is set to 0 after a power-on reset. -8- W83C43 Status Register (PS/2 Mode), continued BIT BIT FUNCTION DESCRIPTION 3 Command/Data 0: Data byte 1: Command byte 4 Inhinit Switch 0: Keyboard is inhibited 1: Keyboard is not inhibited 5 Auxiliary Device Output Buffer 0: Auxiliary device output buffer empty 1: Auxiliary device output buffer full 6 General Purpose Timeout 0: No time-out error 1: Time-out error 7 Parity Error 0: Odd parity 1: Even parity (error) Input Port Definition BIT FUNCTION 0 Keyboard Data Input 1 Mouse Data Input 2 Undefined 3 Undefined 4 RAM on System Board 0: Disable second 256 KB of system board RAM 1: Enable second 256 KB of system board RAM 5 Manufacturing Jumper 0: Manufacturing jumper 1: Jumper not installed 6 Display Type Switch 0: Primary display attached to color/graphics 1: Primary display attached to monochrome 7 Keyboard Input Switch 0: Keyboard inhibited 1: Keyboard not inhibited Output Port Definition BIT FUNCTION 0 System Reset 1 Gate A20 2 Mouse Data Output 3 Mouse Clock Output -9- Publication Release Date: January 1996 Revision A2 W83C43 Output Port Definition, continued BIT FUNCTION 4 Keyboard Output Buffer Full Interrupt 5 Mouse Output Buffer Full Interrupt 6 Keyboard Clock Output 7 Keyboard Data Output Test-input Port Definition BIT FUNCTION 0 Keyboard Clock Input 1 Mouse Clock Input Commands (I/O Address HEX 64) (AT Mode) COMMAND FUNCTION 20 Read Command Byte of Keyboard Controller 60 Write Command Byte of Keyboard Controller BIT BIT DEFINITION 7 Reserved 6 IBM PC Compatible Mode 5 IBM PC Mode 4 Disable Keyboard 3 Inhibit Override 2 System Flag 1 Reserved 0 Enable Output Buffer Full Interrupt AA Self-test AB Interface Test BIT BIT DEFINITION 00 No Error Detected 01 K/B Clock Line is Stuck Low 02 K/B Clock Line is Stuck High 03 K/B Data Line is Stuck Low 04 K/B Data Line is Stuck High AD Disable Keyboard Feature AE Enable Keyboard Interface - 10 - W83C43 Commands (I/O Address HEX 64) (AT Mode), continued COMMAND FUNCTION C0 Read Input Port D0 Read Output Port D1 Write Output Port E0 Read Test Inputs F0-FF Pulse Output Port Commands (I/O Address HEX 64) (PS/2 Mode) COMMAND FUNCTION 20 Read Command Byte of Keyboard Controller 60 Write Command Byte of Keyboard Controller BIT BIT DEFINITION 7 Reserved 6 IBM Keyboard Translate Mode 5 Disable Auxiliary Device 4 Disable Keyboard 3 Reserve 2 System Flag 1 Enable Auxiliary Interrupt 0 Enable Keyboard Interrupt A7 Disable Auxiliary Device Interface A8 Enable Auxiliary Device Interface A9 Interface Test BIT AA BIT DEFINITION 00 No Error Detected 01 Auxiliary Device "Clock" line is stuck low 02 Auxiliary Device "Clock" line is stuck high 03 Auxiliary Device "Data" line is stuck low 04 Auxiliary Device "Data" line is stuck low Self-test - 11 - Publication Release Date: January 1996 Revision A2 W83C43 Commands (I/O Address HEX 64) (PS/2 Mode), continued COMMAND AB FUNCTION Interface Test BIT DEFINITION BIT 00 No Error Detected 01 Keyboard "Clock" line is stuck low 02 Keyboard "Clock" line is stuck high 03 Keyboard "Data" line is stuck low 04 Keyboard "Data" line is stuck high AD Disable Keyboard Interface AE Enable Keyboard Interface C0 Read Input Port C1 Poll Input Port Low C2 Poll Input Port High D0 Read Output Port D1 Write Output Port D2 Write Keyboard Output Buffer D3 Write Auxiliary Device Output Buffer D4 Write to Auxiliary Device E0 Read Test Inputs F0-FF Pulse Output Port AC TIMING NO. DESCRIPTION MIN. MAX. UNIT T1 Address Setup Time from WRB 0 nS T2 Address Setup Time from RDB 0 nS T3 WRB Strobe Width 20 nS T4 RDB Strobe Width 20 nS T5 Address Hold Time from WRB 0 nS T6 Address Hold Time from RDB 0 nS T7 Data Setup Time 50 nS T8 Data Hold Time 0 nS T9 Gate Delay Time from WRB 10 - 12 - 30 nS W83C43 AC Timing, continued NO. DESCRIPTION MIN. MAX. UNIT 40 nS 20 nS 4 µS T10 RDB to Drive Data Delay T11 RDB to Floating Data Delay T12 Data Valid After Clock Falling (SEND) T13 K/B Clock Period 20 µS T14 K/B Clock Pulse Width 10 µS T15 Data Valid Before Clock Falling (RECEIVE) 4 µS T16 K/B ACK After Finish Receiving 20 µS T17 RC Fast Reset Pulse Delay (8 MHz) 2 T18 RC Pulse Width (8 MHz) 6 T19 Transmit Timeout T20 Data Valid Hold Time 0 T21 X1/X2 Period (6−12 MHz) 83 167 nS T22 Duration of CLK inactive 30 50 µS T23 Duration of CLK active 30 50 µS T24 Time from inactive CLK transition, used to time when the auxiliary device sample DATA 5 25 µS T25 Time of inhibit mode 100 300 µS T26 Time from rising edge of CLK to DATA transition 5 T28-5 µS T27 Duration of CLK inactive 30 50 µS T28 Duration of CLK active 30 50 µS T29 Time from DATA transition to falling edge of CLK 5 25 µS T30 Mode detect signal after P10 goes high Typical 1 mS T31 High pulse of mode detect signal Typical 220 µS T32 Low pulse of mode detect signal Typical 220 µS T33 Mode detect signal after RESET goes high Typical 1 mS T34 Time out of AT mode‘ s mode detect signal Typical 64 mS 0 3 µS 2 - 13 - µS mS µS Publication Release Date: January 1996 Revision A2 W83C43 TIMING WAVEFORMS Write Cycle Timing A2, CSB T1 T5 T3 WRB ACTIVE T8 T7 D0~D7 DATA IN T9 GA20 OUTPUT PORT T17 T18 FAST RESET PULSE RC FE COMMAND Read Cycle Timing A2,CSB AEN T2 RDB T6 T4 ACTIVE T10 D0-D7 T11 DATA OUT Send Data to K/B CLOCK (KCLK) T12 SERIAL DATA (KDAT) START T13 T14 D0 D1 D2 D3 D4 T19 - 14 - T16 D5 D6 D7 P STOP W83C43 Receive Data from K/B CLOCK (KCLK) T14 T15 SERIAL DATA (T1) START D0 D1 D2 T13 D3 D5 D4 D6 D7 P STOP T20 X1/X2 Clock CLOCK CLOCK T21 Send Data to Mouse MCLK T25 MDAT START Bit T22 D0 D1 T23 T24 D2 D3 D4 D5 D6 D7 P STOP Bit Receive Data from Mouse MCLK T29 T26 T27 T28 MDAT START D0 D1 D2 D3 D4 - 15 - D5 D6 D7 P STOP Bit Publication Release Date: January 1996 Revision A2 W83C43 PS2 Mode's Mode Detect (P10 released to high by keyboard before RESET goes high) RESET P27 T31 T33 P10 T32 PS2 Mode's Mode Detect (P10 released to high by keyboard after RESET goes high) RESET P27 T31 T30 P10 T32 AT Mode's Mode Detect (P10 internal pull high. As there is no external loop between P27 and P10 so P27 issues pulse until time out ) RESET T34 P27 T31 T33 P10 - 16 - T32 W83C43 TYPICAL APPLICATION CIRCUITS Application for AT Mode 2 3 RESETB SA2 8042CS# IORD# IOWR# D[0..7] 4 1 39 9 6 5 8 10 X1 Vcc Vcc 40 25 X2 P10 P11 P12 P13 P14 P15 P16 P17 27 28 29 30 31 32 33 34 RESET T0 T1 A2 CS Vcc RD WR 12 13 14 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7 7 20 GND GND P20 P21 P22 P23 P24/OB P25 P26/KCLK P27/KDAT NC NC RAM SELECT JUMPER MANUFACTURING MODE JUMPER 21 22 23 24 35 36 37 38 RCB GATE20 Vcc KEYBOARD INTERRUPT 11 26 7407 KB8042-DIP 1 2 1 2 7407 1 2 KEYBOARD CLOCK 74ALS04 - 17 - KEYBOARD DATA Publication Release Date: January 1996 Revision A2 W83C43 Application for PS/2 Mode KEYBOARD INTERRUPT PS/2 MOUSE INTERRUPT 2 3 RESETB SA2 8042CS# IORD# IOWR# D[0..7] X1 Vcc Vcc 40 25 X2 P10 P11 P12 P13 P14 P15 P16 P17 27 28 29 30 31 32 33 34 P20 P21 P22 P23 P24/OB P25 P26/KCLK P27/KDAT 21 22 23 24 35 36 37 38 NC NC 11 26 4 1 39 9 6 5 8 10 RESET T0 T1 A2 CS Vcc RD WR 12 13 14 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7 7 20 GND GND RAM SELECT JUMPER MANUFACTURING MODE JUMPER RCB GATE20 Vcc PS/2 MOUSE DATA 7406 1 2 7406 1 2 KB8042-DIP PS/2 MOUSE CLOCK Vcc 1 2 1 2 - 18 - 7406 KEYBOARD CLOCK 7406 KEYBOARD DATA W83C43 Driving from External Source OPTION 1 2 PCLK OPTION 2 PCLK 1 2 1 2 N.C. 3 X2 2 X1 3 X2 +5V OPTION 3 470 PCLK X1 1 2 1 7404 2 470 2 X1 7407 1 2 3 X2 7407 - 19 - Publication Release Date: January 1996 Revision A2 W83C43 PACKAGE DIMENSIONS 40-pin DIP Symbol A A1 A2 B B1 c D E E1 e1 L D 40 21 1 0.25 0.150 0.155 0.160 3.81 3.94 4.06 0.016 0.018 0.022 0.41 0.46 0.56 0.048 0.050 0.054 1.22 1.27 1.37 0.008 0.010 0.014 0.20 0.25 0.36 2.055 2.070 52.20 52.58 0.590 0.600 0.610 14.99 15.24 15.49 0.540 0.545 0.550 13.72 13.84 13.97 0.090 0.100 0.110 2.29 2.54 2.79 0.120 0.130 0.140 3.05 3.30 3.56 15 0 0.670 16.00 16.51 17.02 0 0.630 0.650 15 0.090 2.29 Notes: 20 1. Dimensions D Max & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include . mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. E S c 2 AA 1 A Base Plane Seating Plane L B 5.33 0.210 eA S 1 Dimension in mm Min. Nom. Max. 0.010 a E Dimension in inch Min. Nom. Max. e1 eA a B1 44-pin PLCC HD D 6 1 44 40 7 Symbol 39 E E E H 17 G 29 18 28 L c A A e b b1 Dimension in mm Min. Nom. Max. 0.185 4.70 0.020 0.51 0.145 0.150 0.155 3.68 3.81 3.94 0.026 0.028 0.032 0.66 0.71 0.81 0.016 0.018 0.022 0.41 0.46 0.56 0.008 0.010 0.014 0.20 0.25 0.36 0.648 0.653 0.658 16.46 16.59 16.71 0.648 0.653 0.658 16.46 16.59 16.71 0.050 BSC 1.27 0.590 0.610 0.630 14.99 15.49 16.00 0.680 0.690 0.700 17.27 17.53 17.78 0.680 0.690 0.700 17.27 17.53 17.78 0.090 0.100 0.110 2.29 2.54 0.004 1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec. 1 A y GD - 20 - BSC 0.590 0.610 0.630 14.99 15.49 16.00 Notes: 2 Seating Plane A A1 A2 b1 b c D E e GD GE HD HE L y Dimension in inch Min. Nom. Max. 2.79 0.10 W83C43 Headquarters Winbond Electronics (H.K.) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792646 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006 Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27516023 FAX: 852-27552064 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2730 Orchard Parkway, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. - 21 - Publication Release Date: January 1996 Revision A2