WOLFSON WM8310CGEB/RV

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WM8310
Processor Power Management Subsystem
DESCRIPTION
FEATURES
The WM8310 is an integrated power-management subsystem
which provides a cost-effective, flexible, single-chip solution for
power management. It is specifically targeted at the
requirements of a range of low-power portable consumer
products, but is suitable to any application with a multimedia
processor. The WM8310 is designed to operate as a system
PMIC supporting a variety of industry-standard processors and
accessories in a wide range of consumer multimedia
applications.
Power Management
The start-up behaviour and configuration is fully programmable
in an integrated OTP non-volatile memory. This highly flexible
solution helps reduce time-to-market, as changing application
requirements can be very easily accommodated in the OTP.
The InstantConfig™ interface enables an external EEPROM to
configure the WM8310.

2 x DC-DC synchronous buck converters
(0.6V - 1.8V, 1.2A, DVS)

1 x DC-DC synchronous buck converter (0.85V - 3.4V, 1A)

1 x DC-DC boost converter (up to 30V, up to 90mA)

1 x LDO regulator (0.9V - 3.3V, 300mA, 1)

2 x LDO regulators (0.9V - 3.3V, 200mA, 1)

3 x LDO regulators (0.9V - 3.3V, 100mA, 2)

2 x Low-noise LDO regulators (1.0V - 3.5V, 200mA, 1)

2 x Low-noise LDO regulators (1.0V - 3.5V, 150mA, 2)

1 x ‘Alive’ LDO regulator (0.8V – 1.55V, up to 25mA)
Backlight LED Current Sinks

2 x programmable constant current sinks, suitable for
multi-LED display backlight control
The WM8310 power management subsystem comprises of
four programmable DC-DC converters, eleven LDO regulators
(four of which are low-noise for supplying sensitive analogue
subsystems). The integrated OTP bootstrap circuitry controls
the start-up sequencing and voltages of the converters and
regulators as well as the sequencing of system clocks.
Battery Charger
WM8310 can be powered from a battery, a wall adaptor or
from a USB power source. An on-chip regulator provides
power for always-on PMIC functions such as register map and
the RTC. The device provides autonomous backup battery
switchover. A low-power LDO is included to support ‘Alive’
processor power domains external to the WM8310.

I C or SPI compatible primary control interface

Interrupt based feedback communication scheme

Watchdog timer and system reset control

Autonomous power sequencing and fault detection

Intelligent power path and power source selection
A linear on-chip battery charger supports trickle charging and
constant current / constant voltage charging of single-cell
lithium-ion / lithium-polymer batteries. The charge current,
termination voltage, and charger time-out are programmable.
WM8310 detects and handles battery fault conditions with a
minimum of system software involvement.

OTP memory bootstrap configuration function
A 12-bit Auxiliary ADC supports a wide range of applications
for internal as well as external analogue sampling, such as
voltage detection and temperature measurement.
WM8310 includes a crystal oscillator, an internal RC oscillator
and Frequency Locked Loop (FLL) to generate clock signals
for autonomous system start-up and processor clocking. A
Secure Real-time Clock (S-RTC) and alarm function is
included, capable of system wake-up from low-power modes.
A watchdog function is provided to ensure system integrity.
To maximise battery life, highly-granular power management
enables each function in the WM8310 subsystem to be
independently powered down through a control interface or
alternatively through register and OTP-configurable GPIOs.
The device offers a standby power consumption of <10uA,
making it particularly suitable for portable applications.
The WM8310 is supplied in a 7x7mm 169-ball BGA package,
ideal for use in portable systems. The WM8310 forms part of
the Wolfson series of audio and power management solutions.

Programmable single-cell lithium-ion / lithium-polymer
battery charger (1A max charge current)

Battery monitoring for temperature and voltage

Autonomous backup battery charging and switching
System Control
2
Additional Features

Auxiliary ADC for multi-function analogue measurement

128-bit pseudo-random unique ID

Secure Real-Time Clock with wake-up alarm

12 x configurable multi-function (GPIO) pins

Comprehensive clocking scheme: low-power 32kHz RTC
crystal oscillator, Frequency Locked Loop, GPIO clock
output and 4MHz RC clock for power management

System LED outputs indicating power state, battery
charger or fault status

Selectable USB current limiting up to 1.8A (in accordance
with USB Battery Charging specification Rev 1.1)
Package Options

7x7mm, 169-ball BGA package, 0.5mm ball pitch
APPLICATIONS

Portable Media Players

Portable Navigation Devices

Cellular Handsets

Electronic Books

Electronic Gaming Devices
WOLFSON MICROELECTRONICS plc
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Pre-Production, May 2012, Rev 3.1
Copyright 2012 Wolfson Microelectronics plc
WM8310
Pre-Production
LED1
LED2
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
System
Status
LED
Driver
ON
DC-DC1
Buck
0.6 to 1.8V
1.2A
DC-DC2
Buck
0.6 to 1.8V
1.2A
DC-DC3
Buck
0.85 to 3.4V
1A
DC-DC4
Boost
up to 30V,
up to 90mA
DVS
DVS
OTP NVM
Bootstrap
Config &
Unique ID
Register Map and
Application Processor
Interface
MultiFunction Pin
(GPIO)
Controller
DC4GND
DC4FB
DC4LX
DC4VDD
InstantConfig™
EEPROM
Interface
Primary Control
Interface
DC3GND
DC3FB
DC3LX
DC3VDD
DBGND
PROGVDD
Interrupt and
Reset Controller
DC2GND
DC2FB
DC2LX
DC2VDD
DBVDD
DC1GND
DC1FB
DC1LX
DC1VDD
SDA2
SCLK2
IRQ
RESET
CS
SDA1
SCLK1
SDOUT1
CIFMODE
BLOCK DIAGRAM
LDO 1 Standard LDO
0.9 to 3.3V 300mA
LDO 2 Standard LDO
0.9 to 3.3V 200mA
1 to 4MHz
RC
Oscillator
Power
Management
Control
LDO 3 Standard LDO
0.9 to 3.3V 200mA
WM8310
PM SubSystem
Monitoring
LED Sink
LDO 4 Standard LDO
0.9 to 3.3V 100mA
LDO 5 Standard LDO
0.9 to 3.3V 100mA
`
LDO 6 Standard LDO
0.9 to 3.3V 100mA
LDO 7 Analogue LDO
1.0 to 3.5V 200mA
AP Interface, GPIOs and PM Control
LDO 8 Analogue LDO
1.0 to 3.5V 200mA
LDO 9 Analogue LDO
1.0 to 3.5V 150mA
LDO 10 Analogue LDO
1.0 to 3.5V 150mA
AUXADCIN1
AUXADCIN2
AUXADCIN3
AUXADCIN4
USBVMON
SYSVMON
BATTVMON
NTCBIAS
NTCMON
XTO
XTI
XOSCGND
Aux
ADC
PVDD
ISINK1
ISINK2
ISINKGND
LDO1VDD
LDO1VOUT
LDO2VDD
LDO2VOUT
LDO3VDD
LDO3VOUT
LDO4VDD
LDO4VOUT
LDO5VDD
LDO5VOUT
LDO6VDD
LDO6VOUT
LDO7VDD
LDO7VOUT
LDO8VDD
LDO8VOUT
LDO9VDD
LDO9VOUT
LDO10VDD
LDO10VOUT
LDO 11 Alive LDO
0.8 to 1.55V 25mA
LDO11VOUT
LDO 12 Internal LDO
2.1V 2mA
LDO12VOUT
(Backup Battery Connection)
LDO 13 Internal LDO
2.5V 20mA
LDO13VOUT
Supply Voltage
and Battery
Monitor
SYSVDD
WALLVDD
32.768kHz
Oscillator
GND
Real-Time
Clock
Wake-Up
Timer
Battery
Charger
1A
Power Path
Management
Switching
Matrix
USBVDD
BATTVDD
BATTFETENA
WALLVDD
WALLFETENA
CLKOUT
FLL
CLKIN
Auxiliary Functions
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References
VREFC
IREFR
REFGND
Power Management
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TYPICAL APPLICATIONS
The WM8310 is designed as a system PMIC device that manages multiple power supply paths (wall
adapter, USB, battery) and generates configurable DC supplies to power processors and associated
peripherals within a system. The WM8310 provides three DC-DC synchronous buck (step-down)
converters and one DC-DC boost (step-up) converter. Eleven LDO regulators provide a high degree
of flexibility to provide power to multiple devices, with the capability to power-up and power-down
different circuits independently.
Two of the DC-DC buck converters incorporate Wolfson’s BuckWise™ technology specifically
designed to handle rapid changes in load current; programmable slew rate DVS is also provided, as
required by modern application processors. Selectable operating modes on all of the DC-DC
converters allow each converter to be optimally configured for light, heavy or transient load
conditions. Flexible operating configurations allow the converters to be tailored for minimum PCB
area, maximum performance, or for maximum efficiency. The analogue LDOs provide low-noise
outputs suitable for powering sensitive circuits such as RF / Wi-Fi / bluetooth radio applications.
The WM8310 powers up the converters and LDOs according to a programmable sequence. A
configurable ‘SLEEP’ state is also available, providing support for an alternate configuration, typically
for low-power / standby operation. The power control sequences and many other parameters can be
stored in an integrated user-configurable OTP (One-Time Programmable) memory or may be loaded
from an external memory. The WM8310 supports the programming and verification of the integrated
OTP memory.
The WM8310 provides power path management which seamlessly switches between wall adapter,
USB and battery power sources according to the prevailing conditions. A backup power source is also
supported in order to maintain the Real Time Clock (RTC) in the absence of any other supplies. The
WM8310 provides a configurable battery charger for the main battery, powered from either the wall
adapter or USB supplies. The backup power source is maintained using a constant-voltage output
from the WM8310.
Programmable GPIO pins may be configured as hardware inputs for general use or for selecting
different power management configurations. As outputs, the GPIOs can provide indications of the
device status, or may be used as control signals for other power management circuits. The WM8310
also provides two LED drivers, which can be controlled manually or configured as status indicators for
the OTP memory programmer, operating power state or battery charger.
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TABLE OF CONTENTS
DESCRIPTION ....................................................................................................... 1 FEATURES ............................................................................................................ 1 APPLICATIONS..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................ 2 TYPICAL APPLICATIONS .................................................................................... 3 TABLE OF CONTENTS ......................................................................................... 4 1 PIN CONFIGURATION.................................................................................. 8 2 ORDERING INFORMATION ......................................................................... 8 3 PIN DESCRIPTION ....................................................................................... 9 4 THERMAL CHARACTERISTICS ................................................................ 13 5 ABSOLUTE MAXIMUM RATINGS.............................................................. 14 6 RECOMMENDED OPERATING CONDITIONS .......................................... 14 7 ELECTRICAL CHARACTERISTICS ........................................................... 15 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 DC-DC SYNCHRONOUS BUCK CONVERTERS ............................................... 15 DC-DC STEP UP CONVERTER ......................................................................... 17 CURRENT SINKS................................................................................................ 17 LDO REGULATORS ............................................................................................ 18 RESET THRESHOLDS ....................................................................................... 22 REFERENCES .................................................................................................... 22 BATTERY CHARGER ......................................................................................... 23 USB POWER CONTROL .................................................................................... 24 GENERAL PURPOSE INPUTS / OUTPUTS (GPIO)........................................... 24 DIGITAL INTERFACES .................................................................................... 25 AUXILIARY ADC .............................................................................................. 25 SYSTEM STATUS LED DRIVERS ................................................................... 25 CLOCKING ....................................................................................................... 25 8 TYPICAL POWER CONSUMPTION ........................................................... 26 9 TYPICAL PERFORMANCE DATA.............................................................. 27 9.1 DC-DC CONVERTERS ....................................................................................... 27 9.2 LDO REGULATORS ............................................................................................ 27 10 SIGNAL TIMING REQUIREMENTS ............................................................ 28 10.1 CONTROL INTERFACE ................................................................................... 28 11 DEVICE DESCRIPTION .............................................................................. 30 11.1 GENERAL DESCRIPTION ............................................................................... 30 11.2 POWER STATES ............................................................................................. 30 11.3 POWER STATE CONTROL ............................................................................. 32 11.4 POWER STATE INTERRUPTS........................................................................ 37 11.5 POWER STATE GPIO INDICATION ................................................................ 37 11.6 ON PIN FUNCTION .......................................................................................... 38 11.7 RESET PIN FUNCTION ................................................................................... 39 12 CONTROL INTERFACE.............................................................................. 41 12.1 GENERAL DESCRIPTION ............................................................................... 41 12.2 2-WIRE (I2C) CONTROL MODE ...................................................................... 41 12.3 4-WIRE (SPI) CONTROL MODE ...................................................................... 44 12.4 REGISTER LOCKING ...................................................................................... 44 12.5 SOFTWARE RESET AND CHIP ID .................................................................. 45 12.6 SOFTWARE SCRATCH REGISTER ................................................................ 45 w
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CLOCKING AND OSCILLATOR CONTROL .............................................. 46 13.1 13.2 13.3 GENERAL DESCRIPTION ............................................................................... 46 CRYSTAL OSCILLATOR ................................................................................. 48 FREQUENCY LOCKED LOOP (FLL) ............................................................... 49 13.3.1 FLL AUTO MODE ................................................................................................................ 53 14 INSTANTCONFIG™ (ICE) AND OTP MEMORY CONTROL ...................... 54 14.1 GENERAL DESCRIPTION ............................................................................... 54 14.2 ICE AND OTP MEMORY DEFINITION ............................................................ 54 14.3 BOOTSTRAP (START-UP) FUNCTION ........................................................... 55 14.3.1 START-UP FROM OTP MEMORY ...................................................................................... 55 14.3.2 START-UP FROM ICE MEMORY (DEVELOPMENT MODE).............................................. 56 14.3.3 START-UP FROM DCRW REGISTER SETTINGS ............................................................. 56 14.3.4 EXTERNAL ICE MEMORY CONNECTION ......................................................................... 56 14.4 OTP / ICE MEMORY CONTROL ...................................................................... 57 14.4.1 ENTERING / EXITING THE PROGRAM STATE ................................................................. 58 14.4.2 OTP / ICE READ COMMAND .............................................................................................. 58 14.4.3 OTP WRITE COMMAND ..................................................................................................... 59 14.4.4 OTP VERIFY COMMAND .................................................................................................... 59 14.4.5 OTP FINALISE COMMAND ................................................................................................. 60 14.4.6 OTP CONTROL REGISTER ................................................................................................ 61 14.5 OTP / ICE INTERRUPTS ................................................................................. 62 14.6 DCRW MEMORY CONTENTS ......................................................................... 62 14.6.1 DCRW PAGE 0 .................................................................................................................... 63 14.6.2 DCRW PAGE 1 .................................................................................................................... 63 14.6.3 DCRW PAGE 2 .................................................................................................................... 63 14.6.4 DCRW PAGE 3 .................................................................................................................... 65 14.6.5 DCRW PAGE 4 .................................................................................................................... 66 15 POWER MANAGEMENT ............................................................................ 67 15.1 GENERAL DESCRIPTION ............................................................................... 67 15.2 DC-DC CONVERTER AND LDO REGULATOR CONTROL ............................ 67 15.3 TIMESLOT CONTROL AND HARDWARE ENABLE (GPIO) CONTROL ......... 68 15.4 OPERATING MODE CONTROL ...................................................................... 69 15.4.1 DC-DC SYNCHRONOUS BUCK CONVERTERS ................................................................ 69 15.4.2 DC-DC BOOST CONVERTERS .......................................................................................... 69 15.4.3 LDO REGULATORS ............................................................................................................ 69 15.5 OUTPUT VOLTAGE CONTROL ...................................................................... 70 15.5.1 DC-DC SYNCHRONOUS BUCK CONVERTERS ................................................................ 70 15.5.2 DC-DC BOOST CONVERTERS .......................................................................................... 70 15.5.3 LDO REGULATORS 1-10 .................................................................................................... 70 15.5.4 LDO REGULATOR 11 .......................................................................................................... 70 15.6 DC-DC SYNCHRONOUS BUCK CONVERTER CONTROL ............................ 71 15.7 DC-DC BOOST CONVERTER CONTROL....................................................... 72 15.8 LDO REGULATOR CONTROL ........................................................................ 72 15.9 HARDWARE CONTROL (GPIO) ...................................................................... 72 15.10 FAULT PROTECTION ...................................................................................... 73 15.11 MONITORING AND FAULT REPORTING ....................................................... 74 15.12 POWER MANAGEMENT REGISTER DEFINITIONS ...................................... 74 15.12.1 DC-DC CONVERTER AND LDO REGULATOR ENABLE ................................................... 74 15.12.2 DC-DC SYNCHRONOUS BUCK CONVERTER CONTROL ................................................ 75 15.12.3 DC-DC BOOST CONVERTER CONTROL .......................................................................... 80 15.12.4 LDO REGULATOR CONTROL ............................................................................................ 81 15.12.5 EXTERNAL POWER ENABLE (EPE) CONTROL ................................................................ 89 15.12.6 MONITORING AND FAULT REPORTING ........................................................................... 89 15.13 POWER MANAGEMENT INTERRUPTS ......................................................... 90 w
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15.14 POWER GOOD INDICATION .......................................................................... 91 15.15 DC-DC CONVERTER OPERATION ................................................................ 92 15.15.1 OVERVIEW .......................................................................................................................... 92 15.15.2 DC-DC SYNCHRONOUS BUCK CONVERTERS ................................................................ 93 15.15.3 DC-DC STEP UP CONVERTER .......................................................................................... 96 15.16 LDO REGULATOR OPERATION ..................................................................... 97 15.16.1 OVERVIEW .......................................................................................................................... 97 15.16.2 LDO REGULATORS ............................................................................................................ 97 16 CURRENT SINKS ....................................................................................... 99 16.1 GENERAL DESCRIPTION ............................................................................... 99 16.2 CURRENT SINK CONTROL ............................................................................ 99 16.2.1 ENABLING THE SINK CURRENT ....................................................................................... 99 16.2.2 PROGRAMMING THE SINK CURRENT ........................................................................... 100 16.2.3 ON/OFF RAMP TIMING ..................................................................................................... 101 16.3 CURRENT SINK INTERRUPTS ..................................................................... 102 16.4 LED DRIVER CONNECTIONS ....................................................................... 103 17 POWER SUPPLY CONTROL ................................................................... 104 17.1 GENERAL DESCRIPTION ............................................................................. 104 17.2 BATTERY POWERED OPERATION ............................................................. 106 17.3 WALL ADAPTOR POWERED OPERATION .................................................. 106 17.4 USB POWERED OPERATION ....................................................................... 107 17.5 POWER PATH MANAGEMENT INTERRUPTS ............................................. 108 17.6 BACKUP POWER .......................................................................................... 109 17.7 BATTERY CHARGER .................................................................................... 109 17.7.1 GENERAL DESCRIPTION ................................................................................................. 109 17.7.2 BATTERY CHARGER ENABLE ......................................................................................... 111 17.7.3 FAST CHARGING .............................................................................................................. 112 17.7.4 CHARGER TIMEOUT AND TERMINATION ...................................................................... 113 17.7.5 BATTERY CHARGE CURRENT MONITORING ................................................................ 115 17.7.6 BATTERY FAULT / OVERVOLTAGE CONDITIONS ......................................................... 116 17.7.7 BATTERY TEMPERATURE MONITORING ...................................................................... 116 17.7.8 BATTERY CHARGER INTERRUPTS ................................................................................ 118 17.7.9 BATTERY CHARGER STATUS ......................................................................................... 119 18 AUXILIARY ADC ....................................................................................... 120 18.1 GENERAL DESCRIPTION ............................................................................. 120 18.2 AUXADC CONTROL ...................................................................................... 120 18.3 AUXADC READBACK .................................................................................... 122 18.4 DIGITAL COMPARATORS............................................................................. 123 18.5 AUXADC INTERRUPTS ................................................................................. 125 19 RESERVED ............................................................................................... 125 20 REAL-TIME CLOCK (RTC) ....................................................................... 126 20.1 GENERAL DESCRIPTION ............................................................................. 126 20.2 RTC CONTROL .............................................................................................. 126 20.3 RTC INTERRUPTS ........................................................................................ 128 20.4 DIGITAL RIGHTS MANAGEMENT ................................................................ 129 20.5 BACKUP MODE CLOCKING OPTIONS ........................................................ 129 21 GENERAL PURPOSE INPUTS / OUTPUTS (GPIO) ................................ 130 21.1 GENERAL DESCRIPTION ............................................................................. 130 21.2 GPIO FUNCTIONS ......................................................................................... 130 21.3 CONFIGURING GPIO PINS ........................................................................... 132 21.4 GPIO INTERRUPTS ....................................................................................... 136 22 SYSTEM STATUS LED DRIVERS ............................................................ 137 w
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22.1 22.2 GENERAL DESCRIPTION ............................................................................. 137 LED DRIVER CONTROL................................................................................ 137 22.2.1 OTP PROGRAM STATUS ................................................................................................. 137 22.2.2 POWER STATE STATUS .................................................................................................. 138 22.2.3 CHARGER STATUS .......................................................................................................... 138 22.2.4 LED DRIVER MANUAL MODE .......................................................................................... 138 22.3 LED DRIVER CONNECTIONS ....................................................................... 140 23 INTERRUPT CONTROLLER .................................................................... 141 23.1 PRIMARY INTERRUPTS ............................................................................... 142 23.2 SECONDARY INTERRUPTS ......................................................................... 144 23.2.1 POWER STATE INTERRUPT ............................................................................................ 144 23.2.2 THERMAL INTERRUPTS .................................................................................................. 145 23.2.3 GPIO INTERRUPTS .......................................................................................................... 145 23.2.4 ON PIN INTERRUPTS ....................................................................................................... 145 23.2.5 WATCHDOG INTERRUPTS .............................................................................................. 146 23.2.6 RESERVED........................................................................................................................ 146 23.2.7 RESERVED........................................................................................................................ 146 23.2.8 AUXADC INTERRUPTS .................................................................................................... 146 23.2.9 POWER PATH MANAGEMENT INTERRUPTS ................................................................. 147 23.2.10 CURRENT SINK INTERRUPTS......................................................................................... 147 23.2.11 REAL TIME CLOCK INTERRUPTS ................................................................................... 148 23.2.12 OTP MEMORY INTERRUPTS ........................................................................................... 148 23.2.13 RESERVED........................................................................................................................ 149 23.2.14 BATTERY CHARGER INTERRUPTS ................................................................................ 149 23.2.15 HIGH CURRENT INTERRUPTS ........................................................................................ 150 23.2.16 UNDERVOLTAGE INTERRUPTS ...................................................................................... 151 24 RESETS AND SUPPLY VOLTAGE MONITORING .................................. 152 24.1 RESETS ......................................................................................................... 152 24.2 HARDWARE RESET ...................................................................................... 154 24.3 SOFTWARE RESET ...................................................................................... 154 24.4 SUPPLY VOLTAGE MONITORING ............................................................... 156 25 WATCHDOG TIMER ................................................................................. 158 26 TEMPERATURE SENSING ...................................................................... 160 27 VOLTAGE AND CURRENT REFERENCES ............................................. 161 27.1 VOLTAGE REFERENCE (VREF) ................................................................... 161 27.2 CURRENT REFERENCE (IREF) ................................................................... 161 28 REGISTER MAP OVERVIEW ................................................................... 162 29 REGISTER BITS BY ADDRESS ............................................................... 169 30 APPLICATIONS INFORMATION .............................................................. 277 30.1 TYPICAL CONNECTIONS ............................................................................. 277 30.2 VOLTAGE AND CURRENT REFERENCE COMPONENTS .......................... 278 30.3 DC-DC BUCK CONVERTER EXTERNAL COMPONENTS ........................... 278 30.4 DC-DC (STEP-UP) CONVERTER EXTERNAL COMPONENTS ................... 281 30.5 LDO REGULATOR EXTERNAL COMPONENTS .......................................... 283 30.6 BATTERY TEMPERATURE MONITORING COMPONENTS ........................ 284 30.7 PCB LAYOUT ................................................................................................. 287 31 PACKAGE DIAGRAM ............................................................................... 288 32 IMPORTANT NOTICE ............................................................................... 289 33 REVISION HISTORY ................................................................................. 290 w
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PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
A
BATTFETEN
A_N
PVDD1
DC3FB
DC3VDD
DC3LX
DC3GND
DC2VDD
DC2LX
DC2GND
DC1GND
DC1LX
DC1VDD
DC1FB
A
B
GND
GND
GND
DC3VDD
DC3LX
DC3GND
DC2VDD
DC2LX
DC2GND
DC1GND
DC1LX
DC1VDD
GND
B
C
LDO6VDD LDO6VOUT
GND
GND
DC3GND
DC2FB
GND
GND
GND
GND
GND
GND
IRQ_N
C
D
LDO5VDD LDO5VOUT
GND
PROGVDD
SDOUT1
GND
SDA1
SCLK1
DBVDD1
CS_N
RESET_N
GND
GPIO2
D
E
LDO4VDD LDO4VOUT
GND
GND
GPIO1
GPIO3
GPIO7
GPIO8
DBVDD1
LDO13VOU
T
DC4FB
GND
GPIO9
E
F
LDO10VDD
LDO10VOU
LDO9VOUT
T
GND
GND
GND
GPIO5
GPIO6
GPIO4
GND
GND
GND
DC4VDD
F
G
LDO8VDD
LDO9VDD LDO8VOUT
GND
AUXADCIN4
GND
GND
GND
GND
GPIO12
GPIO11
DC4LX
DC4GND
G
H
LDO7VDD LDO7VOUT
DNC
NTCBIAS
NTCMON
VREFC
GND
SDA2
DNC
DNC
DNC
GPIO10
DBGND
H
J
LDO3VDD LDO3VOUT
CIFMODE
WALLVDD
SYSVDD
SYSVDD
USBVMON
IREFR
AUXADCIN1
GND
LED1
DBVDD3
DNC
J
K
LDO2VDD LDO2VOUT
DBGND
WALLFETE
NA_N
SYSVDD
SYSVDD
USBVDD
BATTVMON
GND
GND
LED2
DNC
LDO11VOU
T
K
L
LDO1VDD LDO1VOUT
DBGND
CLKOUT
USBVDD
BATTVDD
SYSVDD
GND
GND
XTI
ISINKGND
ISINK2
REFGND
L
ISINK1
AUXADCIN2
M
XOSCGND AUXADCIN3
N
M
GND
DNC
DNC
DBGND
USBVDD
GND
GND
GND
SCLK2
XTO
ISINKGND
N
DNC
DNC
DBVDD2
CLKIN
SYSVMON
SYSVDD
BATTVDD
USBVDD
PVDD2
LDO12VOU
T
ON_N
7x7 BGA - TOP VIEW (WM8310)
2
ORDERING INFORMATION
ORDER CODE
OTP
TEMPERATURE
RANGE (TA)
PACKAGE
MOISTURE
SENSITIVITY
LEVEL
PEAK
SOLDERING
TEMPERATURE
WM8310CGEB/V
Unprogrammed
-40C to +85C
169-ball (7 x 7mm)
MSL3
260C
MSL3
260C
MSL3
260C
(Pb-free)
WM8310CGEB/RV
Unprogrammed
-40C to +85C
169-ball (7 x 7mm)
(Pb-free, tape and reel)
WM8310CGEBxxx/RV*
Custom
-40C to +85C
169-ball (7 x 7mm)
(Pb-free, tape and reel)
**
Note:
Reel quantity = 2200
* xxx = Unique OTP part number
* Custom OTP minimum order quantity 22,000
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PIN DESCRIPTION
Notes:
1.
Pins are sorted by functional groups.
2.
The power domain associated with each pin is noted; VPMIC is the domain powered by LDO12 for the ‘always-on’
functions internal to the WM8310.
3.
Note that an external level-shifter may be required when interfacing between different power domains.
PIN
NAME
TYPE
POWER
DOMAIN
USBVMON
Analogue Input
USBVDD
DESCRIPTION
Auxiliary ADC
J7
USBVDD Supply Voltage Monitor
N5
SYSVMON
Analogue Input
SYSVDD
SYSVDD Supply Voltage Monitor
K8
BATTVMON
Analogue Input
BATTVDD
BATTVDD Supply Voltage Monitor
J9
AUXADCIN1
Analogue
Input/Output
M13
AUXADCIN2
Analogue Input
N13
AUXADCIN3
Analogue Input
G5
AUXADCIN4
Analogue Input
SYSVDD
Auxiliary Analogue Input 1 /
Battery Charge Current Monitor Output
Auxiliary Analogue Input 2
Auxiliary Analogue Input 3
DBVDD
Auxiliary Analogue Input 4
Clocking and Real Time Clock
M10
XTO
Analogue Output
L10
XTI
Analogue Input
N12
XOSCGND
Supply
L4
CLKOUT
Digital Output
N4
CLKIN
Digital Input
VPMIC
Crystal Drive Output
Crystal Drive Input or 32.768kHz CMOS Clock Input
Crystal Oscillator Ground
CMOS Clock Output
DBVDD
Configurable Open Drain / CMOS mode. (External
4.7kΩ pull-up recommended in Open Drain mode.)
CMOS FLL Clock Input
General Purpose Input / Output
E5
GPIO1
D13
GPIO2
Digital I/O
E6
GPIO3
Digital I/O
F9
GPIO4
Digital I/O
F7
GPIO5
Digital I/O
F8
GPIO6
Digital I/O
E7
GPIO7
Digital I/O
E8
GPIO8
Digital I/O
E13
GPIO9
Digital I/O
H12
GPIO10
Digital I/O
G11
GPIO11
Digital I/O
G10
GPIO12
Digital I/O
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GPIO Pin 1
Digital I/O
Selectable pull-up/pull-down.
DBVDD or
VPMIC
GPIO Pin 2
Selectable pull-up/pull-down.
GPIO Pin 3
Selectable pull-up/pull-down.
GPIO Pin 4
Selectable pull-up/pull-down.
DBVDD or
SYSVDD
GPIO Pin 5
Selectable pull-up/pull-down.
GPIO Pin 6
Selectable pull-up/pull-down.
GPIO Pin 7
Selectable pull-up/pull-down.
DBVDD or
VPMIC
GPIO Pin 8
Selectable pull-up/pull-down.
GPIO Pin 9
Selectable pull-up/pull-down.
GPIO Pin 10
Selectable pull-up/pull-down.
DBVDD or
SYSVDD
GPIO Pin 11
Selectable pull-up/pull-down.
GPIO Pin 12
Selectable pull-up/pull-down.
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PIN
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NAME
TYPE
POWER
DOMAIN
DESCRIPTION
Processor Interface and IC Control
N11
¯¯¯
ON
Digital Input
VPMIC
D11
RESET
¯¯¯¯¯¯
Digital I/O
DBVDD
C13
IRQ
¯¯¯
Digital Output
DBVDD
ON Request Pin
(Internal pull-up)
System Reset Input and Open Drain Output.
(Internal pull-up)
PMIC Interrupt Flag Output.
Configurable Open Drain / CMOS mode.
(Internal pull-up in Open Drain mode.)
Primary Control Interface Mode Select:
J3
CIFMODE
Digital Input
DBVDD
2
0 = I C Compatible Control Interface Mode
1 = SPI Compatible Control Interface Mode
SPI Compatible Control
Interface Mode
2
I C Compatible Control
Interface Mode
Control Interface Serial
Data Out.
D5
SDOUT1
Digital Output
D8
SCLK1
Digital Input
Open Drain output;
external 4.7kΩ pull-up
recommended.
No Function
Control Interface Serial
Clock
Control Interface Serial
Clock
DBVDD
D7
SDA1
Control Interface Serial
Data In
Digital I/O
Control Interface Serial
Data Input and Open
Drain Output.
External 4.7kΩ pull-up
recommended.
(Output can extend above
DBVDD domain.)
2
D10
M9
CS
¯¯
SCLK2
Control Interface Chip
Select
Digital Input
I C Address Select:
0 = 68h
1 = 6Ch
Control Interface Serial Clock for external
InstantConfig™ EEPROM (ICE)
Digital I/O
VPMIC
(Internal pull-down)
Control Interface Serial Data to/from external
InstantConfig™ EEPROM (ICE
H8
SDA2
Digital I/O
D9, E9
DBVDD1
Supply
Digital Buffer Supply
N3
DBVDD2
Supply
Digital Buffer Supply
J12
DBVDD3
Supply
Digital Buffer Supply
H13, K3,
L3, M4
DBGND
Supply
Digital Buffer Ground
PROGVDD
Supply
High-voltage input for OTP programming.
(Internal pull-down)
OTP Memory
D4
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PIN
NAME
TYPE
POWER
DOMAIN
DESCRIPTION
DC-DC Converters and LDO Regulators
B1, B2,
B3, B13,
C3, C4,
C7, C8,
C9, C10,
C11, C12,
D3, D6,
D12, E3,
E4, E12,
F4, F5, F6,
F10, F11,
F12, G4,
G6, G7,
G8, G9,
H7, J10,
K9, K10,
L8, L9,
M1, M6,
M7, M8
GND
Supply
Ground
A2
PVDD1
Supply
N9
PVDD2
Supply
A10, B10
DC1GND
Supply
DC-DC1 Power Ground
DC-DC1 Feedback Pin
Internal VDD supply; Connect to SYSVDD
A13
DC1FB
Analogue Input
A11, B11
DC1LX
Analogue I/O
A12, B12
DC1VDD
Supply
DC-DC1 Power Input (connect to SYSVDD supply)
A9, B9
DC2GND
Supply
DC-DC2 Power Ground
DC1VDD
DC-DC1 Inductor Connection
DC-DC2 Feedback Pin
C6
DC2FB
Analogue Input
A8, B8
DC2LX
Analogue I/O
A7, B7
DC2VDD
Supply
DC-DC2 Power Input (connect to SYSVDD supply)
A6, B6, C5
DC3GND
Supply
DC-DC3 Power Ground
DC2VDD
DC-DC2 Inductor Connection
DC-DC3 Feedback Pin
A3
DC3FB
Analogue Input
A5, B5
DC3LX
Analogue I/O
A4, B4
DC3VDD
Supply
DC-DC3 Power Input (connect to SYSVDD supply)
G13
DC4GND
Supply
DC-DC4 Power Ground
E11
DC4FB
Analogue Input
G12
DC4LX
Analogue I/O
F13
DC4VDD
Supply
L1
LDO1VDD
Supply
L2
LDO1VOUT
Analogue Output
K1
LDO2VDD
Supply
K2
LDO2VOUT
Analogue Output
J1
LDO3VDD
Supply
J2
LDO3VOUT
Analogue Output
E1
LDO4VDD
Supply
E2
LDO4VOUT
Analogue Output
D1
LDO5VDD
Supply
D2
LDO5VOUT
Analogue Output
C1
LDO6VDD
Supply
C2
LDO6VOUT
Analogue Output
H1
LDO7VDD
Supply
H2
LDO7VOUT
Analogue Output
G1
LDO8VDD
Supply
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DC3VDD
DC4VDD
DC-DC3 Inductor Connection
DC-DC4 Feedback Connection
DC-DC4 Inductor Connection
DC-DC4 Power Input (connect to SYSVDD supply)
LDO1 Power Input (must be ≤ SYSVDD supply)
LDO1VDD
LDO1 Power Output
LDO2 Power Input (must be ≤ SYSVDD supply)
LDO2VDD
LDO2 Power Output
LDO3 Power Input (must be ≤ SYSVDD supply)
LDO3VDD
LDO3 Power Output
LDO4 Power Input (must be ≤ SYSVDD supply)
LDO4VDD
LDO4 Power Output
LDO5 Power Input (must be ≤ SYSVDD supply)
LDO5VDD
LDO5 Power Output
LDO6 Power Input (must be ≤ SYSVDD supply)
LDO6VDD
LDO6 Power Output
LDO7 Power Input
LDO7VDD
LDO7 Power Output
LDO8 Power Input
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PIN
NAME
TYPE
POWER
DOMAIN
G3
LDO8VOUT
Analogue Output
LDO8VDD
G2
LDO9VDD
Supply
F3
LDO9VOUT
Analogue Output
F1
LDO10VDD
Supply
F2
LDO10VOUT
Analogue Output
LDO10VDD
K13
LDO11VOUT
Analogue Output
PVDD
DESCRIPTION
LDO8 Power Output
LDO9 Power Input
LDO9VDD
LDO9 Power Output
LDO10 Power Input
N10
LDO12VOUT
Analogue I/O
PVDD
E10
LDO13VOUT
Analogue I/O
PVDD
M12
ISINK1
Analogue Output
L12
ISINK2
Analogue Output
L11, M11
ISINKGND
Supply
LDO10 Power Output
LDO11 (Alive) Power Output
LDO12 (Internal VPMIC) Output;
Backup battery supply input / output
LDO13 (Internal INTVDD) Output; not for general use
Current Sinks
SYSVDD
LED String Current Sink 1
LED String Current Sink 2
LED String Current Sink Ground
Voltage and Current References
Voltage Reference capacitor connection point
H6
VREFC
Analogue I/O
J8
IREFR
Analogue I/O
L13
REFGND
Supply
Reference Ground
VPMIC
Current Reference resistor connection point
Power Path Management
J5, J6 K5,
K6, L7, N6
SYSVDD
Supply
System VDD Supply
K7, L5,
M5, N8
USBVDD
Supply
USB VDD Supply
L6, N7
BATTVDD
Supply
Primary Battery Supply
A1
¯¯¯¯¯¯¯¯¯¯¯¯
BATTFETENA
Digital Output
J4
WALLVDD
Supply
K4
WALLFETENA
¯¯¯¯¯¯¯¯¯¯¯¯
Digital Output
H4
NTCBIAS
Analogue Output
H5
NTCMON
Analogue Input
PVDD
External Battery FET Driver
Wall VDD Supply/Sense
highest VDD
supply
VPMIC
External Wall FET Driver.
Power domain is the highest out of WALLVDD,
USBVDD or BATTVDD.
Battery NTC Temperature Monitor Supply
Battery NTC Temperature Monitor Voltage Sense Input
Status LED Drivers
J11
LED1
Digital Output
K11
LED2
Digital Output
SYSVDD
Status LED Driver 1. Open Drain Output
Status LED Driver 2. Open Drain Output
Do Not Connect
H3, H9,
H10, H11,
J13, K12,
M2, M3,
N1, N2
DNC
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Do Not Connect
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4
THERMAL CHARACTERISTICS
Thermal analysis must be performed in the intended application to prevent the WM8310 from
exceeding maximum junction temperature. Several contributing factors affect thermal performance
most notably the physical properties of the mechanical enclosure, location of the device on the PCB
in relation to surrounding components and the number of PCB layers. Connecting the GND balls
through thermal vias and into a large ground plane will aid heat extraction.
Three main heat transfer paths exist to surrounding air:
-
Package top to air (convection and radiation).
-
Package bottom to PCB (convection and radiation).
-
Package leads to PCB (conduction).
(Note that radiation is not normally significant at the moderate temperatures experienced in typical
applications.)
The temperature rise TR is given by TR = PD * ӨJA
-
PD is the power dissipated by the device.
-
ӨJA is the thermal resistance from the junction of the die to the ambient temperature
and is therefore a measure of heat transfer from the die to surrounding air.
-
For WM8310, ӨJA = 45C/W
-
The quoted ӨJA is based on testing to the EIA/JEDEC-51-2 test environment (ie. 1ft
box, still air, with specific PCB stack-up and tracking rules). Note that this is not
guaranteed to reflect all typical end applications.
3
The junction temperature TJ is given by TJ = TA + TR
-
TA, is the ambient temperature.
The worst case conditions are when the WM8310 is operating in a high ambient temperature, and
under conditions which cause high power dissipation, such as the DC-DC converters operating at low
supply voltage, high duty cycle and high output current. Under such conditions, it is possible that the
heat dissipated could cause the maximum junction temperature of the device to be exceeded. Care
must be taken to avoid this situation. An example calculation of the junction temperature is given
below.
-
PD = 500mW (example figure)
-
ӨJA = 45°C/W
-
TR = PD * ӨJA = 22.5°C
-
TA = 85°C (example figure)
-
TJ = TA +TR = 107.5°C
The minimum and maximum operating junction temperatures for the WM8310 are quoted in
Section 5. The maximum junction temperature is 125°C. Therefore, the junction temperature in the
above example is within the operating limits of the WM8310.
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5
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or
beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to
damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of
this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
The WM8310 has been classified as MSL3.
CONDITION
MIN
MAX
OTP Programming Supply (PROGVDD)
-0.3V
7.0V
BATTVDD, WALLVDD and USBVDD supplies
-0.3V
7.0V
Input voltage for LDO regulators
-0.3V
7.0V
Input voltage for DC-DC converters
-0.3V
7.0V
Digital buffer supply (DBVDD1, DBVDD2, DBVDD3)
-0.3V
4.5V
Voltage range for digital inputs
-0.3V
DBVDD + 0.3V
Operating Temperature Range, TA
-40C
+85C
Junction Temperature, TJ
-40C
+125C
Thermal Impedance Junction to Ambient, θJA
45C/W
o
Storage temperature prior to soldering
30 C max / 60% RH max
Storage temperature after soldering
-65C
+150C
Soldering temperature (10 seconds)
+260C
Note: These ratings assume that all ground pins are at 0V.
6
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Wall Input power source
WALLVDD
4.3
5.5
V
Battery Input power source
BATTVDD
2.7
5.5
V
USB Input power source
USBVDD
4.3
5.5
V
Digital buffer supply
DBVDD1, DBVDD2, DBVDD3
1.71
3.6
V
PROGVDD
6.25
OTP Programming Supply
(see note)
Ground
LDO12VOUT
GND, DC1GND, DC2GND,
DC3GND, DC4GND, DBGND,
XOSCGND, REFGND
6.5
6.75
V
3.3
V
0
V
Note:
The OTP Programming Supply PROGVDD should only be present when programming the OTP. At other times, this pin should be
left unconnected. The LDO12VOUT must be overdriven by an external supply when programming the OTP. At other times, the
voltage at this pin is driven by the internal circuits of the WM8310.
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7
ELECTRICAL CHARACTERISTICS
7.1
DC-DC SYNCHRONOUS BUCK CONVERTERS
DC-DC1 and DC-DC2
(1)
Unless otherwise noted: VIN = 3.8V, VOUT = 1.2V, MODE = FCCM , TJ = -40°C to +125°C; typical values are at TJ = 25°C
PARAMETER
Input Voltage
SYMBOL
VIN
Programmable
Output Voltage
VOUT
VOUT Step Size
VOUT_STEP
VOUT Accuracy
VOUT_ACC
IOUT
IP_LIM
Current Limit
Quiescent
Current
Shutdown
Current
ISD
P-channel
RDSP
On Resistance
N-channel
RDSN
On Resistance
Switching
Frequency
FSW
MAX
UNIT
5.5
V
FSW = 2MHz
0.6
1.8
V
FSW = 4MHz
0.6
1.4
12.5
VIN = 2.7V to 5.5V, IOUT = 0mA to 1200mA
-3
0.9V ≤ VOUT < 1.3V
80
1.3V ≤ VOUT ≤ 1.8V
100
(1)
mV
3
50
100
mV
FCCM and Auto (CCM/DCM with PS )
Modes
0
1200
Hysteretic Mode
0
150
LDO Mode
0
FSW = 2MHz
%
mV
(2)
mA
10
1800
FSW = 4MHz
IQ
TYP
2.7
0.6V ≤ VOUT ≤ 1.8V
Overvoltage
margin
P-channel
MIN
0.6V ≤ VOUT < 0.9V
Undervoltage
margin
Output Current
TEST CONDITIONS
VIN = SYSVDD
mA
2000
(1)
IOUT = 0mA, FCCM and Auto (CCM/DCM with
(2)
PS ) Modes (excluding switching losses)
500
IOUT = 0mA, Hysteretic Mode
70
IOUT = 0mA, LDO Mode
25
DCm_ENA = 0
0.01
VIN = VGS = 3.8V, IDCmLX = 100mA
140
VIN = VGS = 3.8V, IDCmLX = -100mA
130
DCm_FREQ = 01
2
DCm_FREQ = 11
4
A
A
m
m
MHz
Notes:
1. Forced Continuous Conduction Mode
2. Continuous / Discontinuous Conduction with Pulse-Skipping Mode
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DC-DC3
(1)
Unless otherwise noted: VIN = 3.8V, VOUT = 1.2V, MODE = FCCM , TJ = -40°C to +125°C; typical values are at TJ = 25°C
PARAMETER
Input Voltage
SYMBOL
VIN
Programmable
Output Voltage
VOUT
VOUT Step Size
VOUT_STEP
VOUT Accuracy
VOUT_ACC
P-channel
MIN
IOUT
0.85
(1)
3.4
V
-4
mV
4
%
50
mV
0
1000
Hysteretic Mode, DC3_STNBY_LIM=01
0
200
LDO Mode
0
10
1600
(1)
IOUT = 0mA, FCCM and Auto (CCM/DCM with
(2)
PS ) Modes (excluding switching losses)
330
IOUT = 0mA, Hysteretic Mode
110
IOUT = 0mA, LDO Mode
30
DC3_ENA = 0
ISD
P-channel
RDSP
VIN = VGS = 3.8V, IDC3LX = 100mA
RDSN
VIN = VGS = 3.8V, IDC3LX = -100mA
On Resistance
On Resistance
Switching
Frequency
V
FCCM and Auto (CCM/DCM with PS )
Modes
Shutdown
Current
N-channel
UNIT
5.5
(2)
IP_LIM
IQ
(4)
MAX
25
VIN = 2.7V to 5.5V, IOUT = 0mA to 1000mA
Current Limit
Quiescent
Current
TYP
2.7
0.85V ≤ VOUT ≤ 3.4V
Undervoltage
margin
Output Current
TEST CONDITIONS
VIN = SYSVDD
FSW
0.01
165
155
2
mA
(3)
mA
A
A
m
m
MHz
Notes:
1.
Forced Continuous Conduction Mode
2.
Continuous / Discontinuous Conduction with Pulse-Skipping Mode
3.
The maximum output current in Hysteretic Mode can be adjusted using the DCm_STNBY_LIM registers
4.
In FCCM mode, the minimum VOUT is 1.2V
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7.2
DC-DC STEP UP CONVERTER
DC-DC4
Unless otherwise noted: VIN = 3.8V, TJ = -40°C to +125°C; typical values are at TJ = 25°C
PARAMETER
SYMBOL
Input Voltage
VIN
Output Voltage
VOUT
Load Current
ILOAD
TEST CONDITIONS
MAX
UNIT
2.7
5.5
V
6.5
30
V
VOUT ≤ 8V
0
90
mA
VOUT = 6.5V to 20V
0
40
VOUT = 20V to 30V
0
25
VIN = SYSVDD
Quiescent
Current
IQ
DC4_ENA=1
Shutdown
Current
ISD
DC4_ENA=0
N-channel On
Resistance
Regulated
feedback
voltage
MIN
TYP
0.1
RDSN
1
A
m
150
VISINKn
mV
500
Out of regulation
level
VISINKn
440
Overvoltage
detection
VDC4FB
500
Switching
frequency
FSW
N-channel
Current limit
IN_LIM
7.3
A
330
mV
mV
MHz
1
mA
800
CURRENT SINKS
Unless otherwise noted: TJ = -40°C to +125°C; Typical values are at TJ = +25ºC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
Sink Current
IISINKn
0.3 <= VISINKn <=
SYSVDD
Current Accuracy
IISINKn
IISINKn =12mA, VISINKn
= 0.5V
TBD
Current matching
IISINKn
IISINKn =12mA, VISINKn
= 0.5V
TBD
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2
MAX
UNIT
28000
A
V
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Pre-Production
LDO REGULATORS
LDO1
Unless otherwise noted: VIN = 3.8V, VOUT = 1.8V, TJ = -40°C to +125°C; Typical values are at TJ = +25ºC
PARAMETER
Input Voltage
SYMBOL
VIN
Programmable
Output Voltage
VOUT
VOUT Step Size
VOUT_STEP
Output Current
IOUT
TEST CONDITIONS
VIN ≤ SYSVDD
MIN
TYP
MAX
UNIT
1.5
5.5
V
0.9
3.3
V
VOUT = 0.9V to 1.6V
50
VOUT = 1.7V to 3.3V
100
mV
Normal mode
0
300
Low power mode, LDOn_LP_MODE=0
0
50
Low power mode, LDOn_LP_MODE=1
0
20
-3
+3
VOUT Accuracy
VOUT_ACC
ILOAD = 1mA
Line Regulation
VOUT LINE
VIN = (VOUT + 0.5) to 5.5V, ILOAD = 150mA
Note that VIN must be >= 1.5V
mA
%
0.1
%/V
Load Regulation
VOUT LOAD
ILOAD =1mA to 300mA
0.015
%/mA
Dropout Voltage
VIN - VOUT
ILOAD =150mA, VOUT > 2.7V
250
mV
ILOAD =150mA, VOUT 1.8V to 2.7V
300
ILOAD =150mA, VOUT < 1.8V
500
Undervoltage
level
Quiescent
Current
VOUT
IQ
VOUT Falling
88
%
Normal mode, no load
30
A
Low power mode, LDOn_LP_MODE=0, no load
10
Low power mode, LDOn_LP_MODE=1, no load
ILOAD = 1mA to 300mA
Power Supply
Rejection Ratio
On Resistance
(Switch mode)
Current Limit
(Switch mode)
Start-up time
Shutdown time
PSRR
RDSON
5
IQ (no load) + 1% of load
ILOAD = 150mA, <= 1kHz
53
ILOAD = 150mA, 10kHz
53
ILOAD = 150mA, 100kHz
32
VIN = 1.5V, ILOAD = 100mA
1.5
VIN = 1.8V, ILOAD = 100mA
1.2
VIN = 2.5V, ILOAD = 100mA
0.85
VIN = 3.3V, ILOAD = 100mA
0.7
VOUT = 0V
600
tstart_up
No load, Output cap 2.2 µF, 90% of VOUT
10
tshut_down
No load, Output cap 2.2 µF, 10% of VOUT
ICL
dB

mA
s
10
ms
LDO2, LDO3
Unless otherwise noted: VIN = 3.8V, VOUT = 1.8V, TJ = -40°C to +125°C; Typical values are at TJ = +25ºC
PARAMETER
Input Voltage
SYMBOL
VIN
Programmable
Output Voltage
VOUT
VOUT Step Size
VOUT_STEP
Output Current
IOUT
TEST CONDITIONS
VIN ≤ SYSVDD
MIN
MAX
UNIT
1.5
TYP
5.5
V
0.9
3.3
V
VOUT = 0.9V to 1.6V
50
VOUT = 1.7V to 3.3V
100
mV
Normal mode
0
200
Low power mode, LDOn_LP_MODE=0
0
50
Low power mode, LDOn_LP_MODE=1
0
20
VOUT Accuracy
VOUT_ACC
ILOAD = 1mA
-3
+3
Line Regulation
VOUT LINE
VIN = (VOUT + 0.5) to 5.5V, ILOAD = 100mA
Note that VIN must be >= 1.5V
Load Regulation
VOUT LOAD
w
ILOAD =1mA to 200mA
mA
%
0.1
%/V
0.015
%/mA
PP, May 2012, Rev 3.1
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Pre-Production
PARAMETER
SYMBOL
Dropout Voltage
VIN - VOUT
Undervoltage
level
Quiescent
Current
VOUT
IQ
TEST CONDITIONS
MIN
200
ILOAD =100mA, VOUT 1.8V to 2.7V
250
ILOAD =100mA, VOUT < 1.8V
400
VOUT Falling
On Resistance
(Switch mode)
Current Limit
(Switch mode)
Start-up time
Shutdown time
RDSON
UNIT
mV
%
Normal mode, no load
30
A
Low power mode, LDOn_LP_MODE=0, no load
10
ILOAD = 1mA to 200mA
PSRR
MAX
88
Low power mode, LDOn_LP_MODE=1, no load
Power Supply
Rejection Ratio
TYP
ILOAD =100mA, VOUT > 2.7V
5
IQ (no load) + 1% of load
ILOAD = 100mA, <= 1kHz
55
ILOAD = 100mA, 10kHz
55
ILOAD = 100mA, 100kHz
32
VIN = 1.5V, ILOAD = 100mA
1.5
VIN = 1.8V, ILOAD = 100mA
1.2
VIN = 2.5V, ILOAD = 100mA
0.85
dB

VIN = 3.3V, ILOAD = 100mA
0.7
VOUT = 0V
400
mA
tstart_up
No load, Output cap 2.2 µF, 90% of VOUT
10
s
tshut_down
No load, Output cap 2.2 µF, 10% of VOUT
ICL
10
ms
LDO4, LDO5, LDO6
Unless otherwise noted: VIN = 3.8V, VOUT = 1.8V, TJ = -40°C to +125°C; Typical values are at TJ = +25ºC
PARAMETER
Input Voltage
SYMBOL
VIN
Programmable
Output Voltage
VOUT
VOUT Step Size
VOUT_STEP
Output Current
IOUT
TEST CONDITIONS
VIN ≤ SYSVDD
MIN
MAX
UNIT
1.5
TYP
5.5
V
0.9
3.3
V
VOUT = 0.9V to 1.6V
50
VOUT = 1.7V to 3.3V
100
Normal mode
0
100
Low power mode, LDOn_LP_MODE=0
0
50
Low power mode, LDOn_LP_MODE=1
0
20
-3
+3
VOUT Accuracy
VOUT_ACC
ILOAD = 1mA
Line Regulation
VOUT LINE
VIN = (VOUT + 0.5) to 5.5V, ILOAD = 50mA
Note that VIN must be >= 1.5V
0.025
%/mA
mV
ILOAD =1mA to 100mA
Dropout Voltage
VIN - VOUT
ILOAD =100mA, VOUT > 2.7V
200
ILOAD =100mA, VOUT 1.8V to 2.7V
250
ILOAD =100mA, VOUT < 1.8V
400
Quiescent
Current
IQ
Power Supply
Rejection Ratio
PSRR
On Resistance
(Switch mode)
RDSON
w
VOUT Falling
%
%/V
VOUT LOAD
VOUT
mA
0.1
Load Regulation
Undervoltage
level
mV
88
%
A
Normal mode, no load
30
Low power mode, LDOn_LP_MODE=0, no load
10
Low power mode, LDOn_LP_MODE=1, no load
5
ILOAD = 1mA to 100mA
IQ (no load) + 1% of load
ILOAD = 50mA, <= 1kHz
55
ILOAD = 50mA, 10kHz
55
ILOAD = 50mA, 100kHz
32
VIN = 1.5V, ILOAD = 100mA
3.2
VIN = 1.8V, ILOAD = 100mA
2.1
VIN = 2.5V, ILOAD = 100mA
1.35
VIN = 3.3V, ILOAD = 100mA
1.1
dB

PP, May 2012, Rev 3.1
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WM8310
PARAMETER
Current Limit
(Switch mode)
Start-up time
Shutdown time
Pre-Production
SYMBOL
TEST CONDITIONS
MIN
TYP
VOUT = 0V
230
tstart_up
No load, Output cap 2.2 µF, 90% of VOUT
10
tshut_down
No load, Output cap 2.2 µF, 10% of VOUT
ICL
MAX
UNIT
mA
s
10
ms
LDO7, LDO8
Unless otherwise noted: VIN = 3.8V, VOUT = 1.8V, TJ = -40°C to +125°C; Typical values are at TJ = +25ºC
PARAMETER
Input Voltage
SYMBOL
Programmable
Output Voltage
VOUT
VOUT Step Size
VOUT_STEP
Output Current
TEST CONDITIONS
VIN
IOUT
MAX
UNIT
1.71
MIN
TYP
5.5
V
1.0
3.5
V
VOUT = 1.0V to 1.6V
50
VOUT = 1.7V to 3.5V
100
mV
Normal mode
0
200
Low Power mode
0
50
-2.5
+2.5
VOUT Accuracy
VOUT_ACC
ILOAD = 1mA
Line Regulation
VOUT LINE
VIN = (VOUT + 0.5) to 5.5V, ILOAD = 100mA
Note that VIN must be >= 1.71V
mA
%
0.025
%/V
Load Regulation
VOUT LOAD
ILOAD =1mA to 200mA
0.003
%/mA
Dropout Voltage
VIN - VOUT
ILOAD =100mA, VOUT =1.8V
95
mV
ILOAD =100mA, VOUT =2.5V
65
ILOAD =100mA, VOUT =3.3V
60
Undervoltage
level
Quiescent
Current
VOUT
IQ
VOUT Falling
93
%
Normal mode, no load
110
A
Low Power mode, no load
70
ILOAD = 1mA to 200mA
Power Supply
Rejection Ratio
PSRR
Output noise
voltage
VOUT
On Resistance
(Switch mode)
RDSON
Current Limit
(Switch mode)
Start-up time
Shutdown time
IQ (no load) + 0.1% of load
ILOAD = 100mA, <= 1kHz
70
ILOAD = 100mA, 10kHz
67
ILOAD = 100mA, 100kHz
48
f=10Hz to 100kHz; VOUT=2.8V, ILOAD = 1mA
30
f=10Hz to 100kHz; VOUT=2.8V, ILOAD = 10mA
32
f=10Hz to 100kHz; VOUT=2.8V, ILOAD = 100mA
32
VIN = 1.71V, ILOAD = 100mA
550
VIN = 1.8V, ILOAD = 100mA
500
VIN = 2.5V, ILOAD = 100mA
330
VIN = 3.5V, ILOAD = 100mA
250
VOUT = 0V
320
tstart_up
No load, Output cap 4.7 µF, 90% of VOUT
50
tshut_down
No load, Output cap 4.7 µF, 10% of VOUT
ICL
dB
VRMS
m
mA
s
10
ms
MAX
UNIT
1.71
5.5
V
1.0
3.5
V
LDO9, LDO10
Unless otherwise noted: VIN = 3.8V, VOUT = 1.8V, TJ = -40°C to +125°C; Typical values are at TJ = +25ºC
PARAMETER
Input Voltage
SYMBOL
VIN
Programmable
Output Voltage
VOUT
VOUT Step Size
VOUT_STEP
Output Current
TEST CONDITIONS
IOUT
w
MIN
TYP
VOUT = 1.0V to 1.6V
50
VOUT = 1.7V to 3.5V
100
mV
Normal mode
0
150
Low Power mode
0
50
mA
PP, May 2012, Rev 3.1
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Pre-Production
PARAMETER
SYMBOL
TEST CONDITIONS
VOUT Accuracy
VOUT_ACC
ILOAD = 1mA
Line Regulation
VOUT LINE
VIN = (VOUT + 0.5) to 5.5V, ILOAD = 75mA
MIN
TYP
-2.5
Note that VIN must be >= 1.71V
MAX
UNIT
+2.5
%
0.025
%/V
Load Regulation
VOUT LOAD
ILOAD =1mA to 150mA
0.004
%/mA
Dropout Voltage
VIN - VOUT
ILOAD =100mA, VOUT =1.8V
135
mV
ILOAD =100mA, VOUT =2.5V
100
ILOAD =100mA, VOUT =3.3V
90
Undervoltage
level
Quiescent
Current
Power Supply
Rejection Ratio
VOUT
IQ
VOUT Falling
Normal mode, no load
Output noise
voltage
VOUT
On Resistance
(Switch mode)
RDSON
70
ILOAD = 1mA to 150mA
IQ (no load) + 0.1% of load
ILOAD = 75mA, <= 1kHz
73
ILOAD = 75mA, 10kHz
69
ILOAD = 75mA, 100kHz
49
f=10Hz to 100kHz; VOUT=2.8V, ILOAD = 1mA
30
f=10Hz to 100kHz; VOUT=2.8V, ILOAD = 10mA
32
f=10Hz to 100kHz; VOUT=2.8V, ILOAD = 100mA
Current Limit
(Switch mode)
Start-up time
Shutdown time
dB
VRMS
32
VIN = 1.71V, ILOAD = 100mA
1000
VIN = 1.8V, ILOAD = 100mA
930
VIN = 2.5V, ILOAD = 100mA
610
VIN = 3.5V, ILOAD = 100mA
430
VOUT = 0V
250
tstart_up
No load, Output cap 4.7 µF, 90% of VOUT
70
tshut_down
No load, Output cap 4.7 µF, 10% of VOUT
ICL
A
110
Low Power mode, no load
PSRR
%
93
m
mA
s
10
ms
MAX
UNIT
1.55
V
mA
LDO11
Unless otherwise noted: VIN = 3.8V, VOUT = 1.2V, TJ = -40°C to +125°C; Typical values are at TJ = +25ºC
PARAMETER
SYMBOL
Programmable
Output Voltage
VOUT
VOUT Step Size
VOUT_STEP
Output Current
IOUT
TEST CONDITIONS
50
0
10
SYSVDD ≥ 3.1V
0
25
VIN = 2.7 to 5.5V ; ILOAD = 100µA
-4
VOUT
VOUT LINE
VIN = 2.7 to 5.5V; ILOAD = 1mA
Load Regulation
VOUT LOAD
Shutdown time
mV
SYSVDD < 3.1V
Line Regulation
Start-up time
TYP
0.8
VOUT Accuracy
Quiescent
Current
MIN
+4
%
0.4
%/V
ILOAD = 100µA to 10mA
0.2
%/mA
No load
2.5
A
tstart_up
No load, Output cap 0.1 µF, 90% of VOUT
0.3
1
ms
tshut_down
No load, Output cap 0.1 µF, 10% of VOUT
0.3
1
ms
IQ
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7.5
Pre-Production
RESET THRESHOLDS
Unless otherwise noted: TJ = -40°C to +125°C; Typical values are at TJ = +25ºC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power On Reset
Power on Reset threshold
VPMIC (LDO12VOUT) voltage
at which device transitions
between NO POWER and
BACKUP states
Power on Reset hysteresis
VPOR, DE-
VPMIC rising
1.18
V
VPMIC falling
1.08
V
100
mV
VPMIC rising
1.94
V
VPMIC falling
1.85
V
92
mV
2.7
V
ASSERT
VPOR, ASSERT
VPOR, HYST
Device Reset Control
Device Reset threshold
VPMIC (LDO12VOUT) voltage
at which device transitions
between BACKUP and OFF
states
Device Reset hysteresis
VRES, DEASSERT
VRES, ASSERT
VRES, HYST
Device Shutdown
Shutdown threshold
VSHUTDOWN
SYSVDD falling
VSYSLO
SYSVDD falling,
SYSVDD voltage at which the
device forces an OFF transition
SYSLO threshold accuracy
SYSOK threshold accuracy
-3.5
+3.5
%
-3.5
+3.5
%
VSYSLO set by SYSLO_THR
(2.8V to 3.5V)
SYSVDD voltage at which
SYSLO is asserted
VSYSOK
SYSVDD rising,
VSYSOK set by SYSOK_THR
(2.8V to 3.5V)
SYSVDD voltage at which
SYSOK is asserted.
Note the SYSOK hysteresis
margin (VSYSOK, HYST) is added
to SYSOK_THR.
SYSOK hysteresis
7.6
40
VSYSOK, HYST
mV
REFERENCES
Unless otherwise noted: TJ = +25ºC
PARAMETER
SYMBOL
Voltage Reference
VVREFC
Current Reference
VIREFR
w
TEST CONDITIONS
100k to REFGND
MIN
TYP
MAX
UNIT
0.8
V
0.5
V
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7.7
BATTERY CHARGER
Unless otherwise noted: TJ = -40°C to +125°C; Typical values are at TJ = +25ºC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
5.5
V
V
General
Supply voltage
VSYSVDD
4.3
(Voltage required to commence
charging; note that charging
can continue at lower supply
voltages, eg. under current
throttling conditions)
Target voltage
VBATT_TGT
CHG_VSEL = 00
4.0
4.05
4.1
CHG_VSEL = 01
4.05
4.10
4.15
CHG_VSEL = 10
4.1
4.15
4.2
CHG_VSEL = 11
4.15
4.20
4.25
VBATT_RSTRT
VBATT_TGT
- 100mV
Defective battery threshold
VBATT_DEF
2.85
V
Defective battery timeout
tBATT_DEF
30
mins
Overvoltage threshold
VBATT_OV
End of Charge Current
IEOC
Charger re-start threshold
(Trickle charging starts when
battery voltage is below this
threshold)
Maximum trickle charge current
Fast charge threshold
ITRKL_LIM
V
4.5
V
Set by CHG_ITERM
20 to 90
mA
Set by CHG_TRKL_ILIM
50 to 200
mA
2.85
V
50 to
1000
mA
VBATTVDD = 3.8V
90
m
VBATTVDD = 3.3V
100
VFAST_CHG
(Fast charging fast-charge is
only possible when battery
voltage is above this threshold)
Maximum fast charge current
IFAST_LIM
Supply voltage regulation level
VSYS_REG
Set by CHG_FAST_ILIM
(Current throttling is applied if
supply drops to this level)
Internal Battery FET ‘On’
Resistance
RCHG_SW
Battery Temperature Monitoring
Battery temperature monitor
source (NTCBIAS)
VNTCBIAS
NTCMON voltage for high
battery temperature detection
VBTEMP_H
NTCMON voltage for low
battery temperature detection
NTCMON voltage for ‘no NTC’
detection
w
VBTEMP_L
VNO_NTC
2.1
V
VNTCMON falling
0.344 
VNTCBIAS
V
VNTCMON rising
0.365 
VNTCBIAS
VNTCMON rising
0.767 
VNTCBIAS
VNTCMON falling
0.743 
VNTCBIAS
VNTCMON rising
0.961 
VNTCBIAS
VNTCMON falling
0.931 
VNTCBIAS
V
V
PP, May 2012, Rev 3.1
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7.8
Pre-Production
USB POWER CONTROL
Unless otherwise noted: TJ = -40°C to +125°C; Typical values are at TJ = +25ºC
PARAMETER
SYMBOL
Supply voltage
VUSBVDD
USB FET ‘On’ Resistance
RUSB_SW
Current limit
IUSBVDD
TEST CONDITIONS
MIN
4.3
MAX
5.5
USB_ILIM = 010
230
USB_ILIM = 011 or greater
96
UNIT
V
m
USB_ILIM = 010
91
100
USB_ILIM = 011
454
500
USB_ILIM = 100
805
900
USB_ILIM = 101
1343
1500
USB_ILIM = 110
1609
1800
USB_ILIM = 111
496
550
Current limit response time
7.9
TYP
mA
s
10
GENERAL PURPOSE INPUTS / OUTPUTS (GPIO)
Unless otherwise noted: TJ = -40°C to +125°C; Typical values are at TJ = +25ºC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GPIO1, GPIO2, GPIO3, GPIO7, GPIO8, GPIO9
Input HIGH Level
VIH
Input LOW Level
VIL
Output HIGH Level
VOH
IOH = 1mA
Output LOW Level
VOL
IOL = -1mA
Pull-up resistance to VDD
RPU
Pull-down resistance
RPD
GPn_PWR_DOM=0 and
DBVDD=1.8V
0.75 x
VDD
V
0.25 x
VDD
0.8 x
VDD
V
V
0.2 x
VDD
V
180
kΩ
180
kΩ
or GPn_PWR_DOM=1
GPIO4, GPIO5, GPIO6, GPIO10, GPIO11, GPIO12
Input HIGH Level
VIH
Input LOW Level
VIL
Output HIGH Level
VOH
IOH = 1mA
Output LOW Level
VOL
IOL = -1mA
Pull-up resistance to VDD
RPU
Pull-down resistance
RPD
GPn_PWR_DOM=0 and
DBVDD=1.8V
0.85 x
VDD
V
0.2 x
VDD
0.8 x
VDD
V
V
0.2 x
VDD
V
180
kΩ
180
kΩ
or GPn_PWR_DOM=1 and
SYSVDD=3.8V
Notes:
1.
‘VDD’ is the voltage of the applicable power domain for each pin (selected by the corresponding GPn_PWR_DOM register).
2.
Pull-up / pull-down resistance only applies when enabled using the GPn_PULL registers.
3.
Pull-up / pull-down resistors are disabled when the GPIO pin is tri-stated.
4.
Pull-up / pull-down resistance may change with the applicable power domain (as selected by GPn_PWR_DOM).
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7.10 DIGITAL INTERFACES
Unless otherwise noted: TJ = -40°C to +125°C; Typical values are at TJ = +25ºC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ON
¯¯ , RESET
¯¯¯¯¯¯, IRQ
¯¯¯, CIFMODE, SDOUT1, SCLK1, SDA1, CS
¯¯ , SCLK2, SDA2
Input HIGH Level
VIH
Input LOW Level
VIL
Output HIGH Level
VOH
IOH = 1mA
Output LOW Level
VOL
IOL = -1mA
0.75 x
VDD
V
0.2 x
VDD
0.8 x
VDD
V
V
0.2 x
VDD
V
‘VDD’ is the voltage of the applicable power domain for each pin, as defined in Section 3.
ON pin pull-up resistance
RESET pin pull-up resistance
IRQ pin pull-up resistance
140
kΩ
DBVDD=1.8V
180
kΩ
DBVDD=3.6V
85
DBVDD=1.8V
180
DBVDD=3.6V
85
RPU
RPU
RPU
kΩ
SCLK2 pin pull-down resistance
RPD
100
kΩ
SDA2 pin pull-down resistance
RPD
100
kΩ
7.11 AUXILIARY ADC
Unless otherwise noted: TJ = +25ºC
PARAMETER
Input resistance
Input voltage range
Input capacitance
SYMBOL
RAUXADCINn
TEST CONDITIONS
MIN
During measurement
TYP
MAX
400
kΩ
VAUXADCIN1, 2, 3
0
VSYSVDD
VAUXADCIN4
0
VDBVDD
CAUXADCINn
AUXADC Resolution
AUXADC Conversion Time
Input voltage = 3V
V
2
pF
12
bits
s
39
AUXADC accuracy
UNIT
-2.5
+2.5
%
MAX
UNIT
7.12 SYSTEM STATUS LED DRIVERS
Unless otherwise noted: TJ = +25ºC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
LED1 and LED2
Sink current
10
mA
7.13 CLOCKING
Unless otherwise noted: TJ = +25ºC
PARAMETER
FLL input reference
FLL output frequency
w
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
32.768kHz
FLL_CLK_SRC=00
CLKIN
FLL_CLK_SRC=01
32
25000
kHz
CLKOUT_SRC=0
32
25000
kHz
CLKOUT
32.768
kHz
PP, May 2012, Rev 3.1
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Pre-Production
TYPICAL POWER CONSUMPTION
Data to follow
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9
9.1
WM8310
TYPICAL PERFORMANCE DATA
DC-DC CONVERTERS
Data to follow
9.2
LDO REGULATORS
Data to follow
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10 SIGNAL TIMING REQUIREMENTS
10.1 CONTROL INTERFACE
Figure 1 Control Interface Timing - 2-wire (I2C) Control Mode
Test Conditions
TJ = -40ºC to +125 ºC unless otherwise stated.
PARAMETER
SYMBOL
SCLK1 Frequency
MIN
0
TYP
MAX
UNIT
400
kHz
SCLK1 Low Pulse-Width
t1
1300
ns
SCLK1 High Pulse-Width
t2
600
ns
Hold Time (Start Condition)
t3
600
ns
Setup Time (Start Condition)
t4
600
ns
Data Setup Time
t5
100
SDA1, SCLK1 Rise Time
t6
SDA1, SCLK1 Fall Time
t7
Setup Time (Stop Condition)
t8
Data Hold Time
t9
Pulse width of spikes that will be suppressed
tps
w
ns
300
ns
300
ns
600
0
ns
900
ns
5
ns
PP, May 2012, Rev 3.1
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Figure 2 Control Interface Timing - 4-wire (SPI) Control Mode (Write Cycle)
CS
(input)
SCLK1
(input)
SDOUT1
(output)
tDL
Figure 3 Control Interface Timing - 4-wire (SPI) Control Mode (Read Cycle)
Test Conditions
TJ = -40ºC to +125 ºC unless otherwise stated.
SYMBOL
MIN
CS
¯¯ falling edge to SCLK1 rising edge
PARAMETER
tCSU
40
TYP
MAX
UNIT
ns
SCLK1 falling edge to CS
¯¯ rising edge
tCHO
10
ns
SCLK1 pulse cycle time
tSCY
200
ns
SCLK1 pulse width low
tSCL
80
ns
SCLK1 pulse width high
tSCH
80
ns
SDA1 to SCLK1 set-up time
tDSU
40
ns
SDA1 to SCLK1 hold time
tDHO
10
ns
Pulse width of spikes that will be suppressed
tps
0
SCLK1 falling edge to SDOUT1 transition
tDL
5
ns
40
ns
The CS
¯¯ pin must be held high for at least 1s after every register write operation in SPI mode.
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11 DEVICE DESCRIPTION
11.1 GENERAL DESCRIPTION
The WM8310 is a multi-purpose Power Management device with a comprehensive range of features.
The WM8310 provides 4 DC-DC converters and 11 LDO regulators which are all programmable to
application-specific requirements. The on-board oscillator and two additional LDOs support the
clocking and control functions for the DC-DC converters and other core functions. The device has
flexible power supply options, which enable hot-switching between external supplies (Wall adaptor or
USB), or a battery. The WM8310 provides a configurable charger for the main battery and maintains
the backup power source using a constant-voltage output. Other features include 2 Current Sinks
(LED drivers), flexible GPIO capability, and LED outputs for system status indications.
The WM8310 also provides a 32.768kHz crystal oscillator and secure Real Time Clock (SRTC). The
Frequency Locked Loop (FLL) enables different clock frequencies to be generated from the 32kHz
reference to provide clocking for external circuits. An auxiliary ADC is included, for measurement of
internal and external voltages.
Under typical operating conditions, the device is powered up and shut down under the control of the
ON
¯¯ pin. The device executes a programmable sequence of enabling or disabling the DC-DC
converters, LDOs and other functions when commanded to power up or shut down respectively. An
alternate device state (SLEEP power state) is provided, in which selected functions may be
separately configured for a low-power or other operating condition. The configuration of the normal
operating state may be programmed into an integrated OTP non-volatile memory. If desired, the OTP
memory can be programmed during device manufacture in accordance with the user’s specification.
See Section 14 for details of the OTP and associated bootstrap configuration functions.
In the absence of suitable power supplies, the WM8310 automatically reverts to a backup state, under
which a minimal functionality is maintained to enable a smooth return to normal operation when the
supplies are restored. With a backup supply present, the RTC is updated in the backup state, allowing
the main battery to be depleted or changed without loss of RTC function. Without a backup battery, a
small capacitor is sufficient to maintain the RTC (unclocked) for up to 5 minutes.
11.2 POWER STATES
The WM8310 has 6 main power states, which are described below. Different levels of functionality are
associated with each of the power states. Some of the state transitions are made autonomously by
the WM8310 (eg. transitions to/from BACKUP are scheduled according to the available power supply
conditions). Other transitions are initiated as a result of instructions issued over the Control Interface
or as a result of software functions (eg. Watchdog timer) or hardware functions such as the ON
¯¯ pin.
The valid transitions and the associated conditions are detailed below.
NO POWER - This is the device state when no power is available. All functions are disabled and all
register data is lost.
OFF - This is the device state when power is available but the device is switched off. The RTC is
enabled and the register map contents are maintained. The RESET
¯¯¯¯¯¯ pin is pulled low in this state.
LDO11 may optionally be enabled in this state; all other DC-DCs and LDOs are disabled (except
LDO12, which supports internal functions).
ON - This is the normal operating state when the device is switched on. All device functions are
available in this state.
SLEEP - This is a user-configurable operating state which is intended for a low-power operating
condition. Selected functions may be enabled, disabled or re-configured according to the user’s
requirements. A programmable configuration sequence for the DC-DCs and LDOs is executed on
transition to/from SLEEP mode.
BACKUP - This is the operating state when the available power supplies are below the reset
threshold of the device. Typically, this means that USB or Wall supplies are not present and that the
main battery is either discharged or removed. All DC-DC converters and LDO regulators are disabled
in this state. The RTC and oscillator and a ‘software scratch’ memory area can be maintained from
the backup supply (if available) in this state. All other functions and registers are reset in BACKUP.
(Note that, for power saving, an ‘unclocked’ mode, in which the RTC is held constant, may be
selected if required.)
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PROGRAM - This is a special operating state which is used for programming the integrated OTP
memory with the device configuration data. The settings stored in the OTP define the device
configuration in the ON state, and also the time/sequencing data associated with ON/OFF power
state transitions. See Section 14 for details of the OTP features.
The valid power state transitions are illustrated in Figure 4.
Figure 4 Power States and Transitions
State transitions to/from the NO POWER state are controlled automatically by the internal supply
(VPMIC) voltage generated by LDO12. The device is in the NO POWER state when this voltage is
below the Power-On Reset (POR) threshold. See Section 24 for more details on Power-On Reset.
State transitions to/from the BACKUP state are controlled automatically by the internal supply
(VPMIC) voltage generated by LDO12. The device is in the BACKUP state when this voltage is below
the Device Reset threshold. See Section 24 for more details on Resets.
State transitions to/from the PROGRAM state are required to follow specific control sequences. See
Section 14 for details of the PROGRAM functions.
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The remaining transitions between the OFF, ON and SLEEP states may be initiated by a number of
different mechanisms - some of them automatic, some of them user-controlled. Transitions between
these states are time-controlled sequences of events. These are the OFF, ON, SLEEP and WAKE
sequences shown in Figure 4. These transitions are programmable, using data stored in the
integrated OTP memory or else data loaded from an external InstantConfig™ EEPROM (ICE)
memory. See Section 14 for details.
Note that a transition from the SLEEP state to the OFF state is not a controlled transition. If an ‘OFF’
event occurs whilst in the SLEEP state, then the WM8310 will select the OFF state, but all the
enabled converters and regulators will be disabled immediately; the time-controlled sequence is not
implemented in this case. See Section 11.3 for details of the WM8310 ‘OFF’ events.
The current power state of the WM8310 can be read from the MAIN_STATE register field. A restricted
definition of this field is shown in Table 1. Note that other values of MAIN_STATE are defined for
transition states, but it is recommended that only the values quoted below should be used to confirm
power state transitions.
A power state transition to the BACKUP, SLEEP, ON or OFF state is indicated by the Interrupt bits
described in Section 11.4.
ADDRESS
R16397
(400Dh)
BIT
4:0
LABEL
MAIN_STATE [4:0]
System
Status
DEFAULT
0_0000
DESCRIPTION
Main State Machine condition
0_0000 = OFF
0_1011 = PROGRAM
1_1100 = SLEEP
1_1111 = ACTIVE (ON)
Table 1 Power State Readback
11.3 POWER STATE CONTROL
The OFF, ON, SLEEP and WAKE sequences are initiated by many different conditions. When such a
condition occurs, the WM8310 schedules a series of 5 timeslots, enabling a sequence of
enable/disable events to be controlled. The nominal duration of the timeslots is fixed at 2ms, though
this may be extended if any selected circuit has not started up within this time, as described later in
this section. The OFF, SLEEP and WAKE sequences commence after a programmable delay set by
PWRSTATE_DLY. This allows a host processor to request a WM8310 state transition and then
complete other tasks before the transition actually occurs.
The ON sequence is the transition from OFF to ON power states. Each LDO and each DC-DC
Converter (except DC-DC4) may be associated with any one of the available timeslots in the ON
sequence. This determines the time, within the sequence, at which that DC-DC Converter or LDO will
be enabled following an ‘ON’ event.
The clock output (CLKOUT) and GPIO pins configured as External Power Enable (EPE) outputs can
also be associated with any one of the available timeslots in the ON sequence. The EPE function is a
logic output that may be used to control external circuits, including external DC-DC converters.
An example ‘ON’ state transition sequence is illustrated in Figure 5. Each of the DC-DC Buck
Converters and LDO Regulators can be individually assigned to one of the five timeslots (shown as
T1, T2, T3, T4, T5), providing total flexibility in the power sequence.
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Figure 5 Example Control Sequence for ‘ON’ State Transition
The possible ‘ON’ events that may trigger the ON sequence are listed in Table 3. The ON sequence
is only permitted when the supply voltage SYSVDD exceeds a programmable threshold SYSOK. See
Section 24 for details of SYSVDD voltage monitoring.
The OFF sequence is the reverse of the ON sequence. Each DC-DC Converter, LDO Regulator or
GPIO output that is associated with a timeslot in the ON sequence is switched off in the reverse
sequence following an ‘OFF’ event. If CLKOUT is assigned to a timeslot in the ON sequence, then
this is disabled in the reverse (OFF) sequence also.
The possible ‘OFF’ events are listed in Table 3. Note that it is possible to modify the OFF sequence
by writing to the associated registers in the ON power state if required; this allows the OFF sequence
to be independent of the ON sequence.
The SLEEP sequence is the transition from ON to SLEEP power states. Each LDO and each DC-DC
Converter (except DC-DC4) may be associated with any one of the available timeslots in the SLEEP
sequence. This determines the time, within the sequence, at which that DC Converter or LDO will be
disabled following a ‘SLEEP’ event.
The clock output (CLKOUT) and GPIO pins configured as External Power Enable (EPE) outputs can
also be associated with any one of the available timeslots in the SLEEP sequence. The possible
‘SLEEP’ events are listed in Table 3.
The WAKE sequence is the reverse of the SLEEP sequence. Each DC-DC Converter, LDO Regulator
or GPIO output that is associated with a timeslot in the SLEEP sequence is switched on in the
reverse sequence following a ‘WAKE’ event. If CLKOUT is assigned to a timeslot in the SLEEP
sequence, then this is disabled in the reverse (WAKE) sequence also.
The possible ‘WAKE’ events are listed in Table 3. Note that it is possible to modify the WAKE
sequence by writing to the associated registers in the SLEEP power state if required; this allows the
WAKE sequence to be independent of the SLEEP sequence.
Any DC-DC Converter or LDO that is not associated with one of the 5 timeslots in the ON sequence
may, instead, be configured to be hardware controlled via a GPIO pin configured as one of the
Hardware Enable inputs. See Section 21 for details of the GPIO functions. Any DC-DC Converter or
LDO that is not under Hardware control may be enabled or disabled under Software control in the ON
state, regardless of whether it is associated with any timeslot in the ON sequence.
When a valid OFF event occurs, any DC-DC Converter or LDO which is not allocated a timeslot in the
ON sequence is disabled immediately. This includes any DC-DC Converter or LDO which is under
GPIO (Hardware Enable) control. The only exception is LDO11 which may, optionally, be configured
to be enabled in the OFF state.
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The WM8310 monitors the DC-DC Converters and LDOs during the ON sequence to ensure that the
required circuits have powered up successfully before proceeding to the next timeslot. The nominal
timeslot durations are extended if necessary in order to wait for the selected DC-DC Converters or
LDOs to power up. If the ON sequence has not completed within 2 seconds of starting the transition,
then a Power Sequence Failure has occurred, resulting in the OFF state being forced.
Note that, when the OFF state is forced as a result of a Power Sequence failure, all converters and
regulators will be shut down. The shutdown sequence is not controlled in this case; all enabled
converters and regulators will be disabled immediately on detection of a Power Sequence failure.
The most recent ON or WAKE event can be determined by reading the bits in the “ON Source”
register, R400Eh. The most recent OFF event can be determined by reading the bits in the “OFF
Source” register, R400Fh.
The “ON Source” register is updated when a new ON event occurs. The “OFF Source” register is
updated when a new OFF event occurs. Note that some Reset conditions (see Section 24) result in
an OFF transition followed by an ON transition; these events are recorded as Reset events in the “ON
Source” register.
The ON Source and OFF Source register fields are defined in Table 2.
ADDRESS
R16387
(4003h)
BIT
15
LABEL
CHIP_ON
DEFAULT
0
Power State
DESCRIPTION
Indicates whether the system is
ON or OFF.
0 = OFF
1 = ON (or SLEEP)
OFF can be commanded by
writing CHIP_ON = 0.
Note that writing CHIP_ON = 1 is
not a valid ‘ON’ event, and will not
trigger an ON transition.
14
CHIP_SLP
0
Indicates whether the system is in
the SLEEP state.
0 = Not in SLEEP
1 = SLEEP
WAKE can be commanded by
writing CHIP_SLP = 0.
SLEEP can be commanded by
writing CHIP_SLP = 1.
11:10
PWRSTATE_DLY
10
Power State transition delay
00 = No delay
01 = No delay
10 = 1ms
11 = 10ms
R16398
(400Eh)
15
ON_TRANS
0
Most recent ON/WAKE event type
0 = WAKE transition
ON Source
1 = ON transition
11
ON_GPIO
0
Most recent ON/WAKE event type
0 = Not caused by GPIO input
1 = Caused by GPIO input
10
ON_SYSLO
0
Most recent WAKE event type
0 = Not caused by SYSVDD
1 = Caused by SYSLO threshold.
Note that the SYSLO threshold
cannot trigger an ON event.
8
ON_CHG
0
Most recent WAKE event type
0 = Not caused by Battery Charger
1 = Caused by Battery Charger
7
ON_WDOG_TO
0
Most recent WAKE event type
0 = Not caused by Watchdog timer
1 = Caused by Watchdog timer
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ADDRESS
BIT
6
LABEL
ON_SW_REQ
DEFAULT
0
DESCRIPTION
Most recent WAKE event type
0 = Not caused by software WAKE
1 = Caused by software WAKE
command (CHIP_SLP = 0)
5
ON_RTC_ALM
0
Most recent ON/WAKE event type
0 = Not caused by RTC Alarm
1 = Caused by RTC Alarm
4
ON_ON_PIN
0
Most recent ON/WAKE event type
0 = Not caused by the ON pin
1 = Caused by the ON pin
3
RESET_CNV_UV
0
Most recent ON event type
0 = Not caused by undervoltage
1 = Caused by a Device Reset due
to a Converter (LDO or DC-DC)
undervoltage condition
2
RESET_SW
0
Most recent ON event type
0 = Not caused by Software Reset
1 = Caused by Software Reset
1
RESET_HW
0
Most recent ON event type
0 = Not caused by Hardware
Reset
1 = Caused by Hardware Reset
0
RESET_WDOG
0
Most recent ON event type
0 = Not caused by the Watchdog
1 = Caused by a Device Reset
triggered by the Watchdog timer
R16399
(400Fh)
13
OFF_INTLDO_ERR
0
Most recent OFF event type
0 = Not caused by LDO13 Error
condition
OFF Source
1 = Caused by LDO13 Error
condition
12
OFF_PWR_SEQ
0
Most recent OFF event type
0 = Not caused by Power
Sequence Failure
1 = Caused by a Power Sequence
Failure
11
OFF_GPIO
0
Most recent OFF event type
0 = Not caused by GPIO input
1 = Caused by GPIO input
10
OFF_SYSVDD
0
Most recent OFF event type
0 = Not caused by SYSVDD
1 = Caused by the SYSLO or
SHUTDOWN threshold
9
OFF_THERR
0
Most recent OFF event type
0 = Not caused by temperature
1 = Caused by over-temperature
6
OFF_SW_REQ
0
Most recent OFF event type
0 = Not caused by software OFF
1 = Caused by software OFF
command (CHIP_ON = 0)
4
OFF_ON_PIN
0
Most recent OFF event type
0 = Not caused by the ON pin
1 = Caused by the ON pin
Table 2 Power State Control Registers
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Table 3 lists all of the events which can trigger an ON, WAKE, OFF or SLEEP transition sequence. It
also lists the associated status bits of the ‘ON Source’ and ‘OFF Source’ register bits which are
asserted under each condition.
TRANSITION
SEQUENCE
ON (see note 1)
WAKE
OFF (see note 2)
EVENT
NOTES
ON SOURCE /
OFF SOURCE
RTC alarm
An ON request occurs if the RTC Alarm occurs
in the OFF power state. See Section 20.
ON_TRANS, ON_RTC_ALM
GPIO ON request
Requires a GPIO to be configured as “Power
On request” or “Power On/Off request”. See
Section 21.
ON_TRANS, ON_GPIO
ON
¯¯ pin request
Requires the ON
¯¯ pin to be configured to
generate ON request. See Section 11.6.
ON_TRANS, ON_ON_PIN
Software WAKE
Writing CHIP_SLP = 0. See Table 2.
ON_SW_REQ
Battery Charger event
Occurs when a Charger Interrupt event is
triggered. See Section 17.7.8.
ON_CHG
Watchdog timeout
Requires the Watchdog to be configured to
generate WAKE request. See Section 25.
ON_WDOG_TO
RTC alarm
A WAKE request occurs if the RTC Alarm
occurs in the SLEEP power state. See
Section 20.
ON_RTC_ALM
GPIO WAKE request
Requires a GPIO to be configured as
“Sleep/Wake request”. See Section 21.
ON_GPIO
SYSVDD undervoltage
Requires the SYSVDD monitor circuit to be
configured to generate WAKE request. See
Section 24.4.
ON_SYSLO
ON
¯¯ pin request
Requires the ON
¯¯ pin to be configured to
generate WAKE request. See Section 11.6.
ON_ON_PIN
Watchdog timeout
Requires the Watchdog to be configured to
generate Device Reset. See Section 25.
RESET_WDOG
Hardware Reset
See Section 24.
(See note 3)
RESET_HW
(See note 3)
Software Reset
See Section 24.
RESET_SW
(See note 3)
SLEEP
Power Management
Undervoltage Reset
Configurable option for each LDO/DC-DC
converter. See Section 15.
RESET_CNV_UV
Software OFF request
Writing CHIP_ON = 0. See Table 2.
OFF_SW_REQ
ON pin request
Requires the ON
¯¯ pin to be configured to
generate OFF request. See Section 11.6.
OFF_ON_PIN
Thermal shutdown
See Section 26.
OFF_THERR
SYSVDD undervoltage
Requires the SYSVDD monitor circuit to be
configured to generate OFF request. See
Section 24.4.
OFF_SYSVDD
SYSVDD shutdown
SYSVDD has fallen below the SHUTDOWN
threshold. See Section 24.4.
OFF_SYSVDD
GPIO OFF request
Requires a GPIO to be configured as “Power
On/Off request”. See Section 21.
OFF_GPIO
Power Sequence failure
DC-DC converters, LDOs or CLKOUT circuits
(including FLL) have failed to start up within the
permitted time.
OFF_PWR_SEQ
(See note 3)
Internal LDO error
Error condition detected in LDO13
OFF_INTLDO_ERR
Software SLEEP request
Writing CHIP_SLP = 1. See Table 2.
See note 4 and note 5
GPIO SLEEP request
Requires a GPIO to be configured as “Sleep
request” or “Sleep/Wake request”. See
Section 21.
See note 4 and note 5
Table 3 Power State Transition Events
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Notes:
1.
An ON sequence is only permitted when the supply voltage SYSVDD exceeds a programmable threshold VSYSOK. See
Section 24.4 for details of SYSVDD voltage monitoring.
2.
Selected OFF events may be masked during Battery Charging using the CHG_OFF_MASK bit. This allows user-initiated OFF
events (Software OFF, ON pin request, GPIO OFF request) to be inhibited. See Section 17.7.2.
3.
These Reset conditions result in an OFF transition followed by an ON transition. These events are recorded as Reset events in
the ‘ON Source’ register.
4.
SLEEP transitions are not possible when any of the Battery Charger Interrupts is set. If any of the Battery Charger Interrupts is
asserted when a SLEEP transition is requested, then the transition will be unsuccessful and the WM8310 will remain in the ON
power state. See Section 17.7.8 for details of the Battery Charger Interrupts.
5.
SLEEP events are not recorded in the ‘OFF Source’ register.
11.4 POWER STATE INTERRUPTS
Power State transitions are associated with a number of Interrupt event flags. Transitions to
BACKUP, SLEEP, ON or OFF states are indicated by the Interrupt bits described in Table 4. Each of
these secondary interrupts triggers a primary Power State Interrupt, PS_INT (see Section 23). This
can be masked by setting the mask bit(s) as described in Table 4.
ADDRESS
R16402
(4012h)
Interrupt Status
2
BIT
2
LABEL
PS_POR_EINT
DESCRIPTION
Power On Reset interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
1
PS_SLEEP_OFF_EINT
SLEEP or OFF interrupt (Power state
transition to SLEEP or OFF states)
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
0
PS_ON_WAKE_EINT
ON or WAKE interrupt (Power state
transition to ON state)
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
R16410
(401Ah)
2
IM_PS_POR_EINT
Interrupt mask.
0 = Do not mask interrupt.
Interrupt Status
2 Mask
1 = Mask interrupt.
Default value is 1 (masked)
1
IM_PS_SLEEP_OFF_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
0
IM_PS_ON_WAKE_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Table 4 Power State Interrupts
11.5 POWER STATE GPIO INDICATION
The WM8310 can be configured to generate logic signals via GPIO pins to indicate the current Power
State. See Section 21 for details of configuring GPIO pins.
A GPIO pin configured as “ON state” output will be asserted when the WM8310 is in the ON state.
A GPIO pin configured as “SLEEP state” output will be asserted when the WM8310 is in the SLEEP
state.
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11.6 ON PIN FUNCTION
The ON
¯¯ pin is intended for connection to the master power switch on the user’s application. It can be
used to start-up the WM8310 from the SLEEP or OFF states and also to power down the system.
This pin operates on the LDO12 (VPMIC) power domain and has an internal pull-up resistor. This pin
is asserted by shorting it to GND. A de-bounce circuit is provided on this input pin.
The behaviour of the ON
¯¯ pin is programmable. The primary action taken on asserting this pin is
determined by the ON_PIN_PRIMACT register field. Note that the ON_PIN_INT interrupt event is
always raised when the ON
¯¯ pin is asserted.
If the pin is held asserted for longer than the timeout period set by ON_PIN_TO, then a secondary
action is executed. The secondary action is determined by the ON_PIN_SECACT register field.
If the pin is held asserted for a further timeout period, then a tertiary action is executed. The tertiary
action is not programmable, and is to generate an OFF request.
An OFF request initiated by the ON
¯¯ pin may be masked during Battery Charging when the
CHG_OFF_MASK bit is set. This allows user-initiated OFF events to be disabled in order to maintain
the Battery Charger operation. See Section 17.7.2.
The status of the ON
¯¯ pin can be read at any time via the ON_PIN_STS register.
Note that the ON
¯¯ pin control registers are locked by the WM8310 User Key. These registers can only
be changed by writing the appropriate code to the Security register, as described in Section 12.4.
ADDRESS
R16389
(4005h) ON
Pin Control
BIT
9:8
LABEL
ON_PIN_SECACT
DEFAULT
DESCRIPTION
01
Secondary action of ON
¯¯ pin (taken
after 1 timeout period)
00 = Interrupt
01 = ON request
10 = OFF request
11 = Reserved
Protected by user key
5:4
ON_PIN_PRIMACT
00
Primary action of ON
¯¯ pin
00 = Ignore
01 = ON request
10 = OFF request
11 = Reserved
Note that an Interrupt is always
raised.
Protected by user key
3
ON_PIN_STS
0
Current status of ON
¯¯ pin
0 = Asserted (logic 0)
1 = Not asserted (logic 1)
1:0
ON_PIN_TO
00
ON
¯¯ pin timeout period
00 = 1s
01 = 2s
10 = 4s
11 = 8s
Protected by user key
Table 5 ON Pin Control Registers
The ON
¯¯ pin interrupt event is always raised as part of the primary action when the ON
¯¯ pin is asserted.
The ON
¯¯ pin interrupt is a selectable option as the secondary action. The ON
¯¯ pin interrupt event is also
raised when the ON
¯¯ pin is de-asserted.
The ON
¯¯ pin interrupt event is indicated by the ON_PIN_CINT register field. This secondary interrupt
triggers a primary ON Pin Interrupt, ON_PIN_INT (see Section 23). This can be masked by setting the
mask bit as described in Table 6.
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ADDRESS
R16401
(4011h)
BIT
12
LABEL
DESCRIPTION
ON_PIN_CINT
ON pin interrupt.
(Rising and Falling Edge triggered)
Interrupt Status
1
R16409
(4019h)
Note: Cleared when a ‘1’ is written.
12
IM_ON_PIN_CINT
Interrupt mask.
0 = Do not mask interrupt.
Interrupt Status
1 Mask
1 = Mask interrupt.
Default value is 1 (masked)
Table 6 ON Pin Interrupt
11.7 RESET PIN FUNCTION
The RESET
¯¯¯¯¯¯ pin is an active low input/output which is used to command Hardware Resets in the
WM8310 and in other connected devices. The pin is an open-drain type, with integrated pull-up; it can
be driven low by external sources or by the WM8310 itself.
The WM8310 drives the RESET
¯¯¯¯¯¯ pin low in the OFF state. The output status of the RESET
¯¯¯¯¯¯ pin in
SLEEP is configurable; this is determined by the RST_SLPENA register bit as defined in Table 7.
The WM8310 clears the RESET
¯¯¯¯¯¯ pin following the transition to ON. On completion of the state
transition, the RESET
¯¯¯¯¯¯ pin is held low for a further delay time period, extending the RESET
¯¯¯¯¯¯ low
duration. The RESET
¯¯¯¯¯¯ delay period is set by the RST_DUR register bit. See Figure 6 for further
details.
The WM8310 detects a Hardware Reset request whenever the RESET
¯¯¯¯¯¯ pin is driven low by an
external source. In this event, the WM8310 resets the internal control registers (excluding the RTC)
and initiates a start-up sequence. See Section 24.
It is possible to mask the RESET
¯¯¯¯¯¯ pin input in the SLEEP state by setting the RST_SLP_MSK register
bit. In SLEEP mode, if RST_SLP_MSK is set, the WM8310 will take no action if the RESET
¯¯¯¯¯¯ pin is
pulled low.
Note that the RESET
¯¯¯¯¯¯ pin control registers are locked by the WM8310 User Key. These registers can
only be changed by writing the appropriate code to the Security register, as described in Section 12.4.
ADDRESS
R16390 (4006h)
Reset Control
BIT
LABEL
DEFAULT
5
RST_SLP_MSK
1
DESCRIPTION
Masks the RESET
¯¯¯¯¯¯ pin input in
SLEEP mode
0 = External RESET
¯¯¯¯¯¯ active in SLEEP
1 = External RESET
¯¯¯¯¯¯ masked in
SLEEP
Protected by user key
4
RST_SLPENA
1
Sets the output status of RESET
¯¯¯¯¯¯ pin
in SLEEP
0 = RESET
¯¯¯¯¯¯ high (not asserted)
1 = RESET
¯¯¯¯¯¯ low (asserted)
Protected by user key
1:0
RST_DUR
11
Delay period for releasing RESET
¯¯¯¯¯¯
after ON or WAKE sequence
00 = 3ms
01 = 11ms
10 = 51ms
11 = 101ms
Protected by user key
Table 7 RESET Pin Control Registers
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The WM8310 can generate an Auxiliary Reset output via a GPIO pin configured as “Auxiliary Reset”
output (see Section 21). This signal is asserted in the OFF state. The status of the Auxiliary Reset in
the SLEEP state is configurable, using the AUXRST_SLPENA register bit as defined in Table 8.
ADDRESS
R16390 (4006h)
Reset Control
BIT
LABEL
DEFAULT
6
AUXRST_SLPE
NA
1
DESCRIPTION
Sets the output status of Auxiliary
Reset (GPIO) function in SLEEP
0 = Auxiliary Reset not asserted
1 = Auxiliary Reset asserted
Protected by user key
Table 8 Auxiliary Reset (GPIO) Control
The timing details of the RESET
¯¯¯¯¯¯ pin relative to an ON state transition are illustrated in Figure 6.
Figure 6 RESET Pin Output
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12 CONTROL INTERFACE
12.1 GENERAL DESCRIPTION
The WM8310 is controlled by writing to its control registers. Readback is available for all registers,
including Chip ID, power management status and GPIO status. The control interface can operate as a
2-wire (I2C) or 4-wire (SPI) control interface. Readback is provided on the bi-directional pin SDA1 in
2-wire (I2C) mode. The WM8310 Control Interface is powered by the DBVDD power domain.
The control interface mode is determined by the logic level on the CIFMODE pin as shown in Table 9.
CIFMODE
INTERFACE FORMAT
Low
2-wire (I2C) mode
High
4-wire (SPI) mode
Table 9 Control Interface Mode Selection
12.2 2-WIRE (I2C) CONTROL MODE
In 2-wire (I2C) mode, the WM8310 is a slave device on the control interface; SCLK1 is a clock input,
while SDA1 is a bi-directional data pin. To allow arbitration of multiple slaves (and/or multiple
masters) on the same interface, the WM8310 transmits logic 1 by tri-stating the SDA1 pin, rather than
pulling it high. An external pull-up resistor is required to pull the SDA1 line high so that the logic 1 can
be recognised by the master.
In order to allow many devices to share a single 2-wire control bus, every device on the bus has a
unique 8-bit device ID (this is not the same as the 16-bit address of each register in the WM8310).
The device ID is determined by the logic level on the CS
¯¯ pin as shown in Table 10. The LSB of the
device ID is the Read/Write bit; this bit is set to logic 1 for “Read” and logic 0 for “Write”.
CS
¯¯
DEVICE ID
Low
0110 100x = 68h(write) / 69h(read)
High
0110 110x = 6Ch(write) / 6Dh(read)
Table 10 Control Interface Device ID Selection
The WM8310 operates as a slave device only. The controller indicates the start of data transfer with a
high to low transition on SDA1 while SCLK1 remains high. This indicates that a device ID, register
address and data will follow. The WM8310 responds to the start condition and shifts in the next eight
bits on SDA1 (8-bit device ID including Read/Write bit, MSB first). If the device ID received matches
the device ID of the WM8310, then the WM8310 responds by pulling SDA1 low on the next clock
pulse (ACK). If the device ID is not recognised or the R/W bit is set incorrectly, the WM8310 returns to
the idle condition and waits for a new start condition and valid address.
If the device ID matches the device ID of the WM8310, the data transfer continues as described
below. The controller indicates the end of data transfer with a low to high transition on SDA1 while
SCLK1 remains high. After receiving a complete address and data sequence the WM8310 returns to
the idle state and waits for another start condition. If a start or stop condition is detected out of
sequence at any point during data transfer (i.e. SDA1 changes while SCLK1 is high), the device
returns to the idle condition.
The WM8310 supports the following read and write operations:

Single write

Single read

Multiple write using auto-increment

Multiple read using auto-increment
The sequence of signals associated with a single register write operation is illustrated in Figure 7.
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Figure 7 Control Interface 2-wire (I2C) Register Write
The sequence of signals associated with a single register read operation is illustrated in Figure 8.
Figure 8 Control Interface 2-wire (I2C) Register Read
The Control Interface also supports other register operations, as listed above. The interface protocol
for these operations is summarised below. The terminology used in the following figures is detailed in
Table 11.
Note that, for multiple write and multiple read operations, the auto-increment option must be enabled.
This feature is enabled by default; it is described in Table 12 below.
TERMINOLOGY
DESCRIPTION
S
Start Condition
Sr
Repeated start
A
Acknowledge (SDA Low)
¯¯
A
Not Acknowledge (SDA High)
P
Stop Condition
R/W
¯¯
ReadNotWrite
0 = Write
1 = Read
[White field]
Data flow from bus master to WM8310
[Grey field]
Data flow from WM8310 to bus master
Table 11 Control Interface Terminology
Figure 9 Single Register Write to Specified Address
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Figure 10 Single Register Read from Specified Address
Figure 11 Multiple Register Write to Specified Address using Auto-increment
Figure 12 Multiple Register Read from Specified Address using Auto-increment
Figure 13 Multiple Register Read from Last Address using Auto-increment
Multiple Write and Multiple Read operations enable the host processor to access sequential blocks of
the data in the WM8310 register map faster than is possible with single register operations. The autoincrement option is enabled when the AUTOINC register bit is set. This bit is defined in Table 12.
Auto-increment is enabled by default.
ADDRESS
R16391 (4007h)
BIT
2
LABEL
AUTOINC
Control Interface
DEFAULT
1
DESCRIPTION
Enable Auto-Increment function
0 = Disabled
1 = Enabled
Table 12 Auto-Increment Control
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12.3 4-WIRE (SPI) CONTROL MODE
In this mode, the WM8310 registers are accessed using a 4-wire serial control interface. The CS
¯¯ and
SCLK1 pins provide the ‘Chip Select’ and ‘Serial Data Clock’ functions respectively. Serial data input
is supported on the SDA1 pin; serial data output is supported on the SDOUT1 pin.
A control word consists of 32 bits. The first bit is the read/write bit (R/W), which is followed by 15
address bits (A14 to A0) that determine which control register is accessed. The remaining 16 bits
(B15 to B0) are data bits, corresponding to the 16 bits in each control register.
In Write operations (R/W=0), all SDA1 bits are driven by the controlling device. Each rising edge of
SCLK1 clocks in one data bit from the SDA1 pin. A rising edge on CS
¯¯ latches in a complete control
word consisting of the last 32 bits.
In Read operations, the SDA1 pin is ignored following receipt of the valid register address. The data
bits are output by the WM8310 on the SDOUT1 pin. SDOUT1 is undriven (high impedance) when not
outputting register data bits.
The SDOUT1 pin is an Open Drain output; an external pull-up resistor to DBVDD is required on
SDOUT1 in 4-wire (SPI) mode.
The sequence of signals associated with a register write operation is illustrated in Figure 14.
CS
SCLK
SDIN
R/W
A14
A13
A12
A2
A1
A0
B15
15-bit control register address
B14
B13
B2
B1
B0
16-bit control register data
Figure 14 Control Interface 4-wire (SPI) Register Write
The sequence of signals associated with a register read operation is illustrated in Figure 15.
Figure 15 Control Interface 4-wire (SPI) Register Read
12.4 REGISTER LOCKING
Selected registers are protected by a security key. These registers can only be written to when the
appropriate ‘unlock’ code has been written to the Security Key register.
The protected registers include those associated with Reset Control, OTP Programming, RTC Trim
and Battery Charger operation. Other selected functions also include protected registers; the affected
registers are identified in the Register Map definitions throughout the document, and also in
Section 29.
To unlock the protected registers, a value of 9716h must be written to the Security register (R16392),
as defined in Table 13.
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It is recommended to re-lock the protected registers immediately after writing to them. This helps
protect the system against accidental overwriting of register values. To lock the protected registers, a
value of 0000h should be written to the Security register.
ADDRESS
R16392 (4008h)
BIT
LABEL
15:0
SECURITY
[15:0]
Security Key
DEFAULT
0000h
DESCRIPTION
Security Key
A value of 9716h must be written
to this register to access the userkeyed registers.
Table 13 Security Key Register
12.5 SOFTWARE RESET AND CHIP ID
A Software Reset can be commanded by writing to Register 0000h. This is a read-only register field
and the contents of this register will not be affected by a write operation. For more details of the
different reset types, see Section 24.
Note that a maximum of 6 Software Resets is permitted. If more than 6 Software Resets are
scheduled, the WM8310 will remain in the OFF state until the next valid ON state transition event
occurs.
The Chip ID can be read back from Register 0000h. Other ID fields can be read from the registers
defined in Table 14.
ADDRESS
R0 (0000h)
BIT
15:0
Reset/ID
LABEL
CHIP_ID
[15:0]
DEFAULT
DESCRIPTION
0000h
Writing to this register causes a
Software Reset. The register map
contents may be reset, depending
on SW_RESET_CFG.
Reading from this register will
indicate Chip ID.
R1 (0001h)
15:8
PARENT_RE
V [7:0]
00h
The revision number of the parent
die
7:0
CHILD_REV
[7:0]
00h
The revision number of the child
die (when present)
15:0
PARENT_ID
[15:0]
6204h
Revision
R16384 (4000h)
Parent ID
The ID of the parent die
Table 14 Reading Device Information
12.6 SOFTWARE SCRATCH REGISTER
The WM8310 provides one 16-bit register as a “Software Scratch” register. This is available for use
by the host processor to store data for any purpose required by the application.
The contents of the Software Scratch register are retained in the BACKUP power state.
ADDRESS
R16393 (4009h)
Software Scratch
BIT
LABEL
DEFAULT
15:0
SW_SCRATC
H [15:0]
0000h
DESCRIPTION
Software Scratch Register for use
by the host processor.
Note that this register’s contents
are retained in the BACKUP power
state.
Table 15 Software Scratch Register
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13 CLOCKING AND OSCILLATOR CONTROL
13.1 GENERAL DESCRIPTION
The WM8310 incorporates a 32.768kHz crystal oscillator in order to maintain the Real Time Clock
(RTC). An external crystal is normally required. Alternatively, a 32.768kHz signal may be input directly
on the XTI pin. The crystal oscillator and RTC are normally enabled at all times, including the OFF
and BACKUP power states. It is possible to disable the crystal oscillator in BACKUP for power-saving
RTC ‘unclocked’ mode if desired. The WM8310 clock functions are illustrated in Figure 16.
Figure 16 Clocking Configuration
The 32.768kHz crystal oscillator is enabled using the XTAL_ENA register. The crystal oscillator is
enabled in the OFF, ON and SLEEP states when XTAL_ENA is set. The status of the crystal
oscillator in BACKUP is selected using the XTAL_BKUPENA register.
Note that the XTAL_ENA field is set via OTP/ICE settings only; it cannot be changed by writing to the
control register. Also, if an external 32.768kHz signal is connected as an input to the XTI pin, and the
crystal is omitted, it is still required to set XTAL_ENA = 1 for normal operation.
The crystal oscillator can be disabled in the BACKUP state by setting the XTAL_BKUPENA register
bit to 0. This feature may be used to minimise the device power consumption in the BACKUP state,
as described in Section 20.5. The crystal oscillator is maintained in the BACKUP state if both
XTAL_ENA and XTAL_BKUPENA are set to 1.
A clock output signal CLKOUT is provided, for the purpose of clocking other devices. This output may
be driven by the 32.768kHz oscillator or by the output of a Frequency Locked Loop (FLL). The FLL
provides a flexible capability to generate a new clock signal either from the 32.768kHz oscillator or
from an external input CLKIN. The FLL is tolerant of jitter and may be used to generate a stable clock
signal from a less stable input reference. The FLL output can be routed to the CLKOUT pin.
The CLKOUT signal can be enabled or disabled directly by writing to the CLKOUT_ENA register in
the ON or SLEEP power states. The CLKOUT can also be controlled as part of the power state
transitions using the CLKOUT_SLOT and CLKOUT_SLP_SLOT register fields. See Section 11.3 for a
description of the state transition timeslots.
The CLKOUT pin may be configured as a CMOS output or as an Open-Drain output. At high
frequencies, the CMOS output is recommended. The CLKOUT signal is referenced to the DBVDD
power domain.
If the XTAL_INH bit is set, then an ‘ON’ state transition is delayed until the CLKOUT output is valid.
(Note that CLKOUT may be the crystal oscillator output, or may be the FLL output.) This may be
desirable if the CLKOUT signal is used as a clock for another circuit, to ensure that the CLKOUT
signal has been verified before the ‘ON’ state transition occurs. Note that the CLKOUT output is
always disabled in the OFF power state; it is typically enabled as part of the ‘ON’ state transition
sequence. Setting XTAL_INH = 1 ensures that the CLKOUT output cannot be enabled until the
source signal (crystal oscillator or FLL) has been verified.
The CLKOUT control fields are described in Table 16. Some of these controls may also be stored in
the integrated OTP memory. See Section 14 for details.
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The 32.768kHz oscillator may also be output on a GPIO pin, as described in Section 21. Note that a
GPIO pin configured as 32.768kHz output will continue to output the oscillator clock in the OFF power
state; this may be used to provide clocking to the processor in the OFF state, provided that the
selected power domain for that GPIO pin remains enabled in the OFF state. The CLKOUT output is
always disabled in the OFF power state.
A separate internal RC oscillator generates the required clocks for the integrated DC-DC Converters
on the WM8310. Note that a 2MHz ‘External Power Clock’, derived from this oscillator, may be output
on a GPIO pin to provide synchronised clocking of external DC-DC Converters if required (see
Section 21). The 2MHz External Power Clock is only enabled when either of the External Power
Enable signals EPE1 or EPE2 is asserted. The External Power Enable (EPE) signals are controlled
as described in Section 15.3.
Note that the CLKOUT_ENA control register is locked by the WM8310 User Key. This register can
only be changed by writing the appropriate code to the Security register, as described in Section 12.4.
ADDRESS
R16528 (4090h)
BIT
15
Clock Control 1
LABEL
CLKOUT_EN
A
DEFAULT
0
DESCRIPTION
CLKOUT output enable
0 = Disabled
1 = Enabled
Protected by user key
13
CLKOUT_OD
0
CLKOUT pin configuration
0 = CMOS
1 = Open Drain
10:8
CLKOUT_SLO
T
000
CLKOUT output enable ON slot
select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Do not enable
111 = Do not enable
6:4
CLKOUT_SLP
SLOT
000
CLKOUT output SLEEP slot select
000 = Controlled by CLKOUT_ENA
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
110 = Controlled by CLKOUT_ENA
111 = Controlled by CLKOUT_ENA
0
CLKOUT_SR
C
0
XTAL_INH
0
CLKOUT output source select
0 = FLL output
1 = 32.768kHz oscillator
R16529 (4091h)
15
Clock Control 2
Crystal Start-Up Inhibit
0 = Disabled
1 = Enabled
When XTAL_INH=1, the ‘ON’
transition is inhibited until the
crystal oscillator is valid
13
XTAL_ENA
0
Crystal Oscillator Enable
0 = Disabled at all times
1 = Enabled in OFF, ON and
SLEEP states
(Note that the BACKUP behaviour
is determined by
XTAL_BKUPENA.)
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ADDRESS
BIT
LABEL
DEFAULT
12
XTAL_BKUPE
NA
1
DESCRIPTION
Selects the RTC and 32.768kHz
oscillator in BACKUP state
0 = RTC unclocked in BACKUP
1 = RTC maintained in BACKUP
(Note that XTAL_ENA must also
be set if the RTC is to be
maintained in BACKUP.)
Table 16 Clocking Control
13.2 CRYSTAL OSCILLATOR
The crystal oscillator generates a 32.768kHz reference clock, which is used to provide reference
clock for the Real Time Clock (RTC) in the WM8310. It may also be used as a reference input to the
FLL, for the purpose of generating other clocks. The oscillator requires an external crystal on the XTI
and XTO pins, as well as two capacitors, connected as shown in Figure 17.
Figure 17 Crystal Oscillator
A suitable crystal oscillator should be selected in accordance with the following requirements:
PARAMETER
MIN
Nominal frequency
MAX
UNITS
32.768
Series resistance
50
Maximum driving level
0.5
kHz
70
k
W
Table 17 Selection of Crystal Oscillator Component
The load capacitors C1 and C2 should be selected according to the recommended load capacitance,
CL of the crystal, which is given by the following equation:
Assuming C1 = C2 and CSTRAY = 2.75pF (typical pad i/o capacitance), then:
C1 = C2 = 2 x (CL - 2.75pF).
For example, if the crystal has a load capacitance CL = 9pF, then C1 = C2 = 12.5pF.
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If a suitable 32.768kHz clock is already present elsewhere in the system, it is possible for the
WM8310 to use that external clock instead. The external clock should be applied to pin XTI, and the
XTO pin left floating in this case.
13.3 FREQUENCY LOCKED LOOP (FLL)
The integrated FLL can be used to generate a clock on the CLKOUT pin from a wide variety of
different reference sources and frequencies. The FLL can use either CLKIN or the 32.768kHz
oscillator as its reference. A wide range of CLKIN frequencies can be supported; this may be a high
frequency (eg. 12.288MHz) or low frequency (eg. 32.768kHz) reference. The FLL is tolerant of jitter
and may be used to generate a stable clock reference from a less stable input signal. The FLL
characteristics are summarised in “Electrical Characteristics”.
To simplify the configuration of the FLL, an ‘automatic’ mode is provided in order to synthesize a
number of commonly used reference frequencies using the 32.768kHz crystal oscillator as a
reference.
The FLL is enabled using the FLL_ENA register bit. Note that, when changing FLL settings, it is
recommended that the digital circuit be disabled via FLL_ENA and then re-enabled after the other
register settings have been updated. When changing the input reference frequency FREF, it is
recommended that the FLL be reset by setting FLL_ENA to 0.
Note that, when FLL_ENA = 0, the readback value of all the FLL configuration registers (R16530
through to R16534) is not valid. It is still possible to write to the registers as normal, but the correct
values will not read back until the FLL is enabled by setting FLL_ENA to 1.
The FLL input reference is configured using the FLL_CLK_SRC register bit. The available sources
are the CLKIN pin or the 32.768kHz crystal oscillator.
The field FLL_CLK_REF_DIV provides the option to divide the selected input reference by 1, 2, 4 or
8. This field should be set to bring the reference down to 13.5MHz or below. For best performance, it
is recommended that the highest possible frequency - within the 13.5MHz limit - should be selected.
The field FLL_CTRL_RATE controls internal functions within the FLL; it is recommended that only the
default setting be used for this parameter. FLL_GAIN controls the internal loop gain and should be set
to the recommended value quoted in Table 20.
The FLL output frequency is directly determined from FLL_FRATIO, FLL_OUTDIV and the real
number represented by FLL_N and FLL_K. The field FLL_N is an integer (LSB = 1); FLL_K is the
fractional portion of the number (MSB = 0.5). The fractional portion is only valid when enabled by the
field FLL_FRAC.
Power consumption in the FLL is reduced in integer mode; however, the performance may also be
reduced, with increased noise or jitter on the output.
If low power consumption is required, then FLL settings must be chosen where N.K is an integer (ie.
FLL_K = 0). In this case, the fractional mode can be disabled by setting FLL_FRAC = 0.
For best FLL performance, a non-integer value of N.K is required. In this case, the fractional mode
must be enabled by setting FLL_FRAC = 1. The FLL settings must be adjusted, if necessary, to
produce a non-integer value of N.K.
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The FLL output frequency is generated according to the following equation:
FOUT = (FVCO / FLL_OUTDIV)
The FLL operating frequency, FVCO is set according to the following equation:
FVCO = (FREF x N.K x FLL_FRATIO)
See Table 20 for the coding of the FLL_OUTDIV and FLL_FRATIO fields.
FREF is the input frequency, as determined by FLL_CLK_REF_DIV.
FVCO must be in the range 90-100 MHz. Frequencies outside this range cannot be supported.
Note that the output frequencies that do not lie within the ranges quoted above cannot be guaranteed
across the full range of device operating temperatures.
In order to follow the above requirements for FVCO, the value of FLL_OUTDIV should be selected
according to the desired output FOUT. The divider, FLL_OUTDIV, must be set so that FVCO is in the
range 90-100MHz. The available divisions are integers from 4 to 64. Some typical settings of
FLL_OUTDIV are noted in Table 18.
OUTPUT FREQUENCY FOUT
FLL_OUTDIV
2.8125 MHz - 3.125 MHz
011111 (divide by 32)
3.75 MHz - 4.1667 MHz
010111 (divide by 24)
5.625 MHz - 6.25 MHz
001111 (divide by 16)
11.25 MHz - 12.5 MHz
000111 (divide by 8)
18 MHz - 20 MHz
000100 (divide by 5)
22.5 MHz - 25 MHz
000011 (divide by 4)
Table 18 Selection of FLL_OUTDIV
The value of FLL_FRATIO should be selected as described in Table 19.
REFERENCE FREQUENCY FREF
1MHz - 13.5MHz
FLL_FRATIO
000 (divide by 1)
256kHz - 1MHz
001 (divide by 2)
128kHz - 256kHz
010 (divide by 4)
64kHz - 128kHz
011 (divide by 8)
Less than 64kHz
100 (divide by 16)
Table 19 Selection of FLL_FRATIO
In order to determine the remaining FLL parameters, the FLL operating frequency, FVCO, must be
calculated, as given by the following equation:
FVCO = (FOUT x FLL_OUTDIV)
The value of FLL_N and FLL_K can then be determined as follows:
N.K = FVCO / (FLL_FRATIO x FREF)
See Table 20 for the coding of the FLL_OUTDIV and FLL_FRATIO fields.
Note that FREF is the input frequency, after division by FLL_CLK_REF_DIV, where applicable.
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In FLL Fractional Mode, the fractional portion of the N.K multiplier is held in the FLL_K register field.
This field is coded as a fixed point quantity, where the MSB has a weighting of 0.5. Note that, if
desired, the value of this field may be calculated by multiplying K by 2^16 and treating FLL_K as an
integer value, as illustrated in the following example:
If N.K = 8.192, then K = 0.192.
Multiplying K by 2^16 gives 0.192 x 65536 = 12582.912 (decimal) = 3126 (hex).
For best FLL performance, the FLL fractional mode is recommended. Therefore, if the calculations
yield an integer value of N.K, then it is recommended to adjust FLL_OUTDIV in order that N.K is a
non-integer value. Care must always be taken to ensure that the FLL operating frequency, FVCO, is
within its recommended limits of 90-100 MHz.
The register fields that control the FLL are described in Table 20.
ADDRESS
R16530 (4092h)
BIT
2
LABEL
FLL_FRAC
DEFAULT
0
FLL Control 1
DESCRIPTION
Fractional enable
0 = Integer Mode
1 = Fractional Mode
Integer mode offers reduced power
consumption. Fractional mode
offers best FLL performance,
provided also that N.K is a noninteger value.
0
FLL_ENA
0
FLL Enable
0 = Disabled
1 = Enabled
Note - this bit is reset to 0 when
the OFF power state is entered.
R16531 (4093h)
13:8
FLL Control 2
FLL_OUTDIV
[5:0]
000000
FOUT clock divider
000000 = Reserved
000001 = Reserved
000010 = Reserved
000011 = 4
000100 = 5
000101 = 6
…
111110 = 63
111111 = 64
(FOUT = FVCO / FLL_OUTDIV)
6:4
FLL_CTRL_R
ATE [2:0]
000
Frequency of the FLL control block
000 = FVCO / 1 (Recommended
value)
001 = FVCO / 2
010 = FVCO / 3
011 = FVCO / 4
100 = FVCO / 5
101 = FVCO / 6
110 = FVCO / 7
111 = FVCO / 8
Recommended that this register is
not changed from default.
2:0
FLL_FRATIO
[2:0]
000
FVCO clock divider
000 = 1
001 = 2
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ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
010 = 4
011 = 8
1XX = 16
000 recommended for high FREF
011 recommended for low FREF
R16532 (4094h)
15:0
FLL_K [15:0]
0000h
R16533 (4095h)
Fractional multiply for FREF
(MSB = 0.5)
FLL Control 3
14:5
FLL_N [9:0]
177h
Integer multiply for FREF
(LSB = 1)
FLL Control 4
3:0
FLL_GAIN
[3:0]
0000
Gain applied to error
0000 = x 1 (Recommended value)
0001 = x 2
0010 = x 4
0011 = x 8
0100 = x 16
0101 = x 32
0110 = x 64
0111 = x 128
1XXX = x 256
Recommended that this register is
not changed from default.
R16534 (4096h)
4:3
FLL Control 5
FLL_CLK_RE
F_DIV [1:0]
00
FLL Clock Reference Divider
00 = 1
01 = 2
10 = 4
11 = 8
CLKIN must be divided down to
<=13.5MHz.
For lower power operation, the
reference clock can be divided
down further if desired.
1:0
FLL_CLK_SR
C [1:0]
00
FLL Clock source
00 = 32.768kHz xtal oscillator
01 = CLKIN
10 = Reserved
11 = Reserved
Table 20 FLL Control
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13.3.1
FLL AUTO MODE
To simplify the configuration of the FLL, an ‘automatic’ mode is provided in order to synthesize a
number of commonly used reference frequencies using the 32.768kHz crystal oscillator as a
reference.
FLL Automatic mode is selected by setting the FLL_AUTO register bit as described in Table 21.
When FLL_AUTO is set, the FLL is automatically configured to select the 32.768kHz oscillator as the
FLL reference, and will generate the output frequency selected by FLL_AUTO_FREQ.
FLL Automatic mode should be selected while the FLL is disabled (FLL_ENA = 0). After Automatic
mode has been selected, the FLL can be enabled and disabled using FLL_ENA, as described in
Table 20.
ADDRESS
R16529 (4091h)
BIT
7
LABEL
FLL_AUTO
DEFAULT
1
Clock Control 2
DESCRIPTION
FLL Automatic Mode Enable
0 = Manual configuration mode
1 = Automatic configuration mode
(To enable the FLL output,
FLL_ENA must also be set in
Automatic mode)
2:0
FLL_AUTO_F
REQ [2:0]
000
FLL Automatic Mode Frequency
select
000 = 2.048MHz
001 = 11.2896MHz
010 = 12MHz
011 = 12.288MHz
100 = 19.2MHz
101 = 22.5792MHz
110 = 24MHz
111 = 24.576MHz
Table 21 FLL Automatic Mode
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14 INSTANTCONFIG™ (ICE) AND OTP MEMORY CONTROL
14.1 GENERAL DESCRIPTION
The WM8310 is a highly configurable device which can be tailored specifically to the requirements of
a complex system application. The sequencing and voltage control of the integrated DC-DC
Converters and LDOs in power-up, shut-down and SLEEP conditions is crucial to the robust operation
of the application.
In development, the WM8310 allows designers to modify or experiment with different settings of the
control sequences by writing to the applicable registers in the OFF state prior to commanding an ‘ON’
state transition. Configuration settings can also be stored on an external EEPROM and loaded onto
the WM8310 as required, using the InstantConfig™ EEPROM (ICE) interface.
For production use, the WM8310 provides an on-chip a One-Time Programmable (OTP) memory, in
which the essential parameters for starting up the device can be programmed. This allows the
WM8310 to start up and shut down the system with no dependency on any other devices for
application-specific configuration parameters.
14.2 ICE AND OTP MEMORY DEFINITION
An illustration of the WM8310 memory locations is shown in Figure 18. The main Register Map of the
WM8310 contains a block of data in a ‘Window’ area which is mirrored in the OTP and/or the ICE
Memory. Data from the external ICE Memory can be loaded into the Window area. Data can be
transferred from the Window into OTP Memory and also from the OTP Memory into the Window. The
Window is called the Device Configuration Register Window (DCRW); the data in this Window is
mirrored in other locations within the WM8310 Register Map.
WM8310
Register Map
Key
Unique ID
Factory Set Data
User Configurable
ICE Check
Power Management
& Configuration
Registers
InstantConfig™
EEPROM (ICE) Memory
00h
08h
ICE
Page 2
Data
10h
18h
ICE
Page 3
Data
20h
28h
ICE
Page 4
Data
OTP Memory
DCRW
Page 0 Data
OTP
Page 0 Data
DCRW
Page 1 Data
OTP
Page 1 Data
DCRW
Page 2 Data
OTP
Page 2 Data
DCRW
Page 3 Data
OTP
Page3 Data
00h
08h
10h
18h
DCRW
Page 4 Data
Note that the recommended external ICE
memory is arranged in 8-bit words
Figure 18 ICE and OTP Memory Layout
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The DCRW contains 5 pages of data, as illustrated in Figure 18.
Page 0 of the DCRW contains a 128-bit pseudo-random unique ID. The unique ID is written to the
OTP at the time of manufacture. It is copied to the DCRW when the WM8310 schedules an ‘ON’
transition. This data cannot be changed.
Page 1 of the DCRW contains factory-set calibration and configuration data. This data is written to the
OTP at the time of manufacture. It is copied to the DCRW when the WM8310 schedules an ‘ON’
transition. This data cannot be changed.
Page 2 and Page 3 of the DCRW contain bootstrap configuration data. This defines the sequence
and voltage requirements for powering up the WM8310, and for configuring functions such as the
clocks, FLL, GPIO1-6 and LED status indicators. Under default conditions, the bootstrap data is
loaded into the DCRW when the WM8310 schedules an ‘ON’ transition. The WM8310 automatically
determines whether to load the bootstrap data from ICE or from OTP as described in Section 14.3.
Page 4 of the DCRW contains a register that is used for ICE validity checking. It is copied to the
DCRW whenever the bootstrap configuration data is loaded from ICE in response to a start-up
request in development mode. This register field enables the ICE data to be checked for valid
content.
The OTP contains 4 pages of data, as illustrated in Figure 18. The contents of the OTP pages
correspond to Pages 0, 1, 2 and 3 of the DCRW register map addresses.
The ICE memory contains 3 pages of data, as illustrated in Figure 18. The contents of the ICE pages
correspond to Pages 2, 3 and 4 of the DCRW register map addresses.
Note that the ICE memory (recommended component) is arranged as 8-bit words in “big-endian”
format, and is therefore addressed as 6 pages of 8-bit data, corresponding to 3 pages of 16-bit data.
For example, the ICE memory address 00h corresponds to bits 15:8 of the first register map word in
DCRW Page 2, and ICE address 01h corresponds to bits 7:0 of that same register word in DCRW.
The DCRW can be accessed directly using the Control Interface in the OFF, ON and SLEEP power
states. Note that Read/Write access to the ICE or OTP memories is not possible directly; these can
only be accessed by copying to/from the DCRW.
In the PROGRAM state, Page 2 and Page 3 of the DCRW can be permanently written to the OTP.
14.3 BOOTSTRAP (START-UP) FUNCTION
Under default conditions, the WM8310 bootstrap configuration data is loaded when the WM8310
schedules an ‘ON’ transition. The bootstrap configuration data is loaded into Page 2 and Page 3 of
the DCRW from either an external ICE or from the integrated OTP. (The factory-set data in Page 0
and Page 1 is always loaded from the integrated OTP memory.)
If Development mode is selected, then the bootstrap data is loaded from the InstantConfig™
EEPROM (ICE). If Development mode is not selected, then the bootstrap data is loaded from the
OTP memory.
14.3.1
START-UP FROM OTP MEMORY
In volume production, development mode is not usually selected. In this case, the bootstrap
configuration data is loaded from the internal OTP memory.
The WM8310 performs a check for valid OTP data; if the OTP_CUST_ID field is set to zero, then the
WM8310 remains in the OFF power state. A non-zero OTP_CUST_ID field is used to confirm valid
OTP contents.
The OTP memory contents are defined similarly to Pages 0, 1, 2 and 3 of the DCRW memory
contents listed in Section 14.6.
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14.3.2
START-UP FROM ICE MEMORY (DEVELOPMENT MODE)
Development mode is selected if a logic high level (referenced to the LDO12 VPMIC voltage) is
present on SCLK2. This should be implemented using a pull-up resistor. See Section 14.3.4 for
details of the External ICE Memory connection.
If development mode is selected, then the WM8310 performs a check for valid ICE data; if the ICE is
not connected or contains invalid data, then the WM8310 remains in the OFF power state. The ICE
data is deemed valid is the ICE_VALID_DATA field contains the value A596h.
The WM8310 also performs a check for valid contents in the OTP_CUST_ID field in development
mode; if the OTP_CUST_ID field is set to zero, then the WM8310 remains in the OFF power state. A
non-zero OTP_CUST_ID field is used to confirm valid ICE contents.
Note that, if a GPIO pin is configured in ICE memory as “Power On/Off request” (GPn_FN=02h), then
inverted (active low) polarity should be selected for that GPIO (GPn_POL=0). The non-inverted
(active high) polarity cannot be fully supported for this function in development mode.
This restriction is only applicable in development mode, and applies only to the GPIO “Power On/Off
request” function. See Section 21 for details of the GPIO pin configuration registers.
The non-inverted (active high) polarity can be supported for the GPIO “Power On/Off request” function
in development mode if the corresponding GPn_POL register bit in the OTP memory is set to 1. Note
that, if the OTP memory is unprogrammed, the GPn_POL bits will default to 0.
14.3.3
START-UP FROM DCRW REGISTER SETTINGS
Under default settings, the bootstrap configuration data is always loaded when an ON transition is
scheduled. For development purposes, this can be disabled by clearing the RECONFIG_AT_ON
register bit. (Note that RECONFIG_AT_ON only selects whether Page 2/3/4 data is loaded; Page 0/1
data is always loaded from OTP whenever an ON transition is scheduled.)
When RECONFIG_AT_ON = 1, the bootstrap data is reloaded from either the ICE or OTP when an
ON transition is scheduled. The logic level on SCLK2 is checked to determine whether the ICE or the
OTP memory should be used. If RECONFIG_AT_ON = 0, then the latest contents of the DCRW are
used to configure the start-up sequence.
Note that, when WM8310 start-up is scheduled using this method, the contents of OTP_CUST_ID is
still checked for valid contents. In development mode, the ICE_VALID_DATA field is also checked.
See Section 14.3.2 for details.
Note that the RECONFIG_AT_ON control register is locked by the WM8310 User Key. This register
can only be changed by writing the appropriate code to the Security register, as described in
Section 12.4.
ADDRESS
BIT
LABEL
DEFAULT
R16390 (4006h)
15
RECONFIG_A
T_ON
1
Reset Control
DESCRIPTION
Selects if the bootstrap configuration
data should be reloaded when an ON
transition is scheduled
0 = Disabled
1 = Enabled
Protected by user key
Table 22 Bootstrap Configuration Reload Control
14.3.4
EXTERNAL ICE MEMORY CONNECTION
The recommended component for the external ICE is the Microchip 24AA32A, which provides 32
bytes of memory space. The ICE interfaces with the WM8310 via the SCLK2 and SDA2 pins, and
initiates an I2C transfer of data from the ICE when required. The necessary electrical connections for
this device are illustrated in Figure 19. The WM8310 assumes an EEPROM device ID of 1010 0001
(A1h) for ICE read cycles.
The ICE memory contents are defined similarly to Pages 2, 3 and 4 of the DCRW memory contents
defined in Section 14.6.
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Figure 19 ICE Memory Connection
Note that the WM8310 does not support programming the external ICE memory.
External programming of ICE whilst physically connected to the WM8310 is possible by putting the
WM8310 in the OFF state. This is supported on the evaluation board, provided the voltage levels on
SCLK2 and SDA2 are less than or equal to the LDO12 VPMIC voltage. Note that the Write-Protect
(WP) pin on the ICE must be connected to GND (Vss) in this case.
14.4 OTP / ICE MEMORY CONTROL
The OTP and ICE Memory commands are initiated by writing to the OTP Control Register, as defined
in Section 14.4.6. The supported commands are described below.
READ ICE MEMORY - This command instructs the WM8310 to load data from the external ICE into
the WM8310 DCRW memory area. Note that this command is performed automatically when the
WM8310 starts up in development mode.
READ OTP MEMORY - This command instructs the WM8310 to load data from the integrated OTP
memory area into the WM8310 DCRW memory area. Note that this command is performed
automatically when the WM8310 starts up in normal (ie. non-development) mode.
WRITE OTP MEMORY - This command instructs the WM8310 to program the integrated OTP, by
writing a copy of the DCRW memory area (Pages 0, 1, 2 and 3) to the OTP memory. This command
should be performed after the required settings have been configured in the DCRW memory. The
required settings can be configured in the DCRW either as a result of a ICE Read command, or else
through register writes in the PROGRAM power state. Note that the Write OTP command should only
be performed once on each OTP page; after the Write OTP command has been performed, the
contents of the affected page(s) cannot be erased or re-programmed.
VERIFY OTP MEMORY - This command instructs the WM8310 to compare the contents of the OTP
memory with the contents of the DCRW memory. The Verify OTP command performs a check that
the OTP data is identical to the DCRW contents, in order to confirm the success of the Write OTP
operation. For increased reliability, the WM8310 can apply a ‘Margin Read’ function when verifying
the OTP memory; it is recommended that the Margin Read option is used, as described in
Section 14.4.4.
FINALISE OTP PAGES - This command instructs the WM8310 to set the OTP_CUST_FINAL bit in
the OTP memory. The Finalise OTP command ensures that any subsequent OTP_WRITE commands
to Page 2 or Page 3 of the OTP will have no effect and that the OTP contents are maintained
securely.
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The OTP and ICE Memory commands are each described in the following sections. Note that, in
some cases, commands may be executed on a single page of memory or may be executed as a Bulk
operation on all available memory pages.
Completion of each OTP or ICE Memory command is indicated via an Interrupt flag, as described in
Section 14.5. The pass/fail outcome of any Verify OTP command is also indicated by the Interrupt
bits. Note that read/write access to the WM8310 Register Map is not supported while a ICE/OTP
command is in progress. It is recommended that the IRQ
¯¯¯ pin is configured to indicate any ICE/OTP
Interrupt event; the host processor should read the OTP/ICE Interrupt event flags to confirm the
OTP/ICE command status following the assertion of the IRQ
¯¯¯ pin.
The programming supply voltage PROGVDD is required for the OTP Write commands and the OTP
Finalise command. It is also necessary to overdrive the LDO12VOUT pin from an external supply.
See Section 6 for details of the required supply voltages.
14.4.1
ENTERING / EXITING THE PROGRAM STATE
The ICE and OTP commands are only supported when the WM8310 is in the PROGRAM state. The
WM8310 can only enter the PROGRAM state as a transition from the OFF state. This is commanded
by setting the OTP_PROG register bit.
Important note - when the PROGRAM state is selected, the WM8310 will read all pages of the OTP
memory into the corresponding pages of the DCRW. This is required in order to confirm if the OTP
contents have already been finalised (see Section 14.4.5). The previous contents of the DCRW
registers will be lost when the PROGRAM state is entered.
The transition into the PROGRAM state can be confirmed by reading the MAIN_STATE register field
as defined in Section 11.2. When the MAIN_STATE register reads back a value of 01011, then the
WM8310 is in the PROGRAM state.
In the PROGRAM state, the ICE and OTP commands are initiated by further writes to the OTP
Control Register (R16394), as described in the following sections.
To exit the PROGRAM state and resume normal operations, a Device Reset must be scheduled.
14.4.2
OTP / ICE READ COMMAND
The Read command loads either one or all data pages from the ICE or OTP into the corresponding
page(s) of the DCRW. The Read commands are selected by writing 1 to the OTP_READ bit.
To read the OTP, the OTP_MEM bit should be set to 1. To read the ICE, the OTP_MEM bit should be
set to 0.
The Read Margin Level is selected by setting the OTP_READ_LVL. Note that this register relates to
the OTP only; it has no effect on ICE Read commands. The recommended setting for the OTP Read
command is ‘Normal’ level. The OTP_READ_LVL field should be set to 00b.
To read a single memory page, the applicable page is selected by setting the OTP_PAGE field. To
read all memory pages, the OTP_BULK bit should be set to 1.
Note that the OTP_PAGE field is defined differently for ICE pages and for OTP pages, as detailed in
Section 14.4.6.
All other bits in the OTP Control Register should be set to 0 when a Read command is issued. (Note
that OTP_PROG should be set to 0 when a Read command is issued.)
For typical applications, the Bulk Read commands are recommended. The OTP Control Register
contents for the OTP / ICE Bulk Read Commands are detailed in Table 23.
READ COMMAND
OTP CONTROL REGISTER VALUE
ICE Read All
0120h
OTP Read All
2120h
Table 23 OTP / ICE Read Command
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14.4.3
OTP WRITE COMMAND
The Write command programs one or more data pages of the OTP with data from the corresponding
page(s) of the DCRW. The Write commands are selected by writing 1 to the OTP_WRITE bit.
The OTP memory is selected by setting the OTP_MEM bit to 1. (Note that the WM8310 does not
support programming the external ICE memory.)
To write a single memory page, the applicable page is selected by setting the OTP_PAGE field. To
write all memory pages, the OTP_BULK bit should be set to 1.
Note that Page 0 and Page 1 will be programmed during manufacture, and cannot be re-written. OTP
Write is then only possible to Page 2 and Page 3. Selecting the OTP_BULK bit will select OTP Write
to Page 2 and Page 3 only.
Note that selecting the OTP_BULK option will cause an OTP Error to be indicated (see Section 14.5).
This is because the Bulk Write to Page 0 and Page 1 is not permitted after the factory configuration of
the WM8310. It is still possible to Verify the OTP Bulk Write, but the OTP_ERR_EINT flag must be
cleared before doing so. The recommended procedure is to Write Page 2 and Page 3 using single
page OTP Write commands.
All other bits in the OTP Control Register should be set to 0 when a Write command is issued. (Note
that OTP_PROG should be set to 0 when a Write command is issued.)
The programming supply voltage PROGVDD is required for the OTP Write command. It is also
necessary to overdrive the LDO12VOUT pin from an external supply. See Section 6 for details of the
required supply voltages.
For typical applications, it is recommended to Write Page 2 and Page 3 in two separate commands.
The OTP Control Register contents for these OTP Write Commands are detailed in Table 24.
WRITE COMMAND
OTP CONTROL REGISTER VALUE
OTP Write Page 2
2202h
OTP Write Page 3
2203h
Table 24 OTP Write Command
14.4.4
OTP VERIFY COMMAND
The Verify command compares one or all data pages of the OTP with data in the corresponding
page(s) of the DCRW. The Verify commands are selected by writing 1 to the OTP_VERIFY bit.
The OTP memory is selected by setting the OTP_MEM bit to 1. (Note that the WM8310 does not
support verifying the external ICE memory.)
The Read Margin Level is selected by setting the OTP_READ_LVL. The recommended setting for the
OTP Verify command is Margin 1. The OTP_READ_LVL field should be set to 10b.
To verify a single memory page, the applicable page is selected by setting the OTP_PAGE field. To
verify all memory pages, the OTP_BULK bit should be set to 1.
All other bits in the OTP Control Register should be set to 0 when a Verify command is issued. (Note
that OTP_PROG should be set to 0 when a Verify command is issued.)
If the OTP Verify operation is unsuccessful (ie. the WM8310 detects a difference between the
selected pages of the OTP and DCRW memories), then this is indicated by the OTP_ERR_EINT
Interrupt flag, as described in Section 14.5.
Note that, when Verifying the OTP after it has been Finalised, the CUST_OTP_FINAL bit needs to be
set in the DCRW using a register write to R30736 prior to the OTP_VERIFY operation. This is
because the OTP_FINAL command does not set the CUST_OTP_FINAL bit in the DCRW; it only sets
it in the OTP memory. If the CUST_OTP_FINAL bit is not set in DCRW, then the OTP_VERIFY
command will result in an OTP error indication.
The OTP Control Register contents for all OTP Verify Commands are detailed in Table 25.
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VERIFY COMMAND
OTP CONTROL REGISTER VALUE
OTP Verify Page 0
2480h
OTP Verify Page 1
2481h
OTP Verify Page 2
2482h
OTP Verify Page 3
2483h
OTP Verify All
24A0h
Table 25 OTP Verify Command (Margin 1)
14.4.5
OTP FINALISE COMMAND
The Finalise command sets the OTP finalise bit for the user-programmable pages of the OTP
memory. The Finalise commands are selected by writing 1 to the OTP_FINAL bit.
Note that Page 0 and Page 1 will be programmed and finalised during manufacture; these memory
pages cannot be re-written by users. Following the user Finalise command, Page 2 and Page 3 of the
OTP memory will be prevented from any further OTP Write commands. Each page of the OTP
memory can be programmed only once; the OTP Finalise command ensures that any subsequent
Write commands will have no effect and that the OTP contents are maintained securely.
The OTP memory is selected by setting the OTP_MEM bit to 1. (Note that the WM8310 does not
support this function on the external ICE memory.)
The Customer Finalise bit (CUST_OTP_FINAL) is in Page 2. This page is selected by setting
OTP_PAGE = 10. Note that the Page 2 finalise bit locks the contents of Page 2 and Page 3.
All other bits in the OTP Control Register should be set to 0 when a Finalise command is issued.
(Note that OTP_PROG should be set to 0 when a Finalise command is issued.)
The programming supply voltage PROGVDD is required for the OTP Finalise command. It is also
necessary to overdrive the LDO12VOUT pin from an external supply. See Section 6 for details of the
required supply voltages.
Note that the OTP_FINAL command does not set the CUST_OTP_FINAL bit in the DCRW; it only
sets it in the OTP memory. Care is required when verifying a Finalised OTP page, to avoid an OTP
error indication, as described in Section 14.4.4.
The OTP Control Register contents for the OTP Finalise Command is detailed in Table 26. This is the
only recommended OTP Finalise Command; no variants of the Finalise Command should be used.
FINALISE COMMAND
OTP Finalise Page 2
OTP CONTROL REGISTER VALUE
2802h
(Note that this command finalises
the contents of OTP Page 2 and
Page 3.)
Table 26 OTP Finalise Command
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14.4.6
OTP CONTROL REGISTER
The OTP Control register (R16394) is defined in Table 27. Note that some of the OTP Programming
registers are locked by the WM8310 User Key. These registers can only be changed by writing the
appropriate code to the Security register, as described in Section 12.4.
ADDRESS
BIT
R16394 (400Ah)
15
LABEL
OTP_PROG
DEFAULT
0
OTP Control
DESCRIPTION
Selects the PROGRAM device state.
0 = No action
1 = Select PROGRAM mode
Note that, after PROGRAM mode has
been selected, the chip will remain in
PROGRAM mode until a Device Reset.
Protected by user key
13
OTP_MEM
1
Selects ICE or OTP memory for Program
commands.
0 = ICE
1 = OTP
Protected by user key
11
OTP_FINAL
0
Selects the FINALISE command,
preventing further OTP programming.
0 = No action
1 = Finalise Command
Protected by user key
10
OTP_VERIFY
0
Selects the VERIFY command for the
selected OTP memory page(s).
0 = No action
1 = Verify Command
Protected by user key
9
OTP_WRITE
0
Selects WRITE command for the
selected OTP memory page(s).
0 = No action
1 = Write Command
Protected by user key
8
OTP_READ
0
Selects READ command for the selected
memory page(s).
0 = No action
1 = Read Command
Protected by user key
7:6
OTP_READ_L
VL [1:0]
00
Selects the Margin Level for READ or
VERIFY OTP commands.
00 = Normal
01 = Reserved
10 = Margin 1
11 = Margin 2
Protected by user key
5
OTP_BULK
0
Selects the number of memory pages for
ICE / OTP commands.
0 = Single Page
1 = All Pages
1:0
OTP_PAGE
[1:0]
00
Selects the single memory page for ICE /
OTP commands (when OTP_BULK=0).
If OTP is selected (OTP_MEM = 1):
00 = Page 0
01 = Page 1
10 = Page 2
11 = Page 3
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ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
If ICE is selected (OTP_MEM = 0):
00 = Page 2
01 = Page 3
10 = Page 4
11 = Reserved
Table 27 OTP Memory Control
14.5 OTP / ICE INTERRUPTS
The OTP and ICE memories are associated with two Interrupt event flags.
The OTP_CMD_END_EINT interrupt is set each time an OTP / ICE Command has completed or if
OTP Auto-Program has completed. (See Section 14.4 for a definition of the OTP and ICE
Commands. See Section 14.6.3 for details of the OTP Auto-Program function.)
The OTP_ERR_EINT interrupt is set when an OTP / ICE Error has occurred. The errors detected
include ICE Read Failure, OTP Verify Failure and attempted OTP Write to a page that has been
Finalised.
Each of these secondary interrupts triggers a primary OTP Memory Interrupt, OTP_INT (see
Section 23). This can be masked by setting the mask bit(s) as described in Table 70.
Note that OTP_CMD_END_EINT is triggered during the normal start-up and shutdown operations,
when the WM8310 accesses the OTP and/or ICE memories. For typical applications, it is
recommended that the OTP_CMD_END_EINT interrupt should be masked at all times except when
performing user-initiated OTP/DBE commands.
ADDRESS
BIT
R16402
(4012h)
Interrupt Status
2
5
LABEL
OTP_CMD_END_EINT
DESCRIPTION
OTP / ICE Command End interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
4
OTP_ERR_EINT
OTP / ICE Command Fail interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
R16410
(401Ah)
5
IM_OTP_CMD_END_EINT
Interrupt mask.
0 = Do not mask interrupt.
Interrupt Status
2 Mask
1 = Mask interrupt.
Default value is 1 (masked)
4
IM_OTP_ERR_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Table 28 OTP Memory Interrupts
14.6 DCRW MEMORY CONTENTS
The DCRW is the ICE/OTP Register Window, as described in Section 14.2. Under normal operating
conditions, this memory area is initialised with data from the integrated OTP or an external ICE
memory. The DCRW memory addresses range from R30720 (7800h) to R30759 (7827h). The
complete register map definition is described in Section 28.
The register fields in the DCRW allow the start-up configuration of the DC-DC Converters, the LDO
Regulators, GPIO pins 1-6 and Status LED outputs to be programmed. The DCRW also provides
control of the Battery Charger, Clocking, USB Current Limit and the Start-Up (SYSOK) voltage
threshold.
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Most of the DCRW contents are duplicates of control registers that exist in the main register area
below the DCRW addresses. In theses cases, reading or writing to either address will have the same
effect.
Some register fields are defined only in the DCRW area; a detailed description of these fields is
provided in the following sub-sections.
14.6.1
DCRW PAGE 0
Page 0 of the DCRW occupies register addresses R30720 (7800h) to R30727 (7807h). This contains
factory-preset data which is loaded from OTP when an ‘ON’ state transition is scheduled.
Page 0 of the DCRW contains a 128-bit unique ID. Note that these fields are Read-Only in the OTP
and cannot be changed.
14.6.2
DCRW PAGE 1
Page 1 of the DCRW occupies register addresses R30728 (7808h) to R30735 (780Fh). This contains
factory-preset data which is loaded from OTP when an ‘ON’ state transition is scheduled.
Page 1 of the DCRW contains trim parameters that ensure the accuracy of the voltage references
and the power management RC oscillator. Note that these fields are Read-Only in the OTP and
cannot be changed.
14.6.3
DCRW PAGE 2
Page 2 of the DCRW occupies register addresses R30736 (7810h) to R30743 (7817h). This contains
user-programmable data.
This page of data is normally loaded from OTP when ‘ON’ state transition is scheduled (except in
Development Mode or if RECONFIG_AT_ON = 0). This page of data can also be loaded from OTP
using the OTP_READ command; it can be written to the OTP using the OTP_WRITE command.
This page of data is loaded from the first page of ICE memory (00h to 0Fh) when ‘ON’ state transition
is scheduled in Development Mode (if RECONFIG_AT_ON = 1). This page of data can also be
loaded from ICE using the ICE Read command. Note that ICE Address 00h corresponds to bits 15:8
at the start address of DCRW Page 2; ICE Address 01h corresponds to bits 7:0 at the same DCRW
address.
If the WM8310 configuration data is loaded from external ICE in response to an ‘ON’ state transition
request, and the OTP_AUTO_PROG register bit is set, then the WM8310 will program the OTP with
the contents Page 2 and Page 3 of the DCRW data, after the ICE data has been loaded and
confirmed as valid. The WM8310 will also perform a Margin 1 Verify as part of the auto-program
function.
The programming supply voltage PROGVDD is required for the OTP_AUTO_PROG command. It is
also necessary to overdrive the LDO12VOUT pin from an external supply. See Section 6 for details of
the required supply voltages.
Using the auto-program function described above, the OTP will be finalised if the OTP_CUST_FINAL
bit is set in the ICE data. Completion of the auto-program is indicated using the OTP interrupts, as
described in Section 14.5. The auto-program completion is also indicated on the Status LED outputs,
as described in Section 22.
The OTP_CUST_ID field is used to hold a Customer Identifier for the OTP data contents. Whenever
an ‘ON’ state transition is requested, then the OTP_CUST_ID field is checked to confirm valid OTP
data. If the OTP_CUST_ID field is set to zero, then the WM8310 remains in the OFF power state. A
non-zero OTP_CUST_ID field is used to confirm valid OTP contents.
The OTP_CUST_FINAL bit is used to control whether the user-programmable OTP data (Page 2 and
Page 3) is finalised. If OTP_CUST_FINAL is set in the OTP and also set in the DCRW, then the
WM8310 prevents any further Writes to the OTP. If the DCRW has been loaded from the OTP, then
the OTP_CUST_FINAL bit indicates whether any further Write operations are possible. If the DCRW
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has been loaded from the ICE, and the OTP auto-programming option is selected (see above), then
the value of the OTP_CUST_FINAL bit will be copied from the ICE memory to the OTP memory.
The above registers are defined in Table 29.
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R30736 (7810h)
15
OTP_AUTO_
PROG
0
If this bit is set when bootstrap data is
loaded from ICE (in development mode),
then the ICE contents will be
programmed in the OTP.
14:1
OTP_CUST_
ID [13:0]
0000h
This field is checked when an ‘ON’
transition is requested. A non-zero value
is used to confirm valid data.
0
OTP_CUST_
FINAL
0
Customer OTP
ID
If OTP_CUST_FINAL is set in the OTP
and also set in the DCRW, then no
further Writes are possible to the OTP.
Table 29 OTP Registers - DCRW Page 2
The remaining contents of DCRW Page 2 include the registers listed in Table 30, which are defined in
other sections of this datasheet.
REGISTER
DC1_ON_SLOT [2:0]
FUNCTION
DC-DC Converter 1
REFERENCE
See Section 15.12.2
DC1_FREQ [1:0]
See Section 15.12.2
DC1_PHASE
See Section 15.12.2
DC1_ON_VSEL [6:2]
See Section 15.12.2
DC1_CAP [1:0]
DC2_ON_SLOT [2:0]
See Section 15.12.2
DC-DC Converter 2
See Section 15.12.2
DC2_FREQ [1:0]
See Section 15.12.2
DC2_PHASE
See Section 15.12.2
DC2_ON_VSEL [6:2]
See Section 15.12.2
DC2_CAP [1:0]
DC3_ON_SLOT [2:0]
See Section 15.12.2
DC-DC Converter 3
See Section 15.12.2
DC3_PHASE
See Section 15.12.2
DC3_ON_VSEL [6:2]
See Section 15.12.2
DC3_CAP [1:0]
LDO1_ON_SLOT [2:0]
See Section 15.12.2
LDO Regulator 1
LDO1_ON_VSEL [4:0]
LDO2_ON_SLOT [2:0]
LDO Regulator 2
LDO2_ON_VSEL [4:0]
LDO3_ON_SLOT [2:0]
LDO Regulator 3
LDO Regulator 4
LDO Regulator 5
LDO8_ON_VSEL [4:0]
See Section 15.12.4
See Section 15.12.4
LDO Regulator 7
LDO7_ON_VSEL [4:0]
LDO8_ON_SLOT [2:0]
See Section 15.12.4
See Section 15.12.4
LDO Regulator 6
LDO6_ON_VSEL [4:0]
LDO7_ON_SLOT [2:0]
See Section 15.12.4
See Section 15.12.4
LDO5_ON_VSEL [4:0]
LDO6_ON_SLOT [2:0]
See Section 15.12.4
See Section 15.12.4
LDO4_ON_VSEL [4:0]
LDO5_ON_SLOT [2:0]
See Section 15.12.4
See Section 15.12.4
LDO3_ON_VSEL [4:0]
LDO4_ON_SLOT [2:0]
See Section 15.12.4
See Section 15.12.4
See Section 15.12.4
See Section 15.12.4
LDO Regulator 8
See Section 15.12.4
See Section 15.12.4
Table 30 DCRW Page 2
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14.6.4
DCRW PAGE 3
Page 3 of the DCRW occupies register addresses R30744 (7818h) to R30751 (781Fh). This contains
user-programmable data.
This page of data is normally loaded from OTP when ‘ON’ state transition is scheduled (except in
Development Mode or if RECONFIG_AT_ON = 0). This page of data can also be loaded from OTP
using the OTP_READ command; it can be written to the OTP using the OTP_WRITE command.
This page of data is loaded from the second page of ICE memory (10h to 1Fh) when ‘ON’ state
transition is scheduled in Development Mode (if RECONFIG_AT_ON = 1). This page of data can also
be loaded from ICE using the ICE Read command. Note that ICE Address 10h corresponds to bits
15:8 at the start address of DCRW Page 3; ICE Address 11h corresponds to bits 7:0 at the same
DCRW address.
The contents of DCRW Page 3 include the registers listed in Table 31.
REGISTER
LDO9_ON_SLOT [2:0]
FUNCTION
LDO Regulator 9
LDO9_ON_VSEL [4:0]
LDO10_ON_SLOT [2:0]
See Section 15.12.4
LDO Regulator 10
LDO10_ON_VSEL [4:0]
LDO11_ON_SLOT [2:0]
EPE2_ON_SLOT [2:0]
GP1_DIR
LDO Regulator 11
See Section 15.12.4
See Section 15.12.4
External Power Converter
Enable
GPIO1
See Section 15.12.5
See Section 15.12.5
See Section 21.3
GP1_PULL [1:0]
See Section 21.3
GP1_INT_MODE
See Section 21.3
GP1_PWR_DOM
See Section 21.3
GP1_POL
See Section 21.3
GP1_OD
See Section 21.3
GP1_ENA
See Section 21.3
GP1_FN [3:0]
GP2_DIR
See Section 21.3
GPIO2
See Section 21.3
GP2_PULL [1:0]
See Section 21.3
GP2_INT_MODE
See Section 21.3
GP2_PWR_DOM
See Section 21.3
GP2_POL
See Section 21.3
GP2_OD
See Section 21.3
GP2_ENA
See Section 21.3
GP2_FN [3:0]
GP3_DIR
See Section 21.3
GPIO3
GP3_PULL [1:0]
See Section 21.3
See Section 21.3
GP3_INT_MODE
See Section 21.3
GP3_PWR_DOM
See Section 21.3
GP3_POL
See Section 21.3
GP3_OD
See Section 21.3
GP3_ENA
See Section 21.3
GP3_FN [3:0]
GP4_DIR
GP4_PULL [1:0]
w
See Section 15.12.4
See Section 15.12.4
LDO11_ON_VSEL [3:0]
EPE1_ON_SLOT [2:0]
REFERENCE
See Section 15.12.4
See Section 21.3
GPIO4
See Section 21.3
See Section 21.3
GP4_INT_MODE
See Section 21.3
GP4_PWR_DOM
See Section 21.3
GP4_POL
See Section 21.3
GP4_OD
See Section 21.3
GP4_ENA
See Section 21.3
GP4_FN [3:0]
See Section 21.3
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REGISTER
FUNCTION
GP5_DIR
GPIO5
REFERENCE
See Section 21.3
GP5_PULL [1:0]
See Section 21.3
GP5_INT_MODE
See Section 21.3
GP5_PWR_DOM
See Section 21.3
GP5_POL
See Section 21.3
GP5_OD
See Section 21.3
GP5_ENA
See Section 21.3
GP5_FN [3:0]
See Section 21.3
GP6_DIR
GPIO6
See Section 21.3
GP6_PULL [1:0]
See Section 21.3
GP6_INT_MODE
See Section 21.3
GP6_PWR_DOM
See Section 21.3
GP6_POL
See Section 21.3
GP6_OD
See Section 21.3
GP6_ENA
See Section 21.3
GP6_FN [3:0]
See Section 21.3
CLKOUT_SLOT [2:0]
Clocking
See Section 13.1
CLKOUT_SRC
See Section 13.1
XTAL_ENA
See Section 13.1
XTAL_INH
See Section 13.1
FLL_AUTO_FREQ [2:0]
USB_ILIM [2:0]
See Section 13.3
USB Configuration
USB100MA_STARTUP [1:0]
CHG_ENA
See Section 17.4
Battery Charger Enable
WDOG_ENA
Watchdog Timer
LED1_SRC [1:0]
See Section 17.4
See Section 17.7
See Section 25
System Status LED Drivers
See Section 22.2
Supply Voltage Monitoring
See Section 24.4
LED2_SRC [1:0]
See Section 22.2
SYSOK_THR [2:0]
Table 31 DCRW Page 3
14.6.5
DCRW PAGE 4
Page 4 of the DCRW occupies register addresses R30752 (7820h) to R30759 (7827h).
This page of data is loaded from the third page of ICE memory (20h to 2Fh) when ‘ON’ state transition
is scheduled in Development Mode. This page of data can also be loaded from ICE using the ICE
Read command. Note that ICE Address 20h corresponds to bits 15:8 at the start address of DCRW
Page 4; ICE Address 21h corresponds to bits 7:0 at the same DCRW address.
The ICE_VALID_DATA register is used to hold a validation field for the ICE data contents. If the
WM8310 configuration data is loaded from the external ICE in response to an ‘ON’ state transition
request in Development Mode, then the ICE_VALID_DATA field is checked to confirm valid ICE data.
The ICE data is deemed valid if the ICE_VALID_DATA field contains the value A596h. If the ICE is
not connected or contains invalid data, then the WM8310 remains in the OFF power state until a
Device Reset.
The ICE_VALID_DATA register is defined in Table 32.
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R30759 (7827h)
15:0
ICE_VALID_
DATA [15:0]
0000h
This field is checked in development
mode when an ‘ON’ transition is
requested. A value of A596h is required
to confirm valid data.
ICE CHECK
DATA
Table 32 ICE Registers - DCRW Page 4
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15 POWER MANAGEMENT
15.1 GENERAL DESCRIPTION
The WM8310 provides 4 DC-DC Converters and 11 LDO Regulators. The DC-DC Converters
comprise 3 step-down (Buck) converters and 1 step-up (Boost) converter. The Regulators comprise
general purpose LDOs (LDO1 - LDO6) and low-noise analogue LDOs (LDO7 - LDO10). The analogue
LDOs offer superior PSRR, noise and load-transient performance. LDO11 is a low power LDO
intended for powering “always on” circuits connected to the WM8310; this LDO can be configured to
remain enabled in the OFF state.
These power management components are designed to support application processors and
associated peripherals. DC-DC1 and DC-DC2 are intended to provide power to the processor voltage
domains; DC-DC3 is suitable for powering memory circuits or for use as a pre-regulator for the LDOs.
The output voltage of each of the buck converters and regulators is programmable in software
through control registers.
The WM8310 can execute programmable sequences of enabling and disabling the DC-DC Buck
Converters and LDO Regulators as part of the transitions between the ON, OFF and SLEEP power
states. The WM8310 power management circuits can also interface with configurable hardware
control functions supported via GPIO pins. These include GPIO inputs for selecting alternate voltages
or operating modes, and GPIO outputs for controlling external power management circuits.
The configuration of the power management circuits, together with some of the GPIO pins and other
functions, may be stored in the integrated OTP memory. This avoids any dependence on a host
processor to configure the WM8310 at start-up. See Section 14 for details of the OTP memory.
15.2 DC-DC CONVERTER AND LDO REGULATOR CONTROL
The integrated DC-DC Converters and LDO Regulators can each be enabled in the ON or SLEEP
power states by setting the DCm_ENA or LDOn_ENA bits as defined in Section 15.12.1. Note that
setting the DCm_ENA or LDOn_ENA bits in the OFF state will not enable the DC-DC Converters or
LDO Regulators. These bits should not be written to when the WM8310 is in the OFF state; writing to
these bits in the OFF state may cause a malfunction.
In many applications, there will be no need to write to the DCm_ENA or LDOn_ENA bits, as these bits
are controlled by the WM8310 when a power state transition is scheduled. Dynamic, run-time control
of the DC-DC Converters or LDO Regulators is also possible by writing to these registers. Note that
the DC-DC4 Boost Converter cannot be configured as part of the power state transitions; this
Converter must always be enabled by writing to the DC4_ENA bit.
The DC-DC Converters and LDO Regulators can be assigned to a Hardware Enable (GPIO) input for
external enable/disable control. In this case, the converter or regulator is not affected by the
associated DCm_ENA or LDOn_ENA bits. See Section 15.3 for further details.
The WM8310 can also control other circuits, including external DC-DC Converters or LDO Regulators
using the External Power Enable (EPE) outputs. The External Power Enable outputs are alternate
functions supported via GPIO - see Section 21. The External Power Enable outputs can be controlled
in the same way as the internal DC-DC Converters and LDO Regulators. The associated control bits
are EPE1_ENA and EPE2_ENA, as defined in Section 15.12.1.
LDO Regulator 11 is a Low Power LDO Regulator, which is configured differently to the other LDOs. It
is a low-power LDO intended for “Always-On” functions external to the WM8310 and can be enabled
when the WM8310 is in the OFF power state.
When LDO11_FRCENA is set, then LDO11 is enabled at all times in the OFF, ON and SLEEP states.
Note that LDO11 is always disabled in the BACKUP and NO POWER states. See Section 15.12.4 for
the definition of LDO11_FRCENA.
The current commanded state of each of the DC-DC Converters, LDO Regulators and EPE outputs is
indicated in the DCm_STS, LDOn_STS and EPEn_STS register bits.
If a fault condition causes any converter or regulator to be disabled, then the associated _ENA and
_STS fields are reset to 0.
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15.3 TIMESLOT CONTROL AND HARDWARE ENABLE (GPIO) CONTROL
The DC-DC Converters 1-3 and LDO Regulators 1-11 may be programmed to switch on in a selected
timeslot within the ON sequence using the DCm_ON_SLOT or LDOn_ON_SLOT fields. These
register fields are defined in Section 15.12.2 and Section 15.12.4. Alternatively, these fields can be
used to assign a converter / regulator to one of the Hardware Enable Inputs. (The Hardware Enable
Inputs are alternate functions supported via GPIO - see Section 21.)
Converters / regulators which are assigned to one of the Hardware Enable Inputs are enabled or
disabled according to the logic level of the respective GPIO input in the ON or SLEEP power states.
The Hardware Enable Inputs are effective from the end of the ON sequence until the start of the OFF
sequence. Note that the GPIO Hardware Enable function is not the same as the GPIO Hardware
Control function.
Any converters / regulators which are assigned to timeslots within the ON sequence will be disabled
in the reverse sequence when an OFF sequence is scheduled. Any converters / regulators which are
not assigned to timeslots, or are assigned to Hardware Enable Inputs, will be disabled immediately at
the start of the OFF sequence.
Each of the converters / regulators may also be programmed to be disabled in a selected timeslot
within the SLEEP sequence using the DCm_SLP_SLOT or LDOn_SLP_SLOT fields. In the case of
converters / regulators which are not disabled by the SLEEP sequence, these fields determine in
which timeslot each converter or regulator enters its SLEEP configuration.
Any converters / regulators which are disabled as part of the SLEEP sequence will be enabled in the
reverse sequence when a WAKE transition is scheduled.
By default, the OFF sequence is the reverse of the ON sequence. Similarly, the WAKE sequence is
the reverse of the SLEEP sequence. If a different behaviour is required, this can be achieved by
writing to the _ON_SLOT or _SLP_SLOT registers between transitions in order to re-define the
sequences.
Any converters / regulators which are assigned to Hardware Enable Inputs will remain under control
of the Hardware Enable Inputs in the SLEEP power state. In this case, the DCm_SLP_SLOT or
LDOn_SLP_SLOT fields determine in which timeslot the converter / regulator enters its SLEEP
configuration.
The WM8310 will control the DCm_ENA or LDOn_ENA bit (see Section 15.2) for any converter /
regulator that is enabled or disabled during the power state transitions. In the case of a converter /
regulator assigned to a Hardware Enable (GPIO) input, the DCm_ENA or LDOn_ENA bit is not
controlled and the converter / regulator is not affected by this bit.
The DC-DC converters include a soft-start feature that limits in-rush current at start-up. However, in
order to further reduce supply in-rush current, it is recommended that the individual converters are
programmed to start up in different time slots within the start-up sequence, as described in
Section 11.3.
Similarly, it is recommended that the individual LDO regulators are programmed to start up in different
time slots within the start-up sequence, as described in Section 11.3.
Note that the DC-DC4 Boost Converter cannot be configured as part of the power state transitions;
this Converter must always be enabled by writing to the DC4_ENA bit.
The External Power Enable (EPE) outputs, EPE1 and EPE2, may also be assigned to timeslots in the
ON / SLEEP sequences or assigned to Hardware Enable inputs using the EPEn_ON_SLOT and
EPEn_SLP_SLOT fields described in 15.12.5.
Note that a transition from the SLEEP state to the OFF state is not a controlled transition. If an ‘OFF’
event occurs whilst in the SLEEP state, then the WM8310 will select the OFF state, but all the
enabled converters and regulators will be disabled immediately; the time-controlled sequence is not
implemented in this case. See Section 11.3 for details of the WM8310 ‘OFF’ events.
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15.4 OPERATING MODE CONTROL
15.4.1
DC-DC SYNCHRONOUS BUCK CONVERTERS
The DC-DC (Buck) Converters DC-DC1, DC-DC2 and DC-DC3 can be configured to operate in four
different operating modes. The operating modes are summarised in Table 33. For more detailed
information on the DC-DC (Buck) Converter operating modes, see Section 15.15.2.
DC-DC CONVERTER
OPERATING MODE
DESCRIPTION
Forced Continuous Conduction
Mode (FCCM)
High performance mode for all static and transient load
conditions.
Auto Mode: Continuous /
Discontinuous Conduction with
Pulse-Skipping Mode (CCM/DCM
with PS)
High efficiency mode for all static and transient load
conditions. Performance may be less than FCCM mode for
heavy load transients.
Hysteretic Mode
High efficiency mode for light static and light transient loads
only. Maximum load current is restricted; output voltage ripple
is increased.
LDO Mode
Power saving mode for light loads only. High efficiency for
ultra light loads. Low current soft-start control.
Table 33 DC-DC Synchronous Buck Converters Operating Modes
The operating mode of the DC-DC Converters in the ON power state is selected using the
DCm_ON_MODE register fields. The operating mode of the DC-DC Converters in the SLEEP power
state is selected using the DCm_SLP_MODE register fields.
When changing the operating mode of the DC-DC Converters in preparation for an increased load, a
set-up time of 100s should be allowed for the operating mode to be established before applying the
new load.
Note that the operating mode of the DC-DC Converters may also be controlled by the Hardware
Control inputs. The Hardware Control inputs are alternate functions supported via GPIO. See
Section 15.9 for details of Hardware Control.
Note that, for minimum DC-DC3 quiescent current in LDO mode, the converter must first be enabled
in FCCM, CCM/DCM with PS or Hysteretic mode, before LDO mode is selected.
15.4.2
DC-DC BOOST CONVERTERS
The DC-DC4 Boost Converter is enabled by setting the DC4_ENA bit as described in Section 15.2.
Note that this Converter cannot be enabled automatically under timeslot control in the ON transition.
However, the Converter can either be disabled or unchanged in the SLEEP transition, as determined
by DC4_SLPENA.
The Boost Converter is intended to be used as a power supply for either of the Current Sinks, ISINK1
or ISINK2 (see Section 16). The Boost Converter must be configured for the applicable Current Sink
using the DC4_FBSRC bit.
When the DC-DC4 Boost Converter is enabled, its output voltage is regulated in such a way that the
selected ISINK voltage (at ISINK1 or ISINK2) is 0.5V. Output voltages of up to 30V can be generated
in order to support the current that has been selected for the ISINK. The required voltage range must
be set using the DC4_RANGE field in order to ensure stable operation.
If the Boost Converter is used to provide a supply for both ISINKs simultaneously, then the
DC4_RANGE and DC4_FBSRC bits should be set according to whichever of the ISINKs requires the
higher supply voltage.
15.4.3
LDO REGULATORS
The LDO Regulators LDO1 - LDO10 can be configured to operate in Normal operating mode or in
Low Power mode.
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The operating mode of the LDO Regulators in the ON power state is selected using the
LDOn_ON_MODE register fields. The operating mode of the LDO Regulators in the SLEEP power
state is selected using the LDOn_SLP_MODE register fields.
For the standard LDOs, LDO1 - LDO6, two different Low Power modes are provided, offering limited
load current capability and reduced quiescent current. When Low Power mode is selected in the ON
or SLEEP power states, then the LDOn_LP_MODE register bits determine which Low Power mode is
selected.
Note that the operating mode and output voltage of the LDO Regulators may also be controlled by the
Hardware Control inputs. The Hardware Control inputs are alternate functions supported via GPIO.
See Section 15.9 for details of Hardware Control.
15.5 OUTPUT VOLTAGE CONTROL
15.5.1
DC-DC SYNCHRONOUS BUCK CONVERTERS
The output voltage of the DC-DC Converters 1-3 in the ON power state is selected using the
DCm_ON_VSEL register fields. The output voltage of these converters in the SLEEP power state is
selected using the DCm_SLP_VSEL register fields.
DC-DC Converters 1 and 2 support two different switching frequencies, as described in Section 15.6.
Note that the supported output voltage range for these converters is restricted in the 4MHz mode; for
output voltages greater than 1.4V, the 2MHz mode must be used.
The DC-DC Converters are dynamically programmable - the output voltage may be adjusted in
software at any time. These converters are step-down converters; their output voltage can therefore
be lower than the input voltage, but cannot be higher.
Note that the output voltage of DC-DC Converters 1 and 2 may also be controlled using the Dynamic
Voltage Scaling features described in Section 15.6. Software control (using register writes) and
hardware control (using the Hardware DVS Control inputs supported via GPIO) is supported.
Note that the output voltage of the DC-DC Converters may also be controlled by the Hardware
Control inputs. The Hardware Control inputs are alternate functions supported via GPIO. See
Section 15.9 for details of Hardware Control.
When changing the output voltage of DC-DC Converters 1 and 2, the GPIO output “DC-DCm DVS
Done” can be used to confirm the DVS Control has completed; see Section 15.6 for details.
15.5.2
DC-DC BOOST CONVERTERS
The output voltage of the DC-DC4 Boost Converter is set as described in Section 15.4.3. The voltage
is not commanded directly, but is regulated automatically by the WM8310 in order to support the
current that has been commanded for the selected Current Sink (ISINK).
15.5.3
LDO REGULATORS 1-10
The output voltage of the LDO Regulators 1-10 in the ON power state is selected using the
LDOn_ON_VSEL register fields. The output voltage of the LDO Regulators in the SLEEP power state
is selected using the LDOn_SLP_VSEL register fields.
The LDO Regulators are dynamically programmable - the output voltage may be adjusted in software
at any time.
Note that the output voltage of the LDO Regulators may also be controlled by the Hardware Control
inputs. The Hardware Control inputs are alternate functions supported via GPIO. See Section 15.9 for
details of Hardware Control.
15.5.4
LDO REGULATOR 11
The output voltage of LDO11 can be set in two ways - it can be commanded directly, or it can be
commanded to follow the DC-DC Converter 1 output voltage.
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When LDO11_VSEL_SRC = 0, then the output voltage of LDO11 is set by LDO11_ON_VSEL (in the
ON state) or by LDO11_SLP_VSEL (in the SLEEP state) in the same way as the other LDOs.
When LDO11_VSEL_SRC = 1, the output voltage of LDO11 follows the output voltage of DC-DC
Converter 1. This enables both domains to be changed at the same time, eg. the processor core and
processor ‘alive’ domains. In this case, the LDO11 output voltage follows DC1_ON_VSEL or
DC1_SLP_VSEL in the ON state or SLEEP state respectively.
Note that, when LDO11_VSEL_SRC = 1, the LDO11 regulator adopts the nearest achievable output
voltage, which may not be identical to the DC-DC1 voltage, due to the more limited range and
resolution of LDO11 - the output voltage of LDO11 is in the range 0.8V to 1.55V in 50mV steps; the
output voltage of DC-DC1 is in the range 0.6V to 1.8V in 12.5mV steps. If DC-DC1 is disabled, then
the LDO11 voltage tracking feature is not supported, and the LDO11 output voltage will be 0.8V.
15.6 DC-DC SYNCHRONOUS BUCK CONVERTER CONTROL
Soft-Start control is provided for each of the DC-DC synchronous buck converters, using the
DCm_SOFT_START register fields. When a DC-DC Converter is switched on, the soft-start circuit will
apply current limiting in order to control the in-rush current. For DC-DC1 and DC-DC2, the current
limit is increased through up to 8 stages to the full load condition. The DCm_SOFT_START registers
select the duration of these stages. (Note that, under light loads, the full start-up may be achieved in
fewer than 8 stages.) A similar function is provided for DC-DC3, but only 3 intermediate stages are
implemented for this converter.
When DC-DC3 is operating in Hysteretic Mode, the maximum DC output current can be set using the
DC3_STNBY_LIM register. See Section 15.4.1 for details of the DC-DC3 operating modes.
To ensure stable operation, the register fields DCm_CAP must be set for each of the DC-DC
Converters according to the output capacitance. (Note that these fields are set via OTP/ICE settings
only; they cannot be changed by writing to the control register.) The choice of output capacitor is
described in Section 30.3.
When a DC-DC Converter is disabled, the output pin can be configured to be floating or to be actively
discharged. This is selected using DCm_FLT.
DC-DC Converters 1 and 2 also support selectable switching frequency. This can either be 2MHz or
4MHz, according to the DCm_FREQ register field. (Note that these fields are set via OTP/ICE
settings only; they cannot be changed by writing to the control register.) The switching frequency of
DC-DC3 is fixed at 2MHz.
Note that the supported output voltage range for DC-DC Converters 1 and 2 is restricted in the 4MHz
mode; for output voltages greater than 1.4V, the 2MHz mode must be used.
The switching phase of each DC-DC converter can be set using the DCm_PHASE bits. Where two
converters are operating at the same switching frequency, the supply current ripple can be minimised
by selecting a different switching phase for each converter.
The Dynamic Voltage Scaling (DVS) feature on DC-DC1 and DC-DC2 enables hardware or software
selection of an alternate output voltage, DCm_DVS_VSEL. This may be useful if a short-term
variation in output voltage is required.
The DVS voltage (set by DCm_DVS_VSEL) may be selected by setting DCm_DVS_SRC = 01.
Alternatively, the DVS voltage may be selected under control of one of the Hardware DVS Control
inputs supported via the GPIO pins. See Section 21 for details of configuring the GPIO pins as
Hardware DVS Control inputs.
Whenever the DVS voltage is selected by any method, the DVS selection takes precedence over the
ON, SLEEP or Hardware Control (HWC) configuration. See Section 15.9 for details of Hardware
Control options.
The output voltage ramp rate is selectable for DC-DC Converters 1 and 2. The DCm_RATE field
selects the rate of change of output voltage, whether this is in response to an operating mode
transition, or any hardware or software command. Note that the DCm_RATE field is accurate in
Forced Continuous Conduction Mode (FCCM); in other modes, the actual slew rate may be longer in
the case of a decreasing output voltage selection, especially under light load conditions.
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The WM8310 can indicate the status of the Dynamic Voltage Scaling via a GPIO pin configured as a
“DC-DC1 DVS Done” or “DC-DC2 DVS Done” output (see Section 21). When a GPIO pin is
configured to indicate the DVS status, this signal is temporarily de-asserted during a DVS transition
on the associated DC-DC Converter, and is subsequently asserted to indicate the transition has
completed.
Note that the GPIO DVS outputs indicate the progress of all output voltage slews; they are not limited
to transitions associated with DCm_DVS_SRC; the GPIO DVS output also indicates the status of a
slew caused by a write to the DCm_ON_VSEL register, or a slew to the DCm_SLP_VSEL voltage.
Note also that the GPIO DVS outputs are indicators of the DVS control mechanism only; they do not
confirm the output voltage accuracy. The output voltage can be checked using the voltage status bits
if required (see Section 15.2).
15.7 DC-DC BOOST CONVERTER CONTROL
The DC-DC4 Boost Converter is designed as a power source for the Current Sinks described in
Section 16. The associated control registers for DC-DC4 are described in Section 15.4.2.
The Boost Converter uses one or other of the Current Sinks to provide voltage feedback in order to
control the converter output voltage. The selected Current Sink is determined by the DC4_FBSRC
register bit. If the Boost Converter is used to provide a supply for both ISINKs simultaneously, then
the DC4_RANGE and DC4_FBSRC bits should be set according to whichever of the ISINKs requires
the higher supply voltage.
It is important to follow the recommended control sequences for switching on/off the Boost Converter
and Current Sinks. These sequences are described in Section 16.
The maximum current that can be supported by the Boost Converter varies with the output voltage, as
noted in the Electrical Characteristics (see Section 7.2).
The Current Sinks are suited to controlling LED backlight circuits. At low output voltages (eg. 5V), the
DC-DC4 boost converter is capable of supporting currents which exceed the maximum current rating
of the Current Sinks. Please contact Wolfson Applications support if further guidance is required on
configuring DC-DC4 for higher current than is supported by the Current Sinks.
15.8 LDO REGULATOR CONTROL
The LDO Regulators 1-10 can be configured to act as Current Limited Switches by setting the
LDOn_SWI field. When this bit is selected, there is no voltage regulation and the operating mode and
output voltage controls of the corresponding LDO are ignored. In Switch mode, the switch is enabled
(closed) and disabled (opened) by enabling or disabling the LDO.
Note that Switch mode cannot be selected via the OTP memory settings, and must be configured
after the WM8310 has entered the ON state.
When the LDO Regulator is disabled (and Switch mode is not selected), the output pin can be
configured to be floating or to be actively discharged. This is selected using LDOn_FLT.
15.9 HARDWARE CONTROL (GPIO)
The DC-DC Converters, LDO Regulators and EPE outputs may be controlled by the Hardware
Control inputs supported via the GPIO pins. The DCm_HWC_SRC, LDOn_HWC_SRC or
EPEn_HWC_SRC fields determine which of these Hardware Control inputs is effective.
See Section 21 for details of configuring the GPIO pins as Hardware Control inputs. Note that the
GPIO Hardware Control function is not the same as the GPIO Hardware Enable function.
Hardware Control is only possible when the applicable DCm_ENA, LDOn_ENA or EPEn_ENA control
bit is set (see Section 15.2), or if a Hardware Enable has been assigned to the relevant function and
is asserted.
The action taken in response to the selected Hardware Control inputs is configurable for each DC-DC
Converter, LDO Regulator or EPE output. The available options are described below.
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When a Hardware Control input is assigned to a DC-DC Buck Converter (DC-DC1, DC-DC2 or DCDC3), and is asserted, the operating mode and output voltage of the relevant DC-DC Converter is
determined by the DCm_HWC_VSEL and DCm_HWC_MODE fields; this takes precedence over the
normal ON or SLEEP settings.
Note that the Hardware Control input can be used to disable a DC-DC Buck Converter if required, by
setting DCm_HWC_MODE = 01.
When a Hardware Control input is assigned to the DC-DC4 Boost Converter, and is asserted, the
Converter is controlled as determined by the DC4_HWC_MODE field; this takes precedence over the
normal ON or SLEEP settings. The available options are to disable the Converter, or to remain under
control of DC4_ENA.
When a Hardware Control input is assigned to LDO Regulators 1-10, and is asserted, the operating
mode and output voltage of the relevant LDO Regulators is determined by the LDOn_HWC_VSEL
and LDOn_HWC_MODE fields; this takes precedence over the normal ON or SLEEP settings.
Note that, for the standard LDOs (LDO1 - LDO6), when Low Power Mode is selected
(LDOn_HWC_MODE = 00 or 10), then the Low Power mode type is determined by the
LDOn_LP_MODE register bits.
When a Hardware Control input is assigned to the External Power Enable (EPE) outputs, and is
asserted, the relevant EPE outputs are controlled as determined by the EPEn_HWC_ENA field; this
takes precedence over the normal ON or SLEEP settings. The available options are to de-assert the
EPE, or for the EPE to remain under control of EPEn_ENA.
15.10 FAULT PROTECTION
Each of the DC-DC Buck Converters (1 to 3) is monitored for voltage accuracy and fault conditions.
An undervoltage condition is set if the output voltage falls below the required level by more than the
applicable undervoltage margin, as specified in Section 7.1.
The DC-DC4 Boost Converter is monitored for voltage accuracy and fault conditions. The voltage at
ISINK1 or ISINK2 is monitored as an indicator of an overcurrent condition.
Each LDO Regulator (1 to 10) is monitored for voltage accuracy and fault conditions. An undervoltage
condition is set if the output voltage falls below the required level by more than the undervoltage
margin, as specified in Section 7.4.
The DCm_ERR_ACT and LDOn_ERR_ACT fields configure the fault response to an Undervoltage
condition. An Interrupt is always triggered under this condition (see Section 15.13); additional action
can also be selected independently for each converter / regulator. The options are to ignore the fault,
shut down the converter, or to shut down the system. To prevent false alarms during short current
surges, faults are only signalled if the fault condition persists.
If a fault condition is detected, and the selected response is to shut down the converter or regulator,
then the associated _ENA and _STS fields are reset to 0, as described in Section 15.2.
If a fault condition is detected, and the selected response is to shut down the system, then a Device
Reset is triggered, as described in Section 24.1, forcing a transition to the OFF state. The WM8310
will automatically return to the ON state after performing the Device Reset.
Note that, if the fault condition persists, then a maximum of 6 Device Resets will be attempted to
initiate the start-up sequence. If the sequence fails more than 6 times, the WM8310 will remain in the
OFF state until the next valid ON state transition event occurs.
Note that the DC-DC4 Boost Converter will not be automatically enabled following a Device Reset;
this must be re-enabled using the DC4_ENA bit if required.
Note that DC-DC1 and DC-DC2 overvoltage and high current conditions can be detected and
reported as described in Section 15.11. The DCm_ERR_ACT fields have no relation to these
conditions.
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The DC-DC3 Buck Converter has a selectable overvoltage protection feature, controlled by
DC3_OVP. This affects the converter response when DC3 is enabled or when its output voltage is
increased. When the overvoltage protection is enabled, there is less overshoot in the output voltage,
but some oscillation may occur as the voltage settles. This function should only be enabled if steep
load transients are present on the output of DC-DC3 and if voltage overshoot is critical.
15.11 MONITORING AND FAULT REPORTING
Each of the DC-DC Converters (1 to 4) and LDOs (1 to 10) is monitored for voltage accuracy and fault
conditions. An undervoltage condition is detected if the voltage falls below the required level by more
than a pre-determined tolerance. If an undervoltage condition occurs, then this is indicated using the
corresponding status bit(s) defined in Section 15.12.6. An undervoltage condition also triggers an
Undervoltage Interrupt (see Section 15.13). Additional actions to shut down the converter or perform
a Device Reset may also be selected.
The Internal LDO (LDO13) is also monitored for voltage accuracy and fault conditions. An
undervoltage condition in LDO13 is indicated using the INTLDO_UV_STS bit. This undervoltage
condition also causes an OFF transition to be scheduled, as described in Section 11.3.
DC-DC Converters 1 and 2 are monitored for overvoltage conditions. An overvoltage condition is set if
the voltage is more than 100mV above the required level. If an overvoltage condition occurs, then this
is indicated using the corresponding status bit(s). Note that there is no Interrupt or other selectable
response to an overvoltage condition.
The current draw on DC-DC Converters 1 and 2 can be monitored against user-programmable
thresholds in order to detect a high current condition. This feature is enabled using
DCm_HC_IND_ENA and the current threshold is set using DCm_HC_THR. Note that the high current
threshold is not the same as the maximum current capability of the DC-DC Converters, but is set
according to the application requirements. If a high current condition occurs, then this is indicated
using the corresponding status bit(s). A high current condition also triggers a High Current Interrupt
(see Section 15.13).
15.12 POWER MANAGEMENT REGISTER DEFINITIONS
15.12.1 DC-DC CONVERTER AND LDO REGULATOR ENABLE
The Enable and Status register bits for the DC-DC Converters and LDO Regulators are defined in
Table 34.
ADDRESS
BIT
LABEL
R16464 (4050h)
3:0
DCm_ENA
DEFAULT
0
DCDC Enable
DESCRIPTION
DC-DCm Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated
in DCm_STS)
R16465 (4051h)
10:0
LDOn_ENA
0
LDO Enable
LDOn Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated
in LDOn_STS)
R16466 (4052h)
3:0
DCm_STS
0
DCDC Status
DC-DCm Status
0 = Disabled
1 = Enabled
R16467 (4053h)
10:0
LDOn_STS
0
LDO Status
LDOn Status
0 = Disabled
1 = Enabled
Notes:
1.
n is a number between 1 and 11 that identifies the individual LDO Regulator.
2.
m is a number between 1 and 4 that identifies the individual DC-DC Converter.
Table 34 DC-DC Converter and LDO Regulator Control
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The Enable and Status register bits for the External Power Enable (EPE) Controls are defined in
Table 35.
ADDRESS
BIT
R16464 (4050h)
7
LABEL
DEFAULT
EPE2_ENA
0
DCDC Enable
DESCRIPTION
EPE2 Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated
in EPE2_STS)
6
EPE1_ENA
0
EPE1 Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated
in EPE1_STS)
R16466 (4052h)
7
EPE2_STS
0
DCDC Status
EPE2 Status
0 = Disabled
1 = Enabled
6
EPE1_STS
0
EPE1 Status
0 = Disabled
1 = Enabled
Table 35 External Power Enable (EPE) Control
15.12.2 DC-DC SYNCHRONOUS BUCK CONVERTER CONTROL
The register controls for configuring the DC-DC synchronous buck converters 1-3 are defined in Table
36.
Note that the DCm_ON_SLOT fields and the 5 MSBs of DCm_ON_VSEL may also be stored in the
integrated OTP memory. See Section 14 for details.
ADDRESS
BIT
R16470 (4056h)
15:14
DC1 Control 1
LABEL
DC1_RATE
[1:0]
DEFAULT
10
DESCRIPTION
DC-DC1 Voltage Ramp rate
00 = 1 step every 32us
01 = 1 step every 16us
10 = 1 step every 8us
11 = Immediate voltage change
12
DC1_PHASE
0
DC-DC1 Clock Phase Control
0 = Normal
1 = Inverted
9:8
DC1_FREQ
[1:0]
00
DC-DC1 Switching Frequency
00 = Reserved
01 = 2.0MHz
10 = Reserved
11 = 4.0MHz
7
DC1_FLT
0
DC-DC1 Output float
0 = DC-DC1 output discharged when
disabled
1 = DC-DC1 output floating when
disabled
5:4
DC1_SOFT_
START [1:0]
00
DC-DC1 Soft-Start Control
(Duration in each of the 8 startup current
limiting steps.
00 = 32us steps
01 = 64us steps
10 = 128us steps
11 = 256us steps
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ADDRESS
BIT
LABEL
1:0
DC1_CAP
DEFAULT
00
DESCRIPTION
DC-DC1 Output Capacitor
00 = 4.7uF to 20uF
01 = Reserved
10 = 22uF to 47uF
11 = Reserved
R16471 (4057h)
15:14
DC1 Control 2
DC1_ERR_A
CT [1:0]
00
DC-DC1 Error Action (Undervoltage)
00 = Ignore
01 = Shut down converter
10 = Shut down system (Device Reset)
11 = Reserved
Note that an Interrupt is always raised.
12:11
DC1_HWC_
SRC [1:0]
00
DC-DC1 Hardware Control Source
00 = Disabled
01 = Hardware Control 1
10 = Hardware Control 2
11 = Hardware Control 1 or 2
10
DC1_HWC_
VSEL
0
DC-DC1 Hardware Control Voltage
select
0 = Set by DC1_ON_VSEL
1 = Set by DC1_SLP_VSEL
9:8
DC1_HWC_
MODE [1:0]
11
DC-DC1 Hardware Control Operating
Mode
00 = Forced Continuous Conduction
Mode
01 = Disabled
10 = LDO Mode
11 = Hysteretic Mode
6:4
DC1_HC_TH
R [2:0]
000
DC-DC1 High Current threshold
000 = 125mA
001 = 250mA
010 = 375mA
011 = 500mA
100 = 625mA
101 = 750mA
110 = 875mA
111 = 1000mA
0
DC1_HC_IN
D_ENA
0
DC1_ON_SL
OT [2:0]
000
DC-DC1 High Current detect enable
0 = Disabled
1 = Enabled
R16472 (4058h)
DC1 ON Config
15:13
DC-DC1 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
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ADDRESS
BIT
LABEL
DEFAULT
9:8
DC1_ON_M
ODE [1:0]
00
DESCRIPTION
DC-DC1 ON Operating Mode
00 = Forced Continuous Conduction
Mode
01 = Auto Mode (Continuous /
Discontinuous Conduction with PulseSkipping)
10 = LDO Mode
11 = Hysteretic Mode
6:2
DC1_ON_VS
EL [6:2]
00000
1:0
DC1_ON_VS
EL [1:0]
00
DC-DC1 ON Voltage select
DC1_ON_VSEL[6:0] selects the DCDC1 output voltage from 0.6V to 1.8V in
12.5mV steps.
DC1_ON_VSEL[6:2] also exist in
ICE/OTP memory, controlling the
voltage in 50mV steps.
DC1_ON_VSEL[6:0] is coded as
follows:
00h to 08h = 0.6V
09h = 0.6125V
…
48h = 1.4V (see note)
…
67h = 1.7875V
68h to 7Fh = 1.8V
Note - Maximum output voltage
selection in 4MHz switching mode is
48h (1.4V).
R16473 (4059h)
15:13
DC1 SLEEP
Control
DC1_SLP_S
LOT [2:0]
000
DC-DC1 SLEEP Slot select
000 = SLEEP voltage / operating mode
transition in Timeslot 5
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
110 = SLEEP voltage / operating mode
transition in Timeslot 3
111 = SLEEP voltage / operating mode
transition in Timeslot 1
If DC-DC1 is assigned to a Hardware
Enable Input, then codes 001-101 select
in which timeslot the converter enters its
SLEEP condition.
9:8
DC1_SLP_M
ODE [1:0]
00
DC-DC1 SLEEP Operating Mode
00 = Forced Continuous Conduction
Mode
01 = Auto Mode (Continuous /
Discontinuous Conduction with PulseSkipping)
10 = LDO Mode
11 = Hysteretic Mode
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ADDRESS
BIT
LABEL
DEFAULT
6:0
DC1_SLP_V
SEL [6:0]
000_0000
DESCRIPTION
DC-DC1 SLEEP Voltage select
0.6V to 1.8V in 12.5mV steps
00h to 08h = 0.6V
09h = 0.6125V
…
48h = 1.4V (see note)
…
67h = 1.7875V
68h to 7Fh = 1.8V
Note - Maximum output voltage
selection in 4MHz switching mode is
48h (1.4V).
R16474 (405Ah)
12:11
DC1 DVS
Control
DC1_DVS_S
RC [1:0]
00
DC-DC1 DVS Control Source
00 = Disabled
01 = Enabled
10 = Controlled by Hardware DVS1
11 = Controlled by Hardware DVS2
6:0
DC1_DVS_V
SEL [6:0]
000_0000
DC-DC1 DVS Voltage select
0.6V to 1.8V in 12.5mV steps
00h to 08h = 0.6V
09h = 0.6125V
…
48h = 1.4V (see note)
…
67h = 1.7875V
68h to 7Fh = 1.8V
Note - Maximum output voltage
selection in 4MHz switching mode is
48h (1.4V).
R16475 (405Bh)
15:14
DC2 Control 1
DC2_PHASE
0
Same as DC-DC1
DC2_FREQ
[1:0]
00
Same as DC-DC1
DC2_FLT
0
Same as DC-DC1
5:4
DC2_SOFT_
START [1:0]
00
Same as DC-DC1
1:0
DC2_CAP
00
Same as DC-DC1
15:14
DC2_ERR_A
CT [1:0]
00
Same as DC-DC1
12:11
DC2_HWC_
SRC [1:0]
00
Same as DC-DC1
10
DC2_HWC_
VSEL
0
Same as DC-DC1
9:8
DC2_HWC_
MODE [1:0]
11
Same as DC-DC1
6:4
DC2_HC_TH
R [2:0]
000
Same as DC-DC1
0
DC2_HC_IN
D_ENA
0
Same as DC-DC1
15:13
DC2_ON_SL
OT [2:0]
000
Same as DC-DC1
9:8
DC2_ON_M
ODE [1:0]
00
Same as DC-DC1
DC2 ON Config
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Same as DC-DC1
12
DC2 Control 2
R16477 (405Dh)
10
9:8
7
R16476 (405Ch)
DC2_RATE
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ADDRESS
R16478 (405Eh)
DC2 SLEEP
Control
BIT
LABEL
DEFAULT
6:2
DC2_ON_VS
EL [6:2]
00000
DESCRIPTION
1:0
DC2_ON_VS
EL [1:0]
00
15:13
DC2_SLP_S
LOT [2:0]
000
Same as DC-DC1
9:8
DC2_SLP_M
ODE [1:0]
00
Same as DC-DC1
6:0
DC2_SLP_V
SEL [6:0]
000_0000
Same as DC-DC1
Same as DC-DC1
12:11
DC2_DVS_S
RC [1:0]
00
Same as DC-DC1
DC2 DVS
Control
6:0
DC2_DVS_V
SEL [6:0]
000_0000
Same as DC-DC1
R16480 (4060h)
12
DC3_PHASE
0
Same as DC-DC1
DC3 Control 1
7
DC3_FLT
0
Same as DC-DC1
DC3_SOFT_
START [1:0]
01
DC-DC3 Soft-Start Control
R16479 (405Fh)
5:4
(Duration in each of the 3 intermediate
startup current limiting steps.)
00 = Immediate start-up
01 = 512us steps
10 = 4.096ms steps
11 = 32.768ms steps
3:2
DC3_STNBY
_LIM [1:0]
01
DC-DC3 Current Limit
Sets the maximum DC output current in
Hysteretic Mode. Typical values shown
below.
00 = 100mA
01 = 200mA
10 = 400mA
11 = 800mA
Protected by user key.
1:0
DC3_CAP
00
DC-DC3 Output Capacitor
00 = 10uF to 20uF
01 = 10uF to 20uF
10 = 22uF to 45uF
11 = 47uF to 100uF
R16481 (4061h)
15:14
DC3_ERR_A
CT [1:0]
00
Same as DC-DC1
12:11
DC3_HWC_
SRC [1:0]
00
Same as DC-DC1
10
DC3_HWC_
VSEL
0
Same as DC-DC1
9:8
DC3_HWC_
MODE [1:0]
11
Same as DC-DC1
DC3_OVP
0
DC-DC3 Overvoltage Protection
DC3 Control 2
7
0 = Disabled
1 = Enabled
R16482 (4062h)
15:13
DC3_ON_SL
OT [2:0]
000
Same as DC-DC1
9:8
DC3_ON_M
ODE [1:0]
00
Same as DC-DC1
6:2
DC3_ON_VS
EL [6:2]
00000
DC3 ON Config
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ADDRESS
BIT
LABEL
DEFAULT
1:0
DC3_ON_VS
EL [1:0]
00
DESCRIPTION
DC3_ON_VSEL[6:0] selects the DCDC3 output voltage from 0.85V to 3.4V
in 25mV steps.
DC3_ON_VSEL[6:2] also exist in
ICE/OTP memory, controlling the
voltage in 100mV steps.
DC3_ON_VSEL[6:0] is coded as
follows:
00h = 0.85V
01h = 0.875V
…
65h = 3.375V
66h to 7Fh = 3.4V
R16483 (4063h)
DC3 SLEEP
Control
15:13
DC3_SLP_S
LOT [2:0]
000
Same as DC-DC1
9:8
DC3_SLP_M
ODE [1:0]
00
Same as DC-DC1
6:0
DC3_SLP_V
SEL [6:0]
000_0000
DC-DC3 SLEEP Voltage select
0.85V to 3.4V in 25mV steps
00h = 0.85V
01h = 0.875V
…
65h = 3.375V
66h to 7Fh = 3.4V
Table 36 DC-DC (Buck) Converter Control
15.12.3 DC-DC BOOST CONVERTER CONTROL
The register controls for configuring the DC-DC4 boost converter are defined in Table 37.
Note that the DC4_RANGE control register is locked by the WM8310 User Key. This register can only
be changed by writing the appropriate code to the Security register, as described in Section 12.4 for
further details.
ADDRESS
BIT
LABEL
DEFAULT
R16484 (4064h)
15:14
DC4_ERR_A
CT [1:0]
00
DC4 Control
DESCRIPTION
DC-DC4 Error Action (Undervoltage)
00 = Ignore
01 = Shut down converter
10 = Shut down system (Device Reset)
11 = Reserved
Note that an Interrupt is always raised.
12:11
DC4_HWC_
SRC[1:0]
00
DC-DC4 Hardware Control Source
00 = Disabled
01 = Hardware Control 1
10 = Hardware Control 2
11 = Hardware Control 1 or 2
8
DC4_HWC_
MODE
1
DC-DC4 Hardware Control Operating
Mode
0 = DC-DC4 is controlled by DC4_ENA
1 = DC-DC4 is disabled when Hardware
Control Source is asserted
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ADDRESS
BIT
LABEL
DEFAULT
3:2
DC4_RANG
E[1:0]
01
DESCRIPTION
Selects the voltage range for DC-DC4
00 = 20V < VOUT <= 30V
01 = 10V < VOUT <= 20V
10 = 6.5V < VOUT <= 10V
11 = Reserved
Protected by user key
0
DC4_FBSRC
0
DC-DC4 Voltage Feedback source
0 = ISINK1
1 = ISINK2
R16485 (4065h)
8
DC4 SLEEP
Control
DC4_SLPEN
A
0
DC-DC4 SLEEP Enable
0 = Disabled
1 = Controlled by DC4_ENA
Table 37 DC-DC (Boost) Converter Control
15.12.4 LDO REGULATOR CONTROL
The register controls for configuring the LDO Regulators 1-6 are defined in Table 38.
Note that the LDOn_ON_SLOT and LDOn_ON_VSEL fields may also be stored in the integrated OTP
memory. See Section 14 for details.
ADDRESS
BIT
LABEL
DEFAULT
R16488 (4068h)
15:14
LDO1_ERR_
ACT [1:0]
00
LDO1 Control
DESCRIPTION
LDO1 Error Action (Undervoltage)
00 = Ignore
01 = Shut down regulator
10 = Shut down system (Device Reset)
11 = Reserved
Note that an Interrupt is always raised.
12:11
LDO1_HWC
_SRC [1:0]
00
LDO1 Hardware Control Source
00 = Disabled
01 = Hardware Control 1
10 = Hardware Control 2
11 = Hardware Control 1 or 2
10
LDO1_HWC
_VSEL
0
LDO1_HWC
_MODE
10
LDO1 Hardware Control Voltage select
0 = Set by LDO1_ON_VSEL
1 = Set by LDO1_SLP_VSEL
9:8
LDO1 Hardware Control Operating
Mode
00 = Low Power mode
01 = Turn converter off
10 = Low Power mode
11 = Set by LDO1_ON_MODE
7
LDO1_FLT
0
LDO1 Output float
0 = LDO1 output discharged when
disabled
1 = LDO1 output floating when disabled
6
LDO1_SWI
0
LDO1 Switch Mode
0 = LDO mode
1 = Switch mode
0
LDO1_LP_M
ODE
0
LDO1 Low Power Mode Select
0 = 50mA (reduced quiescent current)
1 = 20mA (minimum quiescent current)
Selects which Low Power mode is used
in ON, SLEEP, or under HWC modes.
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ADDRESS
BIT
LABEL
DEFAULT
R16489 (4069h)
15:13
LDO1_ON_S
LOT [2:0]
000
LDO1 ON
Control
DESCRIPTION
LDO1 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
8
LDO1_ON_
MODE
0
LDO1 ON Operating Mode
0 = Normal mode
1 = Low Power mode
4:0
LDO1_ON_V
SEL [4:0]
00000
LDO1 ON Voltage select
0.9V to 1.6V in 50mV steps
1.7V to 3.3V in 100mV steps
00h = 0.90V
01h = 0.95V
…
0Eh = 1.60V
0Fh = 1.70V
…
1Eh = 3.20V
1Fh = 3.30V
R16490 (406Ah)
15:13
LDO1 SLEEP
Control
LDO1_SLP_
SLOT [2:0]
000
LDO1 SLEEP Slot select
000 = SLEEP voltage / operating mode
transition in Timeslot 5
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
110 = SLEEP voltage / operating mode
transition in Timeslot 3
111 = SLEEP voltage / operating mode
transition in Timeslot 1
If LDO1 is assigned to a Hardware
Enable Input, then codes 001-101 select
in which timeslot the regulator enters its
SLEEP condition.
8
LDO1_SLP_
MODE
0
LDO1_SLP_
VSEL [4:0]
00000
LDO1 SLEEP Operating Mode
0 = Normal mode
1 = Low Power mode
4:0
LDO1 SLEEP Voltage select
0.9V to 1.6V in 50mV steps
1.7V to 3.3V in 100mV steps
00h = 0.90V
01h = 0.95V
…
0Eh = 1.60V
0Fh = 1.70V
…
1Eh = 3.20V
1Fh = 3.30V
R16491 (406Bh)
w
15:14
LDO2_ERR_
ACT [1:0]
00
Same as LDO1
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ADDRESS
LDO2 Control
R16492 (406Ch)
LDO2 ON
Control
R16493 (406Dh)
LDO2 SLEEP
Control
R16494 (406Eh)
BIT
LABEL
DEFAULT
12:11
LDO2_HWC
_SRC [1:0]
00
Same as LDO1
10
LDO2_HWC
_VSEL
0
Same as LDO1
9:8
LDO2_HWC
_MODE
10
Same as LDO1
7
LDO2_FLT
0
Same as LDO1
6
LDO2_SWI
0
Same as LDO1
0
LDO2_LP_M
ODE
0
Same as LDO1
15:13
LDO2_ON_S
LOT [2:0]
000
Same as LDO1
0
Same as LDO1
8
4:0
LDO2_ON_V
SEL [4:0]
00000
Same as LDO1
15:13
LDO2_SLP_
SLOT [2:0]
000
Same as LDO1
8
LDO2_SLP_
MODE
0
Same as LDO1
4:0
LDO2_SLP_
VSEL [4:0]
00000
Same as LDO1
15:14
LDO3_ERR_
ACT [1:0]
00
Same as LDO1
12:11
LDO3_HWC
_SRC [1:0]
00
Same as LDO1
10
LDO3_HWC
_VSEL
0
Same as LDO1
9:8
LDO3_HWC
_MODE
10
Same as LDO1
7
LDO3_FLT
0
Same as LDO1
6
LDO3_SWI
0
Same as LDO1
0
LDO3_LP_M
ODE
0
Same as LDO1
15:13
LDO3_ON_S
LOT [2:0]
000
Same as LDO1
0
Same as LDO1
LDO3 Control
R16495 (406Fh)
LDO3 ON
Control
R16496 (4070h)
LDO3 SLEEP
Control
R16497 (4071h)
8
LDO3_ON_
MODE
4:0
LDO3_ON_V
SEL [4:0]
00000
Same as LDO1
15:13
LDO3_SLP_
SLOT [2:0]
000
Same as LDO1
8
LDO3_SLP_
MODE
0
Same as LDO1
4:0
LDO3_SLP_
VSEL [4:0]
00000
Same as LDO1
15:14
LDO4_ERR_
ACT [1:0]
00
Same as LDO1
12:11
LDO4_HWC
_SRC [1:0]
00
Same as LDO1
10
LDO4_HWC
_VSEL
0
Same as LDO1
9:8
LDO4_HWC
_MODE
10
Same as LDO1
7
LDO4_FLT
0
Same as LDO1
6
LDO4_SWI
0
Same as LDO1
LDO4 Control
w
LDO2_ON_
MODE
DESCRIPTION
PP, May 2012, Rev 3.1
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WM8310
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ADDRESS
R16498 (4072h)
LDO4 ON
Control
R16499 (4073h)
LDO4 SLEEP
Control
R16500 (4074h)
BIT
LABEL
DEFAULT
0
LDO4_LP_M
ODE
0
Same as LDO1
15:13
LDO4_ON_S
LOT [2:0]
000
Same as LDO1
0
Same as LDO1
8
4:0
LDO4_ON_V
SEL [4:0]
00000
Same as LDO1
15:13
LDO4_SLP_
SLOT [2:0]
000
Same as LDO1
8
LDO4_SLP_
MODE
0
Same as LDO1
4:0
LDO4_SLP_
VSEL [4:0]
00000
Same as LDO1
15:14
LDO5_ERR_
ACT [1:0]
00
Same as LDO1
12:11
LDO5_HWC
_SRC [1:0]
00
Same as LDO1
10
LDO5_HWC
_VSEL
0
Same as LDO1
9:8
LDO5_HWC
_MODE
10
Same as LDO1
7
LDO5_FLT
0
Same as LDO1
6
LDO5_SWI
0
Same as LDO1
0
LDO5_LP_M
ODE
0
Same as LDO1
15:13
LDO5_ON_S
LOT [2:0]
000
Same as LDO1
0
Same as LDO1
LDO5 Control
R16501 (4075h)
LDO5 ON
Control
R16502 (4076h)
LDO5 SLEEP
Control
R16503 (4077h)
8
LDO6 ON
Control
LDO5_ON_V
SEL [4:0]
00000
Same as LDO1
15:13
LDO5_SLP_
SLOT [2:0]
000
Same as LDO1
8
LDO5_SLP_
MODE
0
Same as LDO1
4:0
LDO5_SLP_
VSEL [4:0]
00000
Same as LDO1
15:14
LDO6_ERR_
ACT [1:0]
00
Same as LDO1
12:11
LDO6_HWC
_SRC [1:0]
00
Same as LDO1
10
LDO6_HWC
_VSEL
0
Same as LDO1
9:8
LDO6_HWC
_MODE
10
Same as LDO1
7
LDO6_FLT
0
Same as LDO1
6
LDO6_SWI
0
Same as LDO1
0
LDO6_LP_M
ODE
0
Same as LDO1
15:13
LDO6_ON_S
LOT [2:0]
000
Same as LDO1
0
Same as LDO1
00000
Same as LDO1
8
4:0
w
LDO5_ON_
MODE
4:0
LDO6 Control
R16504 (4078h)
LDO4_ON_
MODE
DESCRIPTION
LDO6_ON_
MODE
LDO6_ON_V
SEL [4:0]
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ADDRESS
BIT
LABEL
DEFAULT
R16505 (4079h)
15:13
LDO6_SLP_
SLOT [2:0]
000
Same as LDO1
8
LDO6_SLP_
MODE
0
Same as LDO1
4:0
LDO6_SLP_
VSEL [4:0]
00000
Same as LDO1
LDO6 SLEEP
Control
DESCRIPTION
Table 38 LDO Regulators 1-6 Control
The register controls for configuring the LDO Regulators 7-10 are defined in Table 39.
Note that the LDOn_ON_SLOT and LDOn_ON_VSEL fields may also be stored in the integrated OTP
memory. See Section 14 for details.
ADDRESS
BIT
LABEL
DEFAULT
R16506 (407Ah)
15:14
LDO7_ERR_
ACT [1:0]
00
LDO7 Control
DESCRIPTION
LDO7 Error Action (Undervoltage)
00 = Ignore
01 = Shut down regulator
10 = Shut down system (Device Reset)
11 = Reserved
Note that an Interrupt is always raised.
12:11
LDO7_HWC
_SRC [1:0]
00
LDO7 Hardware Control Source
00 = Disabled
01 = Hardware Control 1
10 = Hardware Control 2
11 = Hardware Control 1 or 2
10
LDO7_HWC
_VSEL
0
LDO7 Hardware Control Voltage select
0 = Set by LDO7_ON_VSEL
1 = Set by LDO7_SLP_VSEL
9:8
LDO7_HWC
_MODE
00
LDO7 Hardware Control Operating
Mode
00 = Low Power mode
01 = Turn converter off
10 = Low Power mode
11 = Set by LDO7_ON_MODE
7
LDO7_FLT
0
LDO7 Output float
0 = LDO7 output discharged when
disabled
1 = LDO7 output floating when disabled
6
LDO7_SWI
0
LDO7 Switch Mode
0 = LDO mode
1 = Switch mode
R16507 (407Bh)
15:13
LDO7 ON
Control
LDO7_ON_S
LOT [2:0]
000
LDO7 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
8
LDO7_ON_
MODE
0
LDO7 ON Operating Mode
0 = Normal mode
1 = Low Power mode
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ADDRESS
BIT
LABEL
DEFAULT
4:0
LDO7_ON_V
SEL [4:0]
00000
DESCRIPTION
LDO7 ON Voltage select
1.0V to 1.6V in 50mV steps
1.7V to 3.5V in 100mV steps
00h = 1.00V
01h = 1.05V
02h = 1.10V
…
0Ch = 1.60V
0Dh = 1.70V
…
1Eh = 3.40V
1Fh = 3.50V
R16508 (407Ch)
15:13
LDO7 SLEEP
Control
LDO7_SLP_
SLOT [2:0]
000
LDO7 SLEEP Slot select
000 = SLEEP voltage / operating mode
transition in Timeslot 5
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
110 = SLEEP voltage / operating mode
transition in Timeslot 3
111 = SLEEP voltage / operating mode
transition in Timeslot 1
If LDO7 is assigned to a Hardware
Enable Input, then codes 001-101 select
in which timeslot the regulator enters its
SLEEP condition.
8
LDO7_SLP_
MODE
0
LDO7_SLP_
VSEL [4:0]
00000
LDO7 SLEEP Operating Mode
0 = Normal mode
1 = Low Power mode
4:0
LDO7 SLEEP Voltage select
1.0V to 1.6V in 50mV steps
1.7V to 3.5V in 100mV steps
00h = 1.00V
01h = 1.05V
02h = 1.10V
…
0Ch = 1.60V
0Dh = 1.70V
…
1Eh = 3.40V
1Fh = 3.50V
R16509 (407Dh)
15:14
LDO8_ERR_
ACT [1:0]
00
Same as LDO7
12:11
LDO8_HWC
_SRC [1:0]
00
Same as LDO7
10
LDO8_HWC
_VSEL
0
Same as LDO7
9:8
LDO8_HWC
_MODE
00
Same as LDO7
7
LDO8_FLT
0
Same as LDO7
6
LDO8_SWI
0
Same as LDO7
000
Same as LDO7
LDO8 Control
R16510 (407Eh)
w
15:13
LDO8_ON_S
LOT [2:0]
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ADDRESS
LDO8 ON
Control
R16511 (407Fh)
LDO8 SLEEP
Control
R16512 (4080h)
BIT
8
LDO9 ON
Control
DEFAULT
DESCRIPTION
0
Same as LDO7
4:0
LDO8_ON_V
SEL [4:0]
00000
Same as LDO7
15:13
LDO8_SLP_
SLOT [2:0]
000
Same as LDO7
8
LDO8_SLP_
MODE
0
Same as LDO7
4:0
LDO8_SLP_
VSEL [4:0]
00000
Same as LDO7
15:14
LDO9_ERR_
ACT [1:0]
00
Same as LDO7
12:11
LDO9_HWC
_SRC [1:0]
00
Same as LDO7
10
LDO9_HWC
_VSEL
0
Same as LDO7
9:8
LDO9_HWC
_MODE
00
Same as LDO7
7
LDO9_FLT
0
Same as LDO7
6
LDO9_SWI
0
Same as LDO7
000
Same as LDO7
0
Same as LDO7
LDO9 Control
R16513 (4081h)
LABEL
LDO8_ON_
MODE
15:13
8
LDO9_ON_S
LOT [2:0]
LDO9_ON_
MODE
4:0
LDO9_ON_V
SEL [4:0]
00000
Same as LDO7
15:13
LDO9_SLP_
SLOT [2:0]
000
Same as LDO7
8
LDO9_SLP_
MODE
0
Same as LDO7
4:0
LDO9_SLP_
VSEL [4:0]
00000
Same as LDO7
15:14
LDO10_ERR
_ACT [1:0]
00
Same as LDO7
12:11
LDO10_HW
C_SRC [1:0]
00
Same as LDO7
10
LDO10_HW
C_VSEL
0
Same as LDO7
9:8
LDO10_HW
C_MODE
00
Same as LDO7
7
LDO10_FLT
0
Same as LDO7
6
LDO10_SWI
0
Same as LDO7
15:13
LDO10_ON_
SLOT [2:0]
000
Same as LDO7
8
LDO10_ON_
MODE
0
Same as LDO7
4:0
LDO10_ON_
VSEL [4:0]
00000
Same as LDO7
R16517 (4085h)
15:13
LDO10_SLP
_SLOT [2:0]
000
Same as LDO7
LDO10 SLEEP
Control
8
LDO10_SLP
_MODE
0
Same as LDO7
4:0
LDO10_SLP
_VSEL [4:0]
00000
Same as LDO7
R16514 (4082h)
LDO9 SLEEP
Control
R16515 (4083h)
LDO10 Control
R16516 (4084h)
LDO10 ON
Control
Table 39 LDO Regulators 7-10 Control
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The register controls for configuring the LDO Regulator 11 are defined in Table 40.
Note that the LDO11_ON_SLOT and LDO11_ON_VSEL fields may also be stored in the integrated
OTP memory. See Section 14 for details.
ADDRESS
BIT
LABEL
DEFAULT
R16519 (4087h)
15:13
LDO11_ON_
SLOT [2:0]
000
LDO11 ON
Control
DESCRIPTION
LDO11 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
12
LDO11_FRC
ENA
0
LDO11 Force Enable (forces LDO11 to
be enabled at all times in the OFF, ON
and SLEEP states)
0 = Disabled
1 = Enabled
7
LDO11_VSE
L_SRC
0
LDO11 Voltage Select source
0 = Normal (LDO11 settings)
1 = Same as DC-DC Converter 1
3:0
LDO11 ON Voltage select
LDO11_ON_
VSEL [3:0]
0.80V to 1.55V in 50mV steps
0h = 0.80V
1h = 0.85V
2h = 0.90V
…
Eh = 1.50V
Fh = 1.55V
R16520 (4088h)
15:13
LDO11 SLEEP
Control
LDO11_SLP
_SLOT [2:0]
000
LDO11 SLEEP Slot select
000 = SLEEP voltage / operating mode
transition in Timeslot 5
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
110 = SLEEP voltage / operating mode
transition in Timeslot 3
111 = SLEEP voltage / operating mode
transition in Timeslot 1
If LDO11 is assigned to a Hardware
Enable Input, then codes 001-101 select
in which timeslot the regulator enters its
SLEEP condition.
3:0
LDO11_SLP
_VSEL [3:0]
LDO11 SLEEP Voltage select
0.80V to 1.55V in 50mV steps
0h = 0.80V
1h = 0.85V
2h = 0.90V
…
Eh = 1.50V
Fh = 1.55V
Table 40 LDO Regulator 11 Control
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15.12.5 EXTERNAL POWER ENABLE (EPE) CONTROL
The register controls for configuring the External Power Enable (EPE) outputs are defined in Table
41.
Note that the EPE1_ON_SLOT and EPE2_ON_SLOT fields may also be stored in the integrated OTP
memory. See Section 14 for details.
ADDRESS
BIT
LABEL
DEFAULT
R16486 (4066h)
15:13
EPE1_ON_S
LOT [2:0]
000
EPE1 Control
DESCRIPTION
EPE1 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
12:11
EPE1_HWC
_SRC [1:0]
00
EPE1 Hardware Control Source
00 = Disabled
01 = Hardware Control 1
10 = Hardware Control 2
11 = Hardware Control 1 or 2
8
EPE1_HWC
ENA
0
EPE1 Hardware Control Enable
0 = EPE1 is controlled by EPE1_ENA
(Hardware Control input(s) are ignored)
1 = EPE1 is controlled by HWC inputs
(Hardware Control input(s) force EPE1
to be de-asserted)
7:5
EPE1_SLP_
SLOT [2:0]
000
EPE1 SLEEP Slot select
000 = No action
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
110 = No action
111 = No action
R16487 (4067h)
15:13
EPE2_ON_S
LOT [2:0]
000
Same as EPE1
12:11
EPE2_HWC
_SRC [1:0]
00
Same as EPE1
8
EPE2_HWC
ENA
0
Same as EPE1
7:5
EPE2_SLP_
SLOT [2:0]
000
Same as EPE1
EPE2 Control
Table 41 External Power Enable (EPE) Control
15.12.6 MONITORING AND FAULT REPORTING
The overvoltage, undervoltage and high current status registers are defined in Table 42.
ADDRESS
BIT
LABEL
DEFAULT
R16468 (4054h)
13
DC2_OV_ST
S
0
DC1_OV_ST
S
0
DCDC UV
Status
DESCRIPTION
DC-DC2 Overvoltage Status
0 = Normal
1 = Overvoltage
12
DC-DC1 Overvoltage Status
0 = Normal
1 = Overvoltage
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ADDRESS
BIT
LABEL
DEFAULT
9
DC2_HC_ST
S
0
DC1_HC_ST
S
0
DESCRIPTION
DC-DC2 High Current Status
0 = Normal
1 = High Current
8
DC-DC1 High Current Status
0 = Normal
1 = High Current
3:0
DCm_UV_S
TS
0
INTLDO_UV
_STS
0
DC-DCm Undervoltage Status
0 = Normal
1 = Undervoltage
R16469 (4055h)
15
LDO UV Status
LDO13 (Internal LDO) Undervoltage
Status
0 = Normal
1 = Undervoltage
9:0
LDOn_UV_S
TS
0
LDOn Undervoltage Status
0 = Normal
1 = Undervoltage
Notes:
1.
n is a number between 1 and 10 that identifies the individual LDO Regulator (LDO1 - 10).
2.
m is a number between 1 and 4 that identifies the individual DC-DC Converter (DC-DC1 - 4).
Table 42 DC Converter and LDO Regulator Status
15.13 POWER MANAGEMENT INTERRUPTS
Undervoltage monitoring is provided on all DC-DC Converters and LDO Regulators, as described in
Section 15.11. The associated interrupt flags indicate an undervoltage condition in each individual
DC-DC Converter or LDO Regulator. Each of these secondary interrupts triggers a primary
Undervoltage Interrupt, UV_INT (see Section 23). This can be masked by setting the mask bit(s) as
described in Table 43.
Current monitoring is provided on DC-DC1 and DC-DC2, as described in Section 15.11. The interrupt
flags HC_DC1_EINT and HC_DC2_EINT indicate a high current condition in DC-DC1 and DC-DC2
respectively. Each of these secondary interrupts triggers a primary High Current Interrupt, HC_INT
(see Section 23). This can be masked by setting the mask bit(s) as described in Table 43.
The high current thresholds are programmable; these are set by DC1_HC_THR and DC2_HC_THR
for DC-DC1 and DC-DC2 respectively. See Section 15.12.2 for details of these register fields. Note
that these functions are for current monitoring; they do not equate to the DC-DC Converter maximum
current limit.
ADDRESS
R16403
(4013h)
BIT
9:0
LABEL
UV_LDOn_EINT
(Rising Edge triggered)
Interrupt Status
3
R16404
(4014h)
Interrupt Status
4
DESCRIPTION
LDOn Undervoltage interrupt
Note: Cleared when a ‘1’ is written.
9
HC_DC2_EINT
DC-DC2 High current interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
8
HC_DC1_EINT
DC-DC1 High current interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
3:0
UV_DCm_EINT
DC-DCm Undervoltage interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
R16411
(401Bh)
Interrupt Status
3 Mask
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IM_UV_LDOn_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
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ADDRESS
BIT
LABEL
DESCRIPTION
Default value is 1 (masked)
R16412
(401Ch)
IM_HC_DC2_EINT
9
Interrupt mask.
0 = Do not mask interrupt.
Interrupt Status
4 Mask
1 = Mask interrupt.
Default value is 1 (masked)
IM_HC_DC1_EINT
8
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
3:0
IM_UV_DCm_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Notes:
1.
n is a number between 1 and 10 that identifies the individual LDO Regulator (LDO1 - 10).
2.
m is a number between 1 and 4 that identifies the individual DC-DC Converter (DC-DC1 - 4).
Table 43 Power Management Interrupts
15.14 POWER GOOD INDICATION
The WM8310 can indicate the status of the DC-DC Converters and LDO Regulators via a GPIO pin
configured as a “PWR_GOOD” output (see Section 21).
Each DC-DC Converter and LDO Regulator to be monitored in this way must be individually enabled
as an input to the PWR_GOOD function using the register bits defined in Table 44.
When a GPIO pin is configured as a “PWR_GOOD” output, this signal is asserted when all selected
DC-DC Converters and LDO Regulators are operating correctly. If any of the enabled DC-DC
Converters or LDO Regulators is undervoltage, then the PWR_GOOD will be de-asserted. In this
event, the host processor should read the Undervoltage Interrupt fields to determine which DC-DC
Converter or LDO Regulator is affected.
Note that an Undervoltage condition may lead to a Converter being switched off automatically. In this
case, the disabled Converter will not indicate the fault condition via PWR_GOOD. Accordingly, the
PWR_GOOD signal may not be a reliable output in cases where the WM8310 is configured to shut
down any Converters automatically under Undervoltage conditions. It is recommended that the host
processor should read the Undervoltage Interrupts in response to PWR_GOOD being de-asserted.
The host processor can then initiate the most appropriate response.
ADDRESS
R16526 (408Eh)
BIT
3
LABEL
DC4_OK
DEFAULT
0
Power Good
Source 1
DESCRIPTION
DC-DC4 status selected as an input
to PWR_GOOD
0 = Disabled
1 = Enabled
2
DC3_OK
1
DC-DC3 status selected as an input
to PWR_GOOD
0 = Disabled
1 = Enabled
1
DC2_OK
1
DC-DC2 status selected as an input
to PWR_GOOD
0 = Disabled
1 = Enabled
0
DC1_OK
1
DC-DC1 status selected as an input
to PWR_GOOD
0 = Disabled
1 = Enabled
R16527 (408Fh)
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LDO10_OK
1
LDO10 status selected as an input to
PWR_GOOD
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ADDRESS
BIT
LABEL
DEFAULT
Power Good
Source 2
DESCRIPTION
0 = Disabled
1 = Enabled
8
LDO9_OK
1
LDO9 status selected as an input to
PWR_GOOD
0 = Disabled
1 = Enabled
7
LDO8_OK
1
LDO8 status selected as an input to
PWR_GOOD
0 = Disabled
1 = Enabled
6
LDO7_OK
1
LDO7 status selected as an input to
PWR_GOOD
0 = Disabled
1 = Enabled
5
LDO6_OK
1
LDO6 status selected as an input to
PWR_GOOD
0 = Disabled
1 = Enabled
4
LDO5_OK
1
LDO5 status selected as an input to
PWR_GOOD
0 = Disabled
1 = Enabled
3
LDO4_OK
1
LDO4 status selected as an input to
PWR_GOOD
0 = Disabled
1 = Enabled
2
LDO3_OK
1
LDO3 status selected as an input to
PWR_GOOD
0 = Disabled
1 = Enabled
1
LDO2_OK
1
LDO2 status selected as an input to
PWR_GOOD
0 = Disabled
1 = Enabled
0
LDO1_OK
1
LDO1 status selected as an input to
PWR_GOOD
0 = Disabled
1 = Enabled
Table 44 PWR_GOOD (GPIO) Configuration
15.15 DC-DC CONVERTER OPERATION
15.15.1 OVERVIEW
The WM8310 provides four DC-DC switching converters. Three of these are synchronous buck (stepdown) converters; the fourth of these is a boost (step-up) converter. The principal characteristics of
each DC-DC converter are shown below.
Converter Type
DC-DC1 / DC-DC2
DC-DC3
DC-DC4
Buck (step-down)
Buck (step-down)
Boost (step-up)
Input Voltage Range
Output Voltage Range
Load Current Rating
2.7V to 5.5V (connect to SYSVDD supply)
0.6V to 1.8V
0.85V to 3.4V
Up to 1200mA
Up to 1000mA
5V to 30V
Up to 25mA @ 30V
Up to 40mA @ 20V
Up to 90mA @ 8V
Switching Frequency
2MHz or 4MHz
2MHz
1MHz
Table 45 DC-DC Converter Overview
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15.15.2 DC-DC SYNCHRONOUS BUCK CONVERTERS
DC-DC Converters 1, 2 and 3 are synchronous buck converters which deliver high performance and
high efficiency across a wide variety of operating conditions.
The high switching frequency, together with the current mode architecture, delivers exceptional
transient performance suitable for supplying processor power domains and similar applications
requiring high stability through fast-changing load (or line) conditions.
The current mode architecture enables extended bandwidth of the control loop, allowing the DC-DC
converter to adapt for changes in input or output conditions more rapidly than can be achieved using
other feedback mechanisms. This improves the converter’s performance under transient load
conditions.
The flexible design of the DC-DC Converters allows a selection of different operating configurations,
which can be chosen according to the performance, efficiency, space or external component cost
requirements.
The DC-DC Converter design achieves high performance with a small inductor component. This is
highly advantageous in size-critical designs for portable applications. In the case of DC-DC1 and DCDC2, the switching frequency is selectable (2MHz or 4MHz). The higher frequency supports best
transient performance and the smallest external inductor, whilst the lower rate supports best power
efficiency. It should be noted that the supported output voltage range is restricted in the 4MHz mode;
for output voltages greater than 1.4V, the 2MHz mode must be used.
The DC-DC Converters are compatible with a range of external output capacitors. A larger capacitor
(eg. 47F) will deliver best transient performance, whilst a smaller capacitor (eg. 4.7F) may be
preferred for size or cost reasons.
Four different operating modes can be selected, allowing the user to configure the converter
performance and efficiency according to different demands. This includes power-saving modes for
light load conditions and a high performance mode for best transient load performance. A low power
LDO Regulator mode is also provided. The DC-DC Converters maintain output voltage regulation
when switching between operating modes.
Forced Continuous Conduction Mode (FCCM)
This mode delivers the best load transient performance across the entire operating load range of the
converter. It also provides the best EMI characteristics due to the fixed, regular switching pattern.
For normal DC-DC buck converter operation, there is an inductor charging phase followed by a
discharging phase. Under light load conditions, the inductor current may be positive or negative
during this cycle. (Note that the load current corresponds to the average inductor current.) The
negative portion of the cycle corresponds to inefficient operation, as the output capacitor is
discharged unnecessarily by the converter circuit. Accordingly, this mode is not optimally efficient for
light load conditions.
This mode offers excellent performance under transient load conditions. It exceeds the performance
of the other operating modes in the event of a decreasing current demand or a decreasing voltage
selection. This is because FCCM mode can actively pull down the output voltage to the required level,
whilst other modes rely on the load to pull the converter voltage down under these conditions.
Another important benefit of this mode is that the switching pattern is fixed, regardless of load
conditions. This provides best compatibility with noise-sensitive circuits where the noise frequency
spectrum must be well-defined.
Although this mode is not optimally efficient for light loads, it delivers the best possible transient load
performance and fixed frequency switching. This mode should be selected when best performance is
required, delivering minimum output voltage ripple across all static or transient load conditions.
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Auto Mode: Continuous / Discontinuous Conduction with Pulse-Skipping (CCM/DCM with PS)
This is an automatic mode that selects different control modes according to the load conditions. The
converter supports the full range of load conditions in this mode, and automatically selects powersaving mechanisms when the load conditions are suitable. Under light load conditions, the efficiency
in this mode is superior to the FCCM mode. The transient load performance may be slightly worse
than FCCM mode.
The converter operates in Continuous Conduction Mode (CCM) for heavy load conditions, and
Discontinuous Conduction Mode (DCM) under lighter loads. Discontinuous conduction is when the
inductor current falls to zero during the discharge phase, and the converter disables the synchronous
rectifier transistor in order that the inductor current remains at zero until the next charge phase.
Negative inductor current is blocked in this mode, eliminating the associated losses, and improving
efficiency.
The transient response in this mode varies according to the operating conditions; it differs from FCCM
in the case of a decreasing current demand or a decreasing voltage, as the converter uses the load to
pull the output voltage down to the required level. A light load will result in a slow response time.
A minimum inductor charge time is applied in DCM mode; this leads to a minimum average inductor
current when operating as described above. Under very light load conditions, pulse skipping is used
to reduce the average inductor current to the level required by the load. In pulse-skipping mode, the
charge phase of selected cycles is not scheduled, and the load is supported by the output capacitor
over more than one cycle of the switching frequency. As well as supporting very light load current
conditions, this mechanism offers power savings, as the switching losses associated with the skipped
pulses are eliminated. A disadvantage of this is that the transient response is degraded even further
with respect to DCM. When the pulse-skipping behaviour is invoked, an increased output voltage
ripple may be observed under some load conditions.
This mode is suitable for a wide range of operating conditions. It supports the full range of load
currents, and offers efficiency savings under light load conditions.
Hysteretic Mode
Hysteretic mode is a power-saving mode. It does not support the full load capability of the DC-DC
converter, but offers efficiency improvements over the FCCM and Auto (CCM/DCM with PS) modes.
The control circuit in Hysteretic mode operates very differently to the Pulse-Skipping mode that is
available in Auto mode. In Pulse-Skipping mode, selected switching cycles are dropped in order to
reduce the output current to match a light load condition, whilst maintaining good output voltage ripple
as far as possible. In Hysteretic mode, the converter uses switched operation on an adaptive
intermittent basis to deliver the required average current to the load.
In the switched operation portion of the Hysteretic mode, the converter drives the output voltage up;
this is followed by a power-saving period in which the control circuit is largely disabled whilst the load
pulls the output voltage down again over a period of many switching cycles. The duration of the fixed
frequency bursts and the time between bursts is adapted automatically by the output voltage
monitoring circuit.
In this mode, the power dissipation is reduced to a very low level by disabling parts of the control
circuitry for the duration of selected switching cycles. This improves the overall efficiency, but also
leads to output voltage ripple and limited performance. This mode produces a larger output voltage
ripple than the Pulse-Skipping mode. In order to limit the degradation of the DC-DC converter
performance in Hysteretic mode, the control circuit is designed for a restricted range of load
conditions only. Note that the irregular switching pattern also results in degraded EMI behaviour.
Hysteretic mode and Pulse Skipping mode are both Pulse Frequency Modulation (PFM)-type modes,
where the switching pulse frequency is adjusted dynamically according to the load requirements. A
consequence of this frequency modulation is that the circuit’s EMI characteristics are less predictable.
In Hysteretic mode in particular, the EMI effects arising from the DC-DC switching are present across
a wider frequency band than is the case in CCM and DCM. It is more difficult to effectively suppress
the wide band interference, and this factor may result in Hysteretic mode being unsuitable for some
operating conditions.
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Hysteretic mode is suitable for light load conditions only, and only suitable for operating modes that
are not sensitive to wide band RF/EMI effects. The output voltage ripple (and frequency) is load
dependent, and is generally worse than Pulse-Skipping operation in the Auto mode. Provided that the
EMI and voltage ripple can be tolerated, the Hysteretic mode offers an efficiency advantage over the
Auto (CCM/DCM with PS) mode.
LDO Mode
In this mode, there is no FET switching at all, and the converter operates as a Low Drop-Out (LDO)
regulator. In this mode, the FET switching losses are eliminated, as is the power consumption of the
DC-DC control circuit. Under suitable operating conditions, this provides the most efficient option for
light loads, without any of the EMI or voltage ripple limitations of Hysteretic mode.
As with any LDO, the output voltage is constant, and there is no internal source of voltage ripple.
Unlike the switching modes, the power efficiency of the LDO mode is highly dependent on the input
and output voltages; the LDO is most efficient when the voltage drop between input and output is
small. The power dissipated as heat loss by an LDO increases rapidly as the input - output voltage
difference increases.
LDO mode is suitable for light loads, and provides a ripple-free output. The LDO mode features a very
low start-up current; this mode can be used to avoid the higher in-rush current that occurs in the
switching converter modes. The efficiency is dependent on the input - output voltage configuration;
the LDO mode can be highly efficient, but may also be unacceptably inefficient. If an improvement in
power efficiency is required, then Hysteretic mode may be the preferred choice or, for better EMI and
voltage ripple, the Auto (CCM/DCM with PS) mode may be the optimum selection.
Operating Mode Summary
MODE
DESCRIPTION
APPLICATION
Forced Continuous Conduction
Mode (FCCM)
Buck converter operation where inductor
current is continuous at all times.
High performance for all static and transient
load conditions. Fixed frequency switching
offers best compatibility with sensitive
circuits.
Auto Mode: Continuous /
Discontinuous Conduction with
Pulse-Skipping Mode (CCM/DCM
with PS)
Buck converter operation where inductor
current may be discontinuous under reduced
loads; pulse-skipping also enabled under
lighter loads.
High efficiency for all static and transient
load conditions. Performance may be less
than FCCM mode for heavy load transients.
Hysteretic Mode
The converter uses a hysteretic control
scheme with pulsed switching operation. The
control circuitry is disabled intermittently for
power saving.
High efficiency for light static and light
transient loads only. Maximum load current is
restricted; output voltage ripple is increased.
LDO Mode
No FET switching at all; linear regulator
operation.
Power saving mode for light loads only. High
efficiency for ultra light loads. Low current
soft-start control.
Table 46 DC-DC Synchronous Buck Converter Operating Modes Summary
Typical Connections
The typical connections to DC-DC Converter 1 are illustrated in Figure 20. The equivalent circuit
applies to DC-DC Converters 2 and 3 also.
The input voltage connection to DC-DC Converters 1, 2 and 3 is provided on DC1VDD, DC2VDD and
DC3VDD respectively; these are typically connected to the SYSVDD voltage node. Note that the
internal supply pins PVDD1 and PVDD2 must be connected to the same supply voltage as the DCDC Converters (ie. SYSVDD).
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Figure 20 DC-DC Synchronous Buck Converter Connections
The recommended output capacitor COUT varies according to the required transient response. Note
that the DCm_CAP register field must be set according to the output capacitance on each DC-DC
Converter in order to achieve best performance.
In the case of DC-DC1 and DC-DC2, the recommended inductor component varies according to the
DCm_FREQ register field. This register supports a choice of different switching frequencies.
See Section 30.3 for details of specific recommended external components.
15.15.3 DC-DC STEP UP CONVERTER
DC-DC Converter 4 is a step-up DC-DC Converter designed to deliver high power efficiency across
full load conditions. It is designed to provide a voltage which is determined by the selected current of
either Current Sink 1 or Current Sink 2 through an external load - typically a string of LEDs.
DC-DC Converter 4 is designed with fixed frequency current mode architecture. The clock frequency
is set by an internal RC oscillator, which provides a 1MHz clock.
The typical connections to DC-DC Converter 4 are illustrated in Figure 21. The DC4_FBSRC register
field can select either ISINK1 or ISINK2 as input to the feedback circuit.
The input voltage connection, DC4VDD, is typically connected to the SYSVDD voltage node. Note
that the internal supply pins PVDD1 and PVDD2 should also be connected to SYSVDD.
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Figure 21 DC-DC Boost Converter Connections
Note that the recommended output capacitor COUT varies according to the required output voltage.
The DC4_RANGE register field must be set according to the required output voltage.
See Section 30.4 for details of specific recommended external components.
15.16 LDO REGULATOR OPERATION
15.16.1 OVERVIEW
The WM8310 provides 11 LDO Regulators. Four of these are low-noise analogue LDOs. One of the
LDO Regulators (LDO11) can be configured to be enabled even when the WM8310 is in the OFF
state. The principal characteristics of the LDO Regulators are shown below.
LDO1
LDO2, 3
LDO4, 5, 6
LDO7, 8
LDO9, 10
LDO11
Converter Type
General
Purpose
General
Purpose
General
Purpose
Analogue
Analogue
General
Purpose
Input Voltage Range
1.5V to 5.5V (must be ≤ SYSVDD voltage)
1.71V to 5.5V
1.8V to 5.5V
Output Voltage
Range
0.9V to 3.3V
0.9V to 3.3V
0.9V to 3.3V
1.0V to 3.5V
1.0V to 3.5V
0.8V to 1.55V
Load Current Rating
Up to 300mA
Up to
200mA
Up to
100mA
Up to 200mA
Up to 150mA
Up to 25mA
Pass device
impedance @ 2.5V
1
1
2
1
2
n/a
Table 47 LDO Regulator Overview
15.16.2 LDO REGULATORS
The LDO Regulators are configurable circuits which generate accurate, low-noise supply voltages for
various system components. The LDO Regulators are dynamically programmable and can be reconfigured at any time. Two low power modes are provided for the general purpose LDOs 1-6; a
single low power mode is provided for the analogue LDOs 7-10; this enables the overall device power
consumption to be minimised at all times.
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The LDOs 1-10 can also operate as current-limited switches, with no voltage regulation; this is useful
for ‘Hot Swap’ outputs, i.e. supply rails for external devices that are plugged in when the system is
already powered up - the current-limiting function prevents the in-rush current into the external device
from disturbing other system power supplies.
The input voltage to these LDOs is provided on pin LDO1VDD through to LDO10VDD respectively.
The LDO input supply pins are typically connected to the SYSVDD voltage node, or else can be
connected to the output pin of one of the DC-DC buck converters. Note that the internal supply pins
PVDD1 and PVDD2 should also be connected to SYSVDD.
LDO11 is a configurable LDO intended for ‘always-on’ functions external to the WM8310. The
WM8310 contains a further two non-configurable LDOs which support internal functions only.
The connections to LDO Regulator 1 are illustrated in Figure 22. The equivalent circuit applies to
LDO2 through to LDO10.
Figure 22 LDO Regulator Connections
An input and output capacitor are recommended for each LDO Regulator, as illustrated above.
See Section 30.5 for details of specific recommended external components.
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16 CURRENT SINKS
16.1 GENERAL DESCRIPTION
The WM8310 provides two Current Sinks, ISINK1 and ISINK2. These are programmable constantcurrent sinks designed to drive strings of serially connected LEDs, including white LEDs used in
display backlight applications.
The WM8310 Boost Converter, DC-DC4, is designed as a power source for LED strings. Driving
LEDs in this way is particularly power efficient because no series resistor is required. The Boost
Converter can generate voltages higher than the Battery, Wall or USB supply, producing the
necessary combined forward voltages of long LED strings. See Section 15.15.3 for details of DC-DC4
operation.
16.2 CURRENT SINK CONTROL
The configuration of the Current Sinks is described in the following sections.
16.2.1
ENABLING THE SINK CURRENT
In the ON power state, the Current Sinks ISINK1 and ISINK2 can be enabled in software using the
CS1_ENA and CS2_ENA register fields as defined in Table 48. When the Current Sinks are enabled,
the drive current is controlled by the CS1_DRIVE and CS2_DRIVE bits. Note that the Current Sinks
permit current flow only when the applicable CSn_ENA and CSn_DRIVE bits are both set.
The WM8310 Boost Converter, DC-DC4, is the recommended power source for the Current Sinks.
The recommended switch-on sequence is as follows:

Enable Current Sink and Current Drive (CSn_ENA = 1; CSn_DRIVE = 1)

Enable Boost Converter (DC4_ENA = 1)
The status of the Current Sinks in the SLEEP power state are controlled by CS1_SLPENA and
CS2_SLPENA, as described in Table 48. The Current Sinks may either be disabled in SLEEP or
remain under control of the applicable CSn_ENA register bit.
If a Current Sink is disabled in SLEEP, then the applicable CSn_DRIVE bit is automatically reset to 0
as part of the SLEEP transition sequence. Note that the CSn_DRIVE bit will remain reset at 0
following a WAKE transition; the Current Sink can only be re-enabled by writing to the applicable
CSn_DRIVE register bit.
If both Current Sinks are disabled in SLEEP, then DC4 can also be disabled in SLEEP, by setting
DC4_SLPENA = 0, as described in Section 15.4.2. If DC4 is not disabled, then it is important that
CSn_ENA also remains set in the SLEEP power state.
The recommended switch-off sequence for DC-DC4 and the Current Sinks is as follows:

Disable Current Drive (CSn_DRIVE = 0)

Disable Boost Converter (DC4_ENA = 0)

Disable Current Sink (CSn_ENA = 0)
Note that this switch-off sequence is important in order to avoid forward-biasing on-chip ESD
protection diodes.
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When the Current Sinks output drive is enabled or disabled using CS1_DRIVE or CS2_DRIVE, the
current ramps up or down at a programmable rate. The ramp durations are programmed using the
register bits defined in Section 16.2.3. If the current ramp is not required when switching off DC-DC4
and the Current Sinks, then the following switch-off sequence may be used:

Disable Boost Converter (DC4_ENA = 0)

Disable Current Sink and Current Drive (CSn_ENA = 0; CSn_DRIVE = 0)
When the Current Sinks are enabled, the status of each is indicated using the CSn_STS bits. If the
Current Sinks are unable to sink the demanded current (eg. if the power source is too low or if the
load is open circuit), then the respective CSn_STS bit will be set to 1. When the Current Sink circuit is
correctly regulated, then the respective CSn_STS bits are set to 0.
ADDRESS
R16462
(404Eh)
Current Sink 1
BIT
15
LABEL
CS1_ENA
DEFAULT
0
DESCRIPTION
Current Sink 1 Enable (ISINK1 pin)
0 = Disabled
1 = Enabled
Note - this bit is reset to 0 when the OFF
power state is entered.
14
CS1_DRIVE
0
Current Sink 1 output drive enable
0 = Disabled
1 = Enabled
13
CS1_STS
0
Current Sink 1 status
0 = Normal
1 = Sink current cannot be regulated
12
CS1_SLPENA
0
Current Sink 1 SLEEP Enable
0 = Disabled
1 = Controlled by CS1_ENA
R16463
(404Fh)
Current Sink 2
15
CS2_ENA
0
Current Sink 2 Enable (ISINK2 pin)
0 = Disabled
1 = Enabled
Note - this bit is reset to 0 when the OFF
power state is entered.
14
CS2_DRIVE
0
Current Sink 2 output drive enable
0 = Disabled
1 = Enabled
13
CS2_STS
0
Current Sink 2 status
0 = Normal
1 = Sink current cannot be regulated
12
CS2_SLPENA
0
Current Sink 2 SLEEP Enable
0 = Disabled
1 = Controlled by CS2_ENA
Table 48 Enabling ISINK1 and ISINK2
16.2.2
PROGRAMMING THE SINK CURRENT
The sink currents for ISINK1 and ISINK2 can be independently programmed by writing to the
CS1_ISEL and CS2_ISEL register bits. The current steps are logarithmic to match the logarithmic
light sensitivity characteristic of the human eye. The step size is 1.51dB (i.e. the current doubles
every four steps).
Note that the maximum programmable sink current is 27.6mA. The maximum current that can be
supported by the DC-DC4 Boost Converter varies with the output voltage; the maximum ISINK current
that can be supported by the Boost Converter will depend upon the forward voltage required by the
current sink load(s).
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ADDRESS
R16462
(404Eh)
Current Sink 1
BIT
5:0
LABEL
CS1_ISEL
DEFAULT
00 0000
DESCRIPTION
ISINK1 current.
Current = 2.0µA × 2^(CS1_ISEL/4),
where CS1_ISEL is an unsigned binary
number.
Alternatively,
CS1_ISEL = 13.29 x LOG(current/2.0µA)
00_0000 = 2.0µA
11_0111 = 27.6mA
Values greater than 11_0111 will result in
the maximum current of approx 27.6mA.
R16463
(404Fh)
Current Sink 2
5:0
CS2_ISEL
00 0000
ISINK2 current.
Current = 2.0µA × 2^(CS2_ISEL/4),
where CS2_ISEL is an unsigned binary
number.
Alternatively,
CS2_ISEL = 13.29 x LOG(current/2.0µA)
00_0000 = 2.0µA
11_0111 = 27.6mA
Values greater than 11_0111 will result in
the maximum current of approx 27.6mA.
Table 49 Controlling the Sink Current for ISINK1 and ISINK2
16.2.3
ON/OFF RAMP TIMING
When the Current Sinks output drive is enabled or disabled using CS1_DRIVE or CS2_DRIVE, the
current ramps up or down at a programmable rate. This can be used in order to switch the LEDs on or
off gradually. The ramp durations are programmed using the register bits defined in Table 50.
ADDRESS
BIT
LABEL
DEFAULT
R16462
(404Eh)
Current Sink 1
11:10
CS1_OFF_RA
MP
01
DESCRIPTION
ISINK1 Switch-Off ramp
00 = instant (no ramp)
01 = 1 step every 4ms (220ms)
10 = 1 step every 8ms (440ms)
11 = 1 step every 16ms (880ms)
The time quoted in brackets is valid for
the maximum change in current drive
setting. The actual time scales
according to the extent of the change in
current drive setting.
9:8
CS1_ON_RAM
P
01
ISINK1 Switch-On ramp
00 = instant (no ramp)
01 = 1 step every 4ms (220ms)
10 = 1 step every 8ms (440ms)
11 = 1 step every 16ms (880ms)
The time quoted in brackets is valid for
the maximum change in current drive
setting. The actual time scales
according to the extent of the change in
current drive setting.
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ADDRESS
BIT
LABEL
DEFAULT
R16463
(404Fh)
Current Sink 2
11:10
CS2_OFF_RA
MP
01
DESCRIPTION
ISINK2 Switch-Off ramp
00 = instant (no ramp)
01 = 1 step every 4ms (220ms)
10 = 1 step every 8ms (440ms)
11 = 1 step every 16ms (880ms)
The time quoted in brackets is valid for
the maximum change in current drive
setting. The actual time scales
according to the extent of the change in
current drive setting.
9:8
CS2_ON_RAM
P
01
ISINK2 Switch-On ramp
00 = instant (no ramp)
01 = 1 step every 4ms (220ms)
10 = 1 step every 8ms (440ms)
11 = 1 step every 16ms (880ms)
The time quoted in brackets is valid for
the maximum change in current drive
setting. The actual time scales
according to the extent of the change in
current drive setting.
Table 50 Configuring On/Off Ramp Timing for ISINK1 and ISINK2
16.3 CURRENT SINK INTERRUPTS
The Current Sinks are associated with two Interrupt event flags, which indicate if the Current Sinks
are unable to sink the demanded current (eg. if the power source is too low or if the load is open
circuit). Each of these secondary interrupts triggers a primary Current Sink Interrupt, CS_INT (see
Section 23). This can be masked by setting the mask bit(s) as described in Table 51.
ADDRESS
R16402
(4012h)
Interrupt Status
2
BIT
7
LABEL
CS2_EINT
DESCRIPTION
Current Sink 2 interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
6
CS1_EINT
Current Sink 1 interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
R16410
(401Ah)
7
IM_CS2_EINT
Interrupt mask.
0 = Do not mask interrupt.
Interrupt Status
2 Mask
1 = Mask interrupt.
Default value is 1 (masked)
6
IM_CS1_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Table 51 Current Sink Interrupts
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16.4 LED DRIVER CONNECTIONS
The recommended connections for LEDs on ISINK1 and ISINK2 are illustrated in Figure 23.
VDD
WM8310
ISINK1
ISINKGND
Note: Equivalent circuit applies for ISINK2
Figure 23 LED Connections to ISINK1 and ISINK2
The ground connection associated with these two Current Sinks is the ISINKGND pin. The DC-DC4
Boost Converter can be used to provide the VDD supply for ISINK1 or ISINK2. It is also possible to
drive ISINK1 and ISINK2 simultaneously from the DC-DC4 Boost Converter. See Section 15.4.2 for
details of configuring DC-DC4 correctly according to whether it is supplying ISINK1 or ISINK2.
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17 POWER SUPPLY CONTROL
17.1 GENERAL DESCRIPTION
The WM8310 can take its power supply from a Wall adaptor, a USB interface or from a single-cell
lithium battery. The WM8310 autonomously chooses the most appropriate power source available,
and supports hot-swapping between sources (ie. the system can remain in operation while different
sources are connected and disconnected).
Comparators within the WM8310 identify which power supplies are available and select the power
source in the following order of preference:

Wall adaptor (WALLVDD)

USB power rail (USBVDD)

Battery (BATTVDD)
Note that the Wall supply is normally the first choice of supply, provided that it is within the operating
limits quoted in Section 6. The WM8310 can operate with any combination of these power supplies,
or with just a single supply.
When WALLVDD or USBVDD is selected as the power source, this may be used to charge the
Battery, using the integrated battery charger circuit.
The recommended connections between the WM8310 and the WALL, USB and Battery supplies are
illustrated in Figure 24. Note that the external FET components may be omitted in some applications;
as described later in this section.
Figure 24 WM8310 Power Supply Connections
SYSVDD is primarily an output from the WM8310; this output is the preferred supply, where the
WM8310 has arbitrated between the Wall, Battery and USB connections. This output is suitable for
supplying power to the other blocks of the WM8310, including the DC-DC Converters and LDO
Regulators. SYSVDD is also an input under some conditions, such as battery charging from the Wall
supply. The voltage at the SYSVDD load connection point is sensed using the SYSVMON pin.
All loads connected to the WM8310 should be connected to the SYSVDD pin. The inputs to the DCDC Converters and LDOs are typically connected to the SYSVDD pin. The inputs to the LDOs may,
alternatively, be connected to the outputs of the DC-DCs if desired.
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Note that connecting the BATTVDD pin directly to a load is not recommended; this may lead to
incorrect behaviour of the battery charger. A filter capacitor between BATTVDD and GND is
recommended to ensure best performance of the battery charger; for specific recommendations, refer
to the WM8310 evaluation board users manual.
The Wall Adaptor supply connects to SYSVDD via a FET switch as illustrated in Figure 24. The FET
switch is necessary in order to provide isolation between the Wall supply and the Battery/USB
supplies. The Wall Adapter voltage is sensed directly on the WALLVDD pin; this allows the WM8310
to determine the preferred supply, including when the Wall FET is switched off.
The gate connection to the Wall FET is driven by the WALLFETENA
¯¯¯¯¯¯¯¯¯¯¯¯ pin. The drive strength of this pin
can be selected using the WALL_FET_ENA_DRV_STR register bit as described in Section 17.3.
Note that, when the Wall Adapter is the preferred power supply, the Battery will be used if necessary
to supplement the current provided at SYSVDD.
If the Wall Adapter power source is not used, then the associated FET may be omitted, as illustrated
in Figure 24.
The main battery connects directly to the BATTVDD pin. The voltage at the battery is sensed using
the BATTVMON pin.
It is highly recommended that an external FET is connected between BATTVDD and SYSVDD as
illustrated in Figure 24. Under battery-powered operation, this FET controls the current flow from the
battery to SYSVDD. By using this external path, the power losses under heavy load conditions are
reduced, and power efficiency is increased. When this FET is not present, all the system current flows
internally from BATTVDD to SYSVDD, which can lead to unnecessary thermal losses. The external
Battery FET should always be used for average loads in excess of 1A.
The gate connection to the Battery FET is driven by the BATTFETENA
¯¯¯¯¯¯¯¯¯¯¯ pin. The functionality of this
pin is enabled by setting the BATT_FET_ENA register bit, as described in Section 17.2.
If the average load drawn from the Battery is less than 1A, then the associated FET may be omitted,
as illustrated in Figure 24. Note that the external FET is open during battery charging.
The USB interface connects directly to the USBVDD pin. The WM8310 can use this pin as an input to
power the device and/or to charge a battery connected to the BATTVDD pin. The voltage at the USB
supply is sensed using the USBVMON pin.
Note that, when USB is the preferred power supply, the Battery will be used if necessary to
supplement the current drawn from the USBVDD pin.
A backup power source can be supported using a coin cell, super/gold capacitor, or else a standard
capacitor, connected to the LDO12VOUT pin. When no other supply is available, the backup source
provides power to maintain the RTC memory whilst in the BACKUP power state. At other times, the
LDO12VOUT pin provides a constant-voltage output to maintain the backup power source. See
Section 17.6 for more details of Backup Power.
The status of the Wall and USB power supplies is indicated in the System Status register, as
described in Table 52. When PWR_WALL or PWR_USB is set, this indicates that the corresponding
power source is available for powering the WM8310.
If the status of either these power supplies changes, indicating a connection, disconnection, or a
voltage that is outside the required limits, the Power Path Source interrupt, PPM_PWR_SRC_EINT, is
set (see Section 17.5). Note that this interrupt does not indicate the availability of the battery power
source.
The PWR_SRC_BATT bit indicates when the battery is supplying current to the WM8310. This
includes when the battery is supplementing the Wall or USB power supply sources.
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ADDRESS
BIT
LABEL
DEFAULT
10
PWR_SRC_BATT
0
R16397
(400Dh)
DESCRIPTION
Battery Power Source status
0 = Battery is not supplying current
System Status
1 = Battery is supplying current
9
PWR_WALL
0
Wall Adaptor status
0 = Wall Adaptor voltage not present
1 = Wall Adaptor voltage is present
8
PWR_USB
0
USB status
0 = USB voltage not present
1 = USB voltage is present
Table 52 Power Source Status Registers
17.2 BATTERY POWERED OPERATION
The WM8310 selects Battery power via BATTVDD when the battery voltage is higher than the
WALLVDD and USBVDD supply voltages. In practical usage, this means the Battery is used when
the Wall and USB supplies are both disconnected.
The battery will be used to supplement the USB or Wall Adaptor supplies when required.
If the WALLVDD or USBVDD supply becomes available during battery operation, then the selected
power source is adjusted accordingly.
When an external FET is provided between BATTVDD and SYSVDD, as described in Section 17.1,
the BATTFETENA
¯¯¯¯¯¯¯¯¯¯¯ pin functionality must be enabled by setting BATT_FET_ENA as described in
Table 53.
ADDRESS
BIT
R16390
(4006h)
12
LABEL
BATT_FET_ENA
DEFAULT
DESCRIPTION
0
Enables the FET gate functionality on
the BATTFETENA pin. (Note this pin is
Active Low.)
Reset
Control
0 = Disabled
1 = Enabled
Note - this bit is reset to 0 when the
OFF power state is entered.
Table 53 Configuring the Battery Power Operation
17.3 WALL ADAPTOR POWERED OPERATION
The WM8310 selects Wall Adaptor power whenever this supply is within the normal operating limits of
4.3V to 5.5V and WALLVDD is higher than BATTVDD. The Wall adaptor power source is also
selected below 4.3V if USBVDD is less than 4.3V and WALLVDD is higher than BATTVDD.
Note that USBVDD supply is not used when WALLVDD is within its normal operating limits, even if
the USBVDD supply is higher than the WALLVDD supply.
When the WALLVDD supply is selected and a Battery is connected, then battery charging is possible
in the ON or SLEEP power states; see Section 17.7.
The drive strength of the Wall FET gate connection, WALLFETENA
¯¯¯¯¯¯¯¯¯¯¯¯, can be selected using the
WALL_FET_ENA_DRV_STR register bit as described in Table 54.
ADDRESS
R16390
(4006h)
BIT
LABEL
13
WALL_FET_ENA_D
RV_STR
DEFAULT
0
Reset
Control
DESCRIPTION
Sets the drive strength of the
WALLFETENA pin. (Note this pin is
Active Low.)
0 = Weak drive (500kOhm)
1 = Strong drive (50kOhm)
Table 54 Configuring the Wall Adaptor Power Operation
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17.4 USB POWERED OPERATION
The WM8310 selects USB power via the USBVDD pin when this supply is within the normal USB
operating limits of 4.3V to 5.5V, and WALLVDD is less than 4.3V and USBVDD is the highest supply
source available. USB power is also selected below 4.3V if WALLVDD is less than 3.4V and
USBVDD is the highest supply available.
The maximum current drawn from the USB supply is determined by the USB_ILIM register field.
Currents ranging from 0mA to 1800mA may be selected. See also Section 7 for the limits of the USB
Current switch. If the system current demand is greater than the limit set by USB_ILIM, then this is
indicated via the USB_CURR_STS bit and by setting the PPM_USB_CURR_EINT interrupt (see
Section 17.5).
The USB power source will be supplemented by battery power, when available, in order to maintain
the USB current within the applicable limit. If there is no battery connected, or there is insufficient
capacity to support the system demands, then the supply rails may drop as the WM8310 attempts to
meet the USB current limit.
If a suitable WALLVDD supply becomes available during USB operation, then this will be selected as
the preferred power source.
When the USBVDD supply is selected and a Battery is connected, then battery charging is possible in
the ON or SLEEP power states, provided that sufficient current capacity is available. See
Section 17.7 for details of the Battery Charger.
Note that, when the USBVDD supply is selected by the WM8310, and an ‘ON’ state transition is
requested, the USB current limit must be set to 100mA or higher. If a lower current limit is selected,
then the ‘ON’ state transition event may fail. This requirement is also applicable when a battery is
available to provide supplementary power. There is no requirement to set USB_ILIM for start-up when
the WALLVDD supply is selected.
The user-configurable OTP memory contains the USB_ILIM register field. This allows users to
program their chosen USB current limit on start-up (Note that the current limit can still be updated
during normal operation.) If the WM8310 is powered up with USBVDD as the selected power source,
and the applicable USB current limit is 100mA, then the start-up behaviour is determined by the
USB100MA_STARTUP field, as defined in Table 55.
When starting up in 100mA USB mode, the normal or soft-start process can be selected. The softstart option controls the DC-DC converters and LDO Regulators in order to reduce the start-up current
demand. In 100mA USB soft-start operation, the DC-DC Converters are initially enabled in LDO mode
in order that the in-rush current does not exceed the USB limit. The LDO Regulators are also currentlimited during the soft start-up.
Care is required when using the 100mA soft-start; if the LDOs or DC-DCs present an excessive load,
then the WM8310 may be unable to power up; it must be ensured that the connected load is
compatible with the 100mA current limit. In particular, it is important that the loads on the DC-DC
Converters do not exceed the capacity of their LDO operating modes. (See Section 7.1 for the
maximum current in LDO mode.)
It is also possible to delay the USB start-up if the battery voltage is less than a selectable threshold; in
these cases, the WM8310 enables the battery trickle charge mode (provided that CHG_ENA = 1),
and delays the start-up request until the battery voltage threshold has been met. See also
Section 27.1 for specific external component requirements relating to the USB100MA_STARTUP
register setting.
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ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R16387
(4003h)
5:4
USB100MA_START
UP [1:0
00
Sets the device behaviour when starting
up under USB power, when USB_ILIM
= 010 (100mA)
Power
State
00 = Normal
01 = Soft-Start
10 = Only start if BATTVDD > 3.1V
11 = Only start if BATTVDD > 3.4V
In the 1X modes, if the battery voltage
is less than the selected threshold, then
the device will enable trickle charge
mode instead of executing the start-up
request. The start-up request is delayed
until the battery voltage threshold has
been met. Note that trickle charge is
only possible when CHG_ENA=1.
3
USB_CURR_STS
0
Indicates if the USB current limit has
been reached
0 = Normal
1 = USB current limit
2:0
USB_ILIM
010
Sets the USB current limit
000 = 0mA (USB switch is open)
001 = 2.5mA
010 = 100mA
011 = 500mA
100 = 900mA
101 = 1500mA
110 = 1800mA
111 = 550mA
Note that, when starting up the
WM8310 with the USBVDD supply
selected, the USB_ILIM register must
be set to 100mA or higher.
Table 55 Configuring the USB Power Operation
17.5 POWER PATH MANAGEMENT INTERRUPTS
The Power Path Management circuit is associated with three Interrupt event flags.
The PPM_SYSLO_EINT interrupt bit is set when the internal signal SYSLO is asserted. This indicates
a SYSVDD undervoltage condition, described in Section 24.4.
The PPM_PWR_SRC_EINT interrupt bit is set whenever the status of the Wall or USB supplies
changes, indicating a connection, disconnection, or a voltage. See Section 17.1.
The PPM_USB_CURR_EINT interrupt bit is set whenever the permitted USB current limit has been
reached. See Section 17.4.
Each of these secondary interrupts triggers a primary Power Path Management Interrupt, PPM_INT
(see Section 23). This can be masked by setting the mask bit(s) as described in Table 56.
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ADDRESS
R16401
(4011h)
BIT
15
LABEL
PPM_SYSLO_EINT
DESCRIPTION
Power Path SYSLO interrupt
(Rising Edge triggered)
Interrupt Status
1
Note: Cleared when a ‘1’ is written.
14
PPM_PWR_SRC_EINT
Power Path Source interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
13
PPM_USB_CURR_EINT
Power Path USB Current interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
R16409
(4019h)
15
IM_PPM_SYSLO_EINT
Interrupt mask.
0 = Do not mask interrupt.
Interrupt Status
1 Mask
1 = Mask interrupt.
Default value is 1 (masked)
14
IM_PPM_PWR_SRC_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
13
IM_PPM_USB_CURR_EIN
T
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Table 56 Power Path Management Interrupts
17.6 BACKUP POWER
As an option, a backup power source can be provided for the WM8310. This is provided using a coin
cell, super/gold capacitor, or else a standard capacitor, connected to the LDO12VOUT pin.
Note that a 22kΩ series resistor should also be connected to the backup power source.
The LDO12VOUT pin provides a constant-voltage output for charging the backup power source
whenever the SYSVDD power domain is available.
The purpose of the backup is to power the always-on functions such as the crystal oscillator, RTC and
ALARM control registers. The backup power also maintains a ‘software scratch’ memory area in the
register map - see Section 12.6. Maintaining these functions at all times provides system continuity
even when the main battery is removed and no other power supply is available.
The backup duration will vary depending upon the backup power source characteristics. A typical coin
cell can provide power to the WM8310 in BACKUP mode for a month or more whilst also
maintainingthe RTC and the ‘software scratch’ register.
If a standard capacitor is used as the backup power source, then it is particularly important to
minimise the device power consumption in the BACKUP state. A 22F capacitor will maintain the
device settings for up to 5 minutes in ‘unclocked’ mode, where power consumption is minimised by
stopping the RTC in the BACKUP state. The RTC is unclocked in the BACKUP state if the
XTAL_BKUPENA register field is set to 0, as described in Section 20.5.
17.7 BATTERY CHARGER
17.7.1
GENERAL DESCRIPTION
The WM8310 incorporates a battery charger which is designed for charging single-cell lithium
batteries. The battery charger can operate from either the Wall or USB power sources. The battery
charger implements constant-current (CC) and constant-voltage (CV) charge methods, and can run
automatically without any intervention required by the host processor.
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The battery charger voltage and current are programmable. Trickle charging and fast charging modes
are supported. In both modes, the SYSVDD voltage is monitored to ensure the power supply capacity
or USB current limit is not exceeded. If the SYSVDD voltage drops to 3.9V, (eg. if the USB current
limit has been reached), then the battery charge current is automatically reduced to try and prevent
further voltage drop at SYSVDD.
Under high operating load conditions, the battery may be required to supplement the USB or Wall
Adaptor power sources. Note that this capability is supported even when battery charging is enabled;
in this case, the battery provides power to the system when required, and the charger resumes when
sufficient current capacity is available.
Typical connections for the WM8310 battery charger are illustrated in Figure 25.
SYSVDD
Wall Adaptor Supply
System status
LED output
Main battery
connection
SYSVDD
Primary power
source
WM8310
Battery monitor
source
USB host
Battery temperature
measurement
USBVDD
BATTVDD
charge current
NTCBIAS
100K
WALLFETENA
Secondary power
source - used when
primary is unavailable
NTCMON
NTC
WALLVDD
Charge status
indicator LED
LED1
Single-cell
lithium battery
GND
Figure 25 Typical Connections for WM8310 Battery Charger
The main battery terminal is connected to BATTVDD. The WM8310 also incorporates a battery
temperature monitoring circuit, which monitors the NTC thermistor that is typically incorporated within
a rechargeable battery pack. The NTCMON pin allows the charger to detect a hot or cold battery
condition that may be outside the battery’s usable operating conditions. Battery removal is also
detected using the NTCMON pin.
The bias resistor connected between NTCBIAS and NTCMON should be a 1% tolerance resistor with
a nominal value equal to the value of the battery’s NTC thermistor at 25C.
The temperature monitoring circuit can be disabled by shorting NTCMON to LDO12VOUT. This is
only recommended if there is no NTC thermistor incorporated in the battery pack or if battery
temperature monitoring is provided by other methods. Note that the short between NTCMON and
LDO12VOUT is only sensed during start-up; the temperature monitoring circuit cannot be enabled /
disabled dynamically in the ON or SLEEP power states.
See Section 17.7.7 for more details of the battery temperature monitoring function.
A typical battery charge cycle is illustrated in Figure 26. This shows both the trickle charge and fast
charge processes.
The trickle charge mode is a constant current mode. The small charge current in this mode is suitable
for pre-conditioning a deeply discharged battery, or when only limited power is available for battery
charging. When the charger is enabled and the conditions for fast charging are not met, then trickle
charging is selected. (Note that fast charging is not permitted if the battery voltage is below the
defective battery threshold voltage.) Trickle charging is disabled when the charger enters the fast
charging stage, or when the charge current drops to a programmable ‘End of Charge’ threshold level
at the end of the constant voltage charge phase.
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The fast charge mode is also a constant current mode, but higher charge currents are possible in this
mode. In the fast charge phase, the WM8310 drives a programmable constant current into the battery
through the BATTVDD pin. During this phase, the battery voltage rises until the battery reaches the
target voltage.
When the battery reaches the target voltage (through trickle charge and/or fast charge), the charger
enters the constant voltage charge phase, in which the WM8310 regulates BATTVDD to the target
voltage. During this phase of the charge process, the charge current decreases over time as the
battery approaches its fully charged state. Battery charging is terminated when the current falls to a
programmable ‘End of Charge’ threshold level at the end of the constant voltage charge phase.
Note that, at any time during trickle charging or fast charging, the battery may be required to
supplement the USB or Wall Adaptor power source. In this case, the battery voltage may drop while it
is providing power to the system. The charger resumes operation automatically as soon as sufficient
current capacity is available from the main power source.
After the battery has been fully charged and the charge process has terminated, battery charging will
automatically re-start if the battery voltage falls below the charger re-start threshold.
Figure 26 A Typical Charge Cycle
17.7.2
BATTERY CHARGER ENABLE
The battery charger may be enabled when the WM8310 is in the ON or SLEEP power states. Note
that battery charging is only possible when the selected power source is within normal operating
limits. See Section 17.7.8 for further details of battery charging in the SLEEP power state.
The battery charger is enabled when the CHG_ENA register bit is set to 1. When enabled, it checks if
the conditions for charging are fulfilled and it controls the charging processes accordingly. The status
of the battery charger can be read from the CHG_ACTIVE register bit.
The target voltage for the battery is set by the CHG_VSEL field, as defined in Table 57. It is important
that this field is correctly set according to the type of battery that is connected. Incorrect setting of this
register may lead to a safety hazard condition.
The trickle charge current is selected using the CHG_TRKL_ILIM field. This is the maximum trickle
charge current - the actual charge current will be reduced if the battery is fully charged, or if the
system supply, SYSVDD, drops as described in Section 17.7.1.
When the battery reaches the target voltage, the charger enters the constant voltage charge phase, in
which the WM8310 regulates BATTVDD to the target voltage. When the charger is in the constant
voltage charge phase, then the CHG_TOPOFF bit will be set to indicate that the charge is
approaching completion.
The WM8310 incorporates thermal sensors to detect excessive temperatures within the device and to
provide self-protection (see Section 26). By default, the battery charger will be disabled if the Thermal
Warning condition occurs, and will be re-enabled after the condition has cleared. This response can
be disabled by setting CHG_CHIP_TEMP_MON = 0, allowing the battery charge to continue. The
Thermal Warning threshold is the lower of the two device temperature thresholds; the Thermal
Shutdown threshold is the higher threshold. Note that the Thermal Shutdown condition cannot be
ignored; this event causes a System Reset and a termination of battery charging.
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If the WM8310 is commanded to the OFF state for any reason, then battery charging will be
terminated. The CHG_OFF_MASK bit can be used to prevent certain OFF transitions whilst the
battery charger is active. Setting the CHG_OFF_MASK bit causes a ‘Software OFF request’, ‘ON pin
request’ or GPIO OFF request to be ignored whilst the charger is active. See Section 11.3 for a full list
of OFF transition events.
The register control fields for trickle charging are described in Table 57. See Section 17.7.4 for details
of battery charge termination.
Note that the Battery Charger control registers are locked by the WM8310 User Key. These registers
can only be changed by writing the appropriate code to the Security register, as described in
Section 12.4.
ADDRESS
BIT
R16456
(4048h)
15
LABEL
CHG_ENA
DEFAULT
0
DESCRIPTION
Battery Charger Enable
0 = Disable
Charger
Control 1
1 = Enable
Protected by user key
0
CHG_CHIP_TEMP_
MON
1
Battery Charger Thermal warning select
0 = Thermal Warning is ignored
1 = Thermal Warning pauses Battery
Charger
Protected by user key
R16457
(4049h)
14
CHG_OFF_MASK
0
Battery Charger OFF mask select
0 = OFF requests not masked
Charger
Control 2
1 = OFF requests masked during
Charging
Protected by user key
7:6
CHG_TRKL_ILIM
[1:0]
00
Battery Trickle Charge current limit
00 = 50mA
01 = 100mA
10 = 150mA
11 = 200mA
Protected by user key
5:4
CHG_VSEL [1:0]
00
Battery Charger target voltage
00 = 4.05V
01 = 4.10V
10 = 4.15V
11 = 4.20V
Note that incorrect setting of this
register may lead to a safety hazard
condition.
Protected by user key
R16458
(404Ah)
9
CHG_TOPOFF
0
Charger
Status
Battery Charger constant-voltage
charge mode status
0 = Constant-voltage mode not active
1 = Constant-voltage mode is active
8
CHG_ACTIVE
0
Battery Charger status
0 = Not charging
1 = Charging
Table 57 Battery Charger Control
The Battery Charger is associated with a number of Interrupt flags. Whenever the Battery Charger
state changes, the CHG_MODE_EINT interrupt is set (see Section 17.7.8). This interrupt is set
whenever charging starts, charging stops, fast charge is selected, fast charge is de-selected, an
overtemperature condition occurs, or if the charger detects a battery failure. The CHG_START_EINT
interrupt is also set whenever Battery Charging commences, including after pause due to USB limit or
over-temperature condition.
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17.7.3
FAST CHARGING
Fast charging provides a faster way to charge the battery than is possible with trickle charge. See
Section 17.7.1 for a description of fast charging.
Fast charging mode is only possible under certain conditions. It is only possible when the selected
power source is Wall or when the USB current limit is set to 500mA or more. It is also required that
the battery voltage is above the fast charge voltage threshold; this ensures that fast charging is not
applied to a heavily discharged battery.
Fast charging is enabled by setting the CHG_FAST register bit, provided that the conditions for fast
charging are satisfied. The fast charge current limit is selected using the CHG_FAST_ILIM field.
The battery charge current is automatically controlled, up to a maximum set by CHG_FAST_ILIM. The
current is automatically limited when required if the battery is fully charged, or if the system supply,
SYSVDD, drops as described in Section 17.7.1.
The fast charge mode comprises two phases, as described in Section 17.7.1. When the charger is in
the constant voltage charge phase, the CHG_TOPOFF bit will be set to indicate that the charge is
approaching completion.
When the battery reaches the target voltage, the charger enters the constant voltage charge phase, in
which the WM8310 regulates BATTVDD to the target voltage. When the charger is in the constant
voltage charge phase, then the CHG_TOPOFF bit will be set (see Section 17.7.2) to indicate that the
charge is approaching completion.
The register control fields for fast charging are described in Table 58. Note that the Battery Charger
control registers are locked by the WM8310 User Key. These registers can only be changed by
writing the appropriate code to the Security register, as described in Section 12.4.
ADDRESS
BIT
R16456
(4048h)
15
LABEL
CHG_FAST
DEFAULT
0
Battery Fast Charge Enable
0 = Disable
Charger
Control 1
R16457
(4049h)
DESCRIPTION
1 = Enable
Protected by user key
3:0
CHG_FAST_ILIM
[3:0]
Charger
Control 2
0010
Battery Fast Charge current limit
0000 = 0mA
0001 = 50mA
0010 = 100mA
0011 = 150mA
0100 = 200mA
0101 = 250mA
0110 = 300mA
0111 = 350mA
1000 = 400mA
1001 = 450mA
1010 = 500mA
1011 = 600mA
1100 = 700mA
1101 = 800mA
1110 = 900mA
1111 = 1000mA
Protected by user key
Table 58 Fast Charge Control
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17.7.4
CHARGER TIMEOUT AND TERMINATION
Fast charging and trickle charging is terminated under any of the following conditions:

Charge current falls below the ‘End of Charge’ threshold

Charger timeout

Battery fault or overvoltage condition (see Section 17.7.6)

Chip overtemperature condition (see Section 17.7.2)

Transition to the OFF power state
The End of Charge current threshold can be set using the CHG_ITERM register field, as defined in
Table 59. Charging is terminated when the charge current is below the CHG_ITERM threshold,
provided also that the battery voltage has reached the target voltage CHG_VSEL at the end of the
constant voltage charge phase.
If the battery charger current is reduced or paused due to a drop in SYSVDD voltage (as described in
Section 17.7.1), then the End of Charge current threshold does not cause battery charging to be
terminated, as the charge current is not indicative of the battery charge status in this case.
The battery charger has a programmable safety timer to control the battery charge duration. The timer
is started when either fast charging or trickle charging commences, including charging that is
triggered as a result of the battery voltage dropping to the charger re-start threshold. The timer is restarted if the charging mode is changed (eg. between fast charge and trickle charge modes). The
timeout period may be set by writing to the CHG_TIME register field; this allows charge times of up to
510mins (8.5 hours) to be selected.
When the timeout period completes, the battery charge cycle is terminated. In this event, the charger
will not re-start until the charger has been disabled (CHG_ENA = 0) and then re-enabled (CHG_ENA
= 1). Note that the charger re-start threshold is ignored in this case, and the charger will not re-start
automatically.
The elapsed battery charge time can be read from the CHG_TIME_ELAPSED register field. This field
is reset whenever the charger timer is started (ie. by starting charging, stopping charging, or changing
charging modes).
If charging is paused due to a battery temperature or chip temperature condition, then the charge
timer is paused until charging resumes.
Battery charging is terminated if removal of the battery is detected via the NTC monitor connections
(see Section 17.7.2).
The register control fields for battery charger termination are described in Table 59. Note that the
Battery Charger control registers are locked by the WM8310 User Key. These registers can only be
changed by writing the appropriate code to the Security register, as described in Section 12.4.
ADDRESS
R16456
(4048h)
Charger
Control 1
BIT
12:10
LABEL
CHG_ITERM
[2:0]
DEFAULT
000
DESCRIPTION
Battery End of Charge current threshold
000 = 20mA
001 = 30mA
010 = 40mA
011 = 50mA
100 = 60mA
101 = 70mA
110 = 80mA
111 = 90mA
Protected by user key
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ADDRESS
R16457
(4049h)
BIT
11:8
LABEL
CHG_TIME
[3:0]
DEFAULT
0110
DESCRIPTION
Battery charger timeout
0000 = 60min
Charger
Control 2
0001 = 90min
0010 = 120min
0011 = 150min
0100 = 180min
0101 = 210min
0110 = 240min
0111 = 270min
1000 = 300min
1001 = 330min
1010 = 360min
1011 = 390min
1100 = 420min
1101 = 450min
1110 = 480min
1111 = 510min
Protected by user key
R16458
(404Ah)
7:0
CHG_TIME_EL
APSED [7:0]
00h
Battery charger elapsed time
00h = 0min
Charger Status
01h = 2min
02h = 4min
03h = 6min
...
FFh = 510min
Table 59 Battery Charger Termination
The Battery Charger is associated with a number of Interrupt flags, as described in Section 17.7.8. If
battery charging is terminated due to the End of Charge current threshold being reached, then the
CHG_END_EINT interrupt is set. If battery charging is terminated due to the charge timeout, then the
charger will set the CHG_TO_EINT interrupt.
17.7.5
BATTERY CHARGE CURRENT MONITORING
The battery charge current can be monitored externally or internally. When the CHG_IMON_ENA bit
is set, then the WM8310 sources an output current at AUXADCIN1 which is proportional to the battery
charger current.
When a resistor is connected between AUXADCIN1 and GND, then the charge monitor current is
converted to a voltage which can be measured by the Auxiliary ADC. The recommended value of the
resistor is 10k. Larger resistors may also be used in order to improve the measurement resolution,
but the voltage at AUXADCIN1 must not exceed 2.5V.
Note that the CHG_IMON_ENA register is locked by the WM8310 User Key. This register can only be
changed by writing the appropriate code to the Security register, as described in Section 12.4.
ADDRESS
R16456
(4048h)
BIT
2
LABEL
DEFAULT
CHG_IMON_E
NA
0
Charger
Control 1
DESCRIPTION
Enable battery charge current monitor at
AUXADCIN1.
0 = Disabled
1 = Enabled
(Note - a resistor is required between
AUXADCIN1 and GND in order to
measure the charge current using the
AUXADC. The recommended resistor
value is 10k.)
Protected by user key
Table 60 Battery Charge Current Monitoring
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The AUXADCIN1 monitor output current is equal to the battery charge current divided by 12500. The
battery charge current can be determined by measuring the voltage at the AUXADCIN1 pin, as
described in the following equations.
Monitor Current IM =
Charge Current IC =
Charge Current IC
12500
=
VAUXADCIN1
R
VAUXADCIN1 x 12500
(assuming 10k resistor, R)
10000
For example, a measurement of 0.72V at AUXADCIN1 would indicate that the battery charge current
is 900mA.
Note that the integrated Auxiliary ADC can be used to perform this measurement if required. In this
case, the digitised AUXADC measurement (AUX_DATA) represents the battery charge current in
accordance with the following equation.
See Section 18 for further details of the Auxiliary ADC.
17.7.6
BATTERY FAULT / OVERVOLTAGE CONDITIONS
The battery is monitored to detect an overvoltage or failure condition. These features are incorporated
to prevent malfunction of the battery charger or of the WM8310 system.
The BATT_OV_STS bit indicates if an overvoltage condition has been detected. The overvoltage
threshold is defined in Section 7.7. If a battery overvoltage condition is detected, then charging is
terminated and the CHG_OV_EINT interrupt flag is set (see Section 17.7.8).
The battery charger also detects if the battery is faulty. This is detected if the battery voltage does not
reach the fast charge threshold voltage within the defective battery timeout period (see Section 7.7),
or within a quarter of the charging time CHG_TIME (whichever is the longer time).
The battery failure condition is cleared if the battery voltage rises above the defective battery
threshold, or if any of the WM8310 power sources (including the battery) is removed and reconnected. When the failure condition is cleared, the charger then reverts back to its initial state, and
may re-start if the conditions for charging are fulfilled.
If the battery failure condition is detected in fast charge mode, then the charger reverts to trickle
charging mode. If the fault persists, then trickle charging stops as described above.
If battery failure condition is detected, then charging is terminated and the CHG_BATT_FAIL_EINT
interrupt is set (see Section 17.7.8).
The battery overvoltage bit is defined in Table 61.
ADDRESS
R16458
(404Ah)
BIT
15
LABEL
DEFAULT
BATT_OV_STS
0
Charger Status
DESCRIPTION
Battery Overvoltage status
0 = Normal
1 = Battery Overvoltage
Table 61 Battery Overvoltage Status
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17.7.7
BATTERY TEMPERATURE MONITORING
As described in Section 17.7.1, the WM8310 is designed to monitor battery temperature using a
standard NTC thermistor component which is typically incorporated within the battery pack. This
allows the battery charger to detect a hot or cold battery condition that may be outside the battery’s
usable operating conditions. (Note that the temperature monitoring circuit also detects if the NTC
circuit is not connected, in order to mask any erroneous fault indications.)
The BATT_HOT_STS and BATT_COLD_STS register bits indicate if a hot battery or cold battery
temperature condition has been detected. If a battery temperature fault condition is detected, then
charging is paused temporarily and the CHG_BATT_HOT_EINT or CHG_BATT_COLD_EINT
interrupt is set (see Section 17.7.8).
Under typical circuit configurations, the hot and cold temperature conditions are designed to be +40C
and 0C respectively. These temperatures can be adjusted by the use of different resistor
components, as described in the Applications Information in Section 30.6.
Battery removal is also detected using the NTC circuit. This is used to terminate battery charging if a
battery is removed during charging.
The temperature monitoring circuit can be disabled by shorting NTCMON to LDO12VOUT. This is
only recommended if there is no NTC thermistor incorporated in the battery pack or if battery
temperature monitoring is provided by other methods. Note that the short between NTCMON and
LDO12VOUT is only sensed during start-up; the temperature monitoring circuit cannot be enabled /
disabled dynamically in the ON or SLEEP power states.
The battery temperature status bits are described in Table 62.
ADDRESS
R16458
(404Ah)
BIT
11
LABEL
DEFAULT
BATT_HOT_ST
S
0
BATT_COLD_
STS
0
DESCRIPTION
Battery Hot status
0 = Normal
Charger Status
1 = Battery Hot
10
Battery Cold status
0 = Normal
1 = Battery Cold
Table 62 Battery Temperature Status
Battery temperature monitoring is configured as illustrated in Figure 27. The principle of operation is
that a temperature change in the battery pack causes a change in resistance of the NTC thermistor,
which results in a voltage change at the NTCMON pin.
VNTCMON =
Battery monitor
source
NTCBIAS
WM8310
NTC bias resistor RBIAS (100k)
NTCMON
NTC thermistor RNTC (100k at 25 C)
NTC
Battery temperature
measurement
x VNTCBIAS
BATTVDD
100K
Main battery
connection
RNTC
100k + RNTC
Single-cell
lithium battery
GND
Figure 27 Battery Temperature Monitoring
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For information on how to set the hot and cold temperature limits, see the Applications Information in
Section 30.6.
17.7.8
BATTERY CHARGER INTERRUPTS
The Battery Charger is associated with a number of Interrupt event flags, described in Table 63. Each
of these secondary interrupts triggers a primary Battery Charger Interrupt, CHG_INT (see Section 23).
This can be masked by setting the mask bit(s) as described in Table 63.
If any Battery Charger interrupt event occurs while in the SLEEP power state, then a WAKE transition
request is generated. Note that this behaviour is not affected by any of the interrupt mask bits. See
Section 11.3 for a description of the WM8310 power state transitions.
If any of the Battery Charger Interrupts is asserted when a SLEEP transition is requested, then the
transition will be unsuccessful and the WM8310 will remain in the ON power state.
If battery charging is commenced in the SLEEP power state, the WM8310 will transition to the ON
power state, as a result of the CHG_START_EINT interrupt. Battery charging in the SLEEP power
state is only possible by clearing the CHG_START_EINT interrupt before commanding the transition
into the SLEEP power state.
ADDRESS
R16402
(4012h)
Interrupt Status
2
BIT
15
LABEL
CHG_BATT_HOT_EINT
DESCRIPTION
Battery Hot interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
14
CHG_BATT_COLD_EINT
Battery Cold interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
13
CHG_BATT_FAIL_EINT
Battery Fail interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
12
CHG_OV_EINT
Battery Overvoltage interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
11
CHG_END_EINT
Battery Charge End interrupt (End of
Charge Current threshold reached)
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
10
CHG_TO_EINT
Battery Charge Timeout interrupt (Charger
Timer has expired)
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
9
CHG_MODE_EINT
Battery Charge Mode interrupt (Charger
Mode has changed)
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
8
CHG_START_EINT
Battery Charge Start interrupt (Charging
has started)
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
R16410
(401Ah)
15
IM_CHG_BATT_HOT_EINT
Interrupt mask.
0 = Do not mask interrupt.
Interrupt Status
2 Mask
1 = Mask interrupt.
Default value is 1 (masked)
14
IM_CHG_BATT_COLD_EIN
T
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
13
IM_CHG_BATT_FAIL_EINT
Interrupt mask.
0 = Do not mask interrupt.
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ADDRESS
BIT
LABEL
DESCRIPTION
1 = Mask interrupt.
Default value is 1 (masked)
12
IM_CHG_OV_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
11
IM_CHG_END_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
10
IM_CHG_TO_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
9
IM_CHG_MODE_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
8
IM_CHG_START_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Table 63 Battery Charger Interrupts
17.7.9
BATTERY CHARGER STATUS
The status of the Battery Charger can be read from various registers and interrupts noted in the
above sections. The Battery Charger status can also be read from the CHG_STATE register field, as
defined in Table 64.
Note that the LED Status outputs can also be configured to indicate the Battery Charger - see
Section 22.
ADDRESS
R16458
(404Ah)
BIT
14:12
LABEL
CHG_STATE
[2:0]
Charger Status
DEFAULT
000
DESCRIPTION
Battery Charger state
000 = Off
001 = Trickle Charge
010 = Fast Charge
011 = Trickle Charge overtemperature
100 = Fast Charge overtemperature
101 = Defective
110 = Reserved
111 = Reserved
Table 64 Battery Charger State
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18 AUXILIARY ADC
18.1 GENERAL DESCRIPTION
The WM8310 incorporates a 12-bit Auxiliary ADC (AUXADC). This can be used to perform a number
of system measurements (including supply voltages and battery temperature) and can also be used to
measure analogue voltages from external sources and sensors.
External inputs to the AUXADC should be connected to the pins AUXADCIN1, AUXADCIN2,
AUXADCIN3 and AUXADCIN4. The maximum voltage that can be measured is determined by the
power domain associated with each (see Section 3). In the case of AUXADCIN 1-3, the maximum
voltage is SYSVDD; in the case of AUXADCIN4, the maximum voltage is DBVDD. Note that SYSVDD
varies according to the voltage of the preferred power source (WALLVDD, USBVDD or BATTVDD).
The AUXADC can also measure the voltage on WALLVDD, USBVDD and BATTVDD. Internal
resistor dividers enable voltages higher than SYSVDD to be measured by the AUXADC - voltages up
to 6V can be measured on these pins.
18.2 AUXADC CONTROL
The AUXADC is enabled by setting the AUX_ENA register bit. By default, the AUXADC is not enabled
in the SLEEP state, but this can be selected using the AUX_SLPENA field.
The AUXADC measurements can be initiated manually or automatically. For automatic operation, the
AUX_RATE register is set according to the required conversion rate, and conversions are enabled by
setting the AUX_CVT_ENA bit. For manual operation, the AUX_RATE register is set to 00h, and each
manual conversion is initiated by setting the AUX_CVT_ENA bit. In manual mode, the
AUX_CVT_ENA bit is reset by the WM8310 after each conversion. (Note that the conversion result is
not available for readback until the AUXADC interrupt is asserted as described in Section 18.5.)
The AUXADC has 10 available input sources. Each of these inputs is enabled by setting the
respective bit in the AuxADC Source Register (R16431).
For each AUXADC measurement event (in Manual or Automatic modes), the WM8310 selects the
next enabled input source. Any number of inputs may be selected simultaneously; the AUXADC will
measure each one in turn. Note that only a single AUXADC measurement is made on any Manual or
Automatic trigger.
For example, if the AUX1, BATT and USB voltages are enabled for AUXADC measurement, then
AUX1 would be measured in the first instance, and BATT then USB would be measured on the next
manual or automatic AUXADC triggers. In this case, a total of three manual or automatic AUXADC
triggers would be required to measure all of the selected inputs.
The control fields associated with initiating AUXADC measurements are defined in Table 65.
ADDRESS
R16430
(402Eh)
BIT
15
LABEL
AUX_ENA
DEFAULT
0
DESCRIPTION
AUXADC Enable
0 = Disabled
AuxADC
Control
1 = Enabled
Note - this bit is reset to 0 when the OFF
power state is entered.
14
AUX_CVT_ENA
0
AUXADC Conversion Enable
0 = Disabled
1 = Enabled
In automatic mode, conversions are
enabled by setting this bit.
In manual mode (AUX_RATE = 0),
setting this bit will initiate a conversion;
the bit is reset automatically after each
conversion.
12
AUX_SLPENA
0
AUXADC SLEEP Enable
0 = Disabled
1 = Controlled by AUX_ENA
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ADDRESS
BIT
5:0
LABEL
AUX_RATE [5:0]
DEFAULT
00_0000
DESCRIPTION
AUXADC Conversion Rate
0 = Manual
1 = 2 samples/s
2 = 4 samples/s
3 = 6 samples/s
…
31 = 62 samples/s
32 = Reserved
33 = 16 samples/s
34 = 32 samples/s
35 = 48 samples/s
…
63 = 496 samples/s
R16431
(402Fh)
AuxADC
Source
9
AUX_WALL_SEL
0
AUXADC WALL input select
0 = Disable WALLVDD measurement
1 = Enable WALLVDD measurement
8
AUX_BATT_SEL
0
AUXADC BATT input select
0 = Disable BATTVDD measurement
1 = Enable BATTVDD measurement
7
AUX_USB_SEL
0
AUXADC USB input select
0 = Disable USBVDD measurement
1 = Enable USBVDD measurement
6
AUX_SYSVDD_S
EL
0
AUX_BATT_TEM
P_SEL
0
AUX_CHIP_TEM
P_SEL
0
AUXADC SYSVDD input select
0 = Disable SYSVDD measurement
1 = Enable SYSVDD measurement
5
AUXADC Battery Temp input select
0 = Disable Battery Temp measurement
1 = Enable Battery Temp measurement
4
AUXADC Chip Temp input select
0 = Disable Chip Temp measurement
1 = Enable Chip Temp measurement
3
AUX_AUX4_SEL
0
AUXADCIN4 input select
0 = Disable AUXADCIN4 measurement
1 = Enable AUXADCIN4 measurement
2
AUX_AUX3_SEL
0
AUXADCIN3 input select
0 = Disable AUXADCIN3 measurement
1 = Enable AUXADCIN3 measurement
1
AUX_AUX2_SEL
0
AUXADCIN2 input select
0 = Disable AUXADCIN2 measurement
1 = Enable AUXADCIN2 measurement
0
AUX_AUX1_SEL
0
AUXADCIN1 input select
0 = Disable AUXADCIN1 measurement
1 = Enable AUXADCIN1 measurement
Table 65 AUXADC Control
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18.3 AUXADC READBACK
Measured data from the AUXADC is read via the AuxADC Data Register (R16429), which contains
two fields. The AUXADC Data Source is indicated in the AUX_DATA_SRC field; the associated
measurement data is contained in the AUX_DATA field.
Reading from the AuxADC Data Register returns a 12-bit code which represents the most recent
AUXADC measurement on the associated channel. It should be noted that every time an AUXADC
measurement is written to the AuxADC Data Register, the previous data is overwritten - the host
processor should ensure that data is read from this register before it is overwritten. The AUXADC
interrupts can be used to indicate when new data is available - see Section 18.5.
The 12-bit AUX_DATA field can be equated to the actual voltage (or temperature) according to the
following equations, where AUX_DATA is regarded as an unsigned integer:
Battery Temperature measurement varies according to the selected NTC thermistor component.
In a typical application, it is anticipated that the AUXADC Interrupts would be used to control the
AUXADC readback - the host processor should read the AUXADC Data Register in response to the
AUXADC Interrupt event. See Section 18.5 for details of AUXADC Interrupts. In Automatic AUXADC
mode, the processor should complete this action before the next measurement occurs, in order to
avoid losing any AUXADC samples. In Manual conversion mode, the interrupt signal provides
confirmation that the commanded measurement has been completed.
The control fields associated with initiating AUXADC readback are defined in Table 66.
ADDRESS
R16429
(402Dh)
BIT
LABEL
DEFAULT
15:12
AUX_DATA_SRC
[3:0]
000
DESCRIPTION
AUXADC Data Source
0 = Reserved
AuxADC Data
1 = AUXADCIN1
2 = AUXADCIN2
3 = AUXADCIN3
4 = AUXADCIN4
5 = Chip Temperature
6 = Battery Temperature
7 = SYSVDD voltage
8 = USB voltage
9 = BATT voltage
10 = WALL voltage
11 = Reserved
12 = Reserved
13 = Reserved
14 = Reserved
15 = Reserved
11:0
AUX_DATA [11:0]
000h
AUXADC Measurement Data
Voltage (mV) = AUX_DATA x 1.465
ChipTemp (C) = (498 - AUX_DATA) /
1.09
BattTemp (C) = (value is dependent on
NTC thermistor)
Table 66 AUXADC Readback
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18.4 DIGITAL COMPARATORS
The WM8310 has four digital comparators which may be used to compare AUXADC measurement
data against programmable threshold values. Each comparator has a status bit, and also an
associated interrupt flag (described in Section 18.5), which indicates that the associated data is
beyond the threshold value.
The digital comparators are enabled using the DCMPn_ENA register bits as described in Table 65.
After an AUXADC conversion, the measured value is compared with the threshold level of any
associated comparator(s). Note that this comparison is only performed following a conversion.
The source data for each comparator is selected using the DCMPn_SRC register bits; this selects
one of eight possible AUXADC channels for each comparator. If required, the same AUXADC
channel may be selected for more than one comparator; this would allow more than one threshold to
be monitored on the same AUXADC channel. Note that the coding of the 000b value of the
DCMPn_SRC fields differs between the four comparators.
The DCMPn_GT register bits select whether the status bit and associated interrupt flag will be
asserted when the measured value is above the threshold or when the measured value is below the
threshold. The output of the most recent threshold comparison is indicated in the DCOMPn_STS
fields.
The threshold DCMPn_THR is a 12-bit code for each comparator. This field follows the same voltage
or temperature coding as the associated AUXADC channel source (see Section 18.3).
ADDRESS
BIT
R16432 (4030h)
11
LABEL
DCOMP4_STS
DEFAULT
0
Comparator
Control
DESCRIPTION
Digital Comparator 4 status
0 = Comparator 4 threshold not
detected
1 = Comparator 4 threshold detected
(Trigger is controlled by DCMP4_GT)
10
DCOMP3_STS
0
Digital Comparator 3 status
0 = Comparator 3 threshold not
detected
1 = Comparator 3 threshold detected
(Trigger is controlled by DCMP3_GT)
9
DCOMP2_STS
0
Digital Comparator 2 status
0 = Comparator 2 threshold not
detected
1 = Comparator 2 threshold detected
(Trigger is controlled by DCMP2_GT)
8
DCOMP1_STS
0
Digital Comparator 1 status
0 = Comparator 1 threshold not
detected
1 = Comparator 1 threshold detected
(Trigger is controlled by DCMP1_GT)
3
DCMP4_ENA
0
Digital Comparator 4 Enable
0 = Disabled
1 = Enabled
2
DCMP3_ENA
0
Digital Comparator 3 Enable
0 = Disabled
1 = Enabled
1
DCMP2_ENA
0
Digital Comparator 2 Enable
0 = Disabled
1 = Enabled
0
DCMP1_ENA
0
Digital Comparator 1 Enable
0 = Disabled
1 = Enabled
R16433 (4031h)
Comparator 1
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DCMP1_SRC
[2:0]
000
Digital Comparator 1 source select
0 = USB voltage
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ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
1 = AUXADCIN1
2 = AUXADCIN2
3 = AUXADCIN3
4 = AUXADCIN4
5 = Chip Temperature
6 = Battery Temperature
7 = SYSVDD voltage
12
DCMP1_GT
0
Digital Comparator 1 interrupt control
0 = interrupt when less than threshold
1 = interrupt when greater than or equal
to threshold
11:0
DCMP1_THR
000h
Digital Comparator 1 threshold
(12-bit unsigned binary number; coding
is the same as AUX_DATA)
R16434 (4032h)
15:13
Comparator 2
DCMP2_SRC
[2:0]
000
Digital Comparator 2 source select
0 = WALL voltage
1 = AUXADCIN1
2 = AUXADCIN2
3 = AUXADCIN3
4 = AUXADCIN4
5 = Chip Temperature
6 = Battery Temperature
7 = SYSVDD voltage
12
DCMP2_GT
0
Digital Comparator 2 interrupt control
0 = interrupt when less than threshold
1 = interrupt when greater than or equal
to threshold
11:0
DCMP2_THR
000h
Digital Comparator 2 threshold
(12-bit unsigned binary number; coding
is the same as AUX_DATA)
R16435 (4033h)
15:13
Comparator 3
DCMP3_SRC
[2:0]
000
Digital Comparator 3 source select
0 = BATT voltage
1 = AUXADCIN1
2 = AUXADCIN2
3 = AUXADCIN3
4 = AUXADCIN4
5 = Chip Temperature
6 = Battery Temperature
7 = SYSVDD voltage
12
DCMP3_GT
0
Digital Comparator 3 interrupt control
0 = interrupt when less than threshold
1 = interrupt when greater than or equal
to threshold
11:0
DCMP3_THR
000h
Digital Comparator 3 threshold
(12-bit unsigned binary number; coding
is the same as AUX_DATA)
R16436 (4034h)
Comparator 4
15:13
DCMP4_SRC
[2:0]
000
Digital Comparator 4 source select
0 = Reserved
1 = AUXADCIN1
2 = AUXADCIN2
3 = AUXADCIN3
4 = AUXADCIN4
5 = Chip Temperature
6 = Battery Temperature
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ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
7 = SYSVDD voltage
12
DCMP4_GT
0
Digital Comparator 4 interrupt control
0 = interrupt when less than threshold
1 = interrupt when greater than or equal
to threshold
11:0
DCMP4_THR
000h
Digital Comparator 4 threshold
(12-bit unsigned binary number; coding
is the same as AUX_DATA)
Table 67 AUXADC Digital Comparator Control
18.5 AUXADC INTERRUPTS
The AUXADC is associated with a number of Interrupt event flags to indicate when new AUXADC
data is ready, or to indicate that one or more of the digital comparator thresholds has been crossed.
Each of these secondary interrupts triggers a primary AUXADC Interrupt, AUXADC_INT (see
Section 23). This can be masked by setting the mask bit(s) as described in Table 68.
Note that AUXADC_DATA_EINT is not cleared by reading the measured AUXADC data, it can only
be cleared by writing ‘1’ to the AUXADC_DATA_EINT register.
The AUXADC interrupts can be programmed using bits in Table 68.
ADDRESS
R16401
(4011h)
Interrupt Status
1
BIT
8
LABEL
AUXADC_DATA_EINT
DESCRIPTION
AUXADC Data Ready interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
7:4
AUXADC_DCOMPn_EINT
AUXADC Digital Comparator n interrupt
(Trigger is controlled by DCMPn_GT)
Note: Cleared when a ‘1’ is written.
R16409
(4019h)
8
IM_AUXADC_DATA_EINT
Interrupt mask.
0 = Do not mask interrupt.
Interrupt Status
1 Mask
1 = Mask interrupt.
Default value is 1 (masked)
7:4
IM_AUXADC_DCOMPn_EI
NT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Note: n is a number between 1 and 4 that identifies the individual Comparator.
Table 68 AUXADC Interrupts
19 RESERVED
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20 REAL-TIME CLOCK (RTC)
20.1 GENERAL DESCRIPTION
The WM8310 provides a Real Time Clock (RTC) in the form of a 32-bit counter. The RTC uses the
32.768kHz crystal oscillator as its clock source and increments the register value once per second.
(Note that a direct CMOS input may be used in place of the crystal oscillator; both options are
described in Section 13.) To compensate for errors in the clock frequency, the RTC includes a
frequency trim capability.
The RTC is enabled at all times, including when the WM8310 is in the BACKUP state. When required,
the RTC can be maintained via a backup battery in the absence of any other power supply. In the
absence of a backup battery, the RTC contents can be held (unclocked) for a limited period of up to 5
minutes via a 22F capacitor.
The RTC incorporates an Alarm function. The Alarm time is held in a 32-bit register. When the RTC
counter matches the Alarm time, a selectable response will be actioned.
For digital rights management purposes, the RTC includes security features designed to detect
unauthorised modifications to the RTC counter.
20.2 RTC CONTROL
The 32-bit RTC counter value, RTC_TIME is held in two 16-bit registers, R16417 (4021h) and
R16418 (4022h). The value of RTC_TIME is incremented by the WM8310 once per second. On initial
power-up (from the NO POWER state), these registers will be initialised to default values. Once either
of these registers has been written to, the RTC_VALID bit is set to indicate that the RTC_TIME
registers contain valid data.
When RTC registers are updated, the RTC_SYNC_BUSY bit indicates that the RTC is busy. The RTC
registers should not be written to when RTC_SYNC_BUSY = 1.
The RTC_WR_CNT field is provided as a security feature for the RTC. After initialisation, this field is
updated on every write to R16417 (4021h) or to R16418 (4022h). This enables the host processor to
detect unauthorised modifications to the RTC counter value. See Section 20.4 for more details.
For additional security, the WM8310 does not allow the RTC to be updated more than 8 times in a
one-hour period. Additional write attempts will be ignored.
The RTC Alarm time is held in registers R16419 (4023h) and R16420 (4024h). The Alarm function is
enabled when RTC_ALM_ENA is set. When the Alarm is enabled, and the RTC counter matches the
Alarm time, the RTC Alarm Interrupt is triggered, as described in Section 20.3.
If the RTC Alarm occurs in the SLEEP power state, then a WAKE transition request is generated. If
the RTC Alarm occurs in the OFF power state, then an ON transition request is generated. See
Section 11.3 for details.
When updating the RTC Alarm time, it is recommended to disable the Alarm first, by setting
RTC_ALM_ENA = 0. The RTC Alarm registers should not be written to when RTC_SYNC_BUSY = 1.
The RTC has a frequency trim feature to allow compensation for known and constant errors in the
crystal oscillator frequency up to ±8Hz. The RTC_TRIM field is a 10-bit fixed point 2’s complement
number. MSB scaling = -8Hz. To compensate for errors in the clock frequency, this register should be
set to the error (in Hz) with respect to the ideal (32768Hz) of the input crystal frequency.
For example, if the actual crystal frequency = 32769.00Hz, then the frequency error = +1Hz. The
value of RTC_TRIM in this case is 0001_000000.
For example, if the actual crystal frequency = 32763.78Hz, then the frequency error = -4.218750Hz.
The value of RTC_TRIM in this case is 1011_110010.
Note that the RTC_TRIM control register is locked by the WM8310 User Key. This register can only
be changed by writing the appropriate code to the Security register, as described in Section 12.4.
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ADDRESS
R16416
(4020h)
BIT
15:0
LABEL
RTC_WR_CNT
DEFAULT
0000h
This random number is updated on every
write to the RTC_TIME registers.
RTC Write
Counter
R16417
(4021h)
15:0
RTC_TIME
[31:16]
0000h
15:0
RTC_TIME [15:0]
0000h
RTC Seconds counter (LSW)
RTC_TIME increments by 1 every
second. This is the 16 LSBs.
RTC Time 2
R16419
(4023h)
RTC Seconds counter (MSW)
RTC_TIME increments by 1 every
second. This is the 16 MSBs.
RTC Time 1
R16418
(4022h)
DESCRIPTION
RTC Write Counter.
15:0
RTC_ALM [31:16]
0000h
RTC Alarm time (MSW)
16 MSBs of RTC_ALM
RTC Alarm 1
R16420
(4024h)
15:0
RTC_ALM [15:0]
0000h
RTC Alarm time (LSW)
16 LSBs of RTC_ALM
RTC Alarm 2
R16421
(4025h)
15
RTC_VALID
0
RTC Valid status
0 = RTC_TIME has not been set since
Power On Reset
RTC Control
1 = RTC_TIME has been written to since
Power On Reset
14
RTC_SYNC_BUS
Y
0
RTC Busy status
0 = Normal
1 = Busy
The RTC registers should not be written
to when RTC_SYNC_BUSY = 1.
10
RTC_ALM_ENA
0
RTC Alarm Enable
0 = Disabled
1 = Enabled
R16422
(4026h)
9:0
RTC_TRIM
RTC Trim
000h
RTC frequency trim. Value is a 10bit
fixed point <4,6> 2’s complement
number. MSB Scaling = -8Hz.
The register indicates the error (in Hz)
with respect to the ideal 32768Hz) of the
input crystal frequency.
Protected by user key
Table 69 Real Time Clock (RTC) Control
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20.3 RTC INTERRUPTS
The Real Time Clock (RTC) is associated with two Interrupt event flags.
The RTC_PER_EINT interrupt is set each time a periodic timeout occurs. The periodic timeout is
configured using the RTC_PINT_FREQ field described in Table 71.
The RTC_ALM_EINT interrupt is set when the RTC Alarm is triggered. The RTC Alarm time is
configured as described in Section 20.2.
Each of these secondary interrupts triggers a primary Real Time Clock Interrupt, RTC_INT (see
Section 23). This can be masked by setting the mask bit(s) as described in Table 70.
ADDRESS
R16401
(4011h)
Interrupt Status
1
BIT
3
LABEL
DESCRIPTION
RTC_PER_EINT
RTC Periodic interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
2
RTC_ALM_EINT
RTC Alarm interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
R16409
(4019h)
3
IM_RTC_PER_EINT
Interrupt mask.
0 = Do not mask interrupt.
Interrupt Status
1 Mask
1 = Mask interrupt.
Default value is 1 (masked)
2
IM_RTC_ALM_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Table 70 Real Time Clock (RTC) Interrupts
The frequency of the RTC periodic interrupts is set by the RTC_PINT_FREQ field, as described in
Table 71.
ADDRESS
R16421
(4025h)
BIT
LABEL
DEFAULT
6:4
RTC_PINT_FREQ
[2:0]
000
RTC Control
DESCRIPTION
RTC Periodic Interrupt timeout period
000 = Disabled
001 = 2s
010 = 4s
011 = 8s
100 = 16s
101 = 32s
110 = 64s
111 = 128s
Table 71 Real Time Clock (RTC) Periodic Interrupt Control
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20.4 DIGITAL RIGHTS MANAGEMENT
The Real Time Clock (RTC) maintains a continuous record of the time; this is maintained at all times,
including when the WM8310 is powered down and the RTC function is maintained by the backup
supply.
It is highly desirable to be able to write to the RTC counter in order to configure it for logical
translation into hours/minutes and to support calendar functions. However, for digital rights
management purposes, it is important that malicious modification of the RTC is either prevented or
detected.
The security measure implemented on the WM8310 is the RTC Write Counter. This register is
initialised to 0000h during Power On Reset, and is updated automatically whenever a Write operation
is scheduled on either of the RTC_TIME registers. Note that, when the RTC Write Counter is updated,
the new value is generated at random; it is not a sequential counter.
It is assumed that legitimate updates to the RTC_TIME are only those initiated by the Application
Processor (AP). When the AP makes an update to the RTC_TIME, the AP can also read the new
value of the RTC Write Counter, and should store the value in non-volatile memory. If the AP detects
a change in value of the RTC Write Counter, and this was not caused by the AP itself writing to the
RTC_TIME, this means that an unauthorised write to the RTC_TIME registers has occurred.
In order to make it difficult for an unauthorised RTC_TIME update to be masked by simply writing to
the RTC Write Counter, the RTC_WR_CNT field is generated at random by the WM8310 whenever
the RTC_TIME field is updated.
For additional security, the WM8310 does not allow the RTC to be updated more than 8 times in a
one-hour period. Additional write attempts will be ignored.
The RTC Control registers are described in Table 69.
20.5 BACKUP MODE CLOCKING OPTIONS
The BACKUP state is entered when the available power supplies are below the reset threshold of the
device. Typically, this means that USB or Wall supplies are not present and that the main battery is
either discharged or removed. Most of the device functions and registers are reset in this state.
The RTC and oscillator and a ‘software scratch’ memory area can be maintained from a backup
power source in the BACKUP state. This is provided using a coin cell, super/gold capacitor, or else a
standard capacitor, connected to the LDO12VOUT pin via a 22kΩ resistor. See Section 17.6 for
further details.
The RTC and oscillator can be disabled in the BACKUP state by setting the XTAL_BKUPENA register
bit to 0. This feature may be used to minimise the device power consumption in the BACKUP state. A
22F capacitor connected to LDO12VOUT can maintain the RTC value, unclocked, for up to 5
minutes in BACKUP if the oscillator is disabled.
The XTAL_BKUPENA register bit is defined in Section 13.1. For more details on backup power, see
Section 17.6.
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21 GENERAL PURPOSE INPUTS / OUTPUTS (GPIO)
21.1 GENERAL DESCRIPTION
The WM8310 has 12 general-purpose input/output (GPIO) pins, GPIO1 - GPIO12. These can be
configured as inputs or outputs, active high or active low, with optional on-chip pull-up or pull-down
resistors. GPIO outputs can either be CMOS driven or Open Drain configuration. Each GPIO pin can
be tri-stated and can also be used to trigger Interrupts.
The function of each GPIO pin is selected individually. Different voltage power domains are selectable
on a pin by pin basis. Input de-bounce is automatically implemented on selected GPIO functions.
21.2 GPIO FUNCTIONS
The list of GPIO functions supported by the WM8310 is contained in Table 72 (for input functions) and
Table 73 (for output functions). The input functions are selected when the respective GPn_DIR
register bit is 1. The output functions are selected when the respective GPn_DIR register bit is 0.
The selected function for each GPIO pin is selected by writing to the respective GPn_FN register bits.
All functions are available on all GPIO pins. The polarity of each input or output GPIO function can be
selected using the applicable GPn_POL register bit.
The available power domains for each pin are specific to different GPIOs.
The de-bounce time for the GPIO input functions is determined by the GPn_FN field. Some of the
input functions allow a choice of de-bounce times, as detailed in Table 72.
The register controls for configuring the GPIO pins are defined in Section 21.3.
GPn_FN
0h
GPIO INPUT
FUNCTION
GPIO
1h
2h
ON/OFF
Request
DESCRIPTION
DE-BOUNCE
TIME
GPIO input. Logic level is read from the
GPn_LVL register bits. See Section 21.3.
32s to 64s
Control input for requesting an ON/OFF state
transition. See Section 11.3.
32ms 64ms
4ms to 8ms
Under default polarity (GPn_POL=1), a rising
edge requests the ON state and a falling edge
requests the OFF state.
3h
4h
SLEEP/WAKE
Request
Control input for requesting a SLEEP/WAKE
state transition. See Section 11.3.
32s to 64s
32ms to 64ms
Under default polarity (GPn_POL=1), a rising
edge requests the SLEEP state and a falling
edge requests the WAKE transition to the ON
state.
5h
SLEEP
Request
Control input for requesting a SLEEP state
transition. See Section 11.3.
32s to 64s
Under default polarity (GPn_POL=1), a rising
edge requests the SLEEP state and a falling
edge has no effect.
6h
ON Request
Control input for requesting an ON state
transition. See Section 11.3.
32s to 64s
Under default polarity (GPn_POL=1), a rising
edge requests the ON state and a falling edge
has no effect.
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7h
Watchdog
Reset
Control input for resetting the Watchdog Timer.
See Section 25.
8h
Hardware DVS
control 1
Control input for selecting the DVS output
voltage in one or more DC-DC Converters.
See Section 15.6.
None
9h
Hardware DVS
control 2
Control input for selecting the DVS output
voltage in one or more DC-DC Converters.
See Section 15.6.
None
32s to 64s
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GPn_FN
GPIO INPUT
FUNCTION
DESCRIPTION
DE-BOUNCE
TIME
Ah
Hardware
Enable 1
Control input for enabling one or more DC-DC
Converters and LDO Regulators.
See Section 15.
32s to 64s
Bh
Hardware
Enable 2
Control input for enabling one or more DC-DC
Converters and LDO Regulators.
See Section 15.
32s to 64s
Ch
Hardware
Control input 1
Control input for selecting the operating mode
and/or output voltage of one or more DC-DC
Converters and LDO Regulators.
See Section 15.
32s to 64s
Dh
Hardware
Control input 2
Control input for selecting the operating mode
and/or output voltage of one or more DC-DC
Converters and LDO Regulators.
See Section 15.
32s to 64s
Eh
Hardware
Control input 1
Control input for selecting the operating mode
and/or output voltage of one or more DC-DC
Converters and LDO Regulators.
See Section 15.
32ms to 64ms
Fh
Hardware
Control input 2
Control input for selecting the operating mode
and/or output voltage of one or more DC-DC
Converters and LDO Regulators.
See Section 15.
32ms to 64ms
Table 72 List of GPIO Input Functions
Further details of the GPIO input de-bounce time are noted in Section 21.3.
GPn_FN
GPIO OUTPUT
FUNCTION
DESCRIPTION
0h
GPIO
GPIO output. Logic level is set by writing to the GPn_LVL
register bits. See Section 21.3.
1h
Oscillator clock
32.768kHz clock output. See Section 13.
2h
ON state
Logic output indicating that the WM8310 is in the ON state. See
Section 11.5.
3h
SLEEP state
Logic output indicating that the WM8310 is in the SLEEP state.
See Section 11.5.
4h
Power State
Change
Logic output asserted whenever a Power On Reset, or an ON,
OFF, SLEEP or WAKE transition has completed.
Under default polarity (GPn_POL=1), the logic level is the same
as the PS_INT interrupt status flag. Note that, if any of the
associated Secondary interrupts is masked, then the respective
event will not affect the Power State Change GPIO output.
See Section 11.2 and Section 11.4.
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8h
DC-DC1 DVS
Done
Logic output indicating that DC-DC1 buck converter DVS slew
has been completed. This signal is temporarily de-asserted
during voltage transitions (including non-DVS transitions). See
Section 15.6.
9h
DC-DC2 DVS
Done
Logic output indicating that DC-DC1 buck converter DVS slew
has been completed. This signal is temporarily de-asserted
during voltage transitions (including non-DVS transitions). See
Section 15.6.
Ah
External Power
Enable 1
Logic output assigned to one of the timeslots in the ON/OFF
and SLEEP/WAKE sequences. This can be used for sequenced
control of external circuits. See Section 15.3.
Bh
External Power
Enable 2
Logic output assigned to one of the timeslots in the ON/OFF
and SLEEP/WAKE sequences. This can be used for sequenced
control of external circuits. See Section 15.3.
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GPn_FN
GPIO OUTPUT
FUNCTION
DESCRIPTION
Ch
System Supply
Good (SYSVDD
Good)
Logic output from SYSVDD monitoring circuit. This function
represents the internal SYSOK signal. See Section 24.4.
Dh
Converter Power
Good
(PWR_GOOD)
Status output indicating that all selected DC-DC Converters and
LDO Regulators are operating correctly. Only asserted in ON
and SLEEP modes. See Section 15.14.
Eh
External Power
Clock
2MHz clock output suitable for clocking external DC-DC
Converters. This clock signal is synchronized with the WM8310
DC-DC Converters clocking signal. See Section 13.
This clock output is only enabled when either of the External
Power Enable signals (EPE1 or EPE2) is asserted. These
signals can be assigned to one of the timeslots in the ON/OFF
and SLEEP/WAKE sequences. See Section 15.3.
Fh
Auxiliary Reset
Logic output indicating a Reset condition. This signal is
asserted in the OFF state. The status in SLEEP mode is
configurable. See Section 11.7.
Note that the default polarity for this function (GPn_POL=1) is
“Active High”. Setting GPn_POL=0 will select “Active Low”
function.
Table 73 List of GPIO Output Functions
21.3 CONFIGURING GPIO PINS
The GPIO pins are configured using the Resister fields defined in Table 74.
The function of each GPIO is selected using the GPn_FN register field. The pin direction field
GPn_DIR selects between input functions and output functions. See Section 21.2 for a summary of
the available GPIO functions.
The polarity of each GPIO can be configured using the GPn_POL bits. This inversion is effective both
on GPIO inputs and outputs. When GPn_POL = 1, the non-inverted ‘Active High’ polarity applies. The
opposite logic can be selected by setting GPn_POL = 0.
The voltage power domain of each GPIO is determined by the GPn_PWR_DOM register. Note that
the available options vary between different GPIO pins, as described in Table 76.
A GPIO output may be either CMOS driven or Open Drain. This is selected using the GPn_OD bits.
Internal pull-up or pull-down resistors can be enabled on each pin using the GPn_PULL field. Both
resistors are available for use when the associated GPIO is an input. When the GPIO pin is
configured as an Open Drain output, the internal pull-up resistor may be required if no external pull-up
resistors are present.
The GPIO pins may be enabled or tri-stated using the GPn_ENA register field. When GPn_ENA = 0,
the respective pin is tri-stated. A tri-stated pin exhibits high impedance to any external circuit and is
disconnected from the internal GPIO circuits. The pull-up and pull-down resistors are disabled when a
GPIO pin is tri-stated.
GPIO pins can generate an interrupt (see Section 21.4). The GPn_INT_MODE field selects whether
the interrupt occurs on a single edge only, or else on both rising and falling edges. When single edge
is selected, the active edge is the rising edge (when GPn_POL = 1) or the falling edge (when
GPn_POL = 0.
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ADDRESS
R16440
(4038h)
BIT
15
LABEL
GPn_DIR
DEFAULT
1
DESCRIPTION
GPIOn pin direction
0 = Output
1 = Input
to
14:13
GPn_PULL
[1:0]
01
R16451
(4043h)
GPIOn Pull-Up / Pull-Down
configuration
00 = No pull resistor
01 = Pull-down enabled
10 = Pull-up enabled
11 = Reserved
12
GPn_INT_M
ODE
0
GPIOn Interrupt Mode
0 = GPIO interrupt is rising edge
triggered (if GPn_POL=1) or falling
edge triggered (if GPn_POL =0)
1 = GPIO interrupt is triggered on
rising and falling edges
11
GPn_PWR_D
OM
0
10
GPn_POL
1
GPIOn Power Domain
See Table 76.
GPIOn Polarity select
0 = Inverted (active low)
1 = Non-Inverted (active high)
9
GPn_OD
0
GPIOn Output pin configuration
0 = CMOS
1 = Open Drain
7
GPn_ENA
0
GPIOn Enable control
0 = GPIO pin is tri-stated
1 = Normal operation
3:0
GPn_FN [3:0]
0000
GPIOn Pin Function
See Table 77.
Note: n is a number between 1 and 12 that identifies the individual GPIO.
Note: The default values noted are valid when the WM8310 powers up to the OFF state, or if the
Register Map is reset following a Device Reset or Software Reset event. In the case of GPIO pins
1 to 6, these registers are overwritten with the respective ICE or OTP memory contents when an
ON transition is scheduled.
Table 74 GPIO Pin Configuration
When the GPIO output function is selected (GPn_FN = 0h, GPn_DIR = 0), the state of a GPIO output
is controlled by writing to the corresponding GPn_LVL register bit, as defined in Table 75.
The logic level of a GPIO input is determined by reading the corresponding GPn_LVL register bit. If
GPn_POL is set, then the read value of the GPn_LVL field for a GPIO input is the inverse of the
external signal. Note that, when the GPIO input level changes, the logic level of GPn_LVL will only be
updated after the maximum de-bounce period, as listed in Table 72. An input pulse that is shorter
than the minimum de-bounce period will be filtered by the de-bounce function and will be ignored.
If a GPIO is configured as a CMOS output (ie. GPn_OD = 0), then the read value of the GPn_LVL
field will indicate the logic level of that output. If GPn_POL is set, then the read value of the GPn_LVL
field for a GPIO output is the inverse of the level on the external pad.
If a GPIO is configured as an Open Drain output, then the read value of GPn_LVL is only valid when
the internal pull-up resistor is enabled on the pin (ie. when GPn_PULL = 10). The read value is also
affected by the GPn_POL bit, as described above for the CMOS case.
If a GPIO is tri-stated (GPn_ENA = 0), then the read value of the corresponding GPn_LVL field is
invalid.
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ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R16396
(400Ch)
11
GP12_LVL
0
GPIOn level.
10
GP11_LVL
0
GPIO Level
9
GP10_LVL
0
8
GP9_LVL
0
When GPn_FN = 0h and GPn_DIR
= 0, write to this bit to set a GPIO
output.
7
GP8_LVL
0
6
GP7_LVL
0
5
GP6_LVL
0
4
GP5_LVL
0
3
GP4_LVL
0
2
GP3_LVL
0
1
GP2_LVL
0
0
GP1_LVL
0
Read from this bit to read GPIO
input level.
When GPn_POL is 0, the register
contains the opposite logic level to
the external pin. Write to this bit to
set a GPIO output.
Table 75 GPIO Level Register
The power domain for each GPIO is controlled using the GPn_PWR_DOM registers as described in
Table 76.
ADDRESS
R16440
(4038h)
BIT
LABEL
DEFAULT
11
GP1_PWR_DO
M
0
GP2_PWR_DO
M
0
0 = DBVDD
GPIO1 Control
R16441
(4039h)
1 = VPMIC (LDO12)
11
1 = VPMIC (LDO12)
11
GP3_PWR_DO
M
0
1 = VPMIC (LDO12)
11
GP4_PWR_DO
M
0
GP5_PWR_DO
M
0
GP6_PWR_DO
M
0
GP7_PWR_DO
M
0
GP8_PWR_DO
M
0
GP9_PWR_DO
M
0
1 = SYSVDD
11
1 = SYSVDD
11
1 = SYSVDD
11
1 = VPMIC (LDO12)
11
1 = VPMIC (LDO12)
11
1 = VPMIC (LDO12)
11
GP10_PWR_D
OM
0
GPIO11
Control
w
GPIO10 Power Domain select
0 = DBVDD
GPIO10
Control
R16450
(4042h)
GPIO9 Power Domain select
0 = DBVDD
GPIO9 Control
R16449
(4041h)
GPIO8 Power Domain select
0 = DBVDD
GPIO8 Control
R16448
(4040h)
GPIO7 Power Domain select
0 = DBVDD
GPIO7 Control
R16447
(403Fh)
GPIO6 Power Domain select
0 = DBVDD
GPIO6 Control
R16446
(403Eh)
GPIO5 Power Domain select
0 = DBVDD
GPIO5 Control
R16445
(403Dh)
GPIO4 Power Domain select
0 = DBVDD
GPIO4 Control
R16444
(403Ch)
GPIO3 Power Domain select
0 = DBVDD
GPIO3 Control
R16443
(403Bh)
GPIO2 Power Domain select
0 = DBVDD
GPIO2 Control
R16442
(403Ah)
DESCRIPTION
GPIO1 Power Domain select
1 = SYSVDD
11
GP11_PWR_D
OM
0
GPIO11 Power Domain select
0 = DBVDD
1 = SYSVDD
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ADDRESS
R16451
(4043h)
BIT
LABEL
DEFAULT
11
GP12_PWR_D
OM
0
DESCRIPTION
GPIO12 Power Domain select
0 = DBVDD
GPIO12
Control
1 = SYSVDD
Table 76 GPIO Power Domain Registers
The function of each GPIO is controlled using the GPn_FN registers defined in Table 77. Note that
the selected function also depends on the associated GPn_DIR field described in Table 74.
See also Section 21.2 for additional details of each GPIO function, including the applicable de-bounce
times for GPIO input functions.
ADDRESS
R16440
(4038h)
BIT
3:0
LABEL
GP1_FN [3:0]
DEFAULT
0000
0h = GPIO input (long de-bounce)
GPIO1 Control
R16441
(4039h)
1h = GPIO input
3:0
GP2_FN [3:0]
0000
3:0
GP3_FN [3:0]
0000
6h = Power On request
3:0
GP4_FN [3:0]
0000
3:0
GP5_FN [3:0]
0000
3:0
GP6_FN [3:0]
0000
GPIO6 Control
R16446
(403Eh)
3:0
GP7_FN [3:0]
0000
3:0
GP8_FN [3:0]
0000
GPIO7 Control
R16447
(403Fh)
3:0
GP9_FN [3:0]
0000
3:0
GP10_FN [3:0]
0000
Eh = HW Control1 input (long debounce)
Fh = HW Control2 input (long debounce)
Output functions:
1h = 32.768kHz oscillator output
2h = ON state
4h = Power State Change
5h = Reserved
7h = Reserved
3:0
GP11_FN [3:0]
0000
8h = DC-DC1 DVS Done
9h = DC-DC2 DVS Done
GPIO11
Control
R16451
(4043h)
Dh = HW Control2 input
6h = Reserved
GPIO10
Control
R16450
(4042h)
Ch = HW Control1 input
3h = SLEEP state
GPIO9 Control
R16449
(4041h)
Ah = HW Enable1 input
0h = GPIO output
GPIO8 Control
R16448
(4040h)
9h = DVS2 input
Bh = HW Enable2 input
GPIO5 Control
R16445
(403Dh)
7h = Watchdog Reset input
8h = DVS1 input
GPIO4 Control
R16444
(403Ch)
4h = Sleep/Wake request (long debounce)
5h = Sleep request
GPIO3 Control
R16443
(403Bh)
2h = Power On/Off request
3h = Sleep/Wake request
GPIO2 Control
R16442
(403Ah)
DESCRIPTION
Input functions:
Ah = External Power Enable1
Bh = External Power Enable2
3:0
GP12_FN [3:0]
GPIO12
Control
0000
Ch = System Supply Good (SYSOK)
Dh = Converter Power Good
(PWR_GOOD)
Eh = External Power Clock (2MHz)
Fh = Auxiliary Reset
Table 77 GPIO Function Select Registers
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Note that GPIO input functions 2h, 3h, 4h, 5h and 6h are edge-triggered only. The associated state
transition(s) are scheduled only when a rising or falling edge is detected on the respective GPIO pin.
At other times, it is possible that other state transition events may cause a state transition regardless
of the state of the GPIO input. See Section 11.3 for details of all the state transition events.
Note that SLEEP transitions are not possible when any of the Battery Charger Interrupts is set. If any
of the Battery Charger Interrupts is asserted when a SLEEP transition is requested, then the transition
will be unsuccessful and the WM8310 will remain in the ON power state. See Section 17.7.8 for
details of the Battery Charger Interrupts.
21.4 GPIO INTERRUPTS
Each GPIO pin has an associated interrupt flag, GPn_EINT, in Register R16405 (4015h). Each of
these secondary interrupts triggers a primary GPIO Interrupt, GP_INT (see Section 23). This can be
masked by setting the mask bit(s) as described in Table 78.
See Section 28 and Section 29 for a definition of the register bit positions applicable to each GPIO.
ADDRESS
R16405
(4015h)
BIT
11:0
LABEL
GPn_EINT
(Trigger is controlled by GPn_INT_MODE)
Interrupt Status
5
R16413
(401Dh)
DESCRIPTION
GPIO interrupt.
Note: Cleared when a ‘1’ is written.
11:0
Interrupt Status
5 Mask
IM_GPn_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Note: n is a number between 1 and 12 that identifies the individual GPIO.
Table 78 GPIO Interrupts
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22 SYSTEM STATUS LED DRIVERS
22.1 GENERAL DESCRIPTION
The WM8310 provides two System Status LED Drivers. These are digital outputs intended for driving
LEDs directly. The LED outputs can be assigned to indicate OTP Program status, Power State status
or Battery Charger status. They can also be commanded directly via register control, in order to
provide any other required functionality.
22.2 LED DRIVER CONTROL
LED Drivers are configurable in the ON and SLEEP power states only. The functionality of the LED
Drivers is controlled by the LEDn_SRC register bits, as described in Table 79.
ADDRESS
R16460
(404Ch)
BIT
15:14
LABEL
LED1_SRC
[1:0]
DEFAULT
11
DESCRIPTION
LED1 Source
(Selects the LED1 function.)
Status LED1
00 = Off
01 = Power State Status
10 = Charger Status
11 = Manual Mode
Note: LED1 also indicates
completion of OTP Auto Program
R16461
(404Dh)
15:14
LED2_SRC
[1:0]
11
LED2 Source
(Selects the LED2 function.)
Status LED2
00 = Off
01 = Power State Status
10 = Charger Status
11 = Manual Mode
Note: LED2 also indicates an OTP
Auto Program Error condition
Table 79 System Status LED Control
22.2.1
OTP PROGRAM STATUS
The LED drivers indicate the status of the OTP Auto Program function, where the contents of the
external InstantConfig™ (ICE) memory are automatically programmed into the OTP. See
Section 14.6.3 for further details of the OTP Auto Program function.
When the OTP Auto Program function is executed, the System Status LED drivers follow the
functionality defined in Table 80.
LED DRIVER
DESCRIPTION
DRIVE MODE
LED ‘ON’
TIME
ON:OFF
DUTY CYCLE
LED1
OTP Auto Program
Complete
Constant
n/a
n/a
LED2
OTP Auto Progam Error
Constant
n/a
n/a
Table 80 System Status LED Outputs - OTP Program Status
The OTP Program Status LED outputs will continue until a Device Reset.
Note that the OTP Program Status is always indicated via the LED outputs, regardless of the
LEDn_SRC register fields.
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22.2.2
POWER STATE STATUS
Setting LEDn_SRC = 01 configures the associated LED to indicate Power State status. Under this
selection, four different conditions may be indicated, as defined in Table 81.
LED DRIVER
LED1 or
LED2
DESCRIPTION
DRIVE MODE
LED ‘ON’
TIME
ON:OFF
DUTY CYCLE
Power Sequence Failure
Pulsed sequence
(4 pulses)
1s
1:1
SYSVDD Low
Continuous
pulsed
250ms
1:3
ON state
Constant
n/a
n/a
SLEEP state
Continuous
pulsed
250ms
1:7
Table 81 System Status LED Outputs - Power State Status
If more than one of the conditions listed occurs simultaneously, then the LED output pattern is
controlled by the condition in the highest position within the list above.
For example, if the SYSVDD Low condition occurs while in the ON or SLEEP states, then the LED
output follows the pattern defined for the SYSVDD Low condition.
The SYSVDD Low indication is asserted if SYSVDD is less than the user-selectable threshold
SYSLO_THR, as described in Section 24.4.
Note that, in the case of Power Sequence Failure, the transition to OFF occurs after the 4 LED pulses
have been emitted.
22.2.3
CHARGER STATUS
Setting LEDn_SRC = 10 configures the associated LED to indicate Battery Charger status. Under this
selection, two different conditions may be indicated, as defined in Table 82.
LED DRIVER
LED1 or
LED2
DESCRIPTION
DRIVE MODE
LED ‘ON’
TIME
ON:OFF
DUTY CYCLE
Charger Complete
Constant
n/a
n/a
Charger On
Continuous
pulsed
1s
1:2
Table 82 System Status LED Outputs - Charger Status
22.2.4
LED DRIVER MANUAL MODE
Setting LEDn_SRC = 11 configures the associated LED to operate in Manual Mode, which is further
configurable using additional register fields.
In Manual Mode, the LED output can be commanded as Off, On (Constant), Continuous Pulsed or
Pulsed Sequence. The selected operation is determined by the LEDn_MODE registers as described
in Table 83.
In Continuous Pulsed mode and Pulsed Sequence mode, the ‘On’ time and the Duty Cycle can be
configured using the LEDn_DUR and LEDn_DUTY_CYC registers respectively.
In Pulsed Sequence mode, the number of pulses in the sequence can be selected using the
LEDn_SEQ_LEN register. On completion of the commanded number of pulses, the LED remains off
until LEDn_MODE or LEDn_SRC is changed to another value.
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ADDRESS
R16460
(404Ch)
BIT
9:8
LABEL
DEFAULT
LED1_MODE
[1:0]
00
LED1_SEQ_LE
N [1:0]
10
LED1_DUR
[1:0]
01
LED1_DUTY_C
YC [1:0]
10
LED2_MODE
[1:0]
00
(Controls LED1 in Manual Mode
only.)
00 = Off
01 = Constant
10 = Continuous Pulsed
11 = Pulsed Sequence
Status LED1
5:4
3:2
1:0
R16461
(404Dh)
9:8
DESCRIPTION
LED1 Mode
LED1 Pulse Sequence Length
(when LED1_MODE = Pulsed
Sequence)
00 = 1 pulse
01 = 2 pulses
10 = 4 pulses
11 = 7 pulses
LED1 On time
(when LED1_MODE = Continuous
Pulsed or Pulsed Sequence)
00 = 1 second
01 = 250ms
10 = 125ms
11 = 62.5ms
LED1 Duty Cycle (On:Off ratio)
(when LED1_MODE = Continuous
Pulsed or Pulsed Sequence)
00 = 1:1 (50% on)
01 = 1:2:(33.3% on)
10 = 1:3 (25% on)
11 = 1:7 (12.5% on)
LED2 Mode
(Controls LED2 in Manual Mode
only.)
Status LED2
00 = Off
01 = Constant
10 = Continuous Pulsed
11 = Pulsed Sequence
5:4
LED2_SEQ_LE
N [1:0]
10
LED2 Pulse Sequence Length
(when LED2_MODE = Pulsed
Sequence)
00 = 1 pulse
01 = 2 pulses
10 = 4 pulses
11 = 7 pulses
3:2
LED2_DUR
[1:0]
01
LED2 On time
(when LED2_MODE = Continuous
Pulsed or Pulsed Sequence)
00 = 1 second
01 = 250ms
10 = 125ms
11 = 62.5ms
1:0
LED2_DUTY_C
YC [1:0]
10
LED2 Duty Cycle (On:Off ratio)
(when LED2_MODE = Continuous
Pulsed or Pulsed Sequence)
00 = 1:1 (50% on)
01 = 1:2:(33.3% on)
10 = 1:3 (25% on)
11 = 1:7 (12.5% on)
Table 83 System Status LED Outputs - Manual Mode Control
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22.3 LED DRIVER CONNECTIONS
The recommended connection for System Status LEDs is illustrated in Figure 28. The LED outputs
are referenced to the SYSVDD power domain. A series resistor may be required, depending on the
LED characteristics and the SYSVDD voltage.
SYSVDD
WM8310
LED1
GND
Figure 28 System Status LED Connections
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23 INTERRUPT CONTROLLER
The WM8310 has a comprehensive Interrupt logic capability. The dedicated IRQ
¯¯¯ pin can be used to
alert a host processor to selected events or fault conditions. Each of the interrupt conditions can be
individually enabled or masked. Following an interrupt event, the host processor should read the
interrupt registers in order to determine what caused the interrupt, and take appropriate action if
required.
The WM8310 interrupt controller has two levels:
Secondary interrupts indicate a single event in one of the circuit blocks. The event is indicated by
setting a register bit. This bit is a latching bit - once it is set, it remains at logic 1 even if the trigger
condition is cleared. The secondary interrupts are cleared by writing a logic 1 to the relevant register
bit. Note that reading the register does not clear the secondary interrupt.
Primary interrupts are the logical OR of the associated secondary interrupts (usually all the interrupts
associated with one particular circuit block). Each of the secondary interrupts can be individually
masked or enabled as an input to the corresponding primary interrupt. The primary interrupt register
R16400 (4010h) is read-only.
The status of the IRQ
¯¯¯ pin reflects the logical NOR of the primary interrupts. A logic 0 indicates that
one or more of the primary interrupts is asserted. Each of the primary interrupts can be individually
masked or enabled as an input to the IRQ
¯¯¯ pin output.
The IRQ
¯¯¯ pin output can either be CMOS driven or Open Drain (integrated pull-up) configuration, as
determined by the IRQ_OD register bit. When the IRQ
¯¯¯ pin is Open Drain, it is actively driven low when
asserted; the pull-up causes a logic high output when not asserted. The Open Drain configuration
enables multiple devices to share a common Interrupt line with the host processor.
The IRQ
¯¯¯ pin output can be masked by setting the IM_IRQ register bit. When the IRQ
¯¯¯ pin is masked, it
is held in the logic 1 (or Open Drain) state regardless of any internal interrupt event.
Note that the secondary interrupt bits are always valid - they are set as normal, regardless of whether
the bit is enabled or masked as an input to the corresponding primary interrupt. The primary interrupt
bits are set and cleared as normal in response to any unmasked secondary interrupt, regardless of
whether the primary interrupt bit is enabled or masked as an input to the IRQ
¯¯¯ pin output.
Note also that if any internal condition is configured to trigger an event other than an Interrupt (eg. the
Watchdog timer triggers Reset), these events are always actioned, regardless of the state of any
interrupt mask bits.
The IRQ
¯¯¯ pin output is configured using the register bits described in Table 84.
ADDRESS
R16407
(4017h)
BIT
1
LABEL
IRQ_OD
DESCRIPTION
IRQ pin configuration
0 = CMOS
IRQ Config
1 = Open Drain (integrated pull-up)
0
IM_IRQ
IRQ pin output mask
0 = Normal
1 = IRQ output is masked
Table 84 IRQ Pin Configuration
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The interrupt logic is illustrated in Figure 29.
event / fault
condition sets
secondary interrupt
e.g. RTC Alarm
“mask” register bit
(read/write)
“mask” register bit
(read/write)
e.g. IM_RTC_ALM_EINT
e.g. IM_RTC_INT
IRQ mask bit
IM_IRQ
AND
AND
OR
event-level register
bit (read only)
OR
NOR
IRQ pin
e.g. RTC_ALM_EINT
Primary interrupt
register bit
(read only)
e.g. RTC_INT
Writing ‘1’ to this bit
clears the
secondary interrupt
other secondary
interrupts
other primary interrupts
e.g. CHG_INT,
AUXADC_INT
e.g. RTC_PER_EINT
Figure 29 Interrupt Logic
Following the assertion of the IRQ
¯¯¯ pin to indicate an Interrupt event, the host processor can determine
which primary interrupt caused the event by reading the primary interrupt register R16400 (4010h).
This register is defined in Section 23.1.
After reading the primary interrupt register, the host processor must read the corresponding
secondary interrupt register(s) in order to determine which specific event caused the IRQ
¯¯¯ pin to be
asserted. The host processor clears the secondary interrupt bit by writing a logic 1 to that bit.
23.1 PRIMARY INTERRUPTS
The primary interrupts are defined in Table 85. These bits are Read Only. They are set when any of
the associated unmasked secondary interrupts is set. They can only be reset when all of the
associated secondary resets are cleared or masked.
Each primary interrupt can be masked. When a mask bit is set, the corresponding primary interrupt is
masked and does not cause the IRQ
¯¯¯ pin to be asserted. The primary interrupt bits in R16408 (4018h)
are valid regardless of whether the mask bit is set. The primary interrupts are all masked by default.
ADDRESS
R16400
(4010h)
System
Interrupts
BIT
15
LABEL
PS_INT
DESCRIPTION
Power State primary interrupt
0 = No interrupt
1 = Interrupt is asserted
14
TEMP_INT
Thermal primary interrupt
0 = No interrupt
1 = Interrupt is asserted
13
GP_INT
GPIO primary interrupt
0 = No interrupt
1 = Interrupt is asserted
12
ON_PIN_INT
ON Pin primary interrupt
0 = No interrupt
1 = Interrupt is asserted
11
WDOG_INT
Watchdog primary interrupt
0 = No interrupt
1 = Interrupt is asserted
8
AUXADC_INT
AUXADC primary interrupt
0 = No interrupt
1 = Interrupt is asserted
7
PPM_INT
Power Path Management primary interrupt
0 = No interrupt
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ADDRESS
BIT
LABEL
DESCRIPTION
1 = Interrupt is asserted
6
CS_INT
Current Sink primary interrupt
0 = No interrupt
1 = Interrupt is asserted
5
RTC_INT
Real Time Clock primary interrupt
0 = No interrupt
1 = Interrupt is asserted
4
OTP_INT
OTP Memory primary interrupt
0 = No interrupt
1 = Interrupt is asserted
2
CHG_INT
Battery Charger primary interrupt
0 = No interrupt
1 = Interrupt is asserted
1
HC_INT
High Current primary interrupt
0 = No interrupt
1 = Interrupt is asserted
0
UV_INT
Undervoltage primary interrupt
0 = No interrupt
1 = Interrupt is asserted
R16408
(4018h)
System
Interrupts
Mask
15
IM_PS_INT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
14
IM_TEMP_INT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
13
IM_GP_INT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
12
IM_ON_PIN_INT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
11
IM_WDOG_INT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
8
IM_AUXADC_INT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
7
IM_PPM_INT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
6
IM_CS_INT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
5
IM_RTC_INT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
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ADDRESS
BIT
LABEL
DESCRIPTION
Default value is 1 (masked)
4
IM_OTP_INT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
2
IM_CHG_INT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
1
IM_HC_INT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
0
IM_UV_INT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Table 85 Primary Interrupt Status and Mask Bits
23.2 SECONDARY INTERRUPTS
The following sections define the secondary interrupt status and control bits associated with each of
the primary interrupt bits defined in Table 85.
23.2.1
POWER STATE INTERRUPT
The primary PS_INT interrupt comprises three secondary interrupts as described in Section 11.4. The
secondary interrupt bits are defined in Table 86.
Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt
event is masked and does not trigger a PS_INT interrupt. The secondary interrupt bits in R16402
(4012h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked
by default.
ADDRESS
R16402
(4012h)
Interrupt Status
2
BIT
2
LABEL
PS_POR_EINT
DESCRIPTION
Power On Reset interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
1
PS_SLEEP_OFF_EINT
SLEEP or OFF interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
0
PS_ON_WAKE_EINT
ON or WAKE interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
R16410
(401Ah)
2
IM_PS_POR_EINT
Interrupt mask.
0 = Do not mask interrupt.
Interrupt Status
2 Mask
1 = Mask interrupt.
Default value is 1 (masked)
1
IM_PS_SLEEP_OFF_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
0
IM_PS_ON_WAKE_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Table 86 Power State Interrupts
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23.2.2
THERMAL INTERRUPTS
The primary TEMP_INT interrupt comprises a single secondary interrupt as described in Section 26.
The secondary interrupt bit is defined in Table 87.
The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event
is masked and does not trigger a TEMP_INT interrupt. The secondary interrupt bit in R16401 (4011h)
is valid regardless of whether the mask bit is set. The secondary interrupt is masked by default.
ADDRESS
R16401
(4011h)
BIT
1
LABEL
TEMP_THW_CINT
DESCRIPTION
Thermal Warning interrupt
(Rising and Falling Edge triggered)
Interrupt Status
1
R16410
(4019h)
Note: Cleared when a ‘1’ is written.
1
IM_TEMP_THW_CINT
Interrupt mask.
0 = Do not mask interrupt.
Interrupt Status
1 Mask
1 = Mask interrupt.
Default value is 1 (masked)
Table 87 Thermal Interrupts
23.2.3
GPIO INTERRUPTS
The primary GP_INT interrupt comprises twelve secondary interrupts as described in Section 21.4.
The secondary interrupt bits are defined in Table 88.
Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt
event is masked and does not trigger a GP_INT interrupt. The secondary interrupt bits in R16405
(4015h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked
by default.
ADDRESS
R16405
(4015h)
BIT
11:0
LABEL
GPn_EINT
DESCRIPTION
GPIO interrupt.
(Trigger is controlled by GPn_INT_MODE)
Interrupt Status
5
R16413
(401Dh)
Note: Cleared when a ‘1’ is written.
11:0
IM_GPn_EINT
Interrupt mask.
0 = Do not mask interrupt.
Interrupt Status
5 Mask
1 = Mask interrupt.
Default value is 1 (masked)
Note: n is a number between 1 and 12 that identifies the individual GPIO.
Table 88 GPIO Interrupts
23.2.4
ON PIN INTERRUPTS
The primary ON_PIN_INT interrupt comprises a single secondary interrupt as described in
Section 11.6. The secondary interrupt bit is defined in Table 89.
The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event
is masked and does not trigger an ON_PIN_INT interrupt. The secondary interrupt bit in R16401
(4011h) is valid regardless of whether the mask bit is set. The secondary interrupt is masked by
default.
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ADDRESS
R16401
(4011h)
BIT
12
LABEL
ON_PIN_CINT
DESCRIPTION
ON pin interrupt.
(Rising and Falling Edge triggered)
Interrupt Status
1
R16409
(4019h)
Note: Cleared when a ‘1’ is written.
12
IM_ON_PIN_CINT
Interrupt mask.
0 = Do not mask interrupt.
Interrupt Status
1 Mask
1 = Mask interrupt.
Default value is 1 (masked)
Table 89 ON Pin Interrupt
23.2.5
WATCHDOG INTERRUPTS
The primary WDOG_INT interrupt comprises a single secondary interrupt as described in Section 25.
The secondary interrupt bits are defined in Table 90.
The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event
is masked and does not trigger a WDOG_INT interrupt. The secondary interrupt bit in R16401
(4011h) is valid regardless of whether the mask bit is set. The secondary interrupt is masked by
default.
ADDRESS
R16401
(4011h)
BIT
LABEL
11
WDOG_TO_EINT
DESCRIPTION
Watchdog timeout interrupt.
(Rising Edge triggered)
Interrupt Status
1
R16409
(4019h)
Note: Cleared when a ‘1’ is written.
11
IM_WDOG_TO_EINT
Interrupt mask.
0 = Do not mask interrupt.
Interrupt Status
1 Mask
1 = Mask interrupt.
Default value is 1 (masked)
Table 90 Watchdog Timer Interrupts
23.2.6
RESERVED
23.2.7
RESERVED
23.2.8
AUXADC INTERRUPTS
The primary AUXADC_INT interrupt comprises five secondary interrupts as described in Section 18.5.
The secondary interrupt bits are defined in Table 91.
Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt
event is masked and does not trigger a AUXADC_INT interrupt. The secondary interrupt bits in
R16401 (4011h) are valid regardless of whether the mask bit is set. The secondary interrupts are all
masked by default.
ADDRESS
R16401
(4011h)
Interrupt Status
1
BIT
8
LABEL
AUXADC_DATA_EINT
DESCRIPTION
AUXADC Data Ready interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
7:4
AUXADC_DCOMPn_EINT
AUXADC Digital Comparator n interrupt
(Trigger is controlled by DCMPn_GT)
Note: Cleared when a ‘1’ is written.
R16409
(4019h)
Interrupt Status
1 Mask
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8
IM_AUXADC_DATA_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
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ADDRESS
BIT
LABEL
7:4
IM_AUXADC_DCOMPn_EI
NT
DESCRIPTION
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Note: n is a number between 1 and 4 that identifies the individual Comparator.
Table 91 AUXADC Interrupts
23.2.9
POWER PATH MANAGEMENT INTERRUPTS
The primary PPM_INT interrupt comprises three secondary interrupts as described in Section 17.5.
The secondary interrupt bits are defined in Table 92.
Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt
event is masked and does not trigger a PPM_INT interrupt. The secondary interrupt bits in R16401
(4011h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked
by default.
ADDRESS
R16401
(4011h)
Interrupt Status
1
BIT
15
LABEL
PPM_SYSLO_EINT
DESCRIPTION
Power Path SYSLO interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
14
PPM_PWR_SRC_EINT
Power Path Source interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
13
PPM_USB_CURR_EINT
Power Path USB Current interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
R16409
(4019h)
15
IM_PPM_SYSLO_EINT
Interrupt mask.
0 = Do not mask interrupt.
Interrupt Status
1 Mask
1 = Mask interrupt.
Default value is 1 (masked)
14
IM_PPM_PWR_SRC_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
13
IM_PPM_USB_CURR_EIN
T
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Table 92 Power Path Management Interrupts
23.2.10 CURRENT SINK INTERRUPTS
The primary CS_INT interrupt comprises two secondary interrupts as described in Section 16.3. The
secondary interrupt bits are defined in Table 93.
Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt
event is masked and does not trigger a CS_INT interrupt. The secondary interrupt bits in R16402
(4012h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked
by default.
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ADDRESS
R16402
(4012h)
Interrupt Status
2
BIT
7
LABEL
CS2_EINT
DESCRIPTION
Current Sink 2 interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
6
CS1_EINT
Current Sink 1 interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
R16410
(401Ah)
7
IM_CS2_EINT
Interrupt mask.
0 = Do not mask interrupt.
Interrupt Status
2 Mask
1 = Mask interrupt.
Default value is 1 (masked)
6
IM_CS1_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Table 93 Current Sink Interrupts
23.2.11 REAL TIME CLOCK INTERRUPTS
The primary RTC_INT interrupt comprises two secondary interrupts as described in Section 20.3. The
secondary interrupt bits are defined in Table 94.
Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt
event is masked and does not trigger a RTC_INT interrupt. The secondary interrupt bits in R16401
(4011h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked
by default.
ADDRESS
R16401
(4011h)
Interrupt Status
1
BIT
3
LABEL
RTC_PER_EINT
DESCRIPTION
RTC Periodic interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
2
RTC_ALM_EINT
RTC Alarm interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
R16409
(4019h)
3
IM_RTC_PER_EINT
Interrupt mask.
0 = Do not mask interrupt.
Interrupt Status
1 Mask
1 = Mask interrupt.
Default value is 1 (masked)
2
IM_RTC_ALM_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Table 94 Real Time Clock (RTC) Interrupts
23.2.12 OTP MEMORY INTERRUPTS
The primary OTP_INT interrupt comprises two secondary interrupts as described in Section 14.5. The
secondary interrupt bits are defined in Table 95.
Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt
event is masked and does not trigger a OTP_INT interrupt. The secondary interrupt bits in R16402
(4012h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked
by default.
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ADDRESS
R16402
(4012h)
Interrupt Status
2
BIT
5
LABEL
OTP_CMD_END_EINT
DESCRIPTION
OTP / ICE Command End interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
4
OTP_ERR_EINT
OTP / ICE Command Fail interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
R16410
(401Ah)
5
IM_OTP_CMD_END_EINT
Interrupt mask.
0 = Do not mask interrupt.
Interrupt Status
2 Mask
1 = Mask interrupt.
Default value is 1 (masked)
4
IM_OTP_ERR_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Table 95 OTP Memory Interrupts
23.2.13 RESERVED
23.2.14 BATTERY CHARGER INTERRUPTS
The primary CHG_INT interrupt comprises six secondary interrupts as described in Section 17.7.8.
The secondary interrupt bits are defined in Table 96.
Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt
event is masked and does not trigger a CHG_INT interrupt. The secondary interrupt bits in R16402
(4012h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked
by default.
ADDRESS
R16402
(4012h)
Interrupt Status
2
BIT
15
LABEL
CHG_BATT_HOT_EINT
DESCRIPTION
Battery Hot interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
14
CHG_BATT_COLD_EINT
Battery Cold interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
13
CHG_BATT_FAIL_EINT
Battery Fail interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
12
CHG_OV_EINT
Battery Overvoltage interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
11
CHG_END_EINT
Battery Charge End interrupt (End of
Charge Current threshold reached)
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
10
CHG_TO_EINT
Battery Charge Timeout interrupt
(Charger Timer has expired)
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
9
CHG_MODE_EINT
Battery Charge Mode interrupt (Charger
Mode has changed)
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
8
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CHG_START_EINT
Battery Charge Start interrupt (Charging
has started)
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ADDRESS
BIT
LABEL
DESCRIPTION
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
R16410
(401Ah)
15
IM_CHG_BATT_HOT_EINT
Interrupt mask.
0 = Do not mask interrupt.
Interrupt Status
2 Mask
1 = Mask interrupt.
Default value is 1 (masked)
14
IM_CHG_BATT_COLD_EIN
T
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
13
IM_CHG_BATT_FAIL_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
12
IM_CHG_OV_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
11
IM_CHG_END_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
10
IM_CHG_TO_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
9
IM_CHG_MODE_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
8
IM_CHG_START_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Table 96 Battery Charger Interrupts
23.2.15 HIGH CURRENT INTERRUPTS
The primary HC_INT interrupt comprises two secondary interrupts as described in Section 15.13. The
secondary interrupt bits are defined in Table 97.
Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt
event is masked and does not trigger a HC_INT interrupt. The secondary interrupt bits in R16404
(4014h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked
by default.
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ADDRESS
R16404
(4014h)
Interrupt Status
4
BIT
9
LABEL
HC_DC2_EINT
DESCRIPTION
DC-DC2 High Current interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
8
HC_DC1_EINT
DC-DC1 High Current interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
R16412
(401Ch)
9
IM_HC_DC2_EINT
Interrupt mask.
0 = Do not mask interrupt.
Interrupt Status
4 Mask
1 = Mask interrupt.
Default value is 1 (masked)
8
IM_HC_DC1_EINT
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Table 97 Overcurrent Interrupts
23.2.16 UNDERVOLTAGE INTERRUPTS
The primary UV_INT interrupt comprises fourteen secondary interrupts as described in
Section 15.13). The secondary interrupt bits are defined in Table 98.
Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt
event is masked and does not trigger a UV_INT interrupt. The secondary interrupt bits in R16403
(4013h) and R16404 (4014h) are valid regardless of whether the mask bit is set. The secondary
interrupts are all masked by default.
ADDRESS
R16403
(4013h)
BIT
9:0
LABEL
UV_LDOn_EINT
(Rising Edge triggered)
Interrupt Status
3
R16404
(4014h)
Note: Cleared when a ‘1’ is written.
3:0
UV_DCm_EINT
Note: Cleared when a ‘1’ is written.
9:0
IM_UV_LDOn_EINT
Interrupt mask.
0 = Do not mask interrupt.
Interrupt Status
3 Mask
R16412
(401Ch)
DC-DCm Undervoltage interrupt
(Rising Edge triggered)
Interrupt Status
4
R16411
(401Bh)
DESCRIPTION
LDOn Undervoltage interrupt
1 = Mask interrupt.
Default value is 1 (masked)
3:0
IM_UV_DCm_EINT
Interrupt Status
4 Mask
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Notes:
1.
n is a number between 1 and 10 that identifies the individual LDO Regulator (LDO1-LDO10).
2.
m is a number between 1 and 4 that identifies the individual DC-DC Converter (DC1-DC4).
Table 98 Undervoltage Interrupts
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24 RESETS AND SUPPLY VOLTAGE MONITORING
24.1 RESETS
The WM8310 provides hardware and software monitoring functions as inputs to a Reset management
system. These functions enable the device to take appropriate action when power supplies are
critically low or if a hardware or software fault condition is detected.
There are different levels of Resets, providing different response mechanisms according to the
condition that caused the Reset event. Where applicable, the WM8310 will automatically return to the
ON state and resume normal operation as quickly as possible following a Reset.
A System Reset occurs in the event of a Power Sequence Failure, Device overtemperature, SYSVDD
undervoltage, Software ‘OFF’ request or VPMIC (LDO12) undervoltage condition. Under these
conditions, the WM8310 asserts the RESET
¯¯¯¯¯¯ pin and transitions to the OFF state. In the case of
VPMIC undervoltage, the WM8310 enters the BACKUP state. The contents of the Register map are
not reset under System Reset conditions.
A Device Reset occurs in the event of a Watchdog Timeout, Hardware Reset request or Converter
(LDO or DC-DC) Undervoltage condition. Under these conditions, the WM8310 asserts the RESET
¯¯¯¯¯¯
pin and transitions to the OFF state. The contents of the Register map are cleared to default values,
except for the RTC and software scratch registers, which are maintained. The WM8310 will
automatically return to the ON state after performing the Device Reset.
A Software Reset occurs when any value is written to Register 0000h, as described in Section 12.5.
In this event, the WM8310 asserts the RESET
¯¯¯¯¯¯ pin and transitions to the OFF state. The Register map
contents may or may not be affected, depending on the value of the SW_RESET_CFG field. See
Section 24.3 for further details of Software Reset configuration. The WM8310 will automatically return
to the ON state after performing the Software Reset.
A Power-On Reset occurs when the supply voltage is less than the Power-On Reset threshold, as
described in Section 24.4. In this event, the WM8310 is forced into the NO POWER state, as
described in Section 11.2. All the contents of the Register map are lost in the NO POWER state.
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A summary of the WM8310 Resets is contained in Table 99.
RESET TYPE
System Reset
RESET CONDITION
DESCRIPTION
Power Sequence Failure
DC Converters, LDOs or CLKOUT
circuits (including FLL) have failed
to start up within the permitted time.
See Section 11.3.
Device overtemperature
An overtemperature condition has
been detected. See Section 26.
SYSVDD undervoltage
(1)
SYSVDD is less than the userselectable threshold SYSLO_THR
and SYSLO_ERR_ACT is
configured to select OFF in this
condition. See Section 24.4.
SYSVDD undervoltage
(2)
SYSVDD is less than the
SHUTDOWN voltage.
RESPONSE
AUTOMATIC
RECOVERY
Assert RESET
¯¯¯¯¯¯ pin.
No
Select OFF state.
If the Reset Condition is
VPMIC (LDO12)
undervoltage, then the
WM8310 enters the
BACKUP state.
No
No
No
See Section 24.4.
Software OFF request
OFF has been commanded by
writing CHIP_ON = 0.
No
See Section 11.3
Device Reset
VPMIC (LDO12)
undervoltage
The WM8310 supply voltage is less
than the System Reset threshold.
See Section 24.4.
Watchdog timeout
Watchdog timer has expired and the
selected response is to generate a
Device Reset.
Assert RESET
¯¯¯¯¯¯ pin.
See Section 25.
Reset Register map
The RESET
¯¯¯¯¯¯ pin has been pulled low
by an external source.
(Note the RTC and
software scratch
registers are not reset.)
Hardware Reset
See Section 24.2.
Software Reset
Converter (LDO or DCDC) Undervoltage
An undervoltage condition has been
detected and the selected response
is “Shut down system (Device
Reset)” See Section 15.
Software Reset
Software Reset has been
commanded by writing to Register
0000h. See Section 12.5.
No
Yes
Shutdown and restart
the WM8310.
Yes
Yes
Assert RESET
¯¯¯¯¯¯ pin.
Yes
Shutdown and restart
the WM8310.
See Section 24.3 for
configurable options
regarding the Register
Map contents.
Power On Reset
Power On Reset
The WM8310 supply voltage is less
than the Power-On Reset (POR)
threshold. See Section 24.4.
The WM8310 is in the
NO POWER state.
No
All register contents are
lost.
Table 99 Resets Summary
In the cases where Automatic Recovery is supported (as noted in Table 99), the WM8310 will re-start
the WM8310 following the Reset, and return the device to the ON state. The particular Reset
condition which caused the return to the ON state will be indicated in the “ON Source” register - see
Section 11.3.
Note that, if a Watchdog timeout or Converter undervoltage fault persists, a maximum of 6 Device
Resets will be attempted to initiate the start-up sequence. Similarly, a maximum of 6 Software Resets
is permitted. If these limits are exceeded, the WM8310 will remain in the OFF state until the next valid
ON state transition event occurs.
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The WM8310 asserts the RESET
¯¯¯¯¯¯ low as soon as the device begins the shutdown sequence. RESET
¯¯¯¯¯¯
is held low for the duration of the shutdown sequence and is held low in the OFF state. In the cases
where Automatic Recovery is supported, RESET
¯¯¯¯¯¯ is automatically cleared (high) after successful
completion of the startup sequence. The duration of the RESET
¯¯¯¯¯¯ low period after the startup sequence
has completed is governed by the RST_DUR register field described in Section 11.7.
24.2 HARDWARE RESET
A Hardware Reset is triggered when an external source pulls the RESET
¯¯¯¯¯¯ pin low. Under this
condition, the WM8310 transitions to the OFF state. The contents of the Register map are cleared to
default values, except for the RTC and software scratch registers, which are maintained. The
WM8310 will then automatically schedule an ON state transition to resume normal operation.
If the external source continues to pull the RESET
¯¯¯¯¯¯ pin low, then the WM8310 cannot fully complete
the ON state transition following the Hardware Reset. In this case, the WM8310 will mask the external
reset for up to 32 seconds. If the RESET
¯¯¯¯¯¯ pin is released (ie. it returns to logic ‘1’) during this time,
then the ON state transition is completed and the Hardware Reset input is valid again from this point.
If the RESET
¯¯¯¯¯¯ pin is not released, then the WM8310 will force an OFF condition on expiry of the 32
seconds timeout. Recovery from this forced OFF condition cannot occur until the external reset
condition is de-asserted, followed by a valid ON event. If an ON event occurs before the external
reset is de-asserted, then start-up will be attempted, but the transition will be unsuccessful, causing a
return to the OFF state.
It is possible to mask the RESET
¯¯¯¯¯¯ pin input in the SLEEP state by setting the RST_SLP_MSK register
bit as described in Section 11.7.
24.3 SOFTWARE RESET
A Software Reset is triggered by writing to Register 0000h, as described in Section 12.5. In this event,
the WM8310 asserts the RESET
¯¯¯¯¯¯ pin and transitions to the OFF state. If the Reset occurred in the ON
state, then the WM8310 will automatically return to the ON state following the Reset.
The SWRST_DLY register field determines whether a time delay is applied between the Software
Reset command and the resultant shutdown and start-up sequences. When the SWRST_DLY bit is
set, the programmable time delay PWRSTATE_DLY is applied before commencing the shutdown
sequence.
The timing of the Software Reset is illustrated in Figure 30. See Section 11.3 for a definition of the
PWRSTATE_DLY register.
The SW_RESET_CFG register field determines if the Register Map is reset under a Software Reset
condition.
Note that the SW_RESET_CFG control register is locked by the WM8310 User Key. This register can
only be changed by writing the appropriate code to the Security register, as described in Section 12.4.
ADDRESS
R16387
(4003h)
BIT
9
LABEL
SWRST_DLY
DEFAULT
0
0 = No delay
Power State
R16390
(4006h)
DESCRIPTION
Software Reset Delay
1 = Software Reset is delayed by
PWRSTATE_DLY following the Software
Reset command
10
SW_RESET_C
FG
Reset
Control
1
Software Reset Configuration.
Selects whether the register map is reset to
default values when Software Reset occurs.
0 = All registers except RTC and Software
Scratch registers are reset by Software
Reset
1 = Register Map is not affected by Software
Reset
Protected by user key
Table 100 Software Reset Configuration
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Power State
ON
Software Reset
(shutdown / start-up)
RESET is de-asserted
ON transition completes
ON transition starts
SW Reset command
The timing details of the Software Reset are illustrated in Figure 30.
ON
RESET pin
Time
Time delay set by
SWRST_DLY and
PWRSTATE_DELAY
0ms, 1ms or 10ms
OFF transition then ON transition
Nominal duration = 10 x 2ms
RESET delay set by RST_DUR
3ms, 11ms, 51ms or 101ms
Figure 30 Software Reset Timing
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24.4 SUPPLY VOLTAGE MONITORING
The WM8310 includes a number of mechanisms to prevent the system from starting up, or to force it
to shut down, when the power sources are critically low.
The power supply configuration for the WM8310 is described in Section 17. The chip automatically
chooses the most suitable supply, selecting between a Wall adapter supply, USB or Battery. The
preferred source is routed to the SYSVDD pin, to which the other power management circuits would
typically be connected. The SYSVDD voltage is monitored internally, as described below.
The internal regulator LDO12 is powered from an internal domain equivalent to SYSVDD and
generates an internal supply (VPMIC) to support various “always-on” functions. In the absence of the
Wall, USB or Battery supplies, LDO12 can be powered from a backup supply. (Note that SYSVDD is
not maintained by the backup supply.) The VPMIC monitoring function controls the Power-On Reset
circuit, which sets the threshold below which the WM8310 cannot operate.
The operation of the VPMIC monitoring circuit is illustrated in Figure 31. The internal signal PORRST
¯¯¯¯¯¯¯
is governed by the VPOR thresholds. These determine when the WM8310 is kept in the NO POWER
state. The internal signal PMICRST
¯¯¯¯¯¯¯¯ is governed by the VRES thresholds. These determine when the
WM8310 is kept in the BACKUP state.
NO POWER
BACKUP
BACKUP
NO POWER
The VPMIC monitoring thresholds illustrated in Figure 31 are fixed. The voltage levels are defined in
the Electrical Characteristics - see Section 7.5.
Figure 31 VPMIC Monitoring
The operation of the SYSVDD monitoring circuit is illustrated in Figure 32. The VSHUTDOWN threshold is
the voltage below which the WM8310 forces an OFF transition. This threshold voltage is fixed and is
defined in the Electrical Characteristics - see Section 7.5.
The VSYSOK threshold is the level at which the internal signal SYSOK is asserted. Any ON request will
be inhibited if SYSOK is not set. The VSYSOK threshold can be set using the SYSOK_THR register field
in accordance with the minimum voltage requirements of the application. Note that a hysteresis
margin is added to the SYSOK_THR setting; see Section 7.5 for details.
The VSYSLO threshold is the level at which the internal signal SYSLO is asserted. This indicates a
SYSVDD undervoltage condition, at which a selectable response can be initiated. The VSYSLO
threshold can be set using the SYSLO_THR register field. The action taken under this undervoltage
condition is selected using the SYSLO_ERR_ACT register field, as defined in Table 101. An Interrupt
event is associated with the SYSLO condition - see Section 17.5.
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The SYSLO status can be read from the SYSLO_STS register bit. This bit is asserted when SYSVDD
is below the SYSLO threshold.
The WM8310 can also indicate the status of the SYSOK signal via a GPIO pin configured as a
“SYSVDD Good” output (see Section 21). A GPIO pin configured as “SYSVDD Good” output will be
asserted when the SYSVDD is above the SYSOK threshold.
VSYSVDD
VSYSOK
VSYSLO
VSHUTDOWN
time
SYSOK (SYSLO)
time
SHUTDOWN
time
Figure 32 SYSVDD Monitoring
ADDRESS
R16385
(4001h)
BIT
LABEL
DEFAULT
15:14
SYSLO_ERR_
ACT
00
DESCRIPTION
SYSLO Error Action
Selects the action taken when SYSLO is
asserted
SYSVDD
Control
00 = Interrupt
01 = WAKE transition
10 = Reserved
11 = OFF transition
11
SYSLO_STS
0
SYSLO Status
0 = Normal
1 = SYSVDD is below SYSLO threshold
6:4
SYSLO_THR
[2:0]
010
SYSLO threshold (falling SYSVDD)
This is the falling SYSVDD voltage at
which SYSLO will be asserted
000 = 2.8V
001 = 2.9V
…
111 = 3.5V
2:0
SYSOK_THR
[2:0]
101
SYSOK threshold (rising SYSVDD)
This is the rising SYSVDD voltage at
which SYSOK will be asserted
000 = 2.8V
001 = 2.9V
…
111 = 3.5V
Note that the SYSOK hysteresis margin is
added to these threshold levels.
Table 101 SYSVDD Monitoring Control
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25 WATCHDOG TIMER
The WM8310 includes a Watchdog Timer designed to detect a possible software fault condition
where the host processor has locked up. The Watchdog Timer is a free-running counter driven by the
internal RC oscillator.
The Watchdog Timer is enabled by default; it can be enabled or disabled by writing to the
WDOG_ENA register bit. The Watchdog behaviour in SLEEP is configurable; it can either be set to
continue as normal or to be disabled. The Watchdog behaviour in SLEEP is determined by the
WDOG_SLPENA bit.
The watchdog timer duration is set using WDOG_TO. The watchdog timer can be halted for debug
purposes using the WDOG_DEBUG bit.
The Watchdog reset source is selectable between Software and Hardware triggers. (Note that the deselected reset source has no effect.) If the Watchdog is not reset within a programmable timeout
period, this is interpreted by the WM8310 as a fault condition. The Watchdog Timer then either
triggers a Device Reset, or issues a WAKE request or raises an Interrupt. The action taken is
determined by the WDOG_PRIMACT register field.
If the Watchdog is not reset within a further timeout period of the Watchdog counter, a secondary
action is triggered. The secondary action taken at this point is determined by the WDOG_SECACT
register field.
The Watchdog reset source is selected using the WDOG_RST_SRC register bit. When Software
WDOG reset source is selected, the Watchdog is reset by writing a ‘1’ to the WDOG_RESET field.
When Hardware WDOG reset source is selected, the Watchdog is reset by toggling a GPIO pin that
has been configured as a Watchdog Reset Input (see Section 21).
If a Device Reset is triggered by the watchdog timeout, the WM8310 asserts the RESET
¯¯¯¯¯¯ pin, resets
the internal control registers (excluding the RTC) and initiates a start-up sequence. The Watchdog
Timer is not automatically reset as part of the Device Reset; the Watchdog must be reset by the host
application following the Device Reset.
Note that, following a Device Reset, the action taken on subsequent timeout of the Watchdog Timer
will be determined by the WDOG_PRIMACT register. If the watchdog timeout fault persists, then a
maximum of 6 Device Reset attempts will be made. See Section 24. If the watchdog timeout occurs
more than 6 times, the WM8310 will remain in the OFF state until the next valid ON state transition
event occurs.
Note that the Watchdog control registers are locked by the WM8310 User Key. These registers can
only be changed by writing the appropriate code to the Security register, as described in Section 12.4.
ADDRESS
R16388
(4004h)
BIT
15
LABEL
WDOG_ENA
DEFAULT
1
DESCRIPTION
Watchdog Timer Enable
0 = Disabled
Watchdog
1 = Enabled (enables the watchdog; does
not reset it)
Protected by user key
14
WDOG_DEBU
G
0
Watchdog Pause
0 = Disabled
1 = Enabled (halts the Watchdog timer for
system debugging)
Protected by user key
13
WDOG_RST_S
RC
1
Watchdog Reset Source
0 = Hardware only
1 = Software only
Protected by user key
12
WDOG_SLPE
NA
0
Watchdog SLEEP Enable
0 = Disabled
1 = Controlled by WDOG_ENA
Protected by user key
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ADDRESS
BIT
LABEL
DEFAULT
11
WDOG_RESE
T
0
DESCRIPTION
Watchdog Software Reset
0 = Normal
1 = Watchdog Reset (resets the watchdog, if
WDOG_RST_SRC = 1)
Protected by user key
WDOG_SECA
CT
9:8
10
Secondary action of Watchdog timeout
(taken after 2 timeout periods)
00 = No action
01 = Interrupt
10 = Device Reset
11 = WAKE transition
Protected by user key
WDOG_PRIMA
CT
5:4
01
Primary action of Watchdog timeout
00 = No action
01 = Interrupt
10 = Device Reset
11 = WAKE transition
Protected by user key
WDOG_TO
[2:0]
2:0
111
Watchdog timeout period
000 = 0.256s
001 = 0.512s
010 = 1.024s
011 = 2.048s
100 = 4.096s
101 = 8.192s
110 = 16.384s
111 = 32.768s
Protected by user key
Table 102 Controlling the Watchdog Timer
The Watchdog timeout interrupt event is indicated by the WDOG_TO_EINT register field. This
secondary interrupt triggers a primary Watchdog Interrupt, WDOG_INT (see Section 23). This can be
masked by setting the mask bit as described in Table 103.
ADDRESS
R16401
(4011h)
BIT
LABEL
11
WDOG_TO_EINT
(Rising Edge triggered)
Interrupt Status
1
R16409
(4019h)
DESCRIPTION
Watchdog timeout interrupt.
Note: Cleared when a ‘1’ is written.
11
IM_WDOG_TO_EINT
Interrupt Status
1 Mask
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Table 103 Watchdog Timer Interrupts
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26 TEMPERATURE SENSING
The WM8310 provides temperature monitoring as status information and also for self-protection of the
device. Temperature monitoring is always enabled in the ON and SLEEP states.
The thermal warning temperature can be set using the THW_TEMP register field. The thermal
warning hysteresis ensures that the THW_TEMP is not reset until the device temperature has
dropped below the threshold by a suitable margin. The extent of the hysteresis can be selected using
the THW_HYST register field.
The Thermal Warning condition can be read using the THW_STS register bit. An overtemperature
condition causes the thermal warning interrupt (TEMP_THW_CINT) to be set. The thermal warning
interrupt is also set when the overtemperature condition clears, ie. when the device has returned to its
normal operating limits.
The thermal shutdown temperature is set at a fixed level. If a thermal shutdown condition is detected
whilst in the ON or SLEEP states, then a System Reset is triggered, as described in Section 24.1,
forcing a transition to the OFF state.
The temperature sensing circuit is configured and monitored using the register fields described in
Table 104.
ADDRESS
R16386
(4002h)
BIT
LABEL
DEFAULT
THW_HYST
3
1
DESCRIPTION
Thermal Warning hysteresis
0 = 8 degrees C
1 = 16 degrees C
THW_TEMP
[1:0]
1:0
10
Thermal Warning temperature
00 = 90 degrees C
01 = 100 degrees C
10 = 110 degrees C
11 = 120 degrees C
R16397
(400Dh)
THW_STS
15
0
Thermal Warning status
0 = Normal
1 = Overtemperature Warning
(warning temperature is set by
THW_TEMP)
Table 104 Temperature Sensing Control
The thermal warning interrupt event is indicated by the TEMP_THW_CINT register field. This
secondary interrupt triggers a primary Thermal Interrupt, TEMP_INT (see Section 23). This can be
masked by setting the mask bit as described in Table 105.
ADDRESS
R16401
(4011h)
BIT
1
LABEL
TEMP_THW_CINT
(Rising and Falling Edge triggered)
Interrupt Status
1
R16410
(4019h)
DESCRIPTION
Thermal Warning interrupt
Note: Cleared when a ‘1’ is written.
1
IM_TEMP_THW_CINT
Interrupt Status
1 Mask
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Table 105 Thermal Interrupts
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27 VOLTAGE AND CURRENT REFERENCES
27.1 VOLTAGE REFERENCE (VREF)
The main voltage reference generated by the WM8310 is bonded to the VREFC pin. The accuracy of
this reference is optimised by factory-set trim registers.
The voltage reference (VREF) requires an external decoupling capacitor; a 100nF X5R capacitor is
recommended for typical applications, as noted in Section 30.2. If USB100MA_STARTUP=1X (see
Section 17.4), then a 50nF capacitor should be used. Omitting this capacitor will result in increased
noise on the voltage reference; this will particularly affect the analogue LDOs.
The VREFC capacitor should be grounded to the REFGND pin.
The voltage reference circuit includes a low-power mode, which enables power consumption to be
minimised where appropriate. The low-power reference mode may lead to increased noise on the
voltage reference; this mode should only be selected when minimum power consumption is more
important than voltage stability. Note that the Low Power Reference mode is not supported when the
Auxiliary ADC function is enabled.
The Low Power Reference mode is enabled when REF_LP register is set. The Low Power Reference
mode should only be enabled when the Auxiliary ADC is disabled. Enabling the Low Power Reference
mode will lead to a malfunction of the Auxiliary ADC function.
ADDRESS
R16387
(4003h)
BIT
12
LABEL
REF_LP
DEFAULT
0
DESCRIPTION
Low Power Voltage Reference Control
0 = Normal
1 = Low Power Reference Mode select
Note that Low Power Reference Mode is
only supported when the Auxiliary ADC is
disabled.
Table 106 Low Power Voltage Reference Control
27.2 CURRENT REFERENCE (IREF)
The Power Management circuits of the WM8310 use an integrated current reference.
This current reference (IREF) requires the connection of an external resistor to the IREFR pin; a
100k (1%) resistor is recommended, as noted in Section 30.2. The WM8310 will malfunction if this
resistor is omitted.
The IREFR resistor should be grounded to the REFGND pin.
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Reserved
0005
0006
5
6
Softw are Scratch
OTP Control
4009
400A
400B
400C
400D
16394
16395
16396
16397
4014
4015
4016
16404
16405
16406
4017
4013
16407
4012
16403
Interrupt Status 1
4011
16401
16402
System Interrupts
4010
16400
ON Source
IRQ Config
Reserved
Interrupt Status 5
Interrupt Status 4
Interrupt Status 3
Interrupt Status 2
OFF Source
400E
400F
16398
16399
System Status
GPIO Level
Security Key 2
Security Key
Control Interface
Reset Control
ON Pin Control
16393
4006
16390
4007
4005
16389
Watchdog
Pow er State
4008
4004
16388
16391
4003
16387
Thermal Monitoring
SYSVDD Control
Parent ID
Reserved
Reserved
Reserved
Reserved
Revision
16392
4001
4002
16385
16386
0007
0004
4
4000
0003
3
7
0002
2
16384
Reserved
0001
1
Nam e
0000
0
Reset ID
Hex Addr
Dec Addr
0
0
0
0
0
0
14
0
11
REF_LP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OTP_READ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GP12_EINT
0
0
0
0
GP11_EINT
0
0
0
GP7_LVL
0
0
GP6_LVL
0
OTP_BULK
0
GP5_LVL
0
0
0
GP4_LVL
0
0
0
0
ON_PIN_STS
0
0
0
0
0
0
0
0
0
USB_ILIM[2:0]
THW_TEMP[1:0]
0
PPM_INT
AUXADC_IN
T
CS_INT
OFF_SW_RE
Q
RTC_INT
0
OTP_INT
OFF_ON_PIN
0
0
CHG_INT
0
HC_INT
0
RESET_HW
Bin Default
0000_0000_0000_0100
1000_0100_0111_0011
0000_0001_0000_0000
1010_P010_0001_0111
UU00_1000_0000_0010
0000_0000_0000_1010
0000_0000_0010_0101
0110_0010_0000_0100
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0
0
GP10_EINT
0
0
GP9_EINT
0
0
GP8_EINT
0
0
GP7_EINT
0
0
0
GP6_EINT
0
0
0
GP5_EINT
0
0
0
GP4_EINT
0
0
GP3_EINT
IRQ_OD
0
GP2_EINT
IM_IRQ
0
GP1_EINT
UV_DC4_EIN UV_DC3_EIN UV_DC2_EIN UV_DC1_EIN
T
T
T
T
0000_0000_0000_0010
0000_0000_0000_0000
PPPP_PPPP_PPPP_PPPP
0000_00PP_PP00_PPPP
0
HC_DC2_EIN HC_DC1_EIN
T
T
0
PPPP_PPPP_PPPP_0PPP
CS1_EINT
PPPP_PPPP_PPPP_PPP0
PPPP_PPPP_PPPP_PPPP
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_00PP_PPPP_PPPP
CS2_EINT
U010_0000_0000_0000
0000_0000_0000_0000
UV_LDO10_ UV_LDO9_EI UV_LDO8_EI UV_LDO7_EI UV_LDO6_EI UV_LDO5_EI UV_LDO4_EI UV_LDO3_EI UV_LDO2_EI UV_LDO1_EI
EINT
NT
NT
NT
NT
NT
NT
NT
NT
NT
0
UV_INT
0
RESET_WD
OG
GP1_LVL
0
PS_POR_EIN PS_SLEEP_ PS_ON_WA
T
OFF_EINT
KE_EINT
OTP_CMD_E OTP_ERR_EI
ND_EINT
NT
AUXADC_D AUXADC_D AUXADC_D AUXADC_D AUXADC_D RTC_PER_EI RTC_ALM_EI TEMP_THW_
ATA_EINT COMP4_EINT COMP3_EINT COMP2_EINT COMP1_EINT
NT
NT
CINT
0
GP2_LVL
0
OTP_PAGE[1:0]
0
RST_DUR[1:0]
ON_PIN_TO[1:0]
WDOG_TO[2:0]
MAIN_STATE[4:0]
GP3_LVL
0
0
AUTOINC
0
0
0
0
0
0
0
SYSOK_THR[2:0]
ON_WDOG_ ON_SW_RE ON_RTC_AL
RESET_CNV
ON_ON_PIN
RESET_SW
TO
Q
M
_UV
0
GP8_LVL
0
OTP_READ_LVL[1:0]
0
ON_CHG
CHG_BATT_ CHG_BATT_ CHG_BATT_ CHG_OV_EI CHG_END_EI CHG_TO_EI CHG_MODE CHG_START
HOT_EINT COLD_EINT FAIL_EINT
NT
NT
NT
_EINT
_EINT
0
0
OFF_SYSV
OFF_THERR
DD
0
GP9_LVL
ON_SYSLO
ON_PIN_PRIMACT[1:0]
WDOG_PRIMACT[1:0]
0
0
0
0
0
0
0
1
0000_0000_0000_0000
0
THW_HYST
0
0
0
0
0
0
0
2
SW_SCRATCH[15:0]
PWR_USB
0
0
0
0
0
0
0
0
AUXRST_SL RST_SLP_M RST_SLPEN
PENA
SK
A
0
3
CHILD_REV[7:0]
4
USB_CURR_
USB100MA_STARTUP[1:0]
STS
0
SYSLO_THR[2:0]
0
0
0
0
0
0
5
0000_0000_0000_0000
0
0
0
0
0
0
0
0
0
0
0
6
SECURITY[15:0]
0
0
0
0
ON_PIN_SECACT[1:0]
0
0
0
0
0
WDOG_SECACT[1:0]
SWRST_DL
Y
0
0
GP10_LVL
GP11_LVL
0
0
0
0
0
0
PARENT_ID[15:0]
0
0
0
0
0
0
PWR_SRC_
PWR_WALL
BATT
0
7
CHIP_ID[15:0]
8
0
0
0
0
0
0
0
0
9
OTP_VERIF
OTP_WRITE
Y
0
0
ON_PIN_INT
OFF_GPIO
ON_GPIO
0
GP12_LVL
0
OTP_FINAL
0
0
SW_RESET_
CFG
PPM_SYSLO PPM_PWR_S PPM_USB_C ON_PIN_CIN WDOG_TO_
_EINT
RC_EINT
URR_EINT
T
EINT
GP_INT
OFF_INTLDO OFF_PWR_S
_ERR
EQ
0
0
0
0
OTP_MEM
0
0
0
0
0
TEMP_INT
0
0
0
0
0
0
0
WALL_FET_ BATT_FET_
ENA_DRV_S
ENA
TR
0
0
0
0
0
0
0
0
10
PWRSTATE_DLY[1:0]
0
SYSLO_STS
0
0
0
0
0
0
PARENT_REV[7:0]
12
WDOG_INT
PS_INT
0
ON_TRANS
THW_STS
0
0
OTP_PROG
0
0
0
0
0
0
0
0
0
0
0
0
0
13
WDOG_DEB WDOG_RST WDOG_SLP WDOG_RES
UG
_SRC
ENA
ET
CHIP_SLP
0
RECONFIG_
AT_ON
WDOG_ENA
CHIP_ON
0
SYSLO_ERR_ACT[1:0]
0
0
0
0
0
0
15
WM8310
Pre-Production
28 REGISTER MAP OVERVIEW
PP, May 2012, Rev 3.1
162
w
401F
4020
4021
4022
16415
16416
16417
16418
4036
16438
4037
4035
16437
16439
4034
16436
4031
16433
4033
4030
16432
4032
402F
16431
16435
402E
16430
16434
402C
402D
16428
402B
16427
16429
4029
402A
16425
16426
4027
4028
16423
16424
4026
401E
16414
16422
401D
16413
4025
401C
16412
16421
401B
16411
4023
401A
16410
4024
4019
16409
16419
4018
16408
16420
Hex Addr
Dec Addr
Nam e
Reserved
Reserved
Reserved
Comparator 4
Comparator 3
Comparator 2
Comparator 1
Comparator Control
AuxADC Source
AuxADC Control
AuxADC Data
Touch Data Z
Touch Data Y
Touch Data X
Touch Control 2
Touch Control 1
Reserved
RTC Trim
RTC Control
RTC Alarm 2
RTC Alarm 1
RTC Time 2
RTC Time 1
RTC Write Counter
Reserved
Reserved
Interrupt Status 5 Mask
Interrupt Status 4 Mask
Interrupt Status 3 Mask
Interrupt Status 2 Mask
Interrupt Status 1 Mask
System Interrupts Mask
15
14
13
12
11
IM_TEMP_IN
IM_ON_PIN_ IM_WDOG_I
IM_GP_INT
T
INT
NT
1
10
1
9
0
0
0
0
DCMP4_GT
DCMP4_SRC[2:0]
0
DCMP3_GT
0
0
0
DCMP2_GT
DCMP1_GT
0
0
DCMP3_SRC[2:0]
0
0
0
0
AUX_SLPE
NA
0
0
0
0
0
0
0
0
0
0
1
0
DCMP2_SRC[2:0]
DCMP1_SRC[2:0]
0
0
AUX_CVT_
ENA
0
0
0
0
0
0
0
0
0
0
0
0
1
0
AUX_DATA_SRC[3:0]
0
0
0
0
0
0
0
RTC_SYNC
_BUSY
0
0
1
0
0
0
0
AUX_ENA
0
0
0
0
0
0
0
RTC_VALID
0
0
1
0
8
7
6
5
4
0
0
0
0
0
0
0
0
0
RTC_ALM_
ENA
0
0000_0011_1111_1111
1111_1111_1111_0111
1111_1111_1111_1110
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AUX_DATA[11:0]
0
0
0
0
1
0
0
0
0
0
0
RTC_TRIM[9:0]
RTC_PINT_FREQ[2:0]
0
0
0
1
0
0
0
AUX_RATE[5:0]
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DCMP4_THR[11:0]
DCMP3_THR[11:0]
DCMP2_THR[11:0]
DCMP1_THR[11:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DCMP4_EN DCMP3_EN DCMP2_EN DCMP1_EN
A
A
A
A
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0U00_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0111
0U00_0000_0100_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0
0
RTC_ALM[15:0]
0
0
RTC_ALM[31:16]
0
0
0000_0000_0000_0000
0
0
0000_0000_0000_0000
0
0
RTC_TIME[15:0]
0
0
RTC_TIME[31:16]
0
0
0000_0000_0000_0000
0
0
RTC_WR_CNT[15:0]
0
0
AUX_WALL AUX_BATT AUX_USB_ AUX_SYSV AUX_BATT AUX_CHIP_ AUX_AUX4 AUX_AUX3 AUX_AUX2 AUX_AUX1
_SEL
_SEL
SEL
DD_SEL
_TEMP_SEL TEMP_SEL
_SEL
_SEL
_SEL
_SEL
0
0
0
0
0
0
0
0
0
0
DCOMP4_S DCOMP3_S DCOMP2_S DCOMP1_S
TS
TS
TS
TS
0
0
0
0
0
0
0
0
0
0
0
0
0
Bin Default
1111_1111_1111_1111
1111_1111_1111_1111
0
0
0
0
IM_UV_INT
0000_0011_1000_1111
0
0
1
IM_GP12_EI IM_GP11_EI IM_GP10_EI IM_GP9_EIN IM_GP8_EIN IM_GP7_EIN IM_GP6_EIN IM_GP5_EIN IM_GP4_EIN IM_GP3_EI IM_GP2_EIN IM_GP1_EIN
NT
NT
NT
T
T
T
T
T
T
NT
T
T
1
2
IM_CHG_IN
IM_HC_INT
T
IM_AUXAD IM_RTC_PE IM_RTC_AL IM_TEMP_T
0
C_DCOMP1
R_EINT
M_EINT
HW_CINT
EINT
IM_OTP_ER
IM_PS_POR IM_PS_SLE IM_PS_ON_
0
EP_OFF_EIN WAKE_EINT
R_EINT
_EINT
T
IM_UV_LDO IM_UV_LDO IM_UV_LD IM_UV_LDO IM_UV_LDO
5_EINT
4_EINT
O3_EINT
2_EINT
1_EINT
1
3
IM_UV_DC4 IM_UV_DC IM_UV_DC2 IM_UV_DC1
_EINT
3_EINT
_EINT
_EINT
IM_AUXAD IM_AUXAD IM_AUXAD IM_AUXAD
C_DATA_EI C_DCOMP4 C_DCOMP3 C_DCOMP2
NT
EINT
EINT
EINT
IM_CHG_ST IM_CS2_EIN IM_CS1_EIN IM_OTP_CM
D_END_EIN
ART_EINT
T
T
T
IM_UV_LDO IM_UV_LDO IM_UV_LDO IM_UV_LDO
9_EINT
8_EINT
7_EINT
6_EINT
IM_AUXAD
IM_PPM_INT IM_CS_INT IM_RTC_INT IM_OTP_INT
C_INT
IM_HC_DC2 IM_HC_DC1
_EINT
_EINT
IM_PPM_SY IM_PPM_PW IM_PPM_US IM_ON_PIN_ IM_WDOG_
1
1
CINT
TO_EINT
SLO_EINT R_SRC_EIN B_CURR_EI
T
NT
IM_CHG_BA IM_CHG_BA IM_CHG_BA IM_CHG_O IM_CHG_EN IM_CHG_TO IM_CHG_M
TT_HOT_EIN TT_COLD_E TT_FAIL_EI
V_EINT
D_EINT
_EINT
ODE_EINT
T
INT
NT
IM_UV_LDO
0
0
0
0
0
0
10_EINT
IM_PS_INT
Pre-Production
WM8310
PP, May 2012, Rev 3.1
163
w
4047
16455
4054
4055
4056
16468
16469
16470
4057
4053
16471
4052
4051
16465
16467
4050
16464
16466
404E
404F
16462
16463
404D
4046
16454
404C
4045
16453
16461
4044
16452
16460
4043
16451
404B
4042
16450
404A
4041
16449
16458
4040
16448
16459
403F
16447
4048
403E
4049
403D
16445
16446
16456
403C
16444
16457
403A
403B
4039
16441
16442
4038
16440
16443
Hex Addr
Dec Addr
Nam e
DC1 Control 2
DC1 Control 1
LDO UV Status
DCDC UV Status
LDO Status
DCDC Status
LDO Enable
DCDC Enable
Current Sink 2
Current Sink 1
Status LED 2
Status LED 1
Reserved
Charger Status
Charger Control 2
Charger Control 1
GPIO16 Control
GPIO15 Control
GPIO14 Control
GPIO13 Control
GPIO12 Control
GPIO11 Control
GPIO10 Control
GPIO9 Control
GPIO8 Control
GPIO7 Control
GPIO6 Control
GPIO5 Control
GPIO4 Control
GPIO3 Control
GPIO2 Control
GPIO1 Control
15
11
10
0
CS2_OFF_RAMP[1:0]
0
0
INTLDO_UV
_STS
DC1_RATE[1:0]
0
0
0
DC1_ERR_ACT[1:0]
0
0
0
0
0
DC1_HWC_SRC[1:0]
0
0
0
0
0
0
0
DC1_PHAS
E
DC2_OV_S DC1_OV_S
TS
TS
0
0
0
0
0
0
0
0
0
0
0
0
0
CS1_OFF_RAMP[1:0]
CS2_SLPEN
A
CS1_STS
CS2_DRIVE
CS1_DRIVE
CS2_STS
CS1_ENA
0
0
0
0
0
0
0
0
0
0
LDO10_EN
LDO9_ENA
A
0
CS2_ON_RAMP[1:0]
CS1_ON_RAMP[1:0]
LED2_MODE[1:0]
LED1_MODE[1:0]
0
7
DC1_HWC_
VSEL
0
0
0
EPE1_ENA
0
0
0
0
0
EPE2_STS
0
EPE1_STS
0
LDO7_STS
0
0
0
LDO6_STS
0
LDO5_STS
0
LDO5_ENA
0
LED2_SEQ_LEN[1:0]
0
DC1_HWC_MODE[1:0]
0
DC1_FLT
0
0
0
0
0
0
3
DC1_HC_THR[2:0]
DC1_SOFT_START[1:0]
0
0
DC2_ENA
DC1_ENA
LED2_DUTY_CYC[1:0]
LED1_DUTY_CYC[1:0]
0
DC3_STS
DC2_STS
DC1_STS
0
0
0
0
0
DC1_HC_IN
D_ENA
DC1_CAP[1:0]
LDO4_UV_ LDO3_UV_ LDO2_UV_ LDO1_UV_
STS
STS
STS
STS
DC4_UV_ST DC3_UV_S DC2_UV_S DC1_UV_S
S
TS
TS
TS
LDO4_STS LDO3_STS LDO2_STS LDO1_STS
DC4_STS
LDO4_ENA LDO3_ENA LDO2_ENA LDO1_ENA
DC3_ENA
CS2_ISEL[5:0]
CS1_ISEL[5:0]
0
0
0
0
0
CHG_IMON_ CHG_CHIP_
ENA
TEMP_MON
0
0
0
0
CHG_FAST_ILIM[3:0]
0
0
0
0
0
GP12_FN[3:0]
GP11_FN[3:0]
GP10_FN[3:0]
GP9_FN[3:0]
GP8_FN[3:0]
GP7_FN[3:0]
GP6_FN[3:0]
GP5_FN[3:0]
GP4_FN[3:0]
GP3_FN[3:0]
GP2_FN[3:0]
LED2_DUR[1:0]
DC4_ENA
1
GP1_FN[3:0]
2
LED1_DUR[1:0]
0
CHG_TIME_ELAPSED[7:0]
LED1_SEQ_LEN[1:0]
0
LDO8_ENA LDO7_ENA LDO6_ENA
EPE2_ENA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
CHG_VSEL[1:0]
CHG_FAST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
LDO9_UV_ LDO8_UV_ LDO7_UV_ LDO6_UV_ LDO5_UV_
STS
STS
STS
STS
STS
DC1_FREQ[1:0]
LDO10_UV
_STS
DC2_HC_ST DC1_HC_ST
S
S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
CHG_TRKL_ILIM[1:0]
0
0
0
0
0
GP12_ENA
GP11_ENA
GP10_ENA
GP9_ENA
GP8_ENA
GP7_ENA
GP6_ENA
GP5_ENA
GP4_ENA
GP3_ENA
GP2_ENA
GP1_ENA
LDO11_STS LDO10_STS LDO9_STS LDO8_STS
0
LDO11_EN
A
0
0
0
CS1_SLPEN
A
0
0
0
0
0
0
0
0
0
0
0
0
CHG_TIME[3:0]
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
8
BATT_HOT BATT_COL CHG_TOPO CHG_ACTIV
_STS
D_STS
FF
E
CHG_ITERM[2:0]
0
0
0
LED2_SRC[1:0]
0
0
0
0
0
LED1_SRC[1:0]
CHG_STATE[2:0]
0
CHG_FRC
1
1
1
CHG_OFF_
MSK
0
0
0
1
GP12_OD
0
GP12_PULL[1:0]
0
GP12_INT_ GP12_PWR
GP12_POL
MODE
_DOM
1
GP11_OD
GP11_PULL[1:0]
0
GP10_OD
GP10_INT_ GP10_PWR
GP10_POL
MODE
_DOM
GP11_INT_ GP11_PWR
GP11_POL
MODE
_DOM
GP10_PULL[1:0]
GP8_OD
GP9_OD
0
CS2_ENA
GP6_OD
GP7_OD
GP8_POL
GP7_PULL[1:0]
GP5_OD
GP9_POL
GP7_INT_M GP7_PWR_
ODE
DOM
GP6_PULL[1:0]
GP9_PULL[1:0]
GP6_POL
GP7_POL
GP6_INT_M GP6_PWR_
ODE
DOM
GP5_PULL[1:0]
GP3_OD
GP4_OD
GP8_INT_M GP8_PWR_
ODE
DOM
GP5_POL
GP5_INT_M GP5_PWR_
ODE
DOM
GP4_PULL[1:0]
GP2_OD
GP9_INT_M GP9_PWR_
ODE
DOM
GP3_POL
GP4_POL
GP4_INT_M GP4_PWR_
ODE
DOM
GP3_PULL[1:0]
9
GP1_OD
GP8_PULL[1:0]
GP2_POL
GP2_INT_M GP2_PWR_
ODE
DOM
GP3_INT_M GP3_PWR_
ODE
DOM
GP2_PULL[1:0]
GP1_POL
12
GP1_INT_M GP1_PWR_
ODE
DOM
13
GP1_PULL[1:0]
14
0
0
BATT_OV_S
TS
0
CHG_ENA
1
1
1
1
GP12_DIR
GP11_DIR
GP10_DIR
GP9_DIR
GP8_DIR
GP7_DIR
GP6_DIR
GP5_DIR
GP4_DIR
GP3_DIR
GP2_DIR
GP1_DIR
Bin Default
0000_0011_0000_0000
1000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0UUU_UUUU_UUUU
0000_0000_UU00_UUUU
0U00_0101_0000_0000
0U00_0101_0000_0000
1100_0000_0010_0110
1100_0000_0010_0110
0000_0000_0000_0000
0000_0000_0000_0000
0000_0110_0000_0010
0000_0000_0000_0001
1010_0100_0000_0000
1010_0100_0000_0000
1010_0100_0000_0000
1010_0100_0000_0000
1010_0100_0000_0000
1010_0100_0000_0000
1010_0100_0000_0000
1010_0100_0000_0000
1010_0100_0000_0000
1010_0100_0000_0000
1010_0100_0000_0000
1010_0100_0000_0000
1010_0100_0000_0000
1010_0100_0000_0000
1010_0100_0000_0000
1010_0100_0000_0000
WM8310
Pre-Production
PP, May 2012, Rev 3.1
164
w
405B
405C
405D
405E
405F
4060
4061
4062
4063
4064
4065
4066
4067
16475
16476
16477
16478
16479
16480
16481
16482
16483
16484
16485
16486
16487
4077
4075
4076
16501
16502
16503
4074
16500
4071
16497
4073
4070
16496
4072
406F
16495
16498
406E
16494
16499
406C
406D
16492
16493
406A
406B
16490
16491
4068
405A
16474
4069
4059
16473
16488
4058
16472
16489
Hex Addr
Dec Addr
Nam e
LDO6 Control
LDO5 SLEEP Control
LDO5 ON Control
LDO5 Control
LDO4 SLEEP Control
LDO4 ON Control
LDO4 Control
LDO3 SLEEP Control
LDO3 ON Control
LDO3 Control
LDO2 SLEEP Control
LDO2 ON Control
LDO2 Control
LDO1 SLEEP Control
LDO1 ON Control
LDO1 Control
EPE2 Control
EPE1 Control
DC4 SLEEP Control
DC4 Control
DC3 SLEEP Control
DC3 ON Config
DC3 Control 2
DC3 Control 1
DC2 DVS Control
DC2 SLEEP Control
DC2 ON Config
DC2 Control 2
DC2 Control 1
DC1 DVS Control
DC1 SLEEP Control
DC1 ON Config
0
0
0
LDO5_SLP_SLOT[2:0]
0
0
0
0
0
LDO6_HWC_SRC[1:0]
0
LDO6_ERR_ACT[1:0]
0
LDO5_HWC_SRC[1:0]
LDO5_ON_SLOT[2:0]
LDO5_ERR_ACT[1:0]
0
0
LDO4_ON_SLOT[2:0]
LDO4_SLP_SLOT[2:0]
0
0
0
LDO4_HWC_SRC[1:0]
LDO3_SLP_SLOT[2:0]
0
0
LDO4_ERR_ACT[1:0]
0
0
LDO3_HWC_SRC[1:0]
LDO3_ON_SLOT[2:0]
0
0
0
LDO2_ON_SLOT[2:0]
LDO2_SLP_SLOT[2:0]
LDO3_ERR_ACT[1:0]
0
0
LDO2_HWC_SRC[1:0]
0
0
LDO1_SLP_SLOT[2:0]
LDO2_ERR_ACT[1:0]
0
0
LDO1_ON_SLOT[2:0]
LDO1_HWC_SRC[1:0]
EPE2_HWC_SRC[1:0]
0
EPE2_ON_SLOT[2:0]
0
EPE1_HWC_SRC[1:0]
0
0
EPE1_ON_SLOT[2:0]
LDO1_ERR_ACT[1:0]
0
0
0
0
DC4_HWC_SRC[1:0]
DC3_SLP_SLOT[2:0]
0
0
DC3_HWC_SRC[1:0]
0
DC4_ERR_ACT[1:0]
0
0
DC2_DVS_SRC[1:0]
DC3_PHASE
DC3_ON_SLOT[2:0]
0
0
0
0
DC3_ERR_ACT[1:0]
0
0
0
DC2_HWC_SRC[1:0]
0
0
DC2_ERR_ACT[1:0]
0
0
11
DC1_DVS_SRC[1:0]
DC2_PHASE
DC2_SLP_SLOT[2:0]
0
DC2_ON_SLOT[2:0]
0
0
0
12
DC1_SLP_SLOT[2:0]
13
0
14
DC1_ON_SLOT[2:0]
DC2_RATE[1:0]
0
15
9
8
LDO6_HWC
_VSEL
0
0
LDO5_HWC
_VSEL
0
0
LDO4_HWC
_VSEL
0
0
LDO3_HWC
_VSEL
0
0
LDO2_HWC
_VSEL
0
0
LDO1_HWC
_VSEL
0
0
0
0
0
0
DC3_HWC_
VSEL
0
0
0
0
0
0
0
LDO1_SLP_
MODE
0
0
0
LDO3_SLP_
MODE
0
0
LDO5_SLP_
MODE
LDO6_FLT
0
LDO5_ON_M
ODE
LDO6_HWC_MODE[1:0]
0
0
LDO5_FLT
0
0
LDO4_SLP_
MODE
LDO5_HWC_MODE[1:0]
0
LDO4_ON_M
ODE
LDO4_FLT
0
LDO3_ON_M
ODE
LDO4_HWC_MODE[1:0]
0
0
LDO3_FLT
0
LDO2_SLP_
MODE
LDO3_HWC_MODE[1:0]
0
LDO2_ON_M
ODE
LDO2_FLT
0
LDO1_FLT
LDO1_ON_M
ODE
LDO6_SWI
0
0
LDO5_SWI
0
0
LDO4_SWI
0
0
LDO3_SWI
0
0
LDO2_SWI
0
0
LDO1_SWI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LDO5_SLP_VSEL[4:0]
LDO5_ON_VSEL[4:0]
0
LDO4_SLP_VSEL[4:0]
LDO4_ON_VSEL[4:0]
0
LDO3_SLP_VSEL[4:0]
LDO3_ON_VSEL[4:0]
0
LDO2_SLP_VSEL[4:0]
LDO2_ON_VSEL[4:0]
0
LDO1_SLP_VSEL[4:0]
LDO1_ON_VSEL[4:0]
0
0
0
0
DC4_RANGE[1:0]
DC3_SLP_VSEL[6:0]
DC3_ON_VSEL[6:2]
0
0
2
DC3_STNBY_LIM[1:0]
DC2_DVS_VSEL[6:0]
DC2_SLP_VSEL[6:0]
0
0
DC1_DVS_VSEL[6:0]
DC2_ON_VSEL[6:2]
0
3
DC1_SLP_VSEL[6:0]
DC3_SOFT_START[1:0]
EPE2_SLP_SLOT[2:0]
LDO2_HWC_MODE[1:0]
0
0
4
DC1_ON_VSEL[6:2]
DC2_HC_THR[2:0]
EPE2_HWCE
NA
0
5
DC2_SOFT_START[1:0]
EPE1_SLP_SLOT[2:0]
0
DC4_SLPEN
A
0
0
0
0
6
EPE1_HWCE
NA
0
0
0
DC3_OVP
DC3_FLT
0
0
0
0
DC2_FLT
0
0
0
7
DC4_HWC_
MODE
LDO1_HWC_MODE[1:0]
0
0
0
0
DC3_SLP_MODE[1:0]
DC3_ON_MODE[1:0]
DC3_HWC_MODE[1:0]
0
0
DC2_SLP_MODE[1:0]
DC2_ON_MODE[1:0]
DC2_HWC_MODE[1:0]
DC2_HWC_
VSEL
0
DC2_FREQ[1:0]
0
DC1_SLP_MODE[1:0]
DC1_ON_MODE[1:0]
0
0
0
0
10
1
0
DC2_HC_IND
_ENA
0
0
0
0
0
0
0
0
0
0
0
LDO6_LP_M
ODE
LDO5_LP_M
ODE
LDO4_LP_M
ODE
LDO3_LP_M
ODE
LDO2_LP_M
ODE
LDO1_LP_M
ODE
0
0
0
DC4_FBSRC
DC3_ON_VSEL[1:0]
0
DC3_CAP[1:0]
DC2_ON_VSEL[1:0]
0
DC2_CAP[1:0]
DC1_ON_VSEL[1:0]
Bin Default
0000_0010_0000_0000
0000_0001_0000_0000
0000_0000_0000_0000
0000_0010_0000_0000
0000_0001_0000_0000
0000_0000_0000_0000
0000_0010_0000_0000
0000_0001_0000_0000
0000_0000_0000_0000
0000_0010_0000_0000
0000_0001_0000_0000
0000_0000_0000_0000
0000_0010_0000_0000
0000_0001_0000_0000
0000_0000_0000_0000
0000_0010_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0001_0000_0100
0000_0011_0000_0000
0000_0001_0000_0000
0000_0011_0000_0000
0000_0000_0001_0100
0000_0000_0000_0000
0000_0011_0000_0000
0000_0001_0000_0000
0000_0011_0000_0000
1001_0000_0000_0000
0000_0000_0000_0000
0000_0011_0000_0000
0000_0001_0000_0000
Pre-Production
WM8310
PP, May 2012, Rev 3.1
165
w
4095
4096
16533
16534
4097
4094
16532
16535
4092
4091
16529
4093
4090
16528
16530
408F
16531
408E
16527
4086
16518
16526
4085
16517
408D
4084
16516
408C
4083
16515
16525
4082
16514
16524
4081
16513
408B
4080
16512
408A
407F
16511
16523
407E
16510
16522
407D
16509
4089
407C
16508
16521
407B
16507
4087
407A
16506
4088
4079
16505
16519
4078
16504
16520
Hex Addr
Dec Addr
Nam e
Reserved
FLL Control 5
FLL Control 4
FLL Control 3
FLL Control 2
FLL Control 1
Clock Control 2
Clock Control 1
Pow er Good Source 2
Pow er Good Source 1
Reserved
Reserved
Reserved
Reserved
Reserved
LDO11 SLEEP Control
LDO11 ON Control
Reserved
LDO10 SLEEP Control
LDO10 ON Control
LDO10 Control
LDO9 SLEEP Control
LDO9 ON Control
LDO9 Control
LDO8 SLEEP Control
LDO8 ON Control
LDO8 Control
LDO7 SLEEP Control
LDO7 ON Control
LDO7 Control
LDO6 SLEEP Control
LDO6 ON Control
0
XTAL_INH
0
0
0
0
0
0
0
0
0
CLKOUT_EN
A
0
0
0
0
0
0
0
0
0
XTAL_ENA
CLKOUT_OD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LDO6_SLP_
MODE
0
LDO7_SLP_
MODE
0
LDO8_SLP_
MODE
0
LDO10_OK
0
0
0
0
0
0
0
0
0
0
0
0
LDO10_SLP
_MODE
FLL_N[9:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FLL_AUTO
0
LDO8_OK
FLL_K[15:0]
LDO9_OK
0
0
0
0
0
0
0
LDO11_VSE
L_SRC
0
0
LDO10_ON_
MODE
0
0
0
LDO9_SWI
0
0
LDO8_SWI
0
0
LDO7_SWI
0
0
6
0
0
0
0
LDO6_OK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
0
FLL_CTRL_RATE[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
1
0
LDO1_OK
DC1_OK
0
0
0
0
0
0
0
0
0
0
0
0
CLKOUT_SR
C
FLL_FRATIO[2:0]
FLL_ENA
0
0
FLL_CLK_SRC[1:0]
FLL_GAIN[3:0]
0
0
LDO2_OK
DC2_OK
0
0
0
0
0
FLL_AUTO_FREQ[2:0]
FLL_FRAC
0
LDO3_OK
DC3_OK
0
0
0
0
0
LDO11_SLP_VSEL[3:0]
LDO11_ON_VSEL[3:0]
0
LDO10_SLP_VSEL[4:0]
LDO10_ON_VSEL[4:0]
0
LDO9_SLP_VSEL[4:0]
LDO9_ON_VSEL[4:0]
0
LDO8_SLP_VSEL[4:0]
LDO8_ON_VSEL[4:0]
0
LDO7_SLP_VSEL[4:0]
LDO7_ON_VSEL[4:0]
0
LDO6_SLP_VSEL[4:0]
LDO4_OK
0
2
LDO6_ON_VSEL[4:0]
DC4_OK
0
0
0
0
0
0
0
0
0
0
3
FLL_CLK_REF_DIV[1:0]
0
0
0
LDO5_OK
CLKOUT_SLPSLOT[2:0]
LDO7_OK
0
0
0
0
0
0
0
0
0
0
0
LDO10_FLT LDO10_SWI
0
LDO9_SLP_
MODE
LDO10_HWC_MODE[1:0]
0
0
LDO9_ON_M
ODE
LDO9_FLT
0
LDO8_ON_M
ODE
LDO9_HWC_MODE[1:0]
0
0
LDO8_FLT
0
LDO7_ON_M
ODE
LDO8_HWC_MODE[1:0]
0
0
LDO7_FLT
7
8
LDO6_ON_M
ODE
LDO7_HWC_MODE[1:0]
0
0
9
CLKOUT_SLOT[2:0]
LDO10_HW
C_VSEL
0
0
LDO9_HWC
_VSEL
0
0
LDO8_HWC
_VSEL
0
0
LDO7_HWC
_VSEL
0
0
10
FLL_OUTDIV[5:0]
0
0
XTAL_BKUP
ENA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LDO11_ON_SLOT[2:0]
LDO11_SLP_SLOT[2:0]
0
LDO11_FRC
ENA
0
0
0
0
0
0
0
0
0
0
LDO10_SLP_SLOT[2:0]
0
0
LDO10_ON_SLOT[2:0]
0
0
0
0
0
0
0
0
0
0
LDO10_HWC_SRC[1:0]
0
0
0
LDO9_ON_SLOT[2:0]
LDO9_SLP_SLOT[2:0]
LDO10_ERR_ACT[1:0]
0
LDO9_HWC_SRC[1:0]
0
0
LDO8_SLP_SLOT[2:0]
LDO9_ERR_ACT[1:0]
0
LDO8_ON_SLOT[2:0]
0
0
LDO7_SLP_SLOT[2:0]
0
LDO8_HWC_SRC[1:0]
0
LDO8_ERR_ACT[1:0]
0
0
11
LDO7_HWC_SRC[1:0]
LDO7_ON_SLOT[2:0]
0
0
12
LDO6_SLP_SLOT[2:0]
13
0
14
LDO6_ON_SLOT[2:0]
LDO7_ERR_ACT[1:0]
15
Bin Default
0000_0000_0000_0000
0000_0000_0000_0000
0010_1110_1110_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0001_0000_1000_0000
U000_0000_0000_0000
0000_0011_1111_1111
0000_0000_0000_0111
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0001_0000_0000
0000_0000_0000_0000
0000_0010_0000_0000
0000_0001_0000_0000
0000_0000_0000_0000
0000_0010_0000_0000
0000_0001_0000_0000
0000_0000_0000_0000
0000_0010_0000_0000
0000_0001_0000_0000
0000_0000_0000_0000
0000_0010_0000_0000
0000_0001_0000_0000
0000_0000_0000_0000
WM8310
Pre-Production
PP, May 2012, Rev 3.1
166
w
7817
7818
7819
30743
30744
30745
30751
781F
781E
7816
30742
781D
7815
30741
30750
7814
30740
30749
7813
30739
781C
7812
30738
30748
7811
30737
781B
7810
30736
30747
780F
30735
781A
780E
30746
780D
30734
7808
30728
30733
7807
30727
780C
7806
30726
780B
7805
30725
30732
7804
30724
30731
7803
30723
7809
7802
30722
780A
7801
30721
30730
7800
30720
30729
Hex Addr
Dec Addr
Nam e
13
LDO11_ON_SLOT[2:0]
LDO11/EPE Control
GPIO6 OTP Control
GPIO5 OTP Control
GPIO4 OTP Control
GPIO3 OTP Control
GPIO2 OTP Control
GPIO1 OTP Control
GP6_DIR
GP5_DIR
GP4_DIR
GP3_DIR
GP2_DIR
GP1_DIR
LDO10_ON_VSEL[4:0]
LDO10_ON_SLOT[2:0]
LDO9/10 OTP Control
GP4_POL
GP5_POL
GP4_INT_M GP4_PWR_D
ODE
OM
GP5_INT_M GP5_PWR_D
ODE
OM
GP3_PULL[1:0]
GP4_PULL[1:0]
GP5_PULL[1:0]
GP6_POL
GP3_POL
GP3_INT_M GP3_PWR_D
ODE
OM
GP6_INT_M GP6_PWR_D
ODE
OM
GP2_POL
GP2_INT_M GP2_PWR_D
ODE
OM
GP2_PULL[1:0]
GP6_PULL[1:0]
GP1_POL
GP1_INT_M GP1_PWR_D
ODE
OM
GP1_PULL[1:0]
GP6_OD
GP5_OD
GP4_OD
GP3_OD
GP2_OD
GP1_OD
GP6_ENA
GP5_ENA
GP4_ENA
GP3_ENA
GP2_ENA
GP1_ENA
0
DC2_FREQ[1:0]
0
0
0
0
0
0
0
GP6_FN[3:0]
GP5_FN[3:0]
GP4_FN[3:0]
GP3_FN[3:0]
GP2_FN[3:0]
GP1_FN[3:0]
EPE2_ON_SLOT[2:0]
LDO9_ON_SLOT[2:0]
LDO7_ON_SLOT[2:0]
LDO5_ON_SLOT[2:0]
LDO3_ON_SLOT[2:0]
LDO1_ON_SLOT[2:0]
DC3_PHASE
DC2_PHASE
DC1_PHASE
OTP_CUST_ID[13:0]
0
0
0
0
DC1_FREQ[1:0]
0
0
0
0
OSC_TRIM[3:0]
CHIP_ID[15:0]
0
0
0
0
LPBG_TRIM[2:0]
CH_AW
FLL_AUTO_FREQ[2:0]
SYSOK_THR[2:0]
USB_ILIM[2:0]
LED1_SRC[1:0]
DC3_CAP[1:0]
DC2_CAP[1:0]
CHG_ENA
0
WDOG_ENA
0
0
LED2_SRC[1:0]
XTAL_INH
CLKOUT_SLOT[2:0]
CLKOUT_SR
XTAL_ENA
C
0
OTP_CUST_
FINAL
DC1_CAP[1:0]
0
USB100MA_STARTUP[1:0]
LDO9_ON_VSEL[4:0]
LDO7_ON_VSEL[4:0]
LDO5_ON_VSEL[4:0]
LDO3_ON_VSEL[4:0]
LDO1_ON_VSEL[4:0]
0
DC3_LIM_LO DC2_LIM_LO DC1_LIM_LO
W
W
W
CHARGE_TRIM[5:0]
EPE1_ON_SLOT[2:0]
DC3_ON_VSEL[6:2]
DC2_ON_VSEL[6:2]
DC1_ON_VSEL[6:2]
0
0
CHILD_I2C_ADDR[6:0]
BG_TRIM[3:0]
DC1_TRIM[5:0]
0000_0000_0000_0000
UNIQUE_ID[15:0]
1010_0100_0000_1010
1010_0100_0000_0100
1010_0100_0000_1111
1010_0100_0000_0000
1010_0100_0000_0001
1010_0100_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_1000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
OTP_FACT_
FINAL
0000_0000_0000_0000
UNIQUE_ID[31:16]
OTP_FACT_ID[14:0]
0000_0000_0000_0000
Bin Default
UNIQUE_ID[47:32]
0
UNIQUE_ID[63:48]
1
0000_0000_0000_0000
2
0000_0000_0000_0000
3
UNIQUE_ID[79:64]
4
UNIQUE_ID[95:80]
5
0000_0000_0000_0000
6
UNIQUE_ID[111:96]
7
0000_0000_0000_0000
8
UNIQUE_ID[127:112]
DC2_TRIM[5:0]
9
LDO11_ON_VSEL[3:0]
LDO8_ON_VSEL[4:0]
0
LDO6_ON_VSEL[4:0]
LDO8_ON_SLOT[2:0]
LDO7/8 OTP Control
LDO5/6 OTP Control
LDO3/4 OTP Control
LDO1/2 OTP Control
LDO6_ON_SLOT[2:0]
0
0
LDO4_ON_VSEL[4:0]
0
0
0
0
0
0
0
10
LDO2_ON_VSEL[4:0]
0
0
0
0
0
0
0
11
LDO4_ON_SLOT[2:0]
0
DC3_ON_SLOT[2:0]
0
0
0
0
0
DC2_ON_SLOT[2:0]
0
0
0
0
0
12
0
0
0
0
0
0
DC3_TRIM[3:0]
14
DC1_ON_SLOT[2:0]
OTP_AUTO_
PROG
0
0
0
0
0
15
LDO2_ON_SLOT[2:0]
DC3 OTP Control
DC2 OTP Control
DC1 OTP Control
Customer OTP ID
Reserved
Factory OTP 6
Factory OTP 5
Factory OTP 4
Factory OTP 3
Factory OTP 2
Factory OTP 1
Factory OTP ID
Unique ID 8
Unique ID 7
Unique ID 6
Unique ID 5
Unique ID 4
Unique ID 3
Unique ID 2
Unique ID 1
Pre-Production
WM8310
PP, May 2012, Rev 3.1
167
7822
7823
7824
7825
7826
7827
30756
30757
30758
30759
7821
30753
30755
7820
30752
30754
Hex Addr
Dec Addr
Nam e
w
ICE CHECK DATA
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
15
0
0
0
0
0
0
0
14
0
0
0
0
0
0
0
13
0
0
0
0
0
0
0
12
0
0
0
0
0
0
0
11
0
0
0
0
0
0
0
10
9
0
0
0
0
0
0
0
8
7
0
0
0
0
0
0
0
ICE_VALID_DATA[15:0]
0
0
0
0
0
0
0
6
0
0
0
0
0
0
0
5
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bin Default
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0L0H_H0LL
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
WM8310
Pre-Production
PP, May 2012, Rev 3.1
168
WM8310
Pre-Production
29 REGISTER BITS BY ADDRESS
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R0 (00h)
Reset ID
15:0
CHIP_ID [15:0]
0000_0000 Writing to this register causes a Software Reset. The
_0000_000 register map contents may be reset, depending on
0
SW_RESET_CFG.
Reading from this register will indicate Chip ID.
Register 00h Reset ID
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R1 (01h)
Revision
15:8
7:0
PARENT_REV 0000_0000 The revision number of the parent die
[7:0]
CHILD_REV
[7:0]
0000_0000 The revision number of the child die (when present)
Register 01h Revision
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16384
(4000h)
Parent ID
15:0
PARENT_ID
[15:0]
0110_0010 The ID of the parent die
_0000_010
0
Register 4000h Parent ID
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16385
(4001h)
SYSVDD
Control
15:14
SYSLO_ERR_
ACT [1:0]
00
SYSLO Error Action
Selects the action taken when SYSLO is asserted
00 = Interrupt
01 = WAKE transition
10 = Reserved
11 = OFF transition
11
SYSLO_STS
0
SYSLO Status
0 = Normal
1 = SYSVDD is below SYSLO threshold
6:4
SYSLO_THR
[2:0]
010
SYSLO threshold (falling SYSVDD)
This is the falling SYSVDD voltage at which SYSLO will
be asserted
000 = 2.8V
001 = 2.9V
…
111 = 3.5V
2:0
SYSOK_THR
[2:0]
101
SYSOK threshold (rising SYSVDD)
This is the rising SYSVDD voltage at which SYSOK will
be asserted
000 = 2.8V
001 = 2.9V
…
111 = 3.5V
Note that the SYSOK hysteresis margin is added to
these threshold levels.
Register 4001h SYSVDD Control
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169
WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16386
(4002h)
Thermal
Monitoring
3
THW_HYST
1
Thermal Warning hysteresis
0 = 8 degrees C
1 = 16 degrees C
1:0
THW_TEMP
[1:0]
10
Thermal Warning temperature
00 = 90 degrees C
01 = 100 degrees C
10 = 110 degrees C
11 = 120 degrees C
Register 4002h Thermal Monitoring
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16387
(4003h)
Power State
15
CHIP_ON
0
Indicates whether the system is ON or OFF.
0 = OFF
1 = ON (or SLEEP)
OFF can be commanded by writing CHIP_ON = 0.
Note that writing CHIP_ON = 1 is not a valid ‘ON’ event,
and will not trigger an ON transition.
14
CHIP_SLP
0
Indicates whether the system is in the SLEEP state.
0 = Not in SLEEP
1 = SLEEP
WAKE can be commanded by writing CHIP_SLP = 0.
SLEEP can be commanded by writing CHIP_SLP = 1.
12
REF_LP
0
Low Power Voltage Reference Control
0 = Normal
1 = Low Power Reference Mode select
Note that Low Power Reference Mode is only supported
when the Auxiliary ADC is disabled.
11:10
PWRSTATE_D
LY [1:0]
10
Power State transition delay
00 = No delay
01 = No delay
10 = 1ms
11 = 10ms
9
SWRST_DLY
0
Software Reset Delay
0 = No delay
1 = Software Reset is delayed by PWRSTATE_DLY
following the Software Reset command
5:4
USB100MA_S
TARTUP [1:0]
00
Sets the device behaviour when starting up under USB
power, when USB_ILIM = 010b (100mA)
00 = Normal
01 = Soft-Start
10 = Only start if BATTVDD > 3.1V
11 = Only start if BATTVDD > 3.4V
In the 1X modes, if the battery voltage is less than the
selected threshold, then the device will enable trickle
charge mode instead of executing the start-up request.
The start-up request is delayed until the battery voltage
threshold has been met.
3
USB_CURR_S
TS
0
Indicates if the USB current limit has been reached
0 = Normal
1 = USB current limit
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170
WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
2:0
USB_ILIM [2:0]
010
Sets the USB current limit
000 = 0mA (USB switch is open)
001 = 2.5mA
010 = 100mA
011 = 500mA
100 = 900mA
101 = 1500mA
110 = 1800mA
111 = 550mA
Note that, when starting up the WM8310 with the
USBVDD supply selected, the USB_ILIM register must
be set to 100mA or higher.
Register 4003h Power State
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16388
(4004h)
Watchdog
15
WDOG_ENA
1
Watchdog Timer Enable
0 = Disabled
1 = Enabled (enables the watchdog; does not reset it)
Protected by security key.
14
WDOG_DEBU
G
0
Watchdog Pause
0 = Disabled
1 = Enabled (halts the Watchdog timer for system
debugging)
Protected by security key.
13
WDOG_RST_S
RC
1
Watchdog Reset Source
0 = Hardware only
1 = Software only
Protected by security key.
12
WDOG_SLPE
NA
0
Watchdog SLEEP Enable
0 = Disabled
1 = Controlled by WDOG_ENA
Protected by security key.
11
WDOG_RESE
T
0
Watchdog Software Reset
0 = Normal
1 = Watchdog Reset (resets the watchdog, if
WDOG_RST_SRC = 1)
9:8
WDOG_SECA
CT [1:0]
10
Secondary action of Watchdog timeout (taken after 2
timeout periods)
00 = No action
01 = Interrupt
10 = Device Reset
11 = WAKE transition
Protected by security key.
5:4
WDOG_PRIMA
CT [1:0]
01
Primary action of Watchdog timeout
00 = No action
01 = Interrupt
10 = Device Reset
11 = WAKE transition
Protected by security key.
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171
WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
2:0
WDOG_TO
[2:0]
111
Watchdog timeout period
000 = 0.256s
001 = 0.512s
010 = 1.024s
011 = 2.048s
100 = 4.096s
101 = 8.192s
110 = 16.384s
111 = 32.768s
Protected by security key.
Register 4004h Watchdog
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16389
(4005h) ON
Pin Control
9:8
ON_PIN_SECA
CT [1:0]
01
Secondary action of ON pin (taken after 1 timeout
period)
00 = Interrupt
01 = ON request
10 = OFF request
11 = Reserved
Protected by security key.
5:4
ON_PIN_PRIM
ACT [1:0]
00
Primary action of ON pin
00 = Ignore
01 = ON request
10 = OFF request
11 = Reserved
Note that an Interrupt is always raised.
Protected by security key.
3
ON_PIN_STS
0
Current status of ON pin
0 = Asserted (logic 0)
1 = Not asserted (logic 1)
1:0
ON_PIN_TO
[1:0]
00
ON pin timeout period
00 = 1s
01 = 2s
10 = 4s
11 = 8s
Protected by security key.
Register 4005h ON Pin Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16390
(4006h)
Reset
Control
15
RECONFIG_A
T_ON
1
Selects if the bootstrap configuration data should be
reloaded when an ON transition is scheduled
0 = Disabled
1 = Enabled
Protected by security key.
13
WALL_FET_E
NA_DRV_STR
0
Sets the drive strength of the WALLFETENA pin. (Note
this pin is Active Low.)
0 = Weak drive (500kOhm)
1 = Strong drive (50kOhm)
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
12
BATT_FET_EN
A
0
Enables the FET gate functionality on the
BATTFETENA pin. (Note this pin is Active Low.)
0 = Disabled
1 = Enabled
Note - this bit is reset to 0 when the OFF power state is
entered.
10
SW_RESET_C
FG
1
Software Reset Configuration.
Selects whether the register map is reset to default
values when Software Reset occurs.
0 = All registers except RTC and Software Scratch
registers are reset by Software Reset
1 = Register Map is not affected by Software Reset
Protected by security key.
6
AUXRST_SLP
ENA
1
Sets the output status of Auxiliary Reset (GPIO)
function in SLEEP
0 = Auxiliary Reset not asserted
1 = Auxiliary Reset asserted
Protected by security key.
5
RST_SLP_MS
K
1
Masks the RESET pin input in SLEEP mode
0 = External RESET active in SLEEP
1 = External RESET masked in SLEEP
Protected by security key.
4
RST_SLPENA
1
Sets the output status of RESET pin in SLEEP
0 = RESET high (not asserted)
1 = RESET low (asserted)
Protected by security key.
1:0
RST_DUR [1:0]
11
Delay period for releasing RESET after ON or WAKE
sequence
00 = 3ms
01 = 11ms
10 = 51ms
11 = 101ms
Protected by security key.
Register 4006h Reset Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16391
(4007h)
Control
Interface
2
AUTOINC
1
Enable Auto-Increment function
0 = Disabled
1 = Enabled
Register 4007h Control Interface
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16392
(4008h)
Security Key
15:0
SECURITY
[15:0]
0000_0000 Security Key
_0000_000 A value of 9716h must be written to this register to
0
access the user-keyed registers.
Register 4008h Security Key
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PP, May 2012, Rev 3.1
173
WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16393
(4009h)
Software
Scratch
15:0
SW_SCRATCH 0000_0000 Software Scratch Register for use by the host processor.
[15:0]
_0000_000 Note that this register’s contents are retained in the
0
BACKUP power state.
Register 4009h Software Scratch
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16394
(400Ah)
OTP Control
15
OTP_PROG
0
Selects the PROGRAM device state.
0 = No action
1 = Select PROGRAM mode
Note that, after PROGRAM mode has been selected,
the chip will remain in PROGRAM mode until a Device
Reset.
Protected by security key.
13
OTP_MEM
1
Selects ICE or OTP memory for Program commands.
0 = ICE
1 = OTP
Protected by security key.
11
OTP_FINAL
0
Selects the FINALISE command, preventing further
OTP programming.
0 = No action
1 = Finalise Command
Protected by security key.
10
OTP_VERIFY
0
Selects the VERIFY command for the selected OTP
memory page(s).
0 = No action
1 = Verify Command
Protected by security key.
9
OTP_WRITE
0
Selects WRITE command for the selected OTP memory
page(s).
0 = No action
1 = Write Command
Protected by security key.
8
OTP_READ
0
Selects READ command for the selected memory
page(s).
0 = No action
1 = Read Command
Protected by security key.
7:6
OTP_READ_L
VL [1:0]
00
Selects the Margin Level for READ or VERIFY OTP
commands.
00 = Normal
01 = Reserved
10 = Margin 1
11 = Margin 2
Protected by security key.
5
OTP_BULK
0
Selects the number of memory pages for ICE / OTP
commands.
0 = Single Page
1 = All Pages
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REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
1:0
OTP_PAGE
[1:0]
00
Selects the single memory page for ICE / OTP
commands (when OTP_BULK=0).
If OTP is selected (OTP_MEM = 1):
00 = Page 0
01 = Page 1
10 = Page 2
11 = Page 3
If ICE is selected (OTP_MEM = 0):
00 = Page 2
01 = Page 3
10 = Page 4
11 = Reserved
Register 400Ah OTP Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16396
(400Ch)
GPIO Level
11
GP12_LVL
0
GPIO12 level.
When GP12_FN = 0h and GP12_DIR = 0, write to this
bit to set a GPIO output.
Read from this bit to read GPIO input level.
When GP12_POL is 0, the register contains the
opposite logic level to the external pin. Write to this bit
to set a GPIO output.
10
GP11_LVL
0
GPIO11 level.
When GP11_FN = 0h and GP11_DIR = 0, write to this
bit to set a GPIO output.
Read from this bit to read GPIO input level.
When GP11_POL is 0, the register contains the
opposite logic level to the external pin. Write to this bit
to set a GPIO output.
9
GP10_LVL
0
GPIO10 level.
When GP10_FN = 0h and GP10_DIR = 0, write to this
bit to set a GPIO output.
Read from this bit to read GPIO input level.
When GP10_POL is 0, the register contains the
opposite logic level to the external pin. Write to this bit
to set a GPIO output.
8
GP9_LVL
0
GPIO9 level.
When GP9_FN = 0h and GP9_DIR = 0, write to this bit
to set a GPIO output.
Read from this bit to read GPIO input level.
When GP9_POL is 0, the register contains the opposite
logic level to the external pin. Write to this bit to set a
GPIO output.
7
GP8_LVL
0
GPIO8 level.
When GP8_FN = 0h and GP8_DIR = 0, write to this bit
to set a GPIO output.
Read from this bit to read GPIO input level.
When GP8_POL is 0, the register contains the opposite
logic level to the external pin. Write to this bit to set a
GPIO output.
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REGISTER
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BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
6
GP7_LVL
0
GPIO7 level.
When GP7_FN = 0h and GP7_DIR = 0, write to this bit
to set a GPIO output.
Read from this bit to read GPIO input level.
When GP7_POL is 0, the register contains the opposite
logic level to the external pin. Write to this bit to set a
GPIO output.
5
GP6_LVL
0
GPIO6 level.
When GP6_FN = 0h and GP6_DIR = 0, write to this bit
to set a GPIO output.
Read from this bit to read GPIO input level.
When GP6_POL is 0, the register contains the opposite
logic level to the external pin. Write to this bit to set a
GPIO output.
4
GP5_LVL
0
GPIO5 level.
When GP5_FN = 0h and GP5_DIR = 0, write to this bit
to set a GPIO output.
Read from this bit to read GPIO input level.
When GP5_POL is 0, the register contains the opposite
logic level to the external pin. Write to this bit to set a
GPIO output.
3
GP4_LVL
0
GPIO4 level.
When GP4_FN = 0h and GP4_DIR = 0, write to this bit
to set a GPIO output.
Read from this bit to read GPIO input level.
When GP4_POL is 0, the register contains the opposite
logic level to the external pin. Write to this bit to set a
GPIO output.
2
GP3_LVL
0
GPIO3 level.
When GP3_FN = 0h and GP3_DIR = 0, write to this bit
to set a GPIO output.
Read from this bit to read GPIO input level.
When GP3_POL is 0, the register contains the opposite
logic level to the external pin. Write to this bit to set a
GPIO output.
1
GP2_LVL
0
GPIO2 level.
When GP2_FN = 0h and GP2_DIR = 0, write to this bit
to set a GPIO output.
Read from this bit to read GPIO input level.
When GP2_POL is 0, the register contains the opposite
logic level to the external pin. Write to this bit to set a
GPIO output.
0
GP1_LVL
0
GPIO1 level.
When GP1_FN = 0h and GP1_DIR = 0, write to this bit
to set a GPIO output.
Read from this bit to read GPIO input level.
When GP1_POL is 0, the register contains the opposite
logic level to the external pin. Write to this bit to set a
GPIO output.
Register 400Ch GPIO Level
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REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16397
(400Dh)
System
Status
15
THW_STS
0
Thermal Warning status
0 = Normal
1 = Overtemperature Warning
(warning temperature is set by THW_TEMP)
10
PWR_SRC_BA
TT
0
PWR_WALL
0
Battery Power Source status
0 = Battery is not supplying current
1 = Battery is supplying current
9
Wall Adaptor status
0 = Wall Adaptor voltage not present
1 = Wall Adaptor voltage is present
8
PWR_USB
0
USB status
0 = USB voltage not present
1 = USB voltage is present
4:0
MAIN_STATE
[4:0]
0_0000
Main State Machine condition
0_0000 = OFF
0_0001 = ON_CHK
0_0010 = OTP_DN
0_0011 = READ_OTP
0_0100 = READ_ICE
0_0101 = ICE_DN
0_0110 = BGDELAY
0_0111 = HYST
0_1000 = S_PRG_RD_OTP
0_1001 = S_PRG_OTP_DN
0_1010 = PWRDN1
0_1011 = PROGRAM
0_1100 = PROG_DN
0_1101 = PROG_OTP
0_1110 = VFY_OTP
0_1111 = VFY_DN
1_0000 = SD_RD_OTP
1_0001 = UNUSED
1_0010 = ICE_FAIL
1_0011 = SHUTDOWN
1_0100 = STARTFAIL
1_0101 = STARTUP
1_0110 = PREACTIVE
1_0111 = XTAL_CHK
1_1000 = PWRDN2
1_1001 = SHUT_DLY
1_1010 = RESET
1_1011 = RESET_DLY
1_1100 = SLEEP
1_1101 = SLEEP_DLY
1_1110 = CHK_RST
1_1111 = ACTIVE (ON)
Register 400Dh System Status
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REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16398
(400Eh) ON
Source
15
ON_TRANS
0
11
ON_GPIO
0
10
ON_SYSLO
0
8
ON_CHG
0
Most recent ON/WAKE event type
0 = WAKE transition
1 = ON transition
Reset by state machine.
Most recent ON/WAKE event type
0 = Not caused by GPIO input
1 = Caused by GPIO input
Reset by state machine.
Most recent WAKE event type
0 = Not caused by SYSVDD
1 = Caused by SYSLO threshold. Note that the SYSLO
threshold cannot trigger an ON event.
Reset by state machine.
Most recent WAKE event type
0 = Not caused by Battery Charger
1 = Caused by Battery Charger
TBC if this could cause ON due to Charger plugged in?
Reset by state machine.
7
ON_WDOG_T
O
0
Most recent WAKE event type
0 = Not caused by Watchdog timer
1 = Caused by Watchdog timer
6
ON_SW_REQ
0
5
ON_RTC_ALM
0
4
ON_ON_PIN
0
Most recent ON/WAKE event type
0 = Not caused by the ON pin
1 = Caused by the ON pin
3
RESET_CNV_
UV
0
Most recent ON event type
0 = Not caused by undervoltage
1 = Caused by a Device Reset due to a Converter (LDO
or DC-DC) undervoltage condition
2
RESET_SW
0
Most recent ON event type
0 = Not caused by Software Reset
1 = Caused by Software Reset
Reset by state machine.
Most recent WAKE event type
0 = Not caused by software WAKE
1 = Caused by software WAKE command (CHIP_SLP =
0)
Reset by state machine.
Most recent ON/WAKE event type
0 = Not caused by RTC Alarm
1 = Caused by RTC Alarm
Reset by state machine.
Reset by state machine.
Reset by state machine.
Reset by state machine.
1
RESET_HW
0
0
RESET_WDO
G
0
Most recent ON event type
0 = Not caused by Hardware Reset
1 = Caused by Hardware Reset
Reset by state machine.
Most recent ON event type
0 = Not caused by the Watchdog
1 = Caused by a Device Reset triggered by the
Watchdog timer
Reset by state machine.
Register 400Eh ON Source
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REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16399
(400Fh)
OFF Source
13
OFF_INTLDO_
ERR
0
Most recent OFF event type
0 = Not caused by LDO13 Error condition
1 = Caused by LDO13 Error condition
Reset by state machine.
12
OFF_PWR_SE
Q
0
Most recent OFF event type
0 = Not caused by Power Sequence Failure
1 = Caused by a Power Sequence Failure
Reset by state machine.
11
OFF_GPIO
0
Most recent OFF event type
0 = Not caused by GPIO input
1 = Caused by GPIO input
Reset by state machine.
10
OFF_SYSVDD
0
Most recent OFF event type
0 = Not caused by SYSVDD
1 = Caused by the SYSLO or SHUTDOWN threshold
Reset by state machine.
9
OFF_THERR
0
Most recent OFF event type
0 = Not caused by temperature
1 = Caused by over-temperature
Reset by state machine.
6
OFF_SW_REQ
0
Most recent OFF event type
0 = Not caused by software OFF
1 = Caused by software OFF command (CHIP_ON = 0)
Reset by state machine.
4
OFF_ON_PIN
0
Most recent OFF event type
0 = Not caused by the ON pin
1 = Caused by the ON pin
Reset by state machine.
Register 400Fh OFF Source
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16400
(4010h)
System
Interrupts
15
PS_INT
0
Power State primary interrupt
0 = No interrupt
1 = Interrupt is asserted
14
TEMP_INT
0
Thermal primary interrupt
0 = No interrupt
1 = Interrupt is asserted
13
GP_INT
0
GPIO primary interrupt
0 = No interrupt
1 = Interrupt is asserted
12
ON_PIN_INT
0
ON Pin primary interrupt
0 = No interrupt
1 = Interrupt is asserted
11
WDOG_INT
0
Watchdog primary interrupt
0 = No interrupt
1 = Interrupt is asserted
8
AUXADC_INT
0
AUXADC primary interrupt
0 = No interrupt
1 = Interrupt is asserted
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REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
7
PPM_INT
0
Power Path Management primary interrupt
0 = No interrupt
1 = Interrupt is asserted
6
CS_INT
0
Current Sink primary interrupt
0 = No interrupt
1 = Interrupt is asserted
5
RTC_INT
0
Real Time Clock primary interrupt
0 = No interrupt
1 = Interrupt is asserted
4
OTP_INT
0
OTP Memory primary interrupt
0 = No interrupt
1 = Interrupt is asserted
2
CHG_INT
0
Battery Charger primary interrupt
0 = No interrupt
1 = Interrupt is asserted
1
HC_INT
0
High Current primary interrupt
0 = No interrupt
1 = Interrupt is asserted
0
UV_INT
0
Undervoltage primary interrupt
0 = No interrupt
1 = Interrupt is asserted
Register 4010h System Interrupts
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16401
(4011h)
Interrupt
Status 1
15
PPM_SYSLO_
EINT
0
PPM_PWR_SR
C_EINT
0
Power Path SYSLO interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
14
Power Path Source interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
13
PPM_USB_CU
RR_EINT
0
ON_PIN_CINT
0
Power Path USB Current interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
12
ON pin interrupt.
(Rising and Falling Edge triggered)
Note: Cleared when a ‘1’ is written.
11
WDOG_TO_EI
NT
0
AUXADC_DAT
A_EINT
0
AUXADC_DCO
MP4_EINT
0
AUXADC_DCO
MP3_EINT
0
Watchdog timeout interrupt.
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
8
AUXADC Data Ready interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
7
AUXADC Digital Comparator 4 interrupt
(Trigger is controlled by DCMP4_GT)
Note: Cleared when a ‘1’ is written.
6
AUXADC Digital Comparator 3 interrupt
(Trigger is controlled by DCMP3_GT)
Note: Cleared when a ‘1’ is written.
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REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
5
AUXADC_DCO
MP2_EINT
0
AUXADC_DCO
MP1_EINT
0
RTC_PER_EIN
T
0
RTC_ALM_EIN
T
0
TEMP_THW_C
INT
0
AUXADC Digital Comparator 2 interrupt
(Trigger is controlled by DCMP2_GT)
Note: Cleared when a ‘1’ is written.
4
AUXADC Digital Comparator 1 interrupt
(Trigger is controlled by DCMP1_GT)
Note: Cleared when a ‘1’ is written.
3
RTC Periodic interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
2
RTC Alarm interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
1
Thermal Warning interrupt
(Rising and Falling Edge triggered)
Note: Cleared when a ‘1’ is written.
Register 4011h Interrupt Status 1
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16402
(4012h)
Interrupt
Status 2
15
CHG_BATT_H
OT_EINT
0
CHG_BATT_C
OLD_EINT
0
CHG_BATT_F
AIL_EINT
0
CHG_OV_EINT
0
Battery Hot interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
14
Battery Cold interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
13
Battery Fail interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
12
Battery Overvoltage interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
11
CHG_END_EI
NT
0
Battery Charge End interrupt (End of Charge Current
threshold reached)
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
10
CHG_TO_EINT
0
Battery Charge Timeout interrupt (Charger Timer has
expired)
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
9
CHG_MODE_E
INT
0
Battery Charge Mode interrupt (Charger Mode has
changed)
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
8
CHG_START_
EINT
0
CS2_EINT
0
Battery Charge Start interrupt (Charging has started)
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
7
Current Sink 2 interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
6
CS1_EINT
0
Current Sink 1 interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
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REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
5
OTP_CMD_EN
D_EINT
0
OTP_ERR_EIN
T
0
PS_POR_EINT
0
OTP / ICE Command End interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
4
OTP / ICE Command Fail interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
2
Power On Reset interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
1
PS_SLEEP_O
FF_EINT
0
SLEEP or OFF interrupt (Power state transition to
SLEEP or OFF states)
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
0
PS_ON_WAKE
_EINT
0
ON or WAKE interrupt (Power state transition to ON
state)
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
Register 4012h Interrupt Status 2
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16403
(4013h)
Interrupt
Status 3
9
UV_LDO10_EI
NT
0
8
UV_LDO9_EIN
T
0
UV_LDO8_EIN
T
0
UV_LDO7_EIN
T
0
UV_LDO6_EIN
T
0
UV_LDO5_EIN
T
0
LDO10 Undervoltage interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
LDO9 Undervoltage interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
7
LDO8 Undervoltage interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
6
LDO7 Undervoltage interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
5
LDO6 Undervoltage interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
4
LDO5 Undervoltage interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
3
UV_LDO4_EIN
T
0
UV_LDO3_EIN
T
0
UV_LDO2_EIN
T
0
UV_LDO1_EIN
T
0
LDO4 Undervoltage interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
2
LDO3 Undervoltage interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
1
LDO2 Undervoltage interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
0
LDO1 Undervoltage interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
Register 4013h Interrupt Status 3
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REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16404
(4014h)
Interrupt
Status 4
9
HC_DC2_EINT
0
DC-DC2 High current interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
8
HC_DC1_EINT
0
DC-DC1 High current interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
3
UV_DC4_EINT
0
DC-DC4 Undervoltage interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
2
UV_DC3_EINT
0
DC-DC3 Undervoltage interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
1
UV_DC2_EINT
0
DC-DC2 Undervoltage interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
0
UV_DC1_EINT
0
DC-DC1 Undervoltage interrupt
(Rising Edge triggered)
Note: Cleared when a ‘1’ is written.
Register 4014h Interrupt Status 4
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16405
(4015h)
Interrupt
Status 5
11
GP12_EINT
0
GPIO12 interrupt.
(Trigger is controlled by GP12_INT_MODE)
Note: Cleared when a ‘1’ is written.
10
GP11_EINT
0
GPIO11 interrupt.
(Trigger is controlled by GP11_INT_MODE)
Note: Cleared when a ‘1’ is written.
9
GP10_EINT
0
GPIO10 interrupt.
(Trigger is controlled by GP10_INT_MODE)
Note: Cleared when a ‘1’ is written.
8
GP9_EINT
0
GPIO9 interrupt.
(Trigger is controlled by GP9_INT_MODE)
Note: Cleared when a ‘1’ is written.
7
GP8_EINT
0
GPIO8 interrupt.
(Trigger is controlled by GP8_INT_MODE)
Note: Cleared when a ‘1’ is written.
6
GP7_EINT
0
GPIO7 interrupt.
(Trigger is controlled by GP7_INT_MODE)
Note: Cleared when a ‘1’ is written.
5
GP6_EINT
0
GPIO6 interrupt.
(Trigger is controlled by GP6_INT_MODE)
Note: Cleared when a ‘1’ is written.
4
GP5_EINT
0
GPIO5 interrupt.
(Trigger is controlled by GP5_INT_MODE)
Note: Cleared when a ‘1’ is written.
3
GP4_EINT
0
GPIO4 interrupt.
(Trigger is controlled by GP4_INT_MODE)
Note: Cleared when a ‘1’ is written.
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REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
2
GP3_EINT
0
GPIO3 interrupt.
(Trigger is controlled by GP3_INT_MODE)
Note: Cleared when a ‘1’ is written.
1
GP2_EINT
0
GPIO2 interrupt.
(Trigger is controlled by GP2_INT_MODE)
Note: Cleared when a ‘1’ is written.
0
GP1_EINT
0
GPIO1 interrupt.
(Trigger is controlled by GP1_INT_MODE)
Note: Cleared when a ‘1’ is written.
Register 4015h Interrupt Status 5
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16407
(4017h) IRQ
Config
1
IRQ_OD
1
IRQ pin configuration
0 = CMOS
1 = Open Drain (integrated pull-up)
0
IM_IRQ
0
IRQ pin output mask
0 = Normal
1 = IRQ output is masked
Register 4017h IRQ Config
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16408
(4018h)
System
Interrupts
Mask
15
IM_PS_INT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
14
IM_TEMP_INT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
13
IM_GP_INT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
12
IM_ON_PIN_IN
T
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
11
IM_WDOG_INT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
8
IM_AUXADC_I
NT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
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REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
7
IM_PPM_INT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
6
IM_CS_INT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
5
IM_RTC_INT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
4
IM_OTP_INT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
2
IM_CHG_INT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
1
IM_HC_INT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
0
IM_UV_INT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Register 4018h System Interrupts Mask
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16409
(4019h)
Interrupt
Status 1
Mask
15
IM_PPM_SYSL
O_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
14
IM_PPM_PWR
_SRC_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
13
IM_PPM_USB_
CURR_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
12
IM_ON_PIN_CI
NT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
11
IM_WDOG_TO
_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
8
IM_AUXADC_
DATA_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
7
IM_AUXADC_
DCOMP4_EIN
T
1
IM_AUXADC_
DCOMP3_EIN
T
1
IM_AUXADC_
DCOMP2_EIN
T
1
IM_AUXADC_
DCOMP1_EIN
T
1
IM_RTC_PER_
EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
6
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
5
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
4
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
3
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
2
IM_RTC_ALM_
EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
1
IM_TEMP_TH
W_CINT
1
Default value is 1 (masked)
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Register 4019h Interrupt Status 1 Mask
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16410
(401Ah)
Interrupt
Status 2
Mask
15
IM_CHG_BATT
_HOT_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
14
IM_CHG_BATT
_COLD_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
13
IM_CHG_BATT
_FAIL_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
12
IM_CHG_OV_
EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
11
IM_CHG_END
_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
10
IM_CHG_TO_E
INT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
9
IM_CHG_MOD
E_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
8
IM_CHG_STA
RT_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
7
IM_CS2_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
6
IM_CS1_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
5
IM_OTP_CMD
_END_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
4
IM_OTP_ERR_
EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
2
IM_PS_POR_E
INT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
1
IM_PS_SLEEP
_OFF_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
0
IM_PS_ON_W
AKE_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Register 401Ah Interrupt Status 2 Mask
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16411
(401Bh)
Interrupt
Status 3
Mask
9
IM_UV_LDO10
_EINT
1
8
IM_UV_LDO9_
EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
7
IM_UV_LDO8_
EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
6
IM_UV_LDO7_
EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
5
IM_UV_LDO6_
EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
4
IM_UV_LDO5_
EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
3
IM_UV_LDO4_
EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
2
IM_UV_LDO3_
EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
1
IM_UV_LDO2_
EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
0
IM_UV_LDO1_
EINT
1
Default value is 1 (masked)
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Register 401Bh Interrupt Status 3 Mask
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16412
(401Ch)
Interrupt
Status 4
Mask
9
IM_HC_DC2_E
INT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
8
IM_HC_DC1_E
INT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
3
IM_UV_DC4_E
INT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
2
IM_UV_DC3_E
INT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
1
IM_UV_DC2_E
INT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
0
IM_UV_DC1_E
INT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Register 401Ch Interrupt Status 4 Mask
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16413
(401Dh)
Interrupt
Status 5
Mask
11
IM_GP12_EIN
T
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
10
IM_GP11_EIN
T
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
9
IM_GP10_EIN
T
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
8
IM_GP9_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
7
IM_GP8_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
6
IM_GP7_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
5
IM_GP6_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
4
IM_GP5_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
3
IM_GP4_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
2
IM_GP3_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
1
IM_GP2_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
0
IM_GP1_EINT
1
Interrupt mask.
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Register 401Dh Interrupt Status 5 Mask
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16416
(4020h)
RTC Write
Counter
15:0
RTC_WR_CNT 0000_0000 RTC Write Counter.
[15:0]
_0000_000 This random number is updated on every write to the
0
RTC_TIME registers.
Register 4020h RTC Write Counter
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16417
(4021h)
RTC Time 1
15:0
RTC_TIME
[15:0]
0000_0000 RTC Seconds counter (MSW)
_0000_000 RTC_TIME increments by 1 every second. This is the
0
16 MSBs.
Register 4021h RTC Time 1
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16418
(4022h)
RTC Time 2
15:0
RTC_TIME
[15:0]
0000_0000 RTC Seconds counter (LSW)
_0000_000 RTC_TIME increments by 1 every second. This is the
0
16 LSBs.
Register 4022h RTC Time 2
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16419
(4023h)
RTC Alarm
1
15:0
RTC_ALM
[15:0]
0000_0000 RTC Alarm time (MSW)
_0000_000 16 MSBs of RTC_ALM
0
Register 4023h RTC Alarm 1
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16420
(4024h)
RTC Alarm
2
15:0
RTC_ALM
[15:0]
0000_0000 RTC Alarm time (LSW)
_0000_000 16 LSBs of RTC_ALM
0
Register 4024h RTC Alarm 2
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16421
(4025h)
RTC Control
15
RTC_VALID
0
RTC Valid status
0 = RTC_TIME has not been set since Power On Reset
1 = RTC_TIME has been written to since Power On
Reset
14
RTC_SYNC_B
USY
0
RTC Busy status
0 = Normal
1 = Busy
The RTC registers should not be written to when
RTC_SYNC_BUSY = 1.
10
RTC_ALM_EN
A
0
RTC_PINT_FR
EQ [2:0]
000
RTC Alarm Enable
0 = Disabled
1 = Enabled
6:4
RTC Periodic Interrupt timeout period
000 = Disabled
001 = 2s
010 = 4s
011 = 8s
100 = 16s
101 = 32s
110 = 64s
111 = 128s
Register 4025h RTC Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16422
(4026h)
RTC Trim
9:0
RTC_TRIM
[9:0]
00_0000_0 RTC frequency trim. Value is a 10bit fixed point <4,6>
000
2's complement number. MSB Scaling = -8Hz.
The register indicates the error (in Hz) with respect to
the ideal 32768Hz) of the input crystal frequency.
Protected by security key.
Register 4026h RTC Trim
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16429
(402Dh)
AuxADC
Data
15:12
AUX_DATA_S
RC [3:0]
0000
AUXADC Data Source
0 = Reserved
1 = AUXADCIN1
2 = AUXADCIN2
3 = AUXADCIN3
4 = AUXADCIN4
5 = Chip Temperature
6 = Battery Temperature
7 = SYSVDD voltage
8 = USB voltage
9 = BATT voltage
10 = WALL voltage
11 = Reserved
12 = Reserved
13 = Reserved
14 = Reserved
15 = Reserved
11:0
AUX_DATA
[11:0]
0000_0000 AUXADC Measurement Data
_0000
Voltage (mV) = AUX_DATA x 1.465
ChipTemp (°C) = (498 - AUX_DATA) / 1.09
BattTemp (°C) = (value is dependent on NTC
thermistor)
Register 402Dh AuxADC Data
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16430
(402Eh)
AuxADC
Control
15
AUX_ENA
0
AUXADC Enable
0 = Disabled
1 = Enabled
Note - this bit is reset to 0 when the OFF power state is
entered.
14
AUX_CVT_EN
A
0
AUXADC Conversion Enable
0 = Disabled
1 = Enabled
In automatic mode, conversions are enabled by setting
this bit.
In manual mode (AUX_RATE = 0), setting this bit will
initiate a conversion; the bit is reset automatically after
each conversion.
12
AUX_SLPENA
0
AUXADC SLEEP Enable
0 = Disabled
1 = Controlled by AUX_ENA
5:0
AUX_RATE
[5:0]
00_0000
AUXADC Conversion Rate
0 = Manual
1 = 2 samples/s
2 = 4 samples/s
3 = 6 samples/s
…
31 = 62 samples/s
32 = Reserved
33 = 16 samples/s
34 = 32 samples/s
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
35 = 48 samples/s
…
63 = 496 samples/s
Register 402Eh AuxADC Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16431
(402Fh)
AuxADC
Source
9
AUX_WALL_S
EL
0
AUX_BATT_S
EL
0
AUXADC WALL input select
0 = Disable WALLVDD measurement
1 = Enable WALLVDD measurement
8
AUXADC BATT input select
0 = Disable BATTVDD measurement
1 = Enable BATTVDD measurement
7
AUX_USB_SE
L
0
AUX_SYSVDD
_SEL
0
AUX_BATT_TE
MP_SEL
0
AUX_CHIP_TE
MP_SEL
0
AUX_AUX4_S
EL
0
AUX_AUX3_S
EL
0
AUXADC USB input select
0 = Disable USBVDD measurement
1 = Enable USBVDD measurement
6
AUXADC SYSVDD input select
0 = Disable SYSVDD measurement
1 = Enable SYSVDD measurement
5
AUXADC Battery Temp input select
0 = Disable Battery Temp measurement
1 = Enable Battery Temp measurement
4
AUXADC Chip Temp input select
0 = Disable Chip Temp measurement
1 = Enable Chip Temp measurement
3
AUXADCIN4 input select
0 = Disable AUXADCIN4 measurement
1 = Enable AUXADCIN4 measurement
2
AUXADCIN3 input select
0 = Disable AUXADCIN3 measurement
1 = Enable AUXADCIN3 measurement
1
AUX_AUX2_S
EL
0
AUX_AUX1_S
EL
0
AUXADCIN2 input select
0 = Disable AUXADCIN2 measurement
1 = Enable AUXADCIN2 measurement
0
AUXADCIN1 input select
0 = Disable AUXADCIN1 measurement
1 = Enable AUXADCIN1 measurement
Register 402Fh AuxADC Source
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16432
(4030h)
Comparator
Control
11
DCOMP4_STS
0
Digital Comparator 4 status
0 = Comparator 4 threshold not detected
1 = Comparator 4 threshold detected
(Trigger is controlled by DCMP4_GT)
10
DCOMP3_STS
0
Digital Comparator 3 status
0 = Comparator 3 threshold not detected
1 = Comparator 3 threshold detected
(Trigger is controlled by DCMP3_GT)
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
9
DCOMP2_STS
0
Digital Comparator 2 status
0 = Comparator 2 threshold not detected
1 = Comparator 2 threshold detected
(Trigger is controlled by DCMP2_GT)
8
DCOMP1_STS
0
Digital Comparator 1 status
0 = Comparator 1 threshold not detected
1 = Comparator 1 threshold detected
(Trigger is controlled by DCMP1_GT)
3
DCMP4_ENA
0
Digital Comparator 4 Enable
0 = Disabled
1 = Enabled
2
DCMP3_ENA
0
Digital Comparator 3 Enable
0 = Disabled
1 = Enabled
1
DCMP2_ENA
0
Digital Comparator 2 Enable
0 = Disabled
1 = Enabled
0
DCMP1_ENA
0
Digital Comparator 1 Enable
0 = Disabled
1 = Enabled
Register 4030h Comparator Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16433
(4031h)
Comparator
1
15:13
DCMP1_SRC
[2:0]
000
Digital Comparator 1 source select
0 = USB voltage
1 = AUXADCIN1
2 = AUXADCIN2
3 = AUXADCIN3
4 = AUXADCIN4
5 = Chip Temperature
6 = Battery Temperature
7 = SYSVDD voltage
12
DCMP1_GT
0
Digital Comparator 1 interrupt control
0 = interrupt when less than threshold
1 = interrupt when greater than threshold
11:0
DCMP1_THR
[11:0]
0000_0000 Digital Comparator 1 threshold
_0000
(12-bit unsigned binary number; coding is the same as
AUX_DATA)
Register 4031h Comparator 1
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16434
(4032h)
Comparator
2
15:13
DCMP2_SRC
[2:0]
000
Digital Comparator 2 source select
0 = WALL voltage
1 = AUXADCIN1
2 = AUXADCIN2
3 = AUXADCIN3
4 = AUXADCIN4
5 = Chip Temperature
6 = Battery Temperature
7 = SYSVDD voltage
12
DCMP2_GT
0
Digital Comparator 2 interrupt control
0 = interrupt when less than threshold
1 = interrupt when greater than threshold
11:0
DCMP2_THR
[11:0]
0000_0000 Digital Comparator 2 threshold
_0000
(12-bit unsigned binary number; coding is the same as
AUX_DATA)
Register 4032h Comparator 2
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16435
(4033h)
Comparator
3
15:13
DCMP3_SRC
[2:0]
000
Digital Comparator 3 source select
0 = BATT voltage
1 = AUXADCIN1
2 = AUXADCIN2
3 = AUXADCIN3
4 = AUXADCIN4
5 = Chip Temperature
6 = Battery Temperature
7 = SYSVDD voltage
12
DCMP3_GT
0
Digital Comparator 3 interrupt control
0 = interrupt when less than threshold
1 = interrupt when greater than threshold
11:0
DCMP3_THR
[11:0]
0000_0000 Digital Comparator 3 threshold
_0000
(12-bit unsigned binary number; coding is the same as
AUX_DATA)
Register 4033h Comparator 3
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16436
(4034h)
Comparator
4
15:13
DCMP4_SRC
[2:0]
000
Digital Comparator 4 source select
0 = Reserved
1 = AUXADCIN1
2 = AUXADCIN2
3 = AUXADCIN3
4 = AUXADCIN4
5 = Chip Temperature
6 = Battery Temperature
7 = SYSVDD voltage
12
DCMP4_GT
0
Digital Comparator 4 interrupt control
0 = interrupt when less than threshold
1 = interrupt when greater than threshold
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
11:0
DCMP4_THR
[11:0]
0000_0000 Digital Comparator 4 threshold
_0000
(12-bit unsigned binary number; coding is the same as
AUX_DATA)
Register 4034h Comparator 4
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16440
(4038h)
GPIO1
Control
15
GP1_DIR
1
GPIO1 pin direction
0 = Output
1 = Input
14:13
GP1_PULL
[1:0]
01
GPIO1 Pull-Up / Pull-Down configuration
00 = No pull resistor
01 = Pull-down enabled
10 = Pull-up enabled
11 = Reserved
12
GP1_INT_MOD
E
0
GPIO1 Interrupt Mode
0 = GPIO interrupt is rising edge triggered (if
GP1_POL=1) or falling edge triggered (if GP1_POL=0)
1 = GPIO interrupt is triggered on rising and falling
edges
11
GP1_PWR_DO
M
0
GP1_POL
1
GPIO1 Power Domain select
0 = DBVDD
1 = PMICVDD (LDO12)
10
GPIO1 Polarity select
0 = Inverted (active low)
1 = Non-Inverted (active high)
9
GP1_OD
0
GPIO1 Output pin configuration
0 = CMOS
1 = Open Drain
7
GP1_ENA
0
GPIO1 Enable control
0 = GPIO pin is tri-stated
1 = Normal operation
3:0
GP1_FN [3:0]
0000
GPIO1 Pin Function
Input functions:
0 = GPIO input (long de-bounce)
1 = GPIO input
2 = Power On/Off request
3 = Sleep/Wake request
4 = Sleep/Wake request (long de-bounce)
5 = Sleep request
6 = Power On request
7 = Watchdog Reset input
8 = DVS1 input
9 = DVS2 input
10 = HW Enable1 input
11 = HW Enable2 input
12 = HW Control1 input
13 = HW Control2 input
14 = HW Control1 input (long de-bounce)
15 = HW Control2 input (long de-bounce)
Output functions:
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WM8310
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REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
0 = GPIO output
1 = 32.768kHz oscillator output
2 = ON state
3 = SLEEP state
4 = Power State Change
5 = Reserved
6 = Reserved
7 = Reserved
8 = DC-DC1 DVS Done
9 = DC-DC2 DVS Done
10 = External Power Enable1
11 = External Power Enable2
12 = System Supply Good (SYSOK)
13 = Converter Power Good (PWR_GOOD)
14 = External Power Clock (2MHz)
15 = Auxiliary Reset
Register 4038h GPIO1 Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16441
(4039h)
GPIO2
Control
15
GP2_DIR
1
GPIO2 pin direction
0 = Output
1 = Input
14:13
GP2_PULL
[1:0]
01
GPIO2 Pull-Up / Pull-Down configuration
00 = No pull resistor
01 = Pull-down enabled
10 = Pull-up enabled
11 = Reserved
12
GP2_INT_MOD
E
0
GPIO2 Interrupt Mode
0 = GPIO interrupt is rising edge triggered (if
GP2_POL=1) or falling edge triggered (if GP2_POL=0)
1 = GPIO interrupt is triggered on rising and falling
edges
11
GP2_PWR_DO
M
0
GP2_POL
1
GPIO2 Power Domain select
0 = DBVDD
1 = PMICVDD (LDO12)
10
GPIO2 Polarity select
0 = Inverted (active low)
1 = Non-Inverted (active high)
9
GP2_OD
0
GPIO2 Output pin configuration
0 = CMOS
1 = Open Drain
7
GP2_ENA
0
GPIO2 Enable control
0 = GPIO pin is tri-stated
1 = Normal operation
3:0
GP2_FN [3:0]
0000
GPIO2 Pin Function
Input functions:
0 = GPIO input (long de-bounce)
1 = GPIO input
2 = Power On/Off request
3 = Sleep/Wake request
4 = Sleep/Wake request (long de-bounce)
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
5 = Sleep request
6 = Power On request
7 = Watchdog Reset input
8 = DVS1 input
9 = DVS2 input
10 = HW Enable1 input
11 = HW Enable2 input
12 = HW Control1 input
13 = HW Control2 input
14 = HW Control1 input (long de-bounce)
15 = HW Control2 input (long de-bounce)
Output functions:
0 = GPIO output
1 = 32.768kHz oscillator output
2 = ON state
3 = SLEEP state
4 = Power State Change
5 = Reserved
6 = Reserved
7 = Reserved
8 = DC-DC1 DVS Done
9 = DC-DC2 DVS Done
10 = External Power Enable1
11 = External Power Enable2
12 = System Supply Good (SYSOK)
13 = Converter Power Good (PWR_GOOD)
14 = External Power Clock (2MHz)
15 = Auxiliary Reset
Register 4039h GPIO2 Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16442
(403Ah)
GPIO3
Control
15
GP3_DIR
1
GPIO3 pin direction
0 = Output
1 = Input
14:13
GP3_PULL
[1:0]
01
GPIO3 Pull-Up / Pull-Down configuration
00 = No pull resistor
01 = Pull-down enabled
10 = Pull-up enabled
11 = Reserved
12
GP3_INT_MOD
E
0
GPIO3 Interrupt Mode
0 = GPIO interrupt is rising edge triggered (if
GP3_POL=1) or falling edge triggered (if GP3_POL=0)
1 = GPIO interrupt is triggered on rising and falling
edges
11
GP3_PWR_DO
M
0
GP3_POL
1
GPIO3 Power Domain select
0 = DBVDD
1 = PMICVDD (LDO12)
10
GPIO3 Polarity select
0 = Inverted (active low)
1 = Non-Inverted (active high)
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
9
GP3_OD
0
GPIO3 Output pin configuration
0 = CMOS
1 = Open Drain
7
GP3_ENA
0
GPIO3 Enable control
0 = GPIO pin is tri-stated
1 = Normal operation
3:0
GP3_FN [3:0]
0000
GPIO3 Pin Function
Input functions:
0 = GPIO input (long de-bounce)
1 = GPIO input
2 = Power On/Off request
3 = Sleep/Wake request
4 = Sleep/Wake request (long de-bounce)
5 = Sleep request
6 = Power On request
7 = Watchdog Reset input
8 = DVS1 input
9 = DVS2 input
10 = HW Enable1 input
11 = HW Enable2 input
12 = HW Control1 input
13 = HW Control2 input
14 = HW Control1 input (long de-bounce)
15 = HW Control2 input (long de-bounce)
Output functions:
0 = GPIO output
1 = 32.768kHz oscillator output
2 = ON state
3 = SLEEP state
4 = Power State Change
5 = Reserved
6 = Reserved
7 = Reserved
8 = DC-DC1 DVS Done
9 = DC-DC2 DVS Done
10 = External Power Enable1
11 = External Power Enable2
12 = System Supply Good (SYSOK)
13 = Converter Power Good (PWR_GOOD)
14 = External Power Clock (2MHz)
15 = Auxiliary Reset
Register 403Ah GPIO3 Control
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199
WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16443
(403Bh)
GPIO4
Control
15
GP4_DIR
1
GPIO4 pin direction
0 = Output
1 = Input
14:13
GP4_PULL
[1:0]
01
GPIO4 Pull-Up / Pull-Down configuration
00 = No pull resistor
01 = Pull-down enabled
10 = Pull-up enabled
11 = Reserved
12
GP4_INT_MOD
E
0
GPIO4 Interrupt Mode
0 = GPIO interrupt is rising edge triggered (if
GP4_POL=1) or falling edge triggered (if GP4_POL=0)
1 = GPIO interrupt is triggered on rising and falling
edges
11
GP4_PWR_DO
M
0
GP4_POL
1
GPIO4 Power Domain select
0 = DBVDD
1 = SYSVDD
10
GPIO4 Polarity select
0 = Inverted (active low)
1 = Non-Inverted (active high)
9
GP4_OD
0
GPIO4 Output pin configuration
0 = CMOS
1 = Open Drain
7
GP4_ENA
0
GPIO4 Enable control
0 = GPIO pin is tri-stated
1 = Normal operation
3:0
GP4_FN [3:0]
0000
GPIO4 Pin Function
Input functions:
0 = GPIO input (long de-bounce)
1 = GPIO input
2 = Power On/Off request
3 = Sleep/Wake request
4 = Sleep/Wake request (long de-bounce)
5 = Sleep request
6 = Power On request
7 = Watchdog Reset input
8 = DVS1 input
9 = DVS2 input
10 = HW Enable1 input
11 = HW Enable2 input
12 = HW Control1 input
13 = HW Control2 input
14 = HW Control1 input (long de-bounce)
15 = HW Control2 input (long de-bounce)
Output functions:
0 = GPIO output
1 = 32.768kHz oscillator output
2 = ON state
3 = SLEEP state
4 = Power State Change
5 = Reserved
6 = Reserved
7 = Reserved
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
8 = DC-DC1 DVS Done
9 = DC-DC2 DVS Done
10 = External Power Enable1
11 = External Power Enable2
12 = System Supply Good (SYSOK)
13 = Converter Power Good (PWR_GOOD)
14 = External Power Clock (2MHz)
15 = Auxiliary Reset
Register 403Bh GPIO4 Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16444
(403Ch)
GPIO5
Control
15
GP5_DIR
1
GPIO5 pin direction
0 = Output
1 = Input
14:13
GP5_PULL
[1:0]
01
GPIO5 Pull-Up / Pull-Down configuration
00 = No pull resistor
01 = Pull-down enabled
10 = Pull-up enabled
11 = Reserved
12
GP5_INT_MOD
E
0
GPIO5 Interrupt Mode
0 = GPIO interrupt is rising edge triggered (if
GP5_POL=1) or falling edge triggered (if GP5_POL=0)
1 = GPIO interrupt is triggered on rising and falling
edges
11
GP5_PWR_DO
M
0
GP5_POL
1
GPIO5 Power Domain select
0 = DBVDD
1 = SYSVDD
10
GPIO5 Polarity select
0 = Inverted (active low)
1 = Non-Inverted (active high)
9
GP5_OD
0
GPIO5 Output pin configuration
0 = CMOS
1 = Open Drain
7
GP5_ENA
0
GPIO5 Enable control
0 = GPIO pin is tri-stated
1 = Normal operation
3:0
GP5_FN [3:0]
0000
GPIO5 Pin Function
Input functions:
0 = GPIO input (long de-bounce)
1 = GPIO input
2 = Power On/Off request
3 = Sleep/Wake request
4 = Sleep/Wake request (long de-bounce)
5 = Sleep request
6 = Power On request
7 = Watchdog Reset input
8 = DVS1 input
9 = DVS2 input
10 = HW Enable1 input
11 = HW Enable2 input
12 = HW Control1 input
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
13 = HW Control2 input
14 = HW Control1 input (long de-bounce)
15 = HW Control2 input (long de-bounce)
Output functions:
0 = GPIO output
1 = 32.768kHz oscillator output
2 = ON state
3 = SLEEP state
4 = Power State Change
5 = Reserved
6 = Reserved
7 = Reserved
8 = DC-DC1 DVS Done
9 = DC-DC2 DVS Done
10 = External Power Enable1
11 = External Power Enable2
12 = System Supply Good (SYSOK)
13 = Converter Power Good (PWR_GOOD)
14 = External Power Clock (2MHz)
15 = Auxiliary Reset
Register 403Ch GPIO5 Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16445
(403Dh)
GPIO6
Control
15
GP6_DIR
1
GPIO6 pin direction
0 = Output
1 = Input
14:13
GP6_PULL
[1:0]
01
GPIO6 Pull-Up / Pull-Down configuration
00 = No pull resistor
01 = Pull-down enabled
10 = Pull-up enabled
11 = Reserved
12
GP6_INT_MOD
E
0
GPIO6 Interrupt Mode
0 = GPIO interrupt is rising edge triggered (if
GP6_POL=1) or falling edge triggered (if GP6_POL=0)
1 = GPIO interrupt is triggered on rising and falling
edges
11
GP6_PWR_DO
M
0
GP6_POL
1
GPIO6 Power Domain select
0 = DBVDD
1 = SYSVDD
10
GPIO6 Polarity select
0 = Inverted (active low)
1 = Non-Inverted (active high)
9
GP6_OD
0
GPIO6 Output pin configuration
0 = CMOS
1 = Open Drain
7
GP6_ENA
1
GPIO6 Enable control
0 = GPIO pin is tri-stated
1 = Normal operation
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
3:0
GP6_FN [3:0]
0000
GPIO6 Pin Function
Input functions:
0 = GPIO input (long de-bounce)
1 = GPIO input
2 = Power On/Off request
3 = Sleep/Wake request
4 = Sleep/Wake request (long de-bounce)
5 = Sleep request
6 = Power On request
7 = Watchdog Reset input
8 = DVS1 input
9 = DVS2 input
10 = HW Enable1 input
11 = HW Enable2 input
12 = HW Control1 input
13 = HW Control2 input
14 = HW Control1 input (long de-bounce)
15 = HW Control2 input (long de-bounce)
Output functions:
0 = GPIO output
1 = 32.768kHz oscillator output
2 = ON state
3 = SLEEP state
4 = Power State Change
5 = Reserved
6 = Reserved
7 = Reserved
8 = DC-DC1 DVS Done
9 = DC-DC2 DVS Done
10 = External Power Enable1
11 = External Power Enable2
12 = System Supply Good (SYSOK)
13 = Converter Power Good (PWR_GOOD)
14 = External Power Clock (2MHz)
15 = Auxiliary Reset
Register 403Dh GPIO6 Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16446
(403Eh)
GPIO7
Control
15
GP7_DIR
1
GPIO7 pin direction
0 = Output
1 = Input
14:13
GP7_PULL
[1:0]
01
GPIO7 Pull-Up / Pull-Down configuration
00 = No pull resistor
01 = Pull-down enabled
10 = Pull-up enabled
11 = Reserved
12
GP7_INT_MOD
E
0
GPIO7 Interrupt Mode
0 = GPIO interrupt is rising edge triggered (if
GP7_POL=1) or falling edge triggered (if GP7_POL=0)
1 = GPIO interrupt is triggered on rising and falling
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
edges
11
GP7_PWR_DO
M
0
GP7_POL
1
GPIO7 Power Domain select
0 = DBVDD
1 = PMICVDD (LDO12)
10
GPIO7 Polarity select
0 = Inverted (active low)
1 = Non-Inverted (active high)
9
GP7_OD
0
GPIO7 Output pin configuration
0 = CMOS
1 = Open Drain
7
GP7_ENA
0
GPIO7 Enable control
0 = GPIO pin is tri-stated
1 = Normal operation
3:0
GP7_FN [3:0]
0000
GPIO7 Pin Function
Input functions:
0 = GPIO input (long de-bounce)
1 = GPIO input
2 = Power On/Off request
3 = Sleep/Wake request
4 = Sleep/Wake request (long de-bounce)
5 = Sleep request
6 = Power On request
7 = Watchdog Reset input
8 = DVS1 input
9 = DVS2 input
10 = HW Enable1 input
11 = HW Enable2 input
12 = HW Control1 input
13 = HW Control2 input
14 = HW Control1 input (long de-bounce)
15 = HW Control2 input (long de-bounce)
Output functions:
0 = GPIO output
1 = 32.768kHz oscillator output
2 = ON state
3 = SLEEP state
4 = Power State Change
5 = Reserved
6 = Reserved
7 = Reserved
8 = DC-DC1 DVS Done
9 = DC-DC2 DVS Done
10 = External Power Enable1
11 = External Power Enable2
12 = System Supply Good (SYSOK)
13 = Converter Power Good (PWR_GOOD)
14 = External Power Clock (2MHz)
15 = Auxiliary Reset
Register 403Eh GPIO7 Control
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16447
(403Fh)
GPIO8
Control
15
GP8_DIR
1
GPIO8 pin direction
0 = Output
1 = Input
14:13
GP8_PULL
[1:0]
01
GPIO8 Pull-Up / Pull-Down configuration
00 = No pull resistor
01 = Pull-down enabled
10 = Pull-up enabled
11 = Reserved
12
GP8_INT_MOD
E
0
GPIO8 Interrupt Mode
0 = GPIO interrupt is rising edge triggered (if
GP8_POL=1) or falling edge triggered (if GP8_POL=0)
1 = GPIO interrupt is triggered on rising and falling
edges
11
GP8_PWR_DO
M
0
GP8_POL
1
GPIO8 Power Domain select
0 = DBVDD
1 = PMICVDD (LDO12)
10
GPIO8 Polarity select
0 = Inverted (active low)
1 = Non-Inverted (active high)
9
GP8_OD
0
GPIO8 Output pin configuration
0 = CMOS
1 = Open Drain
7
GP8_ENA
1
GPIO8 Enable control
0 = GPIO pin is tri-stated
1 = Normal operation
3:0
GP8_FN [3:0]
0000
GPIO8 Pin Function
Input functions:
0 = GPIO input (long de-bounce)
1 = GPIO input
2 = Power On/Off request
3 = Sleep/Wake request
4 = Sleep/Wake request (long de-bounce)
5 = Sleep request
6 = Power On request
7 = Watchdog Reset input
8 = DVS1 input
9 = DVS2 input
10 = HW Enable1 input
11 = HW Enable2 input
12 = HW Control1 input
13 = HW Control2 input
14 = HW Control1 input (long de-bounce)
15 = HW Control2 input (long de-bounce)
Output functions:
0 = GPIO output
1 = 32.768kHz oscillator output
2 = ON state
3 = SLEEP state
4 = Power State Change
5 = Reserved
6 = Reserved
7 = Reserved
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
8 = DC-DC1 DVS Done
9 = DC-DC2 DVS Done
10 = External Power Enable1
11 = External Power Enable2
12 = System Supply Good (SYSOK)
13 = Converter Power Good (PWR_GOOD)
14 = External Power Clock (2MHz)
15 = Auxiliary Reset
Register 403Fh GPIO8 Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16448
(4040h)
GPIO9
Control
15
GP9_DIR
1
GPIO9 pin direction
0 = Output
1 = Input
14:13
GP9_PULL
[1:0]
01
GPIO9 Pull-Up / Pull-Down configuration
00 = No pull resistor
01 = Pull-down enabled
10 = Pull-up enabled
11 = Reserved
12
GP9_INT_MOD
E
0
GPIO9 Interrupt Mode
0 = GPIO interrupt is rising edge triggered (if
GP9_POL=1) or falling edge triggered (if GP9_POL=0)
1 = GPIO interrupt is triggered on rising and falling
edges
11
GP9_PWR_DO
M
0
GP9_POL
1
GPIO9 Power Domain select
0 = DBVDD
1 = PMICVDD (LDO12)
10
GPIO9 Polarity select
0 = Inverted (active low)
1 = Non-Inverted (active high)
9
GP9_OD
0
GPIO9 Output pin configuration
0 = CMOS
1 = Open Drain
7
GP9_ENA
0
GPIO9 Enable control
0 = GPIO pin is tri-stated
1 = Normal operation
3:0
GP9_FN [3:0]
0000
GPIO9 Pin Function
Input functions:
0 = GPIO input (long de-bounce)
1 = GPIO input
2 = Power On/Off request
3 = Sleep/Wake request
4 = Sleep/Wake request (long de-bounce)
5 = Sleep request
6 = Power On request
7 = Watchdog Reset input
8 = DVS1 input
9 = DVS2 input
10 = HW Enable1 input
11 = HW Enable2 input
12 = HW Control1 input
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
13 = HW Control2 input
14 = HW Control1 input (long de-bounce)
15 = HW Control2 input (long de-bounce)
Output functions:
0 = GPIO output
1 = 32.768kHz oscillator output
2 = ON state
3 = SLEEP state
4 = Power State Change
5 = Reserved
6 = Reserved
7 = Reserved
8 = DC-DC1 DVS Done
9 = DC-DC2 DVS Done
10 = External Power Enable1
11 = External Power Enable2
12 = System Supply Good (SYSOK)
13 = Converter Power Good (PWR_GOOD)
14 = External Power Clock (2MHz)
15 = Auxiliary Reset
Register 4040h GPIO9 Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16449
(4041h)
GPIO10
Control
15
GP10_DIR
1
GPIO10 pin direction
0 = Output
1 = Input
14:13
GP10_PULL
[1:0]
01
GPIO10 Pull-Up / Pull-Down configuration
00 = No pull resistor
01 = Pull-down enabled
10 = Pull-up enabled
11 = Reserved
12
GP10_INT_MO
DE
0
GPIO10 Interrupt Mode
0 = GPIO interrupt is rising edge triggered (if
GP10_POL=1) or falling edge triggered (if
GP10_POL=0)
1 = GPIO interrupt is triggered on rising and falling
edges
11
GP10_PWR_D
OM
0
GP10_POL
1
GPIO10 Power Domain select
0 = DBVDD
1 = SYSVDD
10
GPIO10 Polarity select
0 = Inverted (active low)
1 = Non-Inverted (active high)
9
GP10_OD
0
GPIO10 Output pin configuration
0 = CMOS
1 = Open Drain
7
GP10_ENA
0
GPIO10 Enable control
0 = GPIO pin is tri-stated
1 = Normal operation
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
3:0
GP10_FN [3:0]
0000
GPIO10 Pin Function
Input functions:
0 = GPIO input (long de-bounce)
1 = GPIO input
2 = Power On/Off request
3 = Sleep/Wake request
4 = Sleep/Wake request (long de-bounce)
5 = Sleep request
6 = Power On request
7 = Watchdog Reset input
8 = DVS1 input
9 = DVS2 input
10 = HW Enable1 input
11 = HW Enable2 input
12 = HW Control1 input
13 = HW Control2 input
14 = HW Control1 input (long de-bounce)
15 = HW Control2 input (long de-bounce)
Output functions:
0 = GPIO output
1 = 32.768kHz oscillator output
2 = ON state
3 = SLEEP state
4 = Power State Change
5 = Reserved
6 = Reserved
7 = Reserved
8 = DC-DC1 DVS Done
9 = DC-DC2 DVS Done
10 = External Power Enable1
11 = External Power Enable2
12 = System Supply Good (SYSOK)
13 = Converter Power Good (PWR_GOOD)
14 = External Power Clock (2MHz)
15 = Auxiliary Reset
Register 4041h GPIO10 Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16450
(4042h)
GPIO11
Control
15
GP11_DIR
1
GPIO11 pin direction
0 = Output
1 = Input
14:13
GP11_PULL
[1:0]
01
GPIO11 Pull-Up / Pull-Down configuration
00 = No pull resistor
01 = Pull-down enabled
10 = Pull-up enabled
11 = Reserved
12
GP11_INT_MO
DE
w
0
GPIO11 Interrupt Mode
0 = GPIO interrupt is rising edge triggered (if
GP11_POL=1) or falling edge triggered (if
GP11_POL=0)
PP, May 2012, Rev 3.1
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
1 = GPIO interrupt is triggered on rising and falling
edges
11
GP11_PWR_D
OM
0
GP11_POL
1
GPIO11 Power Domain select
0 = DBVDD
1 = SYSVDD
10
GPIO11 Polarity select
0 = Inverted (active low)
1 = Non-Inverted (active high)
9
GP11_OD
0
GPIO11 Output pin configuration
0 = CMOS
1 = Open Drain
7
GP11_ENA
0
GPIO11 Enable control
0 = GPIO pin is tri-stated
1 = Normal operation
3:0
GP11_FN [3:0]
0000
GPIO11 Pin Function
Input functions:
0 = GPIO input (long de-bounce)
1 = GPIO input
2 = Power On/Off request
3 = Sleep/Wake request
4 = Sleep/Wake request (long de-bounce)
5 = Sleep request
6 = Power On request
7 = Watchdog Reset input
8 = DVS1 input
9 = DVS2 input
10 = HW Enable1 input
11 = HW Enable2 input
12 = HW Control1 input
13 = HW Control2 input
14 = HW Control1 input (long de-bounce)
15 = HW Control2 input (long de-bounce)
Output functions:
0 = GPIO output
1 = 32.768kHz oscillator output
2 = ON state
3 = SLEEP state
4 = Power State Change
5 = Reserved
6 = Reserved
7 = Reserved
8 = DC-DC1 DVS Done
9 = DC-DC2 DVS Done
10 = External Power Enable1
11 = External Power Enable2
12 = System Supply Good (SYSOK)
13 = Converter Power Good (PWR_GOOD)
14 = External Power Clock (2MHz)
15 = Auxiliary Reset
Register 4042h GPIO11 Control
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16451
(4043h)
GPIO12
Control
15
GP12_DIR
1
GPIO12 pin direction
0 = Output
1 = Input
14:13
GP12_PULL
[1:0]
01
GPIO12 Pull-Up / Pull-Down configuration
00 = No pull resistor
01 = Pull-down enabled
10 = Pull-up enabled
11 = Reserved
12
GP12_INT_MO
DE
0
GPIO12 Interrupt Mode
0 = GPIO interrupt is rising edge triggered (if
GP12_POL=1) or falling edge triggered (if
GP12_POL=0)
1 = GPIO interrupt is triggered on rising and falling
edges
11
GP12_PWR_D
OM
0
GPIO12 Power Domain select
0 = DBVDD
1 = SYSVDD
10
GP12_POL
1
GPIO12 Polarity select
0 = Inverted (active low)
1 = Non-Inverted (active high)
9
GP12_OD
0
GPIO12 Output pin configuration
0 = CMOS
1 = Open Drain
7
GP12_ENA
0
GPIO12 Enable control
0 = GPIO pin is tri-stated
1 = Normal operation
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
3:0
GP12_FN [3:0]
0000
GPIO12 Pin Function
Input functions:
0 = GPIO input (long de-bounce)
1 = GPIO input
2 = Power On/Off request
3 = Sleep/Wake request
4 = Sleep/Wake request (long de-bounce)
5 = Sleep request
6 = Power On request
7 = Watchdog Reset input
8 = DVS1 input
9 = DVS2 input
10 = HW Enable1 input
11 = HW Enable2 input
12 = HW Control1 input
13 = HW Control2 input
14 = HW Control1 input (long de-bounce)
15 = HW Control2 input (long de-bounce)
Output functions:
0 = GPIO output
1 = 32.768kHz oscillator output
2 = ON state
3 = SLEEP state
4 = Power State Change
5 = Reserved
6 = Reserved
7 = Reserved
8 = DC-DC1 DVS Done
9 = DC-DC2 DVS Done
10 = External Power Enable1
11 = External Power Enable2
12 = System Supply Good (SYSOK)
13 = Converter Power Good (PWR_GOOD)
14 = External Power Clock (2MHz)
15 = Auxiliary Reset
Register 4043h GPIO12 Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16456
(4048h)
Charger
Control 1
15
CHG_ENA
0
Battery Charger Enable
0 = Disable
1 = Enable
Protected by security key.
14
CHG_FRC
0
Force charging
0 = Normal behaviour
1 = Force charging
CHG_FRC enables charging even if the battery voltage
is above the restart threshold.
It is not recommended to use this feature; there are
safety implications in its use.
This bit should be reset to 0 after charging has started.
Host processor should monitor CHG_MODE_EINT to
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
confirm that charging has started.
Protected by security key.
12:10
CHG_ITERM
[2:0]
000
Battery End of Charge current threshold
000 = 20mA
001 = 30mA
010 = 40mA
011 = 50mA
100 = 60mA
101 = 70mA
110 = 80mA
111 = 90mA
Protected by security key.
5
CHG_FAST
0
Battery Fast Charge Enable
0 = Disable
1 = Enable
Protected by security key.
1
CHG_IMON_E
NA
0
Enable battery charge current monitor at AUXADCIN1.
0 = Disabled
1 = Enabled
(Note - a resistor is required between AUXADCIN1 and
GND in order to measure the charge current using the
AUXADC. The recommended resistor value is 10k.)
Protected by security key.
0
CHG_CHIP_TE
MP_MON
1
Battery Charger Thermal warning select
0 = Thermal Warning is ignored
1 = Thermal Warning pauses Battery Charger
Protected by security key.
Register 4048h Charger Control 1
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16457
(4049h)
Charger
Control 2
14
CHG_OFF_MS
K
0
Battery Charger OFF mask select
0 = OFF requests not masked
1 = OFF requests masked during Charging
Protected by security key.
11:8
CHG_TIME
[3:0]
0110
Battery charger timeout
0000 = 60min
0001 = 90min
0010 = 120min
0011 = 150min
0100 = 180min
0101 = 210min
0110 = 240min
0111 = 270min
1000 = 300min
1001 = 330min
1010 = 360min
1011 = 390min
1100 = 420min
1101 = 450min
1110 = 480min
1111 = 510min
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
Protected by security key.
7:6
CHG_TRKL_ILI
M [1:0]
00
Battery Trickle Charge current limit
00 = 50mA
01 = 100mA
10 = 150mA
11 = 200mA
Protected by security key.
5:4
CHG_VSEL
[1:0]
00
Battery Charger target voltage
00 = 4.05V
01 = 4.10V
10 = 4.15V
11 = 4.20V
Note that incorrect setting of this register may lead to a
safety hazard condition.
Protected by security key.
3:0
CHG_FAST_ILI
M [3:0]
0010
Battery Fast Charge current limit
0000 = 0mA
0001 = 50mA
0010 = 100mA
0011 = 150mA
0100 = 200mA
0101 = 250mA
0110 = 300mA
0111 = 350mA
1000 = 400mA
1001 = 450mA
1010 = 500mA
1011 = 600mA
1100 = 700mA
1101 = 800mA
1110 = 900mA
1111 = 1000mA
Protected by security key.
Register 4049h Charger Control 2
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16458
(404Ah)
Charger
Status
15
BATT_OV_ST
S
0
CHG_STATE
[2:0]
000
Battery Overvoltage status
0 = Normal
1 = Battery Overvoltage
14:12
Battery Charger state
000 = Off
001 = Trickle Charge
010 = Fast Charge
011 = Trickle Charge overtemperature
100 = Fast Charge overtemperature
101 = Defective
110 = Reserved
111 = Reserved
11
BATT_HOT_ST
S
0
Battery Hot status
0 = Normal
1 = Battery Hot
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213
WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
10
BATT_COLD_
STS
0
9
CHG_TOPOFF
0
8
CHG_ACTIVE
0
Battery Cold status
0 = Normal
1 = Battery Cold
Battery Charger constant-voltage charge mode status
0 = Constant-voltage mode not active
1 = Constant-voltage mode is active
Battery Charger status
0 = Not charging
1 = Charging
7:0
CHG_TIME_EL 0000_0000 Battery charger elapsed time
APSED [7:0]
00h = 0min
01h = 2min
02h = 4min
03h = 6min
...
FFh = 510min
Register 404Ah Charger Status
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16460
(404Ch)
Status LED
1
15:14
LED1_SRC
[1:0]
11
LED1 Source
(Selects the LED1 function.)
00 = Off
01 = Power State Status
10 = Charger Status
11 = Manual Mode
Note - LED1 also indicates completion of OTP Auto
Program
9:8
LED1_MODE
[1:0]
00
LED1 Mode
(Controls LED1 in Manual Mode only.)
00 = Off
01 = Constant
10 = Continuous Pulsed
5:4
LED1_SEQ_LE
N [1:0]
10
3:2
LED1_DUR
[1:0]
01
11 = Pulsed Sequence
LED1 Pulse Sequence Length
(when LED1_MODE = Pulsed Sequence)
00 = 1 pulse
01 = 2 pulses
10 = 4 pulses
11 = 7 pulses
LED1 On time
(when LED1_MODE = Continuous Pulsed or Pulsed
Sequence)
00 = 1 second
01 = 250ms
10 = 125ms
1:0
LED1_DUTY_C
YC [1:0]
w
10
11 = 62.5ms
LED1 Duty Cycle (On:Off ratio)
(when LED1_MODE = Continuous Pulsed or Pulsed
Sequence)
00 = 1:1 (50% on)
01 = 1:2 (33.3% on)
10 = 1:3 (25% on)
PP, May 2012, Rev 3.1
214
WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
11 = 1:7 (12.5% on)
Register 404Ch Status LED 1
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16461
(404Dh)
Status LED
2
15:14
LED2_SRC
[1:0]
11
LED2 Source
(Selects the LED2 function.)
00 = Off
01 = Power State Status
10 = Charger Status
11 = Manual Mode
Note - LED2 also indicates an OTP Auto Program Error
condition
9:8
LED2_MODE
[1:0]
00
LED2 Mode
(Controls LED2 in Manual Mode only.)
00 = Off
01 = Constant
10 = Continuous Pulsed
11 = Pulsed Sequence
5:4
LED2_SEQ_LE
N [1:0]
10
LED2 Pulse Sequence Length
(when LED2_MODE = Pulsed Sequence)
00 = 1 pulse
01 = 2 pulses
10 = 4 pulses
11 = 7 pulses
3:2
LED2_DUR
[1:0]
01
LED2 On time
(when LED2_MODE = Continuous Pulsed or Pulsed
Sequence)
00 = 1 second
01 = 250ms
10 = 125ms
11 = 62.5ms
1:0
LED2_DUTY_C
YC [1:0]
10
LED2 Duty Cycle (On:Off ratio)
(when LED2_MODE = Continuous Pulsed or Pulsed
Sequence)
00 = 1:1 (50% on)
01 = 1:2 (33.3% on)
10 = 1:3 (25% on)
11 = 1:7 (12.5% on)
Register 404Dh Status LED 2
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16462
(404Eh)
Current Sink
1
15
CS1_ENA
0
Current Sink 1 Enable (ISINK1 pin)
0 = Disabled
1 = Enabled
Note - this bit is reset to 0 when the OFF power state is
entered.
14
CS1_DRIVE
0
Current Sink 1 output drive enable
0 = Disabled
1 = Enabled
13
CS1_STS
w
0
Current Sink 1 status
PP, May 2012, Rev 3.1
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
0 = Normal
1 = Sink current cannot be regulated
12
CS1_SLPENA
0
Current Sink 1 SLEEP Enable
0 = Disabled
1 = Controlled by CS1_ENA
11:10
CS1_OFF_RA
MP [1:0]
01
ISINK1 Switch-Off ramp
00 = instant (no ramp)
01 = 1 step every 4ms (220ms)
10 = 1 step every 8ms (440ms)
11 = 1 step every 16ms (880ms)
The time quoted in brackets is valid for the maximum
change in current drive setting. The actual time scales
according to the extent of the change in current drive
setting.
9:8
CS1_ON_RAM
P [1:0]
01
ISINK1 Switch-On ramp
00 = instant (no ramp)
01 = 1 step every 4ms (220ms)
10 = 1 step every 8ms (440ms)
11 = 1 step every 16ms (880ms)
The time quoted in brackets is valid for the maximum
change in current drive setting. The actual time scales
according to the extent of the change in current drive
setting.
5:0
CS1_ISEL [5:0]
00_0000
ISINK1 current.
Current = 2.0µA × 2^(CS1_ISEL/4), where CS1_ISEL is
an unsigned binary number.
Alternatively,
CS1_ISEL = 13.29 x LOG(current/2.0µA)
00_0000 = 2.0µA
11_0111 = 27.6mA
Values greater than 11_0111 will result in the maximum
current of approx 27.6mA.
Register 404Eh Current Sink 1
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16463
(404Fh)
Current Sink
2
15
CS2_ENA
0
Current Sink 2 Enable (ISINK2 pin)
0 = Disabled
1 = Enabled
Note - this bit is reset to 0 when the OFF power state is
entered.
14
CS2_DRIVE
0
Current Sink 2 output drive enable
0 = Disabled
1 = Enabled
13
CS2_STS
0
Current Sink 2 status
0 = Normal
1 = Sink current cannot be regulated
12
CS2_SLPENA
0
Current Sink 2 SLEEP Enable
0 = Disabled
1 = Controlled by CS2_ENA
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
11:10
CS2_OFF_RA
MP [1:0]
01
ISINK2 Switch-Off ramp
00 = instant (no ramp)
01 = 1 step every 4ms (220ms)
10 = 1 step every 8ms (440ms)
11 = 1 step every 16ms (880ms)
The time quoted in brackets is valid for the maximum
change in current drive setting. The actual time scales
according to the extent of the change in current drive
setting.
9:8
CS2_ON_RAM
P [1:0]
01
ISINK2 Switch-On ramp
00 = instant (no ramp)
01 = 1 step every 4ms (220ms)
10 = 1 step every 8ms (440ms)
11 = 1 step every 16ms (880ms)
The time quoted in brackets is valid for the maximum
change in current drive setting. The actual time scales
according to the extent of the change in current drive
setting.
5:0
CS2_ISEL [5:0]
00_0000
ISINK2 current.
Current = 2.0µA × 2^(CS2_ISEL/4), where CS2_ISEL is
an unsigned binary number.
Alternatively,
CS2_ISEL = 13.29 x LOG(current/2.0µA)
00_0000 = 2.0µA
11_0111 = 27.6mA
Values greater than 11_0111 will result in the maximum
current of approx 27.6mA.
Register 404Fh Current Sink 2
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16464
(4050h)
DCDC
Enable
7
EPE2_ENA
0
EPE2 Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated in EPE2_STS)
6
EPE1_ENA
0
EPE1 Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated in EPE1_STS)
3
DC4_ENA
0
DC-DC4 Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated in DC4_STS)
2
DC3_ENA
0
DC-DC3 Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated in DC3_STS)
1
DC2_ENA
0
DC-DC2 Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated in DC2_STS)
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
0
DC1_ENA
0
DC_DC1 Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated in DC1_STS)
Register 4050h DCDC Enable
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16465
(4051h)
LDO Enable
10
LDO11_ENA
0
LDO11 Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated in LDO11_STS)
9
LDO10_ENA
0
LDO10 Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated in LDO10_STS)
8
LDO9_ENA
0
LDO9 Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated in LDO9_STS)
7
LDO8_ENA
0
LDO8 Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated in LDO8_STS)
6
LDO7_ENA
0
LDO7 Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated in LDO7_STS)
5
LDO6_ENA
0
LDO6 Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated in LDO6_STS)
4
LDO5_ENA
0
LDO5 Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated in LDO5_STS)
3
LDO4_ENA
0
LDO4 Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated in LDO4_STS)
2
LDO3_ENA
0
LDO3 Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated in LDO3_STS)
1
LDO2_ENA
0
LDO2 Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated in LDO2_STS)
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218
WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
0
LDO1_ENA
0
LDO1 Enable request
0 = Disabled
1 = Enabled
(Note that the actual status is indicated in LDO1_STS)
Register 4051h LDO Enable
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
R16466
(4052h)
DCDC
Status
7
EPE2_STS
0
EPE2 Status
0 = Disabled
1 = Enabled
6
EPE1_STS
0
EPE1 Status
0 = Disabled
1 = Enabled
3
DC4_STS
0
DC-DC4 Status
0 = Disabled
1 = Enabled
2
DC3_STS
0
DC-DC3 Status
0 = Disabled
1 = Enabled
1
DC2_STS
0
DC-DC2 Status
0 = Disabled
1 = Enabled
0
DC1_STS
0
DC-DC1 Status
0 = Disabled
1 = Enabled
Register 4052h DCDC Status
REGISTER
BIT
LABEL
DEFAULT
ADDRESS
R16467
(4053h)
LDO Status
10
LDO11_STS
0
LDO11 Status
0 = Disabled
1 = Enabled
9
LDO10_STS
0
LDO10 Status
0 = Disabled
1 = Enabled
8
LDO9_STS
0
LDO9 Status
0 = Disabled
1 = Enabled
7
LDO8_STS
0
LDO8 Status
0 = Disabled
1 = Enabled
6
LDO7_STS
0
LDO7 Status
0 = Disabled
1 = Enabled
5
LDO6_STS
0
LDO6 Status
0 = Disabled
1 = Enabled
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
4
LDO5_STS
0
LDO5 Status
0 = Disabled
1 = Enabled
3
LDO4_STS
0
LDO4 Status
0 = Disabled
1 = Enabled
2
LDO3_STS
0
LDO3 Status
0 = Disabled
1 = Enabled
1
LDO2_STS
0
LDO2 Status
0 = Disabled
1 = Enabled
0
LDO1_STS
0
LDO1 Status
0 = Disabled
1 = Enabled
Register 4053h LDO Status
REGISTER
BIT
LABEL
DEFAULT
ADDRESS
R16468
(4054h)
DCDC UV
Status
13
DC2_OV_STS
0
DC-DC2 Overvoltage Status
0 = Normal
1 = Overvoltage
12
DC1_OV_STS
0
DC-DC1 Overvoltage Status
0 = Normal
1 = Overvoltage
9
DC2_HC_STS
0
DC-DC2 High Current Status
0 = Normal
1 = High Current
8
DC1_HC_STS
0
DC-DC1 High Current Status
0 = Normal
1 = High Current
3
DC4_UV_STS
0
DC-DC4 Undervoltage Status
0 = Normal
1 = Undervoltage
2
DC3_UV_STS
0
DC-DC3 Undervoltage Status
0 = Normal
1 = Undervoltage
1
DC2_UV_STS
0
DC-DC2 Undervoltage Status
0 = Normal
1 = Undervoltage
0
DC1_UV_STS
0
DC-DC1 Undervoltage Status
0 = Normal
1 = Undervoltage
Register 4054h DCDC UV Status
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220
WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16469
(4055h)
LDO UV
Status
15
INTLDO_UV_S
TS
0
LDO10_UV_ST
S
0
LDO9_UV_ST
S
0
LDO8_UV_ST
S
0
LDO7_UV_ST
S
0
LDO6_UV_ST
S
0
LDO5_UV_ST
S
0
LDO4_UV_ST
S
0
LDO13 (Internal LDO) Undervoltage Status
0 = Normal
1 = Undervoltage
9
LDO10 Undervoltage Status
0 = Normal
1 = Undervoltage
8
LDO9 Undervoltage Status
0 = Normal
1 = Undervoltage
7
LDO8 Undervoltage Status
0 = Normal
1 = Undervoltage
6
LDO7 Undervoltage Status
0 = Normal
1 = Undervoltage
5
LDO6 Undervoltage Status
0 = Normal
1 = Undervoltage
4
LDO5 Undervoltage Status
0 = Normal
1 = Undervoltage
3
LDO4 Undervoltage Status
0 = Normal
1 = Undervoltage
2
LDO3_UV_ST
S
0
LDO2_UV_ST
S
0
LDO1_UV_ST
S
0
LDO3 Undervoltage Status
0 = Normal
1 = Undervoltage
1
LDO2 Undervoltage Status
0 = Normal
1 = Undervoltage
0
LDO1 Undervoltage Status
0 = Normal
1 = Undervoltage
Register 4055h LDO UV Status
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16470
(4056h) DC1
Control 1
15:14
DC1_RATE
[1:0]
10
DC-DC1 Voltage Ramp rate
00 = 1 step every 32us
01 = 1 step every 16us
10 = 1 step every 8us
11 = Immediate voltage change
12
DC1_PHASE
0
DC-DC1 Clock Phase Control
0 = Normal
1 = Inverted
9:8
DC1_FREQ
[1:0]
00
DC-DC1 Switching Frequency
00 = Reserved
01 = 2.0MHz
10 = Reserved
11 = 4.0MHz
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221
WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
7
DC1_FLT
0
DC-DC1 Output float
0 = DC-DC1 output discharged when disabled
1 = DC-DC1 output floating when disabled
5:4
DC1_SOFT_ST
ART [1:0]
00
DC-DC1 Soft-Start Control
(Duration in each of the 8 startup current limiting steps.)
00 = 32us steps
01 = 64us steps
10 = 128us steps
11 = 256us steps
1:0
DC1_CAP [1:0]
00
DC-DC1 Output Capacitor
00 = 4.7uF to 20uF
01 = Reserved
10 = 22uF to 47uF
11 = Reserved
Register 4056h DC1 Control 1
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16471
(4057h) DC1
Control 2
15:14
DC1_ERR_AC
T [1:0]
00
DC-DC1 Error Action (Undervoltage)
00 = Ignore
01 = Shut down converter
10 = Shut down system (Device Reset)
11 = Reserved
Note that an Interrupt is always raised.
12:11
DC1_HWC_SR
C [1:0]
00
DC-DC1 Hardware Control Source
00 = Disabled
01 = Hardware Control 1
10 = Hardware Control 2
11 = Hardware Control 1 or 2
10
DC1_HWC_VS
EL
0
DC1_HWC_M
ODE [1:0]
11
DC-DC1 Hardware Control Voltage select
0 = Set by DC1_ON_VSEL
1 = Set by DC1_SLP_VSEL
9:8
DC-DC1 Hardware Control Operating Mode
00 = Forced Continuous Conduction Mode
01 = Disabled
10 = LDO Mode
11 = Hysteretic Mode
6:4
DC1_HC_THR
[2:0]
000
DC-DC1 High Current threshold
000 = 125mA
001 = 250mA
010 = 375mA
011 = 500mA
100 = 625mA
101 = 750mA
110 = 875mA
111 = 1000mA
0
DC1_HC_IND_
ENA
0
DC-DC1 High Current detect enable
0 = Disabled
1 = Enabled
Register 4057h DC1 Control 2
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222
WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16472
(4058h) DC1
ON Config
15:13
DC1_ON_SLO
T [2:0]
000
DC-DC1 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
9:8
DC1_ON_MOD
E [1:0]
01
DC-DC1 ON Operating Mode
00 = Forced Continuous Conduction Mode
01 = Auto Mode (Continuous / Discontinuous
Conduction with Pulse-Skipping)
10 = LDO Mode
11 = Hysteretic Mode
6:2
DC1_ON_VSE
L [6:2]
0_0000
DC-DC1 ON Voltage select
DC1_ON_VSEL [6:0] selects the DC-DC1 output
voltage from 0.6V to 1.8V in 12.5mV steps.
DC1_ON_VSEL [6:2] also exist in ICE/OTP memory,
controlling the voltage in 50mV steps.
DC1_ON_VSEL [6:0] is coded as follows:
00h to 08h = 0.6V
09h = 0.6125V
…
48h = 1.4V (see note)
…
67h = 1.7875V
68h to 7Fh = 1.8V
Note - Maximum output voltage selection in 4MHz
switching mode is 48h (1.4V).
1:0
DC1_ON_VSE
L [1:0]
00
DC-DC1 ON Voltage select
DC1_ON_VSEL [6:0] selects the DC-DC1 output
voltage from 0.6V to 1.8V in 12.5mV steps.
See DC1_ON_VSEL [6:2] for definition.
Register 4058h DC1 ON Config
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16473
(4059h) DC1
SLEEP
Control
15:13
DC1_SLP_SLO
T [2:0]
000
DC-DC1 SLEEP Slot select
000 = SLEEP voltage / operating mode transition in
Timeslot 5
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
110 = SLEEP voltage / operating mode transition in
Timeslot 3
111 = SLEEP voltage / operating mode transition in
Timeslot 1
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
If DC-DC1 is assigned to a Hardware Enable Input,
then codes 001-101 select in which timeslot the
converter enters its SLEEP condition.
9:8
DC1_SLP_MO
DE [1:0]
11
DC-DC1 SLEEP Operating Mode
00 = Forced Continuous Conduction Mode
01 = Auto Mode (Continuous / Discontinuous
Conduction with Pulse-Skipping)
10 = LDO Mode
11 = Hysteretic Mode
6:0
DC1_SLP_VSE
L [6:0]
000_0000
DC-DC1 SLEEP Voltage select
0.6V to 1.8V in 12.5mV steps
00h to 08h = 0.6V
09h = 0.6125V
…
48h = 1.4V (see note)
…
67h = 1.7875V
68h to 7Fh = 1.8V
Note - Maximum output voltage selection in 4MHz
switching mode is 48h (1.4V).
Register 4059h DC1 SLEEP Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16474
(405Ah)
DC1 DVS
Control
12:11
DC1_DVS_SR
C [1:0]
00
DC-DC1 DVS Control Source
00 = Disabled
01 = Enabled
10 = Controlled by Hardware DVS1
11 = Controlled by Hardware DVS2
6:0
DC1_DVS_VS
EL [6:0]
000_0000
DC-DC1 DVS Voltage select
0.6V to 1.8V in 12.5mV steps
00h to 08h = 0.6V
09h = 0.6125V
…
48h = 1.4V (see note)
…
67h = 1.7875V
68h to 7Fh = 1.8V
Note - Maximum output voltage selection in 4MHz
switching mode is 48h (1.4V).
Register 405Ah DC1 DVS Control
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16475
(405Bh)
DC2 Control
1
15:14
DC2_RATE
[1:0]
10
DC-DC2 Voltage Ramp rate
00 = 1 step every 32us
01 = 1 step every 16us
10 = 1 step every 8us
11 = Immediate voltage change
12
DC2_PHASE
1
DC-DC2 Clock Phase Control
0 = Normal
1 = Inverted
9:8
DC2_FREQ
[1:0]
00
DC-DC2 Switching Frequency
00 = Reserved
01 = 2.0MHz
10 = Reserved
11 = 4.0MHz
7
DC2_FLT
0
DC-DC2 Output float
0 = DC-DC2 output discharged when disabled
1 = DC-DC2 output floating when disabled
5:4
DC2_SOFT_ST
ART [1:0]
00
DC-DC2 Soft-Start Control
(Duration in each of the 8 startup current limiting steps.)
00 = 32us steps
01 = 64us steps
10 = 128us steps
11 = 256us steps
1:0
DC2_CAP [1:0]
00
DC-DC2 Output Capacitor
00 = 4.7uF to 20uF
01 = Reserved
10 = 22uF to 47uF
11 = Reserved
Register 405Bh DC2 Control 1
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16476
(405Ch)
DC2 Control
2
15:14
DC2_ERR_AC
T [1:0]
00
DC-DC2 Error Action (Undervoltage)
00 = Ignore
01 = Shut down converter
10 = Shut down system (Device Reset)
11 = Reserved
Note that an Interrupt is always raised.
12:11
DC2_HWC_SR
C [1:0]
00
DC-DC2 Hardware Control Source
00 = Disabled
01 = Hardware Control 1
10 = Hardware Control 2
11 = Hardware Control 1 or 2
10
DC2_HWC_VS
EL
0
DC2_HWC_M
ODE [1:0]
11
DC-DC2 Hardware Control Voltage select
0 = Set by DC2_ON_VSEL
1 = Set by DC2_SLP_VSEL
9:8
DC-DC2 Hardware Control Operating Mode
00 = Forced Continuous Conduction Mode
01 = Disabled
10 = LDO Mode
11 = Hysteretic Mode
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
6:4
DC2_HC_THR
[2:0]
000
0
DC2_HC_IND_
ENA
0
DC-DC2 High Current threshold
000 = 125mA
001 = 250mA
010 = 375mA
011 = 500mA
100 = 625mA
101 = 750mA
110 = 875mA
111 = 1000mA
DC-DC2 High Current detect enable
0 = Disabled
1 = Enabled
Register 405Ch DC2 Control 2
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16477
(405Dh)
DC2 ON
Config
15:13
DC2_ON_SLO
T [2:0]
000
DC-DC2 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
9:8
DC2_ON_MOD
E [1:0]
01
DC-DC2 ON Operating Mode
00 = Forced Continuous Conduction Mode
01 = Auto Mode (Continuous / Discontinuous
Conduction with Pulse-Skipping)
10 = LDO Mode
11 = Hysteretic Mode
6:2
DC2_ON_VSE
L [6:2]
0_0000
DC-DC2 ON Voltage select
DC2_ON_VSEL [6:0] selects the DC-DC2 output
voltage from 0.6V to 1.8V in 12.5mV steps.
DC2_ON_VSEL [6:2] also exist in ICE/OTP memory,
controlling the voltage in 50mV steps.
DC2_ON_VSEL [6:0] is coded as follows:
00h to 08h = 0.6V
09h = 0.6125V
…
48h = 1.4V (see note)
…
67h = 1.7875V
68h to 7Fh = 1.8V
Note - Maximum output voltage selection in 4MHz
switching mode is 48h (1.4V).
1:0
DC2_ON_VSE
L [1:0]
00
DC-DC2 ON Voltage select
DC2_ON_VSEL [6:0] selects the DC-DC2 output
voltage from 0.6V to 1.8V in 12.5mV steps.
See DC2_ON_VSEL [6:2] for definition.
Register 405Dh DC2 ON Config
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16478
(405Eh)
DC2 SLEEP
Control
15:13
DC2_SLP_SLO
T [2:0]
000
DC-DC2 SLEEP Slot select
000 = SLEEP voltage / operating mode transition in
Timeslot 5
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
110 = SLEEP voltage / operating mode transition in
Timeslot 3
111 = SLEEP voltage / operating mode transition in
Timeslot 1
If DC-DC2 is assigned to a Hardware Enable Input,
then codes 001-101 select in which timeslot the
converter enters its SLEEP condition.
9:8
DC2_SLP_MO
DE [1:0]
11
DC-DC2 SLEEP Operating Mode
00 = Forced Continuous Conduction Mode
01 = Auto Mode (Continuous / Discontinuous
Conduction with Pulse-Skipping)
10 = LDO Mode
11 = Hysteretic Mode
6:0
DC2_SLP_VSE
L [6:0]
000_0000
DC-DC2 SLEEP Voltage select
0.6V to 1.8V in 12.5mV steps
00h to 08h = 0.6V
09h = 0.6125V
…
48h = 1.4V (see note)
…
67h = 1.7875V
68h to 7Fh = 1.8V
Note - Maximum output voltage selection in 4MHz
switching mode is 48h (1.4V).
Register 405Eh DC2 SLEEP Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16479
(405Fh)
DC2 DVS
Control
12:11
DC2_DVS_SR
C [1:0]
00
DC-DC2 DVS Control Source
00 = Disabled
01 = Enabled
10 = Controlled by Hardware DVS1
11 = Controlled by Hardware DVS2
6:0
DC2_DVS_VS
EL [6:0]
000_0000
DC-DC2 DVS Voltage select
0.6V to 1.8V in 12.5mV steps
00h to 08h = 0.6V
09h = 0.6125V
…
48h = 1.4V (see note)
…
67h = 1.7875V
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227
WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
68h to 7Fh = 1.8V
Note - Maximum output voltage selection in 4MHz
switching mode is 48h (1.4V).
Register 405Fh DC2 DVS Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16480
(4060h) DC3
Control 1
12
DC3_PHASE
0
DC-DC3 Clock Phase Control
0 = Normal
1 = Inverted
7
DC3_FLT
0
DC-DC3 Output float
0 = DC-DC3 output discharged when disabled
1 = DC-DC3 output floating when disabled
5:4
DC3_SOFT_ST
ART [1:0]
01
DC-DC3 Soft-Start Control
(Duration in each of the 3 intermediate startup current
limiting steps.)
00 = Immediate start-up
01 = 512us steps
10 = 4.096ms steps
11 = 32.768ms steps
3:2
DC3_STNBY_L
IM [1:0]
01
DC-DC3 Current Limit
Sets the maximum DC output current in Hysteretic
Mode. Typical values shown below.
00 = 100mA
01 = 200mA
10 = 400mA
11 = 800mA
Protected by security key.
1:0
DC3_CAP [1:0]
00
DC-DC3 Output Capacitor
00 = 10uF to 20uF
01 = 10uF to 20uF
10 = 22uF to 45uF
11 = 47uF to 100uF
Register 4060h DC3 Control 1
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16481
(4061h) DC3
Control 2
15:14
DC3_ERR_AC
T [1:0]
00
DC-DC3 Error Action (Undervoltage)
00 = Ignore
01 = Shut down converter
10 = Shut down system (Device Reset)
11 = Reserved
Note that an Interrupt is always raised.
12:11
DC3_HWC_SR
C [1:0]
00
DC-DC3 Hardware Control Source
00 = Disabled
01 = Hardware Control 1
10 = Hardware Control 2
11 = Hardware Control 1 or 2
10
DC3_HWC_VS
EL
0
DC-DC3 Hardware Control Voltage select
0 = Set by DC3_ON_VSEL
1 = Set by DC3_SLP_VSEL
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
9:8
DC3_HWC_M
ODE [1:0]
11
DC-DC3 Hardware Control Operating Mode
00 = Forced Continuous Conduction Mode
01 = Disabled
10 = LDO Mode
11 = Hysteretic Mode
7
DC3_OVP
0
DC-DC3 Overvoltage Protection
0 = Disabled
1 = Enabled
Register 4061h DC3 Control 2
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16482
(4062h) DC3
ON Config
15:13
DC3_ON_SLO
T [2:0]
000
DC-DC3 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
9:8
DC3_ON_MOD
E [1:0]
01
DC-DC3 ON Operating Mode
00 = Forced Continuous Conduction Mode
01 = Auto Mode (Continuous / Discontinuous
Conduction with Pulse-Skipping)
10 = LDO Mode
11 = Hysteretic Mode
6:2
DC3_ON_VSE
L [6:2]
0_0000
DC-DC3 ON Voltage select
DC3_ON_VSEL [6:0] selects the DC-DC3 output
voltage from 0.85V to 3.4V in 25mV steps.
DC3_ON_VSEL [6:2] also exist in ICE/OTP memory,
controlling the voltage in 100mV steps.
DC3_ON_VSEL [6:0] is coded as follows:
00h = 0.85V
01h = 0.875V
…
65h = 3.375V
66h to 7Fh = 3.4V
1:0
DC3_ON_VSE
L [1:0]
00
DC3 ON Voltage select
DC3_ON_VSEL [6:0] selects the DC3 output voltage
from 0.85V to 3.4V in 25mV steps.
See DC3_ON_VSEL [6:2] for definition.
Register 4062h DC3 ON Config
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16483
(4063h) DC3
SLEEP
Control
15:13
DC3_SLP_SLO
T [2:0]
000
DC-DC3 SLEEP Slot select
000 = SLEEP voltage / operating mode transition in
Timeslot 5
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
110 = SLEEP voltage / operating mode transition in
Timeslot 3
111 = SLEEP voltage / operating mode transition in
Timeslot 1
If DC-DC3 is assigned to a Hardware Enable Input,
then codes 001-101 select in which timeslot the
converter enters its SLEEP condition.
9:8
DC3_SLP_MO
DE [1:0]
11
DC-DC3 SLEEP Operating Mode
00 = Forced Continuous Conduction Mode
01 = Auto Mode (Continuous / Discontinuous
Conduction with Pulse-Skipping)
10 = LDO Mode
11 = Hysteretic Mode
6:0
DC3_SLP_VSE
L [6:0]
000_0000
DC-DC3 SLEEP Voltage select
0.85V to 3.4V in 25mV steps
00h = 0.85V
01h = 0.875V
…
65h = 3.375V
66h to 7Fh = 3.4V
Register 4063h DC3 SLEEP Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16484
(4064h) DC4
Control
15:14
DC4_ERR_AC
T [1:0]
00
DC-DC4 Error Action (Undervoltage)
00 = Ignore
01 = Shut down converter
10 = Shut down system (Device Reset)
11 = Reserved
Note that an Interrupt is always raised.
12:11
DC4_HWC_SR
C [1:0]
00
DC-DC4 Hardware Control Source
00 = Disabled
01 = Hardware Control 1
10 = Hardware Control 2
11 = Hardware Control 1 or 2
8
DC4_HWC_M
ODE
1
DC-DC4 Hardware Control Operating Mode
0 = DC-DC4 is controlled by DC4_ENA
1 = DC-DC4 is disabled when Hardware Control Source
is asserted
3:2
DC4_RANGE
[1:0]
01
Selects the voltage range for DC-DC4
00 = 20V < VOUT <= 30V
01 = 10V < VOUT <= 20V
10 = 6.5V < VOUT <= 10V
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
11 = Reserved
Protected by security key.
0
DC4_FBSRC
0
DC-DC4 Voltage Feedback source
0 = ISINK1
1 = ISINK2
Register 4064h DC4 Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16485
(4065h) DC4
SLEEP
Control
8
DC4_SLPENA
0
DC-DC4 SLEEP Enable
0 = Disabled
1 = Controlled by DC4_ENA
Register 4065h DC4 SLEEP Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16486
(4066h)
EPE1
Control
15:13
EPE1_ON_SL
OT [2:0]
000
EPE1 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
12:11
EPE1_HWC_S
RC [1:0]
00
EPE1 Hardware Control Source
00 = Disabled
01 = Hardware Control 1
10 = Hardware Control 2
11 = Hardware Control 1 or 2
8
EPE1_HWCEN
A
0
EPE1 Hardware Control Enable
0 = EPE1 is controlled by EPE1_ENA (Hardware
Control input(s) are ignored)
1 = EPE1 is controlled by HWC inputs (Hardware
Control input(s) force EPE1 to be de-asserted)
7:5
EPE1_SLP_SL
OT [2:0]
000
EPE1 SLEEP Slot select
000 = No action
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
110 = No action
111 = No action
Register 4066h EPE1 Control
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16487
(4067h)
EPE2
Control
15:13
EPE2_ON_SL
OT [2:0]
000
EPE2 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
12:11
EPE2_HWC_S
RC [1:0]
00
EPE2 Hardware Control Source
00 = Disabled
01 = Hardware Control 1
10 = Hardware Control 2
11 = Hardware Control 1 or 2
8
EPE2_HWCEN
A
0
EPE2 Hardware Control Enable
0 = EPE2 is controlled by EPE2_ENA (Hardware
Control input(s) are ignored)
1 = EPE2 is controlled by HWC inputs (Hardware
Control input(s) force EPE2 to be de-asserted)
7:5
EPE2_SLP_SL
OT [2:0]
000
EPE2 SLEEP Slot select
000 = No action
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
110 = No action
111 = No action
Register 4067h EPE2 Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16488
(4068h)
LDO1
Control
15:14
LDO1_ERR_A
CT [1:0]
00
LDO1 Error Action (Undervoltage)
00 = Ignore
01 = Shut down regulator
10 = Shut down system (Device Reset)
11 = Reserved
Note that an Interrupt is always raised.
12:11
LDO1_HWC_S
RC [1:0]
00
LDO1 Hardware Control Source
00 = Disabled
01 = Hardware Control 1
10 = Hardware Control 2
11 = Hardware Control 1 or 2
10
LDO1_HWC_V
SEL
0
LDO1 Hardware Control Voltage select
0 = Set by LDO1_ON_VSEL
1 = Set by LDO1_SLP_VSEL
9:8
LDO1_HWC_M
ODE [1:0]
10
LDO1 Hardware Control Operating Mode
00 = Low Power mode
01 = Turn converter off
10 = Low Power mode
11 = Set by LDO1_ON_MODE
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232
WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
7
LDO1_FLT
0
LDO1 Output float
0 = LDO1 output discharged when disabled
1 = LDO1 output floating when disabled
6
LDO1_SWI
0
LDO1 Switch Mode
0 = LDO mode
1 = Switch mode
0
LDO1_LP_MO
DE
0
LDO1 Low Power Mode Select
0 = 50mA (reduced quiescent current)
1 = 20mA (minimum quiescent current)
Selects which Low Power mode is used in ON, SLEEP,
or under HWC modes.
Register 4068h LDO1 Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16489
(4069h)
LDO1 ON
Control
15:13
LDO1_ON_SL
OT [2:0]
000
LDO1 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
8
LDO1_ON_MO
DE
0
LDO1 ON Operating Mode
0 = Normal mode
1 = Low Power mode
4:0
LDO1_ON_VS
EL [4:0]
0_0000
LDO1 ON Voltage select
0.9V to 1.6V in 50mV steps
1.7V to 3.3V in 100mV steps
00h = 0.90V
01h = 0.95V
…
0Eh = 1.60V
0Fh = 1.70V
…
1Eh = 3.20V
1Fh = 3.30V
Register 4069h LDO1 ON Control
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233
WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16490
(406Ah)
LDO1
SLEEP
Control
15:13
LDO1_SLP_SL
OT [2:0]
000
LDO1 SLEEP Slot select
000 = SLEEP voltage / operating mode transition in
Timeslot 5
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
110 = SLEEP voltage / operating mode transition in
Timeslot 3
111 = SLEEP voltage / operating mode transition in
Timeslot 1
If LDO1 is assigned to a Hardware Enable Input, then
codes 001-101 select in which timeslot the regulator
enters its SLEEP condition.
8
LDO1_SLP_M
ODE
1
LDO1_SLP_VS
EL [4:0]
0_0000
LDO1 SLEEP Operating Mode
0 = Normal mode
1 = Low Power mode
4:0
LDO1 SLEEP Voltage select
0.9V to 1.6V in 50mV steps
1.7V to 3.3V in 100mV steps
00h = 0.90V
01h = 0.95V
…
0Eh = 1.60V
0Fh = 1.70V
…
1Eh = 3.20V
1Fh = 3.30V
Register 406Ah LDO1 SLEEP Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16491
(406Bh)
LDO2
Control
15:14
LDO2_ERR_A
CT [1:0]
00
LDO2 Error Action (Undervoltage)
00 = Ignore
01 = Shut down regulator
10 = Shut down system (Device Reset)
11 = Reserved
Note that an Interrupt is always raised.
12:11
LDO2_HWC_S
RC [1:0]
00
LDO2 Hardware Control Source
00 = Disabled
01 = Hardware Control 1
10 = Hardware Control 2
11 = Hardware Control 1 or 2
10
LDO2_HWC_V
SEL
0
LDO2_HWC_M
ODE [1:0]
10
LDO2 Hardware Control Voltage select
0 = Set by LDO2_ON_VSEL
1 = Set by LDO2_SLP_VSEL
9:8
LDO2 Hardware Control Operating Mode
00 = Low Power mode
01 = Turn converter off
10 = Low Power mode
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234
WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
11 = Set by LDO2_ON_MODE
7
LDO2_FLT
0
LDO2 Output float
0 = LDO2 output discharged when disabled
1 = LDO2 output floating when disabled
6
LDO2_SWI
0
LDO2 Switch Mode
0 = LDO mode
1 = Switch mode
0
LDO2_LP_MO
DE
0
LDO2 Low Power Mode Select
0 = 50mA (reduced quiescent current)
1 = 20mA (minimum quiescent current)
Selects which Low Power mode is used in ON, SLEEP,
or under HWC modes.
Register 406Bh LDO2 Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16492
(406Ch)
LDO2 ON
Control
15:13
LDO2_ON_SL
OT [2:0]
000
LDO2 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
8
LDO2_ON_MO
DE
0
LDO2_ON_VS
EL [4:0]
0_0000
LDO2 ON Operating Mode
0 = Normal mode
1 = Low Power mode
4:0
LDO2 ON Voltage select
0.9V to 1.6V in 50mV steps
1.7V to 3.3V in 100mV steps
00h = 0.90V
01h = 0.95V
…
0Eh = 1.60V
0Fh = 1.70V
…
1Eh = 3.20V
1Fh = 3.30V
Register 406Ch LDO2 ON Control
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235
WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16493
(406Dh)
LDO2
SLEEP
Control
15:13
LDO2_SLP_SL
OT [2:0]
000
LDO2 SLEEP Slot select
000 = SLEEP voltage / operating mode transition in
Timeslot 5
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
110 = SLEEP voltage / operating mode transition in
Timeslot 3
111 = SLEEP voltage / operating mode transition in
Timeslot 1
If LDO2 is assigned to a Hardware Enable Input, then
codes 001-101 select in which timeslot the regulator
enters its SLEEP condition.
8
LDO2_SLP_M
ODE
1
LDO2_SLP_VS
EL [4:0]
0_0000
LDO2 SLEEP Operating Mode
0 = Normal mode
1 = Low Power mode
4:0
LDO2 SLEEP Voltage select
0.9V to 1.6V in 50mV steps
1.7V to 3.3V in 100mV steps
00h = 0.90V
01h = 0.95V
…
0Eh = 1.60V
0Fh = 1.70V
…
1Eh = 3.20V
1Fh = 3.30V
Register 406Dh LDO2 SLEEP Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16494
(406Eh)
LDO3
Control
15:14
LDO3_ERR_A
CT [1:0]
00
LDO3 Error Action (Undervoltage)
00 = Ignore
01 = Shut down regulator
10 = Shut down system (Device Reset)
11 = Reserved
Note that an Interrupt is always raised.
12:11
LDO3_HWC_S
RC [1:0]
00
LDO3 Hardware Control Source
00 = Disabled
01 = Hardware Control 1
10 = Hardware Control 2
11 = Hardware Control 1 or 2
10
LDO3_HWC_V
SEL
0
LDO3 Hardware Control Voltage select
0 = Set by LDO3_ON_VSEL
1 = Set by LDO3_SLP_VSEL
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PP, May 2012, Rev 3.1
236
WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
9:8
LDO3_HWC_M
ODE [1:0]
10
LDO3 Hardware Control Operating Mode
00 = Low Power mode
01 = Turn converter off
10 = Low Power mode
11 = Set by LDO3_ON_MODE
7
LDO3_FLT
0
LDO3 Output float
0 = LDO3 output discharged when disabled
1 = LDO3 output floating when disabled
6
LDO3_SWI
0
LDO3 Switch Mode
0 = LDO mode
1 = Switch mode
0
LDO3_LP_MO
DE
0
LDO3 Low Power Mode Select
0 = 50mA (reduced quiescent current)
1 = 20mA (minimum quiescent current)
Selects which Low Power mode is used in ON, SLEEP,
or under HWC modes.
Register 406Eh LDO3 Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16495
(406Fh)
LDO3 ON
Control
15:13
LDO3_ON_SL
OT [2:0]
000
LDO3 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
8
LDO3_ON_MO
DE
0
LDO3_ON_VS
EL [4:0]
0_0000
LDO3 ON Operating Mode
0 = Normal mode
1 = Low Power mode
4:0
LDO3 ON Voltage select
0.9V to 1.6V in 50mV steps
1.7V to 3.3V in 100mV steps
00h = 0.90V
01h = 0.95V
…
0Eh = 1.60V
0Fh = 1.70V
…
1Eh = 3.20V
1Fh = 3.30V
Register 406Fh LDO3 ON Control
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PP, May 2012, Rev 3.1
237
WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16496
(4070h)
LDO3
SLEEP
Control
15:13
LDO3_SLP_SL
OT [2:0]
000
LDO3 SLEEP Slot select
000 = SLEEP voltage / operating mode transition in
Timeslot 5
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
110 = SLEEP voltage / operating mode transition in
Timeslot 3
111 = SLEEP voltage / operating mode transition in
Timeslot 1
If LDO3 is assigned to a Hardware Enable Input, then
codes 001-101 select in which timeslot the regulator
enters its SLEEP condition.
8
LDO3_SLP_M
ODE
1
LDO3_SLP_VS
EL [4:0]
0_0000
LDO3 SLEEP Operating Mode
0 = Normal mode
1 = Low Power mode
4:0
LDO3 SLEEP Voltage select
0.9V to 1.6V in 50mV steps
1.7V to 3.3V in 100mV steps
00h = 0.90V
01h = 0.95V
…
0Eh = 1.60V
0Fh = 1.70V
…
1Eh = 3.20V
1Fh = 3.30V
Register 4070h LDO3 SLEEP Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16497
(4071h)
LDO4
Control
15:14
LDO4_ERR_A
CT [1:0]
00
LDO4 Error Action (Undervoltage)
00 = Ignore
01 = Shut down regulator
10 = Shut down system (Device Reset)
11 = Reserved
Note that an Interrupt is always raised.
12:11
LDO4_HWC_S
RC [1:0]
00
LDO4 Hardware Control Source
00 = Disabled
01 = Hardware Control 1
10 = Hardware Control 2
11 = Hardware Control 1 or 2
10
LDO4_HWC_V
SEL
0
LDO4 Hardware Control Voltage select
0 = Set by LDO4_ON_VSEL
1 = Set by LDO4_SLP_VSEL
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PP, May 2012, Rev 3.1
238
WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
9:8
LDO4_HWC_M
ODE [1:0]
10
LDO4 Hardware Control Operating Mode
00 = Low Power mode
01 = Turn converter off
10 = Low Power mode
11 = Set by LDO4_ON_MODE
7
LDO4_FLT
0
LDO4 Output float
0 = LDO4 output discharged when disabled
1 = LDO4 output floating when disabled
6
LDO4_SWI
0
LDO4 Switch Mode
0 = LDO mode
1 = Switch mode
0
LDO4_LP_MO
DE
0
LDO4 Low Power Mode Select
0 = 50mA (reduced quiescent current)
1 = 20mA (minimum quiescent current)
Selects which Low Power mode is used in ON, SLEEP,
or under HWC modes.
Register 4071h LDO4 Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16498
(4072h)
LDO4 ON
Control
15:13
LDO4_ON_SL
OT [2:0]
000
LDO4 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
8
LDO4_ON_MO
DE
0
LDO4_ON_VS
EL [4:0]
0_0000
LDO4 ON Operating Mode
0 = Normal mode
1 = Low Power mode
4:0
LDO4 ON Voltage select
0.9V to 1.6V in 50mV steps
1.7V to 3.3V in 100mV steps
00h = 0.90V
01h = 0.95V
…
0Eh = 1.60V
0Fh = 1.70V
…
1Eh = 3.20V
1Fh = 3.30V
Register 4072h LDO4 ON Control
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PP, May 2012, Rev 3.1
239
WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16499
(4073h)
LDO4
SLEEP
Control
15:13
LDO4_SLP_SL
OT [2:0]
000
LDO4 SLEEP Slot select
000 = SLEEP voltage / operating mode transition in
Timeslot 5
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
110 = SLEEP voltage / operating mode transition in
Timeslot 3
111 = SLEEP voltage / operating mode transition in
Timeslot 1
If LDO4 is assigned to a Hardware Enable Input, then
codes 001-101 select in which timeslot the regulator
enters its SLEEP condition.
8
LDO4_SLP_M
ODE
1
LDO4_SLP_VS
EL [4:0]
0_0000
LDO4 SLEEP Operating Mode
0 = Normal mode
1 = Low Power mode
4:0
LDO4 SLEEP Voltage select
0.9V to 1.6V in 50mV steps
1.7V to 3.3V in 100mV steps
00h = 0.90V
01h = 0.95V
…
0Eh = 1.60V
0Fh = 1.70V
…
1Eh = 3.20V
1Fh = 3.30V
Register 4073h LDO4 SLEEP Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16500
(4074h)
LDO5
Control
15:14
LDO5_ERR_A
CT [1:0]
00
LDO5 Error Action (Undervoltage)
00 = Ignore
01 = Shut down regulator
10 = Shut down system (Device Reset)
11 = Reserved
Note that an Interrupt is always raised.
12:11
LDO5_HWC_S
RC [1:0]
00
LDO5 Hardware Control Source
00 = Disabled
01 = Hardware Control 1
10 = Hardware Control 2
11 = Hardware Control 1 or 2
10
LDO5_HWC_V
SEL
0
LDO5 Hardware Control Voltage select
0 = Set by LDO5_ON_VSEL
1 = Set by LDO5_SLP_VSEL
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PP, May 2012, Rev 3.1
240
WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
9:8
LDO5_HWC_M
ODE [1:0]
10
LDO5 Hardware Control Operating Mode
00 = Low Power mode
01 = Turn converter off
10 = Low Power mode
11 = Set by LDO5_ON_MODE
7
LDO5_FLT
0
LDO5 Output float
0 = LDO5 output discharged when disabled
1 = LDO5 output floating when disabled
6
LDO5_SWI
0
LDO5 Switch Mode
0 = LDO mode
1 = Switch mode
0
LDO5_LP_MO
DE
0
LDO5 Low Power Mode Select
0 = 50mA (reduced quiescent current)
1 = 20mA (minimum quiescent current)
Selects which Low Power mode is used in ON, SLEEP,
or under HWC modes.
Register 4074h LDO5 Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16501
(4075h)
LDO5 ON
Control
15:13
LDO5_ON_SL
OT [2:0]
000
LDO5 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
8
LDO5_ON_MO
DE
0
LDO5_ON_VS
EL [4:0]
0_0000
LDO5 ON Operating Mode
0 = Normal mode
1 = Low Power mode
4:0
LDO5 ON Voltage select
0.9V to 1.6V in 50mV steps
1.7V to 3.3V in 100mV steps
00h = 0.90V
01h = 0.95V
…
0Eh = 1.60V
0Fh = 1.70V
…
1Eh = 3.20V
1Fh = 3.30V
Register 4075h LDO5 ON Control
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PP, May 2012, Rev 3.1
241
WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16502
(4076h)
LDO5
SLEEP
Control
15:13
LDO5_SLP_SL
OT [2:0]
000
LDO5 SLEEP Slot select
000 = SLEEP voltage / operating mode transition in
Timeslot 5
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
110 = SLEEP voltage / operating mode transition in
Timeslot 3
111 = SLEEP voltage / operating mode transition in
Timeslot 1
If LDO5 is assigned to a Hardware Enable Input, then
codes 001-101 select in which timeslot the regulator
enters its SLEEP condition.
8
LDO5_SLP_M
ODE
1
LDO5_SLP_VS
EL [4:0]
0_0000
LDO5 SLEEP Operating Mode
0 = Normal mode
1 = Low Power mode
4:0
LDO5 SLEEP Voltage select
0.9V to 1.6V in 50mV steps
1.7V to 3.3V in 100mV steps
00h = 0.90V
01h = 0.95V
…
0Eh = 1.60V
0Fh = 1.70V
…
1Eh = 3.20V
1Fh = 3.30V
Register 4076h LDO5 SLEEP Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16503
(4077h)
LDO6
Control
15:14
LDO6_ERR_A
CT [1:0]
00
LDO6 Error Action (Undervoltage)
00 = Ignore
01 = Shut down regulator
10 = Shut down system (Device Reset)
11 = Reserved
Note that an Interrupt is always raised.
12:11
LDO6_HWC_S
RC [1:0]
00
LDO6 Hardware Control Source
00 = Disabled
01 = Hardware Control 1
10 = Hardware Control 2
11 = Hardware Control 1 or 2
10
LDO6_HWC_V
SEL
0
LDO6 Hardware Control Voltage select
0 = Set by LDO6_ON_VSEL
1 = Set by LDO6_SLP_VSEL
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PP, May 2012, Rev 3.1
242
WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
9:8
LDO6_HWC_M
ODE [1:0]
10
LDO6 Hardware Control Operating Mode
00 = Low Power mode
01 = Turn converter off
10 = Low Power mode
11 = Set by LDO6_ON_MODE
7
LDO6_FLT
0
LDO6 Output float
0 = LDO6 output discharged when disabled
1 = LDO6 output floating when disabled
6
LDO6_SWI
0
LDO6 Switch Mode
0 = LDO mode
1 = Switch mode
0
LDO6_LP_MO
DE
0
LDO6 Low Power Mode Select
0 = 50mA (reduced quiescent current)
1 = 20mA (minimum quiescent current)
Selects which Low Power mode is used in ON, SLEEP,
or under HWC modes.
Register 4077h LDO6 Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16504
(4078h)
LDO6 ON
Control
15:13
LDO6_ON_SL
OT [2:0]
000
LDO6 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
8
LDO6_ON_MO
DE
0
LDO6_ON_VS
EL [4:0]
0_0000
LDO6 ON Operating Mode
0 = Normal mode
1 = Low Power mode
4:0
LDO6 ON Voltage select
0.9V to 1.6V in 50mV steps
1.7V to 3.3V in 100mV steps
00h = 0.90V
01h = 0.95V
…
0Eh = 1.60V
0Fh = 1.70V
…
1Eh = 3.20V
1Fh = 3.30V
Register 4078h LDO6 ON Control
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PP, May 2012, Rev 3.1
243
WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16505
(4079h)
LDO6
SLEEP
Control
15:13
LDO6_SLP_SL
OT [2:0]
000
LDO6 SLEEP Slot select
000 = SLEEP voltage / operating mode transition in
Timeslot 5
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
110 = SLEEP voltage / operating mode transition in
Timeslot 3
111 = SLEEP voltage / operating mode transition in
Timeslot 1
If LDO6 is assigned to a Hardware Enable Input, then
codes 001-101 select in which timeslot the regulator
enters its SLEEP condition.
8
LDO6_SLP_M
ODE
1
LDO6_SLP_VS
EL [4:0]
0_0000
LDO6 SLEEP Operating Mode
0 = Normal mode
1 = Low Power mode
4:0
LDO6 SLEEP Voltage select
0.9V to 1.6V in 50mV steps
1.7V to 3.3V in 100mV steps
00h = 0.90V
01h = 0.95V
…
0Eh = 1.60V
0Fh = 1.70V
…
1Eh = 3.20V
1Fh = 3.30V
Register 4079h LDO6 SLEEP Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16506
(407Ah)
LDO7
Control
15:14
LDO7_ERR_A
CT [1:0]
00
LDO7 Error Action (Undervoltage)
00 = Ignore
01 = Shut down regulator
10 = Shut down system (Device Reset)
11 = Reserved
Note that an Interrupt is always raised.
12:11
LDO7_HWC_S
RC [1:0]
00
LDO7 Hardware Control Source
00 = Disabled
01 = Hardware Control 1
10 = Hardware Control 2
11 = Hardware Control 1 or 2
10
LDO7_HWC_V
SEL
0
LDO7 Hardware Control Voltage select
0 = Set by LDO7_ON_VSEL
1 = Set by LDO7_SLP_VSEL
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PP, May 2012, Rev 3.1
244
WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
9:8
LDO7_HWC_M
ODE [1:0]
10
LDO7 Hardware Control Operating Mode
00 = Low Power mode
01 = Turn converter off
10 = Low Power mode
11 = Set by LDO7_ON_MODE
7
LDO7_FLT
0
LDO7 Output float
0 = LDO7 output discharged when disabled
1 = LDO7 output floating when disabled
6
LDO7_SWI
0
LDO7 Switch Mode
0 = LDO mode
1 = Switch mode
Register 407Ah LDO7 Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16507
(407Bh)
LDO7 ON
Control
15:13
LDO7_ON_SL
OT [2:0]
000
LDO7 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
8
LDO7_ON_MO
DE
0
LDO7_ON_VS
EL [4:0]
0_0000
LDO7 ON Operating Mode
0 = Normal mode
1 = Low Power mode
4:0
LDO7 ON Voltage select
1.0V to 1.6V in 50mV steps
1.7V to 3.5V in 100mV steps
00h = 1.00V
01h = 1.05V
02h = 1.10V
…
0Ch = 1.60V
0Dh = 1.70V
…
1Eh = 3.40V
1Fh = 3.50V
Register 407Bh LDO7 ON Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16508
(407Ch)
LDO7
SLEEP
Control
15:13
LDO7_SLP_SL
OT [2:0]
000
LDO7 SLEEP Slot select
000 = SLEEP voltage / operating mode transition in
Timeslot 5
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
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PP, May 2012, Rev 3.1
245
WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
110 = SLEEP voltage / operating mode transition in
Timeslot 3
111 = SLEEP voltage / operating mode transition in
Timeslot 1
If LDO7 is assigned to a Hardware Enable Input, then
codes 001-101 select in which timeslot the regulator
enters its SLEEP condition.
8
LDO7_SLP_M
ODE
1
LDO7_SLP_VS
EL [4:0]
0_0000
LDO7 SLEEP Operating Mode
0 = Normal mode
1 = Low Power mode
4:0
LDO7 SLEEP Voltage select
1.0V to 1.6V in 50mV steps
1.7V to 3.5V in 100mV steps
00h = 1.00V
01h = 1.05V
02h = 1.10V
…
0Ch = 1.60V
0Dh = 1.70V
…
1Eh = 3.40V
1Fh = 3.50V
Register 407Ch LDO7 SLEEP Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16509
(407Dh)
LDO8
Control
15:14
LDO8_ERR_A
CT [1:0]
00
LDO8 Error Action (Undervoltage)
00 = Ignore
01 = Shut down regulator
10 = Shut down system (Device Reset)
11 = Reserved
Note that an Interrupt is always raised.
12:11
LDO8_HWC_S
RC [1:0]
00
LDO8 Hardware Control Source
00 = Disabled
01 = Hardware Control 1
10 = Hardware Control 2
11 = Hardware Control 1 or 2
10
LDO8_HWC_V
SEL
0
LDO8_HWC_M
ODE [1:0]
10
LDO8 Hardware Control Voltage select
0 = Set by LDO8_ON_VSEL
1 = Set by LDO8_SLP_VSEL
9:8
LDO8 Hardware Control Operating Mode
00 = Low Power mode
01 = Turn converter off
10 = Low Power mode
11 = Set by LDO8_ON_MODE
7
LDO8_FLT
0
LDO8 Output float
0 = LDO8 output discharged when disabled
1 = LDO8 output floating when disabled
6
LDO8_SWI
0
LDO8 Switch Mode
0 = LDO mode
1 = Switch mode
Register 407Dh LDO8 Control
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PP, May 2012, Rev 3.1
246
WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16510
(407Eh)
LDO8 ON
Control
15:13
LDO8_ON_SL
OT [2:0]
000
LDO8 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
8
LDO8_ON_MO
DE
0
LDO8_ON_VS
EL [4:0]
0_0000
LDO8 ON Operating Mode
0 = Normal mode
1 = Low Power mode
4:0
LDO8 ON Voltage select
1.0V to 1.6V in 50mV steps
1.7V to 3.5V in 100mV steps
00h = 1.00V
01h = 1.05V
02h = 1.10V
…
0Ch = 1.60V
0Dh = 1.70V
…
1Eh = 3.40V
1Fh = 3.50V
Register 407Eh LDO8 ON Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16511
(407Fh)
LDO8
SLEEP
Control
15:13
LDO8_SLP_SL
OT [2:0]
000
LDO8 SLEEP Slot select
000 = SLEEP voltage / operating mode transition in
Timeslot 5
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
110 = SLEEP voltage / operating mode transition in
Timeslot 3
111 = SLEEP voltage / operating mode transition in
Timeslot 1
If LDO8 is assigned to a Hardware Enable Input, then
codes 001-101 select in which timeslot the regulator
enters its SLEEP condition.
8
LDO8_SLP_M
ODE
1
LDO8_SLP_VS
EL [4:0]
0_0000
LDO8 SLEEP Operating Mode
0 = Normal mode
1 = Low Power mode
4:0
LDO8 SLEEP Voltage select
1.0V to 1.6V in 50mV steps
1.7V to 3.5V in 100mV steps
00h = 1.00V
01h = 1.05V
02h = 1.10V
w
PP, May 2012, Rev 3.1
247
WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
…
0Ch = 1.60V
0Dh = 1.70V
…
1Eh = 3.40V
1Fh = 3.50V
Register 407Fh LDO8 SLEEP Control
REGISTER
BIT
LABEL
DEFAULT
ADDRESS
R16512
(4080h)
LDO9
Control
15:14
LDO9_ERR_A
CT [1:0]
00
LDO9 Error Action (Undervoltage)
00 = Ignore
01 = Shut down regulator
10 = Shut down system (Device Reset)
11 = Reserved
Note that an Interrupt is always raised.
12:11
LDO9_HWC_S
RC [1:0]
00
LDO9 Hardware Control Source
00 = Disabled
01 = Hardware Control 1
10 = Hardware Control 2
11 = Hardware Control 1 or 2
10
LDO9_HWC_V
SEL
0
LDO9_HWC_M
ODE [1:0]
10
LDO9 Hardware Control Voltage select
0 = Set by LDO9_ON_VSEL
1 = Set by LDO9_SLP_VSEL
9:8
LDO9 Hardware Control Operating Mode
00 = Low Power mode
01 = Turn converter off
10 = Low Power mode
11 = Set by LDO9_ON_MODE
7
LDO9_FLT
0
LDO9 Output float
0 = LDO9 output discharged when disabled
1 = LDO9 output floating when disabled
6
LDO9_SWI
0
LDO9 Switch Mode
0 = LDO mode
1 = Switch mode
Register 4080h LDO9 Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16513
(4081h)
LDO9 ON
Control
15:13
8
LDO9_ON_SL
OT [2:0]
000
LDO9_ON_MO
DE
0
LDO9 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
LDO9 ON Operating Mode
0 = Normal mode
1 = Low Power mode
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
4:0
LDO9_ON_VS
EL [4:0]
0_0000
LDO9 ON Voltage select
1.0V to 1.6V in 50mV steps
1.7V to 3.5V in 100mV steps
00h = 1.00V
01h = 1.05V
02h = 1.10V
…
0Ch = 1.60V
0Dh = 1.70V
…
1Eh = 3.40V
1Fh = 3.50V
Register 4081h LDO9 ON Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16514
(4082h)
LDO9
SLEEP
Control
15:13
LDO9_SLP_SL
OT [2:0]
000
LDO9 SLEEP Slot select
000 = SLEEP voltage / operating mode transition in
Timeslot 5
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
110 = SLEEP voltage / operating mode transition in
Timeslot 3
111 = SLEEP voltage / operating mode transition in
Timeslot 1
If LDO9 is assigned to a Hardware Enable Input, then
codes 001-101 select in which timeslot the regulator
enters its SLEEP condition.
8
LDO9_SLP_M
ODE
1
LDO9 SLEEP Operating Mode
0 = Normal mode
1 = Low Power mode
4:0
LDO9_SLP_VS
EL [4:0]
0_0000
LDO9 SLEEP Voltage select
1.0V to 1.6V in 50mV steps
1.7V to 3.5V in 100mV steps
00h = 1.00V
01h = 1.05V
02h = 1.10V
…
0Ch = 1.60V
0Dh = 1.70V
…
1Eh = 3.40V
1Fh = 3.50V
Register 4082h LDO9 SLEEP Control
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16515
(4083h)
LDO10
Control
15:14
LDO10_ERR_
ACT [1:0]
00
LDO10 Error Action (Undervoltage)
00 = Ignore
01 = Shut down regulator
10 = Shut down system (Device Reset)
11 = Reserved
Note that an Interrupt is always raised.
12:11
LDO10_HWC_
SRC [1:0]
00
LDO10 Hardware Control Source
00 = Disabled
01 = Hardware Control 1
10 = Hardware Control 2
11 = Hardware Control 1 or 2
10
LDO10_HWC_
VSEL
0
LDO10_HWC_
MODE [1:0]
10
LDO10 Hardware Control Voltage select
0 = Set by LDO10_ON_VSEL
1 = Set by LDO10_SLP_VSEL
9:8
LDO10 Hardware Control Operating Mode
00 = Low Power mode
01 = Turn converter off
10 = Low Power mode
11 = Set by LDO10_ON_MODE
7
LDO10_FLT
0
LDO10 Output float
0 = LDO10 output discharged when disabled
1 = LDO10 output floating when disabled
6
LDO10_SWI
0
LDO10 Switch Mode
0 = LDO mode
1 = Switch mode
Register 4083h LDO10 Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16516
(4084h)
LDO10 ON
Control
15:13
LDO10_ON_SL
OT [2:0]
000
LDO10 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
8
LDO10_ON_M
ODE
0
LDO10 ON Operating Mode
0 = Normal mode
1 = Low Power mode
4:0
LDO10_ON_V
SEL [4:0]
0_0000
LDO10 ON Voltage select
1.0V to 1.6V in 50mV steps
1.7V to 3.5V in 100mV steps
00h = 1.00V
01h = 1.05V
02h = 1.10V
…
0Ch = 1.60V
0Dh = 1.70V
…
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
1Eh = 3.40V
1Fh = 3.50V
Register 4084h LDO10 ON Control
REGISTER
BIT
LABEL
DEFAULT
ADDRESS
R16517
(4085h)
LDO10
SLEEP
Control
15:13
LDO10_SLP_S
LOT [2:0]
000
LDO10 SLEEP Slot select
000 = SLEEP voltage / operating mode transition in
Timeslot 5
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
110 = SLEEP voltage / operating mode transition in
Timeslot 3
111 = SLEEP voltage / operating mode transition in
Timeslot 1
If LDO10 is assigned to a Hardware Enable Input, then
codes 001-101 select in which timeslot the regulator
enters its SLEEP condition.
8
LDO10_SLP_M
ODE
1
LDO10_SLP_V
SEL [4:0]
0_0000
LDO10 SLEEP Operating Mode
0 = Normal mode
1 = Low Power mode
4:0
LDO10 SLEEP Voltage select
1.0V to 1.6V in 50mV steps
1.7V to 3.5V in 100mV steps
00h = 1.00V
01h = 1.05V
02h = 1.10V
…
0Ch = 1.60V
0Dh = 1.70V
…
1Eh = 3.40V
1Fh = 3.50V
Register 4085h LDO10 SLEEP Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16519
(4087h)
LDO11 ON
Control
15:13
LDO11_ON_SL
OT [2:0]
000
LDO11 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
12
LDO11_FRCE
NA
0
LDO11 Force Enable (forces LDO11 to be enabled at
all times in the OFF, ON and SLEEP states)
0 = Disabled
1 = Enabled
7
LDO11_VSEL_
SRC
0
LDO11_ON_V
SEL [3:0]
0000
LDO11 Voltage Select source
0 = Normal (LDO11 settings)
1 = Same as DC-DC Converter 1
3:0
LDO11 ON Voltage select
0.80V to 1.55V in 50mV steps
0h = 0.80V
1h = 0.85V
2h = 0.90V
…
Eh = 1.50V
Fh = 1.55V
Register 4087h LDO11 ON Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16520
(4088h)
LDO11
SLEEP
Control
15:13
LDO11_SLP_S
LOT [2:0]
000
LDO11 SLEEP Slot select
000 = SLEEP voltage / operating mode transition in
Timeslot 5
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
110 = SLEEP voltage / operating mode transition in
Timeslot 3
111 = SLEEP voltage / operating mode transition in
Timeslot 1
If LDO11 is assigned to a Hardware Enable Input, then
codes 001-101 select in which timeslot the regulator
enters its SLEEP condition.
3:0
LDO11_SLP_V
SEL [3:0]
0000
LDO11 SLEEP Voltage select
0.80V to 1.55V in 50mV steps
0h = 0.80V
1h = 0.85V
2h = 0.90V
…
Eh = 1.50V
Fh = 1.55V
Register 4088h LDO11 SLEEP Control
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16526
(408Eh)
Power Good
Source 1
3
DC4_OK
0
DC-DC4 status selected as an input to PWR_GOOD
0 = Disabled
1 = Enabled
2
DC3_OK
1
DC-DC3 status selected as an input to PWR_GOOD
0 = Disabled
1 = Enabled
1
DC2_OK
1
DC-DC2 status selected as an input to PWR_GOOD
0 = Disabled
1 = Enabled
0
DC1_OK
1
DC-DC1 status selected as an input to PWR_GOOD
0 = Disabled
1 = Enabled
Register 408Eh Power Good Source 1
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16527
(408Fh)
Power Good
Source 2
9
LDO10_OK
1
LDO10 status selected as an input to PWR_GOOD
0 = Disabled
1 = Enabled
8
LDO9_OK
1
LDO9 status selected as an input to PWR_GOOD
0 = Disabled
1 = Enabled
7
LDO8_OK
1
LDO8 status selected as an input to PWR_GOOD
0 = Disabled
1 = Enabled
6
LDO7_OK
1
LDO7 status selected as an input to PWR_GOOD
0 = Disabled
1 = Enabled
5
LDO6_OK
1
LDO6 status selected as an input to PWR_GOOD
0 = Disabled
1 = Enabled
4
LDO5_OK
1
LDO5 status selected as an input to PWR_GOOD
0 = Disabled
1 = Enabled
3
LDO4_OK
1
LDO4 status selected as an input to PWR_GOOD
0 = Disabled
1 = Enabled
2
LDO3_OK
1
LDO3 status selected as an input to PWR_GOOD
0 = Disabled
1 = Enabled
1
LDO2_OK
1
LDO2 status selected as an input to PWR_GOOD
0 = Disabled
1 = Enabled
0
LDO1_OK
1
LDO1 status selected as an input to PWR_GOOD
0 = Disabled
1 = Enabled
Register 408Fh Power Good Source 2
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16528
(4090h)
Clock
Control 1
15
CLKOUT_ENA
0
CLKOUT output enable
0 = Disabled
1 = Enabled
Protected by security key
13
CLKOUT_OD
0
CLKOUT pin configuration
0 = CMOS
1 = Open Drain
10:8
CLKOUT_SLO
T [2:0]
000
CLKOUT output enable ON slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Do not enable
111 = Do not enable
6:4
CLKOUT_SLP
SLOT [2:0]
000
CLKOUT output SLEEP slot select
000 = Controlled by CLKOUT_ENA
001 = Disable in Timeslot 5
010 = Disable in Timeslot 4
011 = Disable in Timeslot 3
100 = Disable in Timeslot 2
101 = Disable in Timeslot 1
110 = Controlled by CLKOUT_ENA
111 = Controlled by CLKOUT_ENA
0
CLKOUT_SRC
0
CLKOUT output source select
0 = FLL output
1 = 32.768kHz oscillator
Register 4090h Clock Control 1
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16529
(4091h)
Clock
Control 2
15
XTAL_INH
0
Crystal Start-Up Inhibit
0 = Disabled
1 = Enabled
When XTAL_INH=1, the ‘ON’ transition is inhibited until
the crystal oscillator is valid
13
XTAL_ENA
0
Crystal Oscillator Enable
0 = Disabled at all times
1 = Enabled in OFF, ON and SLEEP states
(Note that the BACKUP behaviour is determined by
XTAL_BKUPENA.)
12
XTAL_BKUPE
NA
1
Selects the RTC and 32.768kHz oscillator in BACKUP
state
0 = RTC unclocked in BACKUP
1 = RTC maintained in BACKUP
(Note that XTAL_ENA must also be set if the RTC is to
be maintained in BACKUP.)
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
7
FLL_AUTO
1
FLL Automatic Mode Enable
0 = Manual configuration mode
1 = Automatic configuration mode
(To enable the FLL output, FLL_ENA must also be set
in Automatic mode)
2:0
FLL_AUTO_FR
EQ [2:0]
000
FLL Automatic Mode Frequency select
000 = 2.048MHz
001 = 11.2896MHz
010 = 12MHz
011 = 12.288MHz
100 = 19.2MHz
101 = 22.5792MHz
110 = 24MHz
111 = 24.576MHz
Register 4091h Clock Control 2
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16530
(4092h) FLL
Control 1
2
FLL_FRAC
0
Fractional enable
0 = Integer Mode
1 = Fractional Mode
Integer mode offers reduced power consumption.
Fractional mode offers best FLL performance, provided
also that N.K is a non-integer value.
0
FLL_ENA
0
FLL Enable
0 = Disabled
1 = Enabled
Note - this bit is reset to 0 when the OFF power state is
entered.
Register 4092h FLL Control 1
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16531
(4093h) FLL
Control 2
13:8
FLL_OUTDIV
[5:0]
00_0000
FOUT clock divider
000000 = Reserved
000001 = Reserved
000010 = Reserved
000011 = 4
000100 = 5
000101 = 6
…
111110 = 63
111111 = 64
(FOUT = FVCO / FLL_OUTDIV)
6:4
FLL_CTRL_RA
TE [2:0]
000
Frequency of the FLL control block
000 = FVCO / 1 (Recommended value)
001 = FVCO / 2
010 = FVCO / 3
011 = FVCO / 4
100 = FVCO / 5
101 = FVCO / 6
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255
WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
110 = FVCO / 7
111 = FVCO / 8
Recommended that this register is not changed from
default.
2:0
FLL_FRATIO
[2:0]
000
FVCO clock divider
000 = 1
001 = 2
010 = 4
011 = 8
1XX = 16
000 recommended for high FREF
011 recommended for low FREF
Register 4093h FLL Control 2
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16532
(4094h) FLL
Control 3
15:0
FLL_K [15:0]
0000_0000 Fractional multiply for FREF
_0000_000 (MSB = 0.5)
0
Register 4094h FLL Control 3
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16533
(4095h) FLL
Control 4
14:5
FLL_N [9:0]
3:0
FLL_GAIN [3:0]
01_0111_0 Integer multiply for FREF
111
(LSB = 1)
0000
Gain applied to error
0000 = x 1 (Recommended value)
0001 = x 2
0010 = x 4
0011 = x 8
0100 = x 16
0101 = x 32
0110 = x 64
0111 = x 128
1XXX = x 256
Recommended that this register is not changed from
default.
Register 4095h FLL Control 4
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256
WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R16534
(4096h) FLL
Control 5
4:3
FLL_CLK_REF
_DIV [1:0]
00
FLL Clock Reference Divider
00 = 1
01 = 2
10 = 4
11 = 8
CLKIN must be divided down to <=13.5MHz.
For lower power operation, the reference clock can be
divided down further if desired.
1:0
FLL_CLK_SRC
[1:0]
00
FLL Clock source
00 = 32.768kHz xtal oscillator
01 = CLKIN
10 = Reserved
11 = Reserved
Register 4096h FLL Control 5
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
R30720
(7800h)
Unique ID 1
15:0
UNIQUE_ID
[15:0]
0000_0000 Unique ID, Word 7
_0000_000
0
Register 7800h Unique ID 1
REGISTER
BIT
LABEL
DEFAULT
ADDRESS
R30721
(7801h)
Unique ID 2
15:0
UNIQUE_ID
[15:0]
0000_0000 Unique ID, Word 6
_0000_000
0
Register 7801h Unique ID 2
REGISTER
BIT
LABEL
DEFAULT
ADDRESS
R30722
(7802h)
Unique ID 3
15:0
UNIQUE_ID
[15:0]
0000_0000 Unique ID, Word 5
_0000_000
0
Register 7802h Unique ID 3
REGISTER
BIT
LABEL
DEFAULT
ADDRESS
R30723
(7803h)
Unique ID 4
15:0
UNIQUE_ID
[15:0]
0000_0000 Unique ID, Word 4
_0000_000
0
Register 7803h Unique ID 4
REGISTER
BIT
LABEL
DEFAULT
ADDRESS
R30724
(7804h)
Unique ID 5
15:0
UNIQUE_ID
[15:0]
0000_0000 Unique ID, Word 3
_0000_000
0
Register 7804h Unique ID 5
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257
WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
DESCRIPTION
REFER TO
ADDRESS
R30725
(7805h)
Unique ID 6
15:0
UNIQUE_ID
[15:0]
0000_0000 Unique ID, Word 2
_0000_000
0
Register 7805h Unique ID 6
REGISTER
BIT
LABEL
DEFAULT
ADDRESS
R30726
(7806h)
Unique ID 7
15:0
UNIQUE_ID
[15:0]
0000_0000 Unique ID, Word 1
_0000_000
0
Register 7806h Unique ID 7
REGISTER
BIT
LABEL
DEFAULT
ADDRESS
R30727
(7807h)
Unique ID 8
15:0
UNIQUE_ID
[15:0]
0000_0000 Unique ID, Word 0
_0000_000
0
Register 7807h Unique ID 8
REGISTER
BIT
LABEL
DEFAULT
ADDRESS
R30728
(7808h)
Factory OTP
ID
15:1
0
OTP_FACT_ID 000_0000_
[14:0]
0000_0000
[No description available]
OTP_FACT_FI
NAL
[No description available]
0
Register 7808h Factory OTP ID
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R30729
(7809h)
Factory OTP
1
15:12
DC3_TRIM
[3:0]
0000
[No description available]
11:6
DC2_TRIM
[5:0]
00_0000
[No description available]
5:0
DC1_TRIM
[5:0]
00_0000
[No description available]
Register 7809h Factory OTP 1
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R30730
(780Ah)
Factory OTP
2
15:0
CHIP_ID [15:0] 0000_0000
_0000_000
0
[No description available]
Register 780Ah Factory OTP 2
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258
WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R30731
(780Bh)
Factory OTP
3
10:7
OSC_TRIM
[3:0]
0000
[No description available]
6:3
BG_TRIM [3:0]
0000
[No description available]
2:0
LPBG_TRIM
[2:0]
000
[No description available]
Register 780Bh Factory OTP 3
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R30732
(780Ch)
Factory OTP
4
7:1
CHILD_I2C_A
DDR [6:0]
000_0000
[No description available]
0
CH_AW
0
[No description available]
Register 780Ch Factory OTP 4
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R30733
(780Dh)
Factory OTP
5
5:0
CHARGE_TRI
M [5:0]
00_0000
[No description available]
Register 780Dh Factory OTP 5
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R30736
(7810h)
Customer
OTP ID
15
14:1
0
OTP_AUTO_P
ROG
0
If this bit is set when bootstrap data is loaded from ICE
(in development mode), then the ICE contents will be
programmed in the OTP.
OTP_CUST_ID 00_0000_0 This field is checked when an ‘ON’ transition is
[13:0]
000_0000 requested. A non-zero value is used to confirm valid
data.
OTP_CUST_FI
NAL
0
If OTP_CUST_FINAL is set in the OTP and also set in
the DCRW, then no further Writes are possible to the
OTP.
Register 7810h Customer OTP ID
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R30737
(7811h) DC1
OTP Control
15:13
DC1_ON_SLO
T [2:0]
000
DC-DC1 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
9:8
DC1_FREQ
[1:0]
00
DC-DC1 Switching Frequency
00 = Reserved
01 = 2.0MHz
10 = Reserved
11 = 4.0MHz
7
DC1_PHASE
0
DC-DC1 Clock Phase Control
0 = Normal
1 = Inverted
6:2
DC1_ON_VSE
L [6:2]
0_0000
DC-DC1 ON Voltage select
DC1_ON_VSEL [6:0] selects the DC-DC1 output
voltage from 0.6V to 1.8V in 12.5mV steps.
DC1_ON_VSEL [6:2] controls the voltage in 50mV
steps.
DC1_ON_VSEL [6:0] is coded as follows:
00h to 08h = 0.6V
09h = 0.6125V
…
48h = 1.4V (see note)
…
67h = 1.7875V
68h to 7Fh = 1.8V
Note - Maximum output voltage selection in 4MHz
switching mode is 48h (1.4V).
1:0
DC1_CAP [1:0]
00
DC-DC1 Output Capacitor
00 = 4.7uF to 20uF
01 = Reserved
10 = 22uF to 47uF
11 = Reserved
Register 7811h DC1 OTP Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R30738
(7812h) DC2
OTP Control
15:13
DC2_ON_SLO
T [2:0]
000
DC-DC2 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
9:8
DC2_FREQ
[1:0]
00
DC-DC2 Switching Frequency
00 = Reserved
01 = 2.0MHz
10 = Reserved
11 = 4.0MHz
7
DC2_PHASE
1
DC-DC2 Clock Phase Control
0 = Normal
1 = Inverted
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260
WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
6:2
DC2_ON_VSE
L [6:2]
0_0000
DC-DC2 ON Voltage select
DC2_ON_VSEL [6:0] selects the DC-DC2 output
voltage from 0.6V to 1.8V in 12.5mV steps.
DC2_ON_VSEL [6:2] controls the voltage in 50mV
steps.
DC2_ON_VSEL [6:0] is coded as follows:
00h to 08h = 0.6V
09h = 0.6125V
…
48h = 1.4V (see note)
…
67h = 1.7875V
68h to 7Fh = 1.8V
Note - Maximum output voltage selection in 4MHz
switching mode is 48h (1.4V).
1:0
DC2_CAP [1:0]
00
DC-DC2 Output Capacitor
00 = 4.7uF to 20uF
01 = Reserved
10 = 22uF to 47uF
11 = Reserved
Register 7812h DC2 OTP Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R30739
(7813h) DC3
OTP Control
15:13
DC3_ON_SLO
T [2:0]
000
DC-DC3 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
7
DC3_PHASE
0
DC-DC3 Clock Phase Control
0 = Normal
1 = Inverted
6:2
DC3_ON_VSE
L [6:2]
0_0000
DC-DC3 ON Voltage select
DC3_ON_VSEL [6:0] selects the DC-DC3 output
voltage from 0.85V to 3.4V in 25mV steps.
DC3_ON_VSEL [6:2] controls the voltage in 100mV
steps.
DC3_ON_VSEL [6:0] is coded as follows:
00h = 0.85V
01h = 0.875V
…
65h = 3.375V
66h to 7Fh = 3.4V
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
1:0
DC3_CAP [1:0]
00
DC-DC3 Output Capacitor
00 = 10uF to 20uF
01 = 10uF to 20uF
10 = 22uF to 45uF
11 = 47uF to 100uF
Register 7813h DC3 OTP Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R30740
(7814h)
LDO1/2
OTP Control
15:13
LDO2_ON_SL
OT [2:0]
000
LDO2 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
12:8
LDO2_ON_VS
EL [4:0]
0_0000
LDO2 ON Voltage select
0.9V to 1.6V in 50mV steps
1.7V to 3.3V in 100mV steps
00h = 0.90V
01h = 0.95V
…
0Eh = 1.60V
0Fh = 1.70V
…
1Eh = 3.20V
1Fh = 3.30V
7:5
LDO1_ON_SL
OT [2:0]
000
LDO1 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
4:0
LDO1_ON_VS
EL [4:0]
0_0000
LDO1 ON Voltage select
0.9V to 1.6V in 50mV steps
1.7V to 3.3V in 100mV steps
00h = 0.90V
01h = 0.95V
…
0Eh = 1.60V
0Fh = 1.70V
…
1Eh = 3.20V
1Fh = 3.30V
Register 7814h LDO1/2 OTP Control
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R30741
(7815h)
LDO3/4
OTP Control
15:13
LDO4_ON_SL
OT [2:0]
000
LDO4 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
12:8
LDO4_ON_VS
EL [4:0]
0_0000
LDO4 ON Voltage select
0.9V to 1.6V in 50mV steps
1.7V to 3.3V in 100mV steps
00h = 0.90V
01h = 0.95V
…
0Eh = 1.60V
0Fh = 1.70V
…
1Eh = 3.20V
1Fh = 3.30V
7:5
LDO3_ON_SL
OT [2:0]
000
LDO3 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
4:0
LDO3_ON_VS
EL [4:0]
0_0000
LDO3 ON Voltage select
0.9V to 1.6V in 50mV steps
1.7V to 3.3V in 100mV steps
00h = 0.90V
01h = 0.95V
…
0Eh = 1.60V
0Fh = 1.70V
…
1Eh = 3.20V
1Fh = 3.30V
Register 7815h LDO3/4 OTP Control
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R30742
(7816h)
LDO5/6
OTP Control
15:13
LDO6_ON_SL
OT [2:0]
000
LDO6 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
12:8
LDO6_ON_VS
EL [4:0]
0_0000
111 = Controlled by Hardware Enable 2
LDO6 ON Voltage select
0.9V to 1.6V in 50mV steps
1.7V to 3.3V in 100mV steps
00h = 0.90V
01h = 0.95V
…
0Eh = 1.60V
0Fh = 1.70V
…
1Eh = 3.20V
1Fh = 3.30V
7:5
LDO5_ON_SL
OT [2:0]
000
LDO5 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
4:0
LDO5_ON_VS
EL [4:0]
0_0000
111 = Controlled by Hardware Enable 2
LDO5 ON Voltage select
0.9V to 1.6V in 50mV steps
1.7V to 3.3V in 100mV steps
00h = 0.90V
01h = 0.95V
…
0Eh = 1.60V
0Fh = 1.70V
…
1Eh = 3.20V
1Fh = 3.30V
Register 7816h LDO5/6 OTP Control
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R30743
(7817h)
LDO7/8
OTP Control
15:13
LDO8_ON_SL
OT [2:0]
000
LDO8 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
12:8
LDO8_ON_VS
EL [4:0]
0_0000
LDO8 ON Voltage select
1.0V to 1.6V in 50mV steps
1.7V to 3.5V in 100mV steps
00h = 1.00V
01h = 1.05V
02h = 1.10V
…
0Ch = 1.60V
0Dh = 1.70V
…
1Eh = 3.40V
1Fh = 3.50V
7:5
LDO7_ON_SL
OT [2:0]
000
LDO7 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
4:0
LDO7_ON_VS
EL [4:0]
0_0000
LDO7 ON Voltage select
1.0V to 1.6V in 50mV steps
1.7V to 3.5V in 100mV steps
00h = 1.00V
01h = 1.05V
02h = 1.10V
…
0Ch = 1.60V
0Dh = 1.70V
…
1Eh = 3.40V
1Fh = 3.50V
Register 7817h LDO7/8 OTP Control
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R30744
(7818h)
LDO9/10
OTP Control
15:13
LDO10_ON_SL
OT [2:0]
000
LDO10 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
12:8
LDO10_ON_V
SEL [4:0]
0_0000
LDO10 ON Voltage select
1.0V to 1.6V in 50mV steps
1.7V to 3.5V in 100mV steps
00h = 1.00V
01h = 1.05V
02h = 1.10V
…
0Ch = 1.60V
0Dh = 1.70V
…
1Eh = 3.40V
1Fh = 3.50V
7:5
LDO9_ON_SL
OT [2:0]
000
LDO9 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
4:0
LDO9_ON_VS
EL [4:0]
0_0000
LDO9 ON Voltage select
1.0V to 1.6V in 50mV steps
1.7V to 3.5V in 100mV steps
00h = 1.00V
01h = 1.05V
02h = 1.10V
…
0Ch = 1.60V
0Dh = 1.70V
…
1Eh = 3.40V
1Fh = 3.50V
Register 7818h LDO9/10 OTP Control
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R30745
(7819h)
LDO11/EPE
Control
15:13
LDO11_ON_SL
OT [2:0]
000
LDO11 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
11:8
LDO11_ON_V
SEL [3:0]
0000
LDO11 ON Voltage select
0.80V to 1.55V in 50mV steps
0h = 0.80V
1h = 0.85V
2h = 0.90V
…
Eh = 1.50V
Fh = 1.55V
7:5
EPE2_ON_SL
OT [2:0]
000
EPE2 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
4:2
EPE1_ON_SL
OT [2:0]
000
EPE1 ON Slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
1:0
USB100MA_S
TARTUP [1:0]
00
Sets the device behaviour when starting up under USB
power, when USB_ILIM = 010b (100mA)
00 = Normal
01 = Soft-Start
10 = Only start if BATTVDD > 3.1V
11 = Only start if BATTVDD > 3.4V
In the 1X modes, if the battery voltage is less than the
selected threshold, then the device will enable trickle
charge mode instead of executing the start-up request.
The start-up request is delayed until the battery voltage
threshold has been met.
Register 7819h LDO11/EPE Control
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R30746
(781Ah)
GPIO1 OTP
Control
15
GP1_DIR
1
GPIO1 pin direction
0 = Output
1 = Input
14:13
GP1_PULL
[1:0]
01
GPIO1 Pull-Up / Pull-Down configuration
00 = No pull resistor
01 = Pull-down enabled
10 = Pull-up enabled
11 = Reserved
12
GP1_INT_MOD
E
0
GPIO1 Interrupt Mode
0 = GPIO interrupt is rising edge triggered (if
GP1_POL=1) or falling edge triggered (if GP1_POL=0)
1 = GPIO interrupt is triggered on rising and falling
edges
11
GP1_PWR_DO
M
0
GP1_POL
1
GPIO1 Power Domain select
0 = DBVDD
1 = PMICVDD (LDO12)
10
GPIO1 Polarity select
0 = Inverted (active low)
1 = Non-Inverted (active high)
9
GP1_OD
0
GPIO1 Output pin configuration
0 = CMOS
1 = Open Drain
8
GP1_ENA
0
GPIO1 Enable control
0 = GPIO pin is tri-stated
1 = Normal operation
7:4
GP1_FN [3:0]
0000
GPIO1 Pin Function
Input functions:
0 = GPIO input (long de-bounce)
1 = GPIO input
2 = Power On/Off request
3 = Sleep/Wake request
4 = Sleep/Wake request (long de-bounce)
5 = Sleep request
6 = Power On request
7 = Watchdog Reset input
8 = DVS1 input
9 = DVS2 input
10 = HW Enable1 input
11 = HW Enable2 input
12 = HW Control1 input
13 = HW Control2 input
14 = HW Control1 input (long de-bounce)
15 = HW Control2 input (long de-bounce)
Output functions:
0 = GPIO output
1 = 32.768kHz oscillator output
2 = ON state
3 = SLEEP state
4 = Power State Change
5 = Reserved
6 = Reserved
7 = Reserved
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
8 = DC-DC1 DVS Done
9 = DC-DC2 DVS Done
10 = External Power Enable1
11 = External Power Enable2
12 = System Supply Good (SYSOK)
13 = Converter Power Good (PWR_GOOD)
14 = External Power Clock (2MHz)
15 = Auxiliary Reset
3
CLKOUT_SRC
0
CLKOUT output source select
0 = FLL output
1 = 32.768kHz oscillator
1
XTAL_INH
0
Crystal Start-Up Inhibit
0 = Disabled
1 = Enabled
When XTAL_INH=1, the ‘ON’ transition is inhibited until
the crystal oscillator is valid
0
CHG_ENA
0
Battery Charger Enable
0 = Disable
1 = Enable
Protected by security key.
Register 781Ah GPIO1 OTP Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R30747
(781Bh)
GPIO2 OTP
Control
15
GP2_DIR
1
GPIO2 pin direction
0 = Output
1 = Input
14:13
GP2_PULL
[1:0]
01
GPIO2 Pull-Up / Pull-Down configuration
00 = No pull resistor
01 = Pull-down enabled
10 = Pull-up enabled
11 = Reserved
12
GP2_INT_MOD
E
0
GPIO2 Interrupt Mode
0 = GPIO interrupt is rising edge triggered (if
GP2_POL=1) or falling edge triggered (if GP2_POL=0)
1 = GPIO interrupt is triggered on rising and falling
edges
11
GP2_PWR_DO
M
0
GP2_POL
1
GPIO2 Power Domain select
0 = DBVDD
1 = PMICVDD (LDO12)
10
GPIO2 Polarity select
0 = Inverted (active low)
1 = Non-Inverted (active high)
9
GP2_OD
0
GPIO2 Output pin configuration
0 = CMOS
1 = Open Drain
8
GP2_ENA
0
GPIO2 Enable control
0 = GPIO pin is tri-stated
1 = Normal operation
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
7:4
GP2_FN [3:0]
0000
GPIO2 Pin Function
Input functions:
0 = GPIO input (long de-bounce)
1 = GPIO input
2 = Power On/Off request
3 = Sleep/Wake request
4 = Sleep/Wake request (long de-bounce)
5 = Sleep request
6 = Power On request
7 = Watchdog Reset input
8 = DVS1 input
9 = DVS2 input
10 = HW Enable1 input
11 = HW Enable2 input
12 = HW Control1 input
13 = HW Control2 input
14 = HW Control1 input (long de-bounce)
15 = HW Control2 input (long de-bounce)
Output functions:
0 = GPIO output
1 = 32.768kHz oscillator output
2 = ON state
3 = SLEEP state
4 = Power State Change
5 = Reserved
6 = Reserved
7 = Reserved
8 = DC-DC1 DVS Done
9 = DC-DC2 DVS Done
10 = External Power Enable1
11 = External Power Enable2
12 = System Supply Good (SYSOK)
13 = Converter Power Good (PWR_GOOD)
14 = External Power Clock (2MHz)
15 = Auxiliary Reset
3:1
CLKOUT_SLO
T [2:0]
000
CLKOUT output enable slot select
000 = Do not enable
001 = Enable in Timeslot 1
010 = Enable in Timeslot 2
011 = Enable in Timeslot 3
100 = Enable in Timeslot 4
101 = Enable in Timeslot 5
110 = Controlled by Hardware Enable 1
111 = Controlled by Hardware Enable 2
0
WDOG_ENA
1
Watchdog Timer Enable
0 = Disabled
1 = Enabled (enables the watchdog; does not reset it)
Protected by security key.
Register 781Bh GPIO2 OTP Control
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R30748
(781Ch)
GPIO3 OTP
Control
15
GP3_DIR
1
GPIO3 pin direction
0 = Output
1 = Input
14:13
GP3_PULL
[1:0]
01
GPIO3 Pull-Up / Pull-Down configuration
00 = No pull resistor
01 = Pull-down enabled
10 = Pull-up enabled
11 = Reserved
12
GP3_INT_MOD
E
0
GPIO3 Interrupt Mode
0 = GPIO interrupt is rising edge triggered (if
GP3_POL=1) or falling edge triggered (if GP3_POL=0)
1 = GPIO interrupt is triggered on rising and falling
edges
11
GP3_PWR_DO
M
0
GP3_POL
1
GPIO3 Power Domain select
0 = DBVDD
1 = PMICVDD (LDO12)
10
GPIO3 Polarity select
0 = Inverted (active low)
1 = Non-Inverted (active high)
9
GP3_OD
0
GPIO3 Output pin configuration
0 = CMOS
1 = Open Drain
8
GP3_ENA
0
GPIO3 Enable control
0 = GPIO pin is tri-stated
1 = Normal operation
7:4
GP3_FN [3:0]
0000
GPIO3 Pin Function
Input functions:
0 = GPIO input (long de-bounce)
1 = GPIO input
2 = Power On/Off request
3 = Sleep/Wake request
4 = Sleep/Wake request (long de-bounce)
5 = Sleep request
6 = Power On request
7 = Watchdog Reset input
8 = DVS1 input
9 = DVS2 input
10 = HW Enable1 input
11 = HW Enable2 input
12 = HW Control1 input
13 = HW Control2 input
14 = HW Control1 input (long de-bounce)
15 = HW Control2 input (long de-bounce)
Output functions:
0 = GPIO output
1 = 32.768kHz oscillator output
2 = ON state
3 = SLEEP state
4 = Power State Change
5 = Reserved
6 = Reserved
7 = Reserved
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
8 = DC-DC1 DVS Done
9 = DC-DC2 DVS Done
10 = External Power Enable1
11 = External Power Enable2
12 = System Supply Good (SYSOK)
13 = Converter Power Good (PWR_GOOD)
14 = External Power Clock (2MHz)
15 = Auxiliary Reset
3:1
FLL_AUTO_FR
EQ [2:0]
000
FLL Automatic Mode Frequency select
000 = 2.048MHz
001 = 11.2896MHz
010 = 12MHz
011 = 12.288MHz
100 = 19.2MHz
101 = 22.5792MHz
110 = 24MHz
111 = 24.576MHz
Register 781Ch GPIO3 OTP Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R30749
(781Dh)
GPIO4 OTP
Control
15
GP4_DIR
1
GPIO4 pin direction
0 = Output
1 = Input
14:13
GP4_PULL
[1:0]
01
GPIO4 Pull-Up / Pull-Down configuration
00 = No pull resistor
01 = Pull-down enabled
10 = Pull-up enabled
11 = Reserved
12
GP4_INT_MOD
E
0
GPIO4 Interrupt Mode
0 = GPIO interrupt is rising edge triggered (if
GP4_POL=1) or falling edge triggered (if GP4_POL=0)
1 = GPIO interrupt is triggered on rising and falling
edges
11
GP4_PWR_DO
M
0
GP4_POL
1
GPIO4 Power Domain select
0 = DBVDD
1 = SYSVDD
10
GPIO4 Polarity select
0 = Inverted (active low)
1 = Non-Inverted (active high)
9
GP4_OD
0
GPIO4 Output pin configuration
0 = CMOS
1 = Open Drain
8
GP4_ENA
0
GPIO4 Enable control
0 = GPIO pin is tri-stated
1 = Normal operation
7:4
GP4_FN [3:0]
0000
GPIO4 Pin Function
Input functions:
0 = GPIO input (long de-bounce)
1 = GPIO input
2 = Power On/Off request
3 = Sleep/Wake request
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WM8310
Pre-Production
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
4 = Sleep/Wake request (long de-bounce)
5 = Sleep request
6 = Power On request
7 = Watchdog Reset input
8 = DVS1 input
9 = DVS2 input
10 = HW Enable1 input
11 = HW Enable2 input
12 = HW Control1 input
13 = HW Control2 input
14 = HW Control1 input (long de-bounce)
15 = HW Control2 input (long de-bounce)
Output functions:
0 = GPIO output
1 = 32.768kHz oscillator output
2 = ON state
3 = SLEEP state
4 = Power State Change
5 = Reserved
6 = Reserved
7 = Reserved
8 = DC-DC1 DVS Done
9 = DC-DC2 DVS Done
10 = External Power Enable1
11 = External Power Enable2
12 = System Supply Good (SYSOK)
13 = Converter Power Good (PWR_GOOD)
14 = External Power Clock (2MHz)
15 = Auxiliary Reset
3:2
LED1_SRC
[1:0]
11
LED1 Source
Selects the LED1 function.)
00 = Off
01 = Power State Status
10 = Charger Status
11 = Manual Mode
Note - LED1 also indicates completion of OTP Auto
Program
1:0
LED2_SRC
[1:0]
11
LED2 Source
Selects the LED2 function.)
00 = Off
01 = Power State Status
10 = Charger Status
11 = Manual Mode
Note - LED2 also indicates an OTP Auto Program Error
condition
Register 781Dh GPIO4 OTP Control
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WM8310
REGISTER
Pre-Production
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R30750
(781Eh)
GPIO5 OTP
Control
15
GP5_DIR
1
GPIO5 pin direction
0 = Output
1 = Input
14:13
GP5_PULL
[1:0]
01
GPIO5 Pull-Up / Pull-Down configuration
00 = No pull resistor
01 = Pull-down enabled
10 = Pull-up enabled
11 = Reserved
12
GP5_INT_MOD
E
0
GPIO5 Interrupt Mode
0 = GPIO interrupt is rising edge triggered (if
GP5_POL=1) or falling edge triggered (if GP5_POL=0)
1 = GPIO interrupt is triggered on rising and falling
edges
11
GP5_PWR_DO
M
0
GP5_POL
1
GPIO5 Power Domain select
0 = DBVDD
1 = SYSVDD
10
GPIO5 Polarity select
0 = Inverted (active low)
1 = Non-Inverted (active high)
9
GP5_OD
0
GPIO5 Output pin configuration
0 = CMOS
1 = Open Drain
8
GP5_ENA
0
GPIO5 Enable control
0 = GPIO pin is tri-stated
1 = Normal operation
7:4
GP5_FN [3:0]
0000
GPIO5 Pin Function
Input functions:
0 = GPIO input (long de-bounce)
1 = GPIO input
2 = Power On/Off request
3 = Sleep/Wake request
4 = Sleep/Wake request (long de-bounce)
5 = Sleep request
6 = Power On request
7 = Watchdog Reset input
8 = DVS1 input
9 = DVS2 input
10 = HW Enable1 input
11 = HW Enable2 input
12 = HW Control1 input
13 = HW Control2 input
14 = HW Control1 input (long de-bounce)
15 = HW Control2 input (long de-bounce)
Output functions:
0 = GPIO output
1 = 32.768kHz oscillator output
2 = ON state
3 = SLEEP state
4 = Power State Change
5 = Reserved
6 = Reserved
7 = Reserved
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REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
8 = DC-DC1 DVS Done
9 = DC-DC2 DVS Done
10 = External Power Enable1
11 = External Power Enable2
12 = System Supply Good (SYSOK)
13 = Converter Power Good (PWR_GOOD)
14 = External Power Clock (2MHz)
15 = Auxiliary Reset
3:1
USB_ILIM [2:0]
010
Sets the USB current limit
000 = 0mA (USB switch is open)
001 = 2.5mA
010 = 100mA
011 = 500mA
100 = 900mA
101 = 1500mA
110 = 1800mA
111 = 550mA
Register 781Eh GPIO5 OTP Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R30751
(781Fh)
GPIO6 OTP
Control
15
GP6_DIR
1
GPIO6 pin direction
0 = Output
1 = Input
14:13
GP6_PULL
[1:0]
01
GPIO6 Pull-Up / Pull-Down configuration
00 = No pull resistor
01 = Pull-down enabled
10 = Pull-up enabled
11 = Reserved
12
GP6_INT_MOD
E
0
GPIO6 Interrupt Mode
0 = GPIO interrupt is rising edge triggered (if
GP6_POL=1) or falling edge triggered (if GP6_POL=0)
1 = GPIO interrupt is triggered on rising and falling
edges
11
GP6_PWR_DO
M
0
GP6_POL
1
GPIO6 Power Domain select
0 = DBVDD
1 = SYSVDD
10
GPIO6 Polarity select
0 = Inverted (active low)
1 = Non-Inverted (active high)
9
GP6_OD
0
GPIO6 Output pin configuration
0 = CMOS
1 = Open Drain
8
GP6_ENA
0
GPIO6 Enable control
0 = GPIO pin is tri-stated
1 = Normal operation
7:4
GP6_FN [3:0]
0000
GPIO6 Pin Function
Input functions:
0 = GPIO input (long de-bounce)
1 = GPIO input
2 = Power On/Off request
3 = Sleep/Wake request
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BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
4 = Sleep/Wake request (long de-bounce)
5 = Sleep request
6 = Power On request
7 = Watchdog Reset input
8 = DVS1 input
9 = DVS2 input
10 = HW Enable1 input
11 = HW Enable2 input
12 = HW Control1 input
13 = HW Control2 input
14 = HW Control1 input (long de-bounce)
15 = HW Control2 input (long de-bounce)
Output functions:
0 = GPIO output
1 = 32.768kHz oscillator output
2 = ON state
3 = SLEEP state
4 = Power State Change
5 = Reserved
6 = Reserved
7 = Reserved
8 = DC-DC1 DVS Done
9 = DC-DC2 DVS Done
10 = External Power Enable1
11 = External Power Enable2
12 = System Supply Good (SYSOK)
13 = Converter Power Good (PWR_GOOD)
14 = External Power Clock (2MHz)
15 = Auxiliary Reset
3:1
SYSOK_THR
[2:0]
101
SYSOK threshold (rising SYSVDD)
This is the rising SYSVDD voltage at which SYSOK will
be asserted
000 = 2.8V
001 = 2.9V
…
111 = 3.5V
Note that the SYSOK hysteresis margin is added to
these threshold levels.
Register 781Fh GPIO6 OTP Control
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R30759
(7827h) ICE
CHECK
DATA
15:0
ICE_VALID_D
ATA [15:0]
0000_0000 This field is checked in development mode when an
_0000_000 ‘ON’ transition is requested. A value of A596h is
0
required to confirm valid data.
Register 7827h ICE CHECK DATA
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30 APPLICATIONS INFORMATION
30.1 TYPICAL CONNECTIONS
SYSVDD
CPU ARM Core
CPU Internal Logic & Caches
Memory NOR / DDR_SDRAM
Backlight LED Supply
R1
CPU ALIVE
LDO11VOUT
CPU_PLL
LDO10VOUT
White LED
backlight
DC4FB
DC4GND
DC4LX
DC4VDD
DC3GND
DC3LX
DC3FB
DC2GND
DC2LX
DC2FB
DC1GND
DC1LX
DC1FB
R2
ISINK2
ISINK1
LED2
WiFi
LDO9VOUT
HD Radio RF
LDO8VOUT
HD Radio Core
LDO7VOUT
ISINKGND
LDO6VOUT
DBGND
Mobile TV
LED1
LDO5VOUT
CPU_IO_Block
CPU_DAC
LDO4VOUT
CPU_ADC
LDO3VOUT
CPU_RTC
LDO2VOUT
CPU_OTG
LDO1VOUT
SYSVDD
CC Sink
Charger ON
Power status
GND
AUXADCIN4
AUXADCIN3
AUXADCIN2
AUXADCIN1
External voltage
measurement
inputs
VREFC
IREFR
REFGND
WM8310
LDO13VOUT
Backup Battery
LDO12VOUT
GPIO12
GPIO11
GPIO10
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
BATTVDD
BATTVMON
NTCMON
NTCBIAS
XOSCGND
/ IRQ
XTI
XTO
DCDC1VDD
32kHz
DBVDD
/ RESET
/ ON
32kHz IN
/ WALLFETENA
SYSVMON
DCDC2VDD
CLKOUT
CLKIN
12.288MHz MCLK OUT
DCDC3VOUT
DCDC3VDD
WALLVDD
/ CS
CIFMODE
PROGVDD
USBVMON
Device ID 34h
2 wire I2C
USBVDD
SDA1
SCLK1
DBVDD
PVDD
/ BATTFETENA
2 wire I2C
slave
DCDC3VOUT
LDO8VDD
LDO7VDD
LDO6VDD
LDO5VDD
LDO4VDD
LDO3VDD
LDO2VDD
LDO1VDD
SDOUT
SDA2
SCLK2
Configuration
data loaded
from internal
OTP
LDO10VDD
LDO9VDD
SYSVDD
General
Purpose
Input/Output
pins
NTC
SingleCell
Li-ion
Battery
USB
Power In
System
Power In
Figure 33 WM8310 Typical Connections Diagram
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For detailed schematics, bill of materials and recommended external components refer to the
WM8310 evaluation board users manual.
30.2 VOLTAGE AND CURRENT REFERENCE COMPONENTS
A decoupling capacitor is required between VREFC and REFGND; a 100nF X5R capacitor is
recommended (available in 0201 package size). If USB100MA_STARTUP=1X (see Section 17.4),
then a 50nF capacitor should be used.
A current reference resistor is required between IREFR and REFGND; a 100k (1%) resistor is
recommended.
30.3 DC-DC BUCK CONVERTER EXTERNAL COMPONENTS
The recommended connections to the DC-DC buck converters are illustrated in Figure 34.
Figure 34 DC-DC Synchronous Buck Converter External Components
When selecting suitable capacitors, is it imperative that the effective capacitance is within the
required limits at the applicable input/output voltage of the converter. It should be noted that some
components’ capacitance changes significantly depending on the DC voltage applied. Ceramic X7R
or X5R types are recommended.
The choice of output capacitor varies depending on the required transient response. Larger values
may be required for optimum performance under large load transient conditions. Smaller values may
be sufficient for a steady load, or in applications without stringent requirements on output voltage
accuracy during load transients.
For layout and size reasons, users may choose to implement large values of output capacitance by
connecting two or more capacitors in parallel. To ensure stable operation, the DCm_CAP register
fields must be set according to the output capacitance, as described in Section 15.6.
When selecting a suitable output inductor, the inductance value and the saturation current must be
compatible with the operating conditions of the converter.
The magnitude of the inductor current ripple is dependant on the inductor value and can be
determined by the following equation:
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As a minimum requirement, the DC current rating should be equal to the maximum load current plus
one half of the inductor current ripple:
To be suitable for the application, the chosen inductor must have a saturation current that is higher
than the peak inductor current given by the above equation. To maximise the converter efficiency, the
inductor should also have a low DC Resistance (DCR), resulting in minimum conduction losses. Care
should also be taken to ensure that the component’s inductance is valid at the applicable operating
temperature.
The WM8310 incorporates a current-limit protection feature for all DC-DC Buck Converter outputs. In
order to achieve the benefit of this feature, the output inductor saturation current limit must be greater
than or equal to the P-channel Current Limit for the applicable converter (see Section 7).
Wolfson recommends the following external components for use with DC-DC Converters 1 and 2.
The output inductor must be consistent with the DCm_FREQ register settings. The supported
configurations are listed in Table 107. Note that for output voltages greater than 1.4V, the 2MHz
mode must be used.
DCm_FREQ
SWITCHING
FREQUENCY
OUTPUT
INDUCTOR
COMMENTS
00
n/a
n/a
n/a
01
2MHz
2.2H
Best efficiency
10
n/a
n/a
n/a
11
4MHz
0.5H
Best transient performance
Table 107 Output Inductor Selection - DC-DC1, DC-DC2
The output capacitor must be consistent with the DCm_CAP register settings. For best performance,
the 47F component is recommended. For typical applications, the 22F is suitable. The alternative
values may be used for size or cost reasons if preferred.
COMPONENT
VALUE
PART NUMBER
SIZE
L
0.5H
Coilcraft XPL2010-501MLB
2 x 2.5 x 1mm
2.2H
COUT
CIN
Coilcraft LPS3015-222ML
3 x 3 x 1.5mm
TDK VLS252012T-2R2M1R3
2 x 1.25 x 1.2mm
47F
MuRata GRM21BR60G476MEA1
0805
22F
MuRata GRM21BR60J226ME39
0805
0603
10F
MuRata GRM188R60J106ME84
4.7F
MuRata GRM188R60J475ME84
0603
10F
MuRata GRM188R60J106ME84
0603
Table 108 Recommended External Components - DC-DC1, DC-DC2
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Wolfson recommends the following external components for use with DC-DC Converter 3.
Note that the switching frequency of DC-DC3 is fixed at 2MHz and the output inductor must be 2.2H
in all cases.
The output capacitor must be consistent with the DC3_CAP register setting. For best performance,
the 47F component is recommended. For typical applications, the 22F is suitable. The alternative
values may be used for size or cost reasons if preferred.
COMPONENT
VALUE
PART NUMBER
SIZE
L
2.2H
Coilcraft LPS3015-222ML
3 x 3 x 1.5mm
TDK VLS252012T-2R2M1R3
2 x 1.25 x 1.2mm
COUT
47F
MuRata GRM21BR60G476MEA1
0805
22F
MuRata GRM21BR60J226ME39
0805
10F
MuRata GRM188R60J106ME84
0603
4.7F
MuRata GRM188R60J475ME84
0603
CIN
Table 109 Recommended External Components - DC-DC3
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30.4 DC-DC (STEP-UP) CONVERTER EXTERNAL COMPONENTS
The recommended connections to the DC-DC (Step-Up) Converter are illustrated in Figure 35.
Figure 35 DC-DC (Step-Up) Converters External Components
In the constant current mode, the DC-DC Converter output voltage is controlled by the WM8310 in
order to achieve the required current in ISINK1 or ISINK2. The required current is set by the
CSn_ISEL register fields, as described in Section 16.2.2. A typical application for this mode would be
a white LED driver, where several LEDs are connected in series to achieve uniform brightness.
The DC-DC (Step-Up) Converter is capable of generating output voltages of up to 30V. The maximum
output voltage is determined by the two external resistors R1 and R2, which form a resistive divider
between load connection and the voltage feedback pin DC4FB. The maximum output voltage is set
as described in the following equation:
Setting R2 to 47kΩ is recommended for most applications; R1 can be calculated using the following
equation, given the required output voltage:
R1 = R2 . (2VOUT – 1)
Note that the resistors determine the maximum output voltage. The actual voltage will be determined
by the selected ISINK current, subject to the device limits.
When selecting a suitable capacitor, is it imperative that the effective capacitance is within the
required limits at the applicable input/output voltage of the converter. Ceramic X7R or X5R types are
recommended. The choice of output capacitor for DC-DC4 varies depending on the required output
voltage. See Table 110 for further details.
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When selecting a suitable output inductor, the inductance value and the saturation current must be
compatible with the operating conditions of the converter.
The magnitude of the inductor current ripple is dependent on the inductor value and can be
determined by the following equation:
The inductor current is also a function of the DC-DC Converter maximum input current, which can be
determined by the following equation:
As a minimum requirement, the DC current rating should be equal to the maximum input current plus
one half of the inductor current ripple.
To be suitable for the application, the chosen inductor must have a saturation current that is higher
than the peak inductor current given by the above equation. To maximise the converter efficiency, the
inductor should also have a low DC Resistance (DCR), resulting in minimum conduction losses. Care
should also be taken to ensure that the component’s inductance is suitable at the applicable
operating temperature.
Wolfson recommends the following external components for use with DC-DC Converter 4.
The output capacitor COUT must be selected according to the required output voltage. For 10V output,
4.7F is recommended. For 15V output, 3.3F is recommended. For 20-30V output, 1.5F is
recommended.
The resistors R1 and R2 must be selected according to the required output voltage - refer to the
equations above. The values quoted below are suitable for 20V output.
COMPONENT
VALUE
PART NUMBER
SIZE
L
10H
Taiyo-Yuden NR3015T100M
3 x 3 x 1.5mm
COUT
4.7F
Murata GRM31CR61C475KA01
1206
3.3F
Murata GRM31CR71C335KA01
1206
1.5F
MuRata GRM31CR71H225KA88
1206
2.2F
MuRata GRM188R61A5KE34
0603
CIN
FET +
shottky diode
Vishay SIA814DJ-T1-GE3
SC-70-6
2.05 x 2.05 x
0.75mm
R1
1.8M
Phycomp 2322 7046 1805
0603
R2
47k
Multicomp MIC 0.063W 0603 1% 47K
0603
Table 110 Recommended External Components - DC-DC4
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30.5 LDO REGULATOR EXTERNAL COMPONENTS
The recommended connections to the LDO Regulators are illustrated in Figure 36.
Figure 36 LDO Regulators External Components
When selecting suitable capacitors, is it imperative that the effective capacitance is within the
required limits at the applicable input/output voltage of the converter. Ceramic X7R or X5R types are
recommended.
Wolfson recommends the following external components for use with LDO Regulators 1 to 6.
COMPONENT
VALUE
PART NUMBER
SIZE
COUT
2.2μF
Kemet C0402C225M9PAC
0402
CIN
1.0μF
MuRata GRM155R61A105KE15
0402
Table 111 Recommended External Components - LDO1 to LDO6
Wolfson recommends the following external components for use with LDO Regulators 7 to 10. For
these regulators, note that it is important that the output capacitance, COUT, does not exceed 4.7F.
COMPONENT
VALUE
PART NUMBER
SIZE
COUT
1.0μF
MuRata GRM155R61A105KE15
0402
CIN
1.0μF
MuRata GRM155R61A105KE15
0402
Table 112 Recommended External Components - LDO7 to LDO10
Wolfson recommends the following external components for use with LDO Regulators 11 to 13.
COMPONENT
VALUE
PART NUMBER
SIZE
COUT (LDO11)
0.1μF
MuRata GRM033R60J104KE19
0201
COUT (LDO12)
0.1μF
MuRata GRM033R60J104KE19
0201
COUT (LDO13)
2.2μF
Kemet C0402C225M9PAC
0402
Table 113 Recommended External Components - LDO11 to LDO13
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30.6 BATTERY TEMPERATURE MONITORING COMPONENTS
Battery temperature monitoring is performed using a reference voltage output on the NTCBIAS pin. A
potential divider is formed between the NTC bias resistor and the NTC thermistor component within
the battery pack. The voltage present at the NTCMON pin is used to determine the battery
temperature. The recommended connections and the derivation of VNTCMON is shown in Figure 37.
Figure 37 Battery Temperature Monitoring
The voltage thresholds for the Hot/Cold Battery Temperature conditions are fixed in the WM8310:
The Cold Battery condition is detected when VNTCMON > 0.765 x VNTCBIAS
The Hot Battery condition is detected when VNTCMON < 0.348 x VNTCBIAS
If the NTC thermistor has a nominal resistance of 100k at 25C, and follows the Vishay ResistanceTemperature Curve 1, then the above equations result in the Hot Battery threshold = 40C and the
Cold Battery threshold = 0C.
For example, if the NTC thermistor resistance is 53.4k at 40C, then VNTCMON is given by the
following equation:
The upper and lower temperature thresholds can be adjusted by modification of the NTC bias resistor
and/or the addition of another resistor between the battery pack and the NTCMON pin.
If only the NTC bias resistor is adjusted, then either the upper or lower threshold can be selected, but
not both; the other threshold will be determined by the thermistor characteristics.
If an additional resistor is inserted between the battery pack and the NTCMON pin, then the upper
and lower thresholds can be independently selected, with the constraint that the upper and lower
thresholds must be at least 40C apart.
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To select a specific Hot Battery threshold, the required NTC bias resistor value may be calculated
using the following equation:
RBIAS = (rHOT / 0.534) x R25
rHOT is the NTC thermistor resistance ratio at the desired temperature threshold
R25 is the NTC thermistor resistance at 25C
For example, at 60C the Vishay Curve 1 resistance ratio, rHOT, is 0.2488.
Therefore, to implement a 60C Hot Battery threshold, assuming a 100k NTC thermistor (at 25C),
the required NTC bias resistor is 46.6k (nearest E12 value 47k).
The resultant Cold Battery threshold is given using the rCOLD equation below. The rCOLD value needs to
be referenced to the Vishay Curve 1 resistance chart in order to find the corresponding temperature.
To select a specific Cold Battery threshold, the required NTC bias resistor value may be calculated
using the following equation:
RBIAS = (rCOLD / 3.255) x R25
rCOLD is the NTC thermistor resistance ratio at the desired temperature threshold
R25 is the NTC thermistor resistance at 25C
For example, at 5C the Vishay Curve 1 resistance ratio, rCOLD, is 2.540.
Therefore, to implement a 5C Cold Battery threshold, assuming a 100k NTC thermistor (at 25C),
the required NTC bias resistor is 78k (nearest E12 value 82k).
The resultant Hot Battery threshold is given using the rHOT equation below. The rHOT value needs to be
referenced to the Vishay Curve 1 resistance chart in order to find the corresponding temperature.
NTC
To select both the Hot Battery threshold and the Cold Battery threshold, an additional resistor, R1, is
required, as illustrated in Figure 38.
Figure 38 Battery Temperature Threshold Selection
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Under the circuit configuration above, the NTC bias resistors RBIAS and R1 are calculated using the
following equations:
RBIAS = ((rCOLD - rHOT) / 2.721) x R25
R1 = (0.534 x RBIAS) - (rHOT x R25)
For example, to select a 45C Hot Battery threshold and a 0C Cold Battery threshold, the applicable
resistance ratios are rHOT = 0.4368 and rCOLD = 3.266.
Assuming a 100k NTC thermistor (at 25C), then R25 = 100k.
From the equations above, it follows that RBIAS = 104k (nearest E12 value 100k).
Assuming the E12 (100k) value of RBIAS, then R1 = 9.72k (nearest E12 value 10k).
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30.7 PCB LAYOUT
Poor PCB layout will degrade the performance and be a contributory factor in EMI, ground bounce
and resistive voltage losses. Poor regulation and instability can result.
Simple design rules can be implemented to negate these effects:
External input and output capacitors should be placed as close to the device as possible using short
wide traces between the external power components. For the DC-DC Converters, the input capacitor
placement takes priority on the DC-DC converters. (For the LDO Regulators, the placement of the
input and output capacitors have equal priority.)
Route the DC-DC converter output voltage feedback as an independent connection to the top of the
output capacitor to create a true sense of the output voltage, routing away from noisy signals such as
the LX connection.
Use a local ground island for each individual DC-DC converter connected at a single point onto a fully
flooded ground plane.
Current loop areas should be kept as small as possible with loop areas changing little during
alternating switching cycles.
Studying the layout below shows, for example, DC-DC1 layout with external components C3, L3 and
C6. The input capacitor, C6, is close into the IC and shares a small ground island with the output
capacitor C3. The inductor, L3, is situated in close proximity to C3 in order to keep loop area small
and minimise the trace resistance. Note also the use of short wide traces with all power tracking on a
single (top) layer.
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31 PACKAGE DIAGRAM
B: 169 BALL BGA PLASTIC PACKAGE 7 X 7 X 1.2 mm BODY, 0.50 mm BALL PITCH
DM062.C
5
2
DETAIL 1
A
A2
13
12
11 10
9
8
7
6
5
4
3
2
D
1
A
A1
CORNER
4
B
C
D
E
F
e
G
E1
E
6
H
J
K
L
M
N
2X
2X
DETAIL 2
e
D1
SIDE VIEW
BOTTOM VIEW
0.10 Z
0.10 Z
TOP VIEW
SOLDER BALL
bbb Z
aaa Z
1
Z
b
A1
DETAIL 2
NOM
MIN
A
D
D1
E
E1
e
3
ccc Z X Y
ddd Z
Dimensions (mm)
Symbols
A1
A2
b
DETAIL 1
MAX
1.20
NOTE
0.21
0.11
0.91 REF
0.30
7.00 BSC
6.00 BSC
7.00 BSC
6.00 BSC
0.50 BSC
Tolerances of Form and Position
0.20
aaa
bbb
ccc
ddd
0.08
0.20
0.15
REF:
JEDEC, MO-195, VARIATION AD
6
0.08
NOTES:
1. PRIMARY DATUM -Z- AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.
2. THIS DIMENSION INCLUDES STAND-OFF HEIGHT ‘A1’.
3. DIMENSION ‘b’ IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM -Z-.
4. A1 CORNER IS IDENTIFIED BY INK/LASER MARK ON TOP PACKAGE.
5. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY.
6. ‘e’ REPRESENTS THE BASIC SOLDER BALL GRID PITCH.
7. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
8. FALLS WITHIN JEDEC, MO-195
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32 IMPORTANT NOTICE
Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,
delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the
right to make changes to its products and specifications or to discontinue any product or service without notice. Customers
should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.
Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating
safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product
design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such
selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where
malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any
use of products by the customer for such purposes is at the customer’s own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual
property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might
be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval,
licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective
third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is
accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not
liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in
this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted
at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed
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PP, May 2012, Rev 3.1
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WM8310
Pre-Production
33 REVISION HISTORY
DATE
REV
18/02/10
3.1
DESCRIPTION OF CHANGES
CHANGED
BY
Updated definition of DCn_SOFT_START registers
PH
RST_DUR description updated
Updated description of AUX_CVT_ENA - measurement data is not available
until the associated interrupt is set.
AUXADC input impedance corrected to 400kohm.
24/06/10
3.1
Amended LDO12 current capability to 2mA.
PH
Amended LDO13 current capability to 20mA
DC4 maximum current spec restored to 90mA.
DC4 Elec Chars updated to include 90mA for Vload ≤ 8V.
DC4_RANGE updated to support Vout >= 6.5V only.
Amended Test Conditions for LDO4, 5, 6 to be same as others.
Clarified (in Section 13) the 32.768kHz GPIO output only supported in OFF state
if the selected power domain remains on.
Clarified (in Section 21) the External Power Clock is controlled in the power
sequences via EPE1 or EPE2.
Updated wording and terminology, making consistent with other PMIC
datasheets. Review input from WM8321 incorporated as applicable.
DORW replaced with DCRW.
DBE replaced with InstantConfig™ EEPROM (ICE).
Added SDOUT1 pull-up requirement.
Typical connections drawing updated to show XOSCGND close to XTI/XTO pins
and to include DC-DC output capacitors.
22/07/10
3.1
Noted maximum output capacitance for LDO7-LDO10 (4.7uF).
PH
Updates regarding Battery Charger Interrupts preventing SLEEP transitions CHG_START_EINT must be cleared first.
Clarification added to CLKOUT function when XTAL_INH=1.
Correction to pin C5 - this is DC3GND.
DBVDD1, DBVDD2, DBVDD3 domains merged into DBVDD.
PVDD1, PVDD2 domains merged into PVDD.
Watchdog description updated wrt Device Reset response.
SDOUT1 description updated as an Open Drain output, with pull-up resistor
required.
“Register Map by Address” section updated.
Default value of PWRSTATE_DLY corrected.
24/11/10
3.1
CE000609 errata added (OTP Command End Interrupt)
PH
CE000610 errata added (DC3 quiescent current in LDO mode)
CE000611 errata added (Power Sequence in failure conditions)
CE000613 errata added (DC4 Hardware Control)
CE000614 errata added (FLL Register readback)
CE000649 errata added (Watchdog timeout)
3/12/10
3.1
Undervoltage margin specified for DC-DC converters 1,2,3.
PH
Overvoltage margin specified for DC-DC converters 1,2.
Chip Temperature (AUX_DATA) equation updated.
NTCBIAS voltage added to Electrical Characteristics.
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PP, May 2012, Rev 3.1
290
WM8310
Pre-Production
DATE
REV
07/03/11
3.1
DESCRIPTION OF CHANGES
CHANGED
BY
RTC_PINT_FREQ definition updated.
PH
Added notes that SLEEP > OFF is not a controlled transition; converters and
regulators are disabled immediately.
RESET pin description updated to note integrated pull-up.
IRQ description updated to note pull-up in Open Drain mode.
System Reset and Device Reset descriptions updated, consistent with the
Summary Table.
Recommended external pull-up resistances added in Pin Description.
Internal pull-up / pull-down resistances added in Electrical Characteristics.
CE000612 errata added (GPn_POL in development mode)
28/03/11
3.1
Noted maximum limit on Software Resets. Also clarification of the maximum
number of Watchdog / Undervoltage Device Resets.
PH
CE000607 errata added (Device start-up, USB_ILIM < 100mA).
CE000608 errata added (Power up failure, USB100MA_STARTUP = 10 or 11).
28/06/11
3.1
DC-DC output inductor saturation limit recommendations added.
PH
SYSOK_THR register description updated.
21/09/11
3.1
Backup battery power updated; Backup charger control registers deleted.
PH
LDO11 output amended for LDO11_VSEL_SRC=1 and DC-DC1 disabled.
17/04/12
3.1
Order codes changed from WM8310GEB/V and WM8310GEB/RV to
WM8310CGEB/V and WM8310CGEB/RV to reflect change to copper wire
bonding.
JMacD
17/04/12
3.1
Package Diagram updated to DM062C to reflect change to copper wire bonding.
JMacD
02/05/12
3.1
Electrical Characteristics updated
PH
LDO7, 8, 9, 10 input voltage range updated.
LDO11 current rating updated.
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PP, May 2012, Rev 3.1
291