November 2000 Revision 2.01 PC87365 128-Pin LPC SuperI/O with System Hardware Monitoring General Description Outstanding Features The PC87365, a member of National Semiconductor’s 128pin LPC SuperI/O family, features National’s new System Hardware Monitoring capability. The PC87365 is PC99 and ACPI compliant, and offers a single-chip solution to the most commonly used PC I/O peripherals. System Hardware Monitoring provides minimum power consumption and maximum operating efficiency within the system environment. It integrates National’s Voltage Level Monitor (VLM) which monitors system voltages using 8-bit Analog to Digital (A/D) conversion, seven analog input channels and VREF input, and National’s diode input Temperature Sensor for full, PC system thermal control. The PC87365 also incorporates: Fan Speed Control and Monitor (FSCM) for three fans, extended wake-up support for a wide range of wake-up events, system design protection features, a Floppy Disk Controller (FDC), a Keyboard and Mouse Controller (KBC), ACCESS.bus® Interface (ACB), System Wake-Up Control (SWC), General-Purpose Input/Output (GPIO) support for 40 ports, Interrupt Serializer for Parallel IRQs, an enhanced WATCHDOG Timer (WDT), a full IEEE 1284 Parallel Port and two enhanced Serial Ports (UARTs), one with Infrared (IR) support. ● System Hardware Monitoring including: — Diode-based Temperature Sensor (TMS) — Voltage Level Monitor (VLM) with VID inputs ● Extended Wake-Up support, including legacy/ACPI power button support, direct power supply control in response to wake-up events, power-fail recovery ● Protection features, including I/O access lock, chassis hood lock/unlock, chassis intrusion detection, GPIO lock and pin configuration lock ● Fan Speed Control and Monitor for three fans ● Serial IRQ support (15 options) ● Interrupt Serializer (11 Parallel IRQs to Serial IRQ) ● Bus interface, based on Intel’s LPC Interface Specification Revision 1.0, September 29th, 1997 ● ACCESS.bus Interface, SMbus® physical layer compatible ● 40 GPIO Ports (29 standard, including 15 with Assert IRQ/SMI/PWUREQs interrupts; 11 VSB powered) ● Blinking LEDs ● 128-pin PQFP Package Block Diagram Serial Interface Serial Infrared Interface Interface Ports Floppy Drive Interface Serial Port 1 Serial Port 2 with IR GPIO Ports Floppy Disk Controller AV DD VDD VBdAT VSB System Wake-Up Control I/O ACCESS.bus Interface Power Wake-Up PWUREQ SCL Control Events SDA WATCHDOG Timer WDO Parallel Port LPC Serial Analog Diode Interface Interface IRQ SMI Inputs VREF Interface Bus Interface System Hardware Monitoring Keyboard & Mouse Controller Interrupt Serializer IEEE 1284 Parallel Port Fan Speed Control & Monitor 3 Control 3 Monitor Keyboard & Ports Mouse I/F Outputs Inputs Parallel IRQs National Semiconductor is a registered trademark of National Semiconductor Corporation. All other brand or product names are trademarks or registered trademarks of their respective holders. © 2000 National Semiconductor Corporation www.national.com PC87365 128-Pin LPC SuperI/O with System Hardware Monitoring PRELIMINARY Features (Continued) • Features • — 11 Parallel IRQs to Serial IRQ — IRQ sharing with internal IRQs Voltage Level Monitor (VLM) — Seven analog inputs that can support both positive and negative voltages — Four internal measuring points — Internal or external VREF • Temperature Sensor (TMS) • — Up to two remote diode inputs — A/D analog channels provide thermal inputs to directly sense die temperature of remote diodes — Meets ACPI requirements for thermal management — Standby mode to minimize power consumption • ❏ Four optional 8-bit DMA channels (where applicable) • Protection 40 General-Purpose I/O (GPIO) Ports — Programmable drive type for each output pin (opendrain, push-pull or output disable) — Programmable option for internal pull-up resistor on each input pin — Output lock option — Input debounce mechanism • Parallel Port — Software or hardware control — Enhanced Parallel Port (EPP) compatible with new version EPP 1.9 and IEEE 1284 compliant — EPP support for version EPP 1.7 of the Xircom specification — EPP support as mode 4 of the Extended Capabilities Port (ECP) — IEEE 1284 compliant ECP, including level 2 — Selection of internal pull-up or pull-down resistor for Paper End (PE) pin — PCI bus utilization reduction by supporting a demand DMA mode mechanism and a DMA fairness mechanism — Protection circuit that prevents damage to the parallel port when a printer connected to it powers up or is operated at high voltages, even if the device is in power-down — Output buffers that can sink and source 14 mA Fan Speed Control and Fan Speed Monitor (FSCM) — Supports different fan types — Speed monitoring for three fans ❏ Digital filtering of the tachometer input signal ❏ Alarm for fan slower than programmable threshold speed ❏ Alarm for fan stop — Three speed control lines with Pulse Width Modulation (PWM) ❏ Output signal in the range of 6 Hz to 93.75 KHz ❏ Duty cycle resolution of 1/256 www.national.com Floppy Disk Controller (FDC) — Programmable write protect — FM and MFM mode support — Enhanced mode command for three-mode Floppy Disk Drive (FDD) support — Perpendicular recording drive support for 2.88 MB — Burst and non-burst modes — Full support for IBM Tape Drive register (TDR) implementation of AT and PS/2 drive types — 16-byte FIFO — Software compatible with the PC8477, which contains a superset of the FDC functions in the microDP8473, the NEC microPD765A and the N82077 — High-performance, digital separator — Standard 5.25” and 3.5” FDD support — 29 standard, with Assert IRQ/SMI/PWUREQ for 15 ports — 11 VSB powered • PC99 and ACPI Compliant ❏ 15 IRQ routing options Extended Wake-Up — Chassis intrusion detection (CHASI, CHASO) — Chassis hood lock and unlock control (CHLOCK, CHUNLOCK) — Access lock to I/O ports (XLOCK) — GPIO lock — Pin configuration lock • Synchronous cycles, up to 33 MHz bus clock 8-bit I/O cycles Up to four DMA channels 8-bit DMA cycles Basic read, write and DMA bus cycles are 13 clock cycles long — PnP Configuration Register structure — Flexible resource allocation for all logical devices ❏ Relocatable base address — Legacy and ACPI power button support — Direct power supply control in response to wake-up events — Power-fail recovery • LPC System Interface — — — — — — VID inputs — Meets ACPI and DMI requirements for system voltage monitoring • Interrupt Serializer 2 Features • (Continued) • Serial Port 1 (UART1) — Software compatible with the 16550A and the 16450 — Shadow register support for write-only bit monitoring — UART data rates up to 1.5 Mbaud • — Times out the system based on user-programmable time-out period — System power-down capability for power saving — User-defined trigger events to restart WATCHDOG — Optional routing of WATCHDOG output on IRQ and/or SMI lines Serial Port 2 with Infrared (UART2) — — — — — — — Software compatible with the 16550A and the 16450 Shadow register support for write-only bit monitoring UART data rates up to 1.5 Mbaud HP-SIR ASK-IR option of SHARP-IR DASK-IR option of SHARP-IR Consumer Remote Control supports RC-5, RC-6, NEC, RCA and RECS 80 — Non-standard DMA support − one or two channels — PnP dongle support • • ❏ External modem ring on serial port ❏ Ring pulse or pulse train on the RING input signal ❏ Preprogrammed CEIR address in a preselected standard (NEC, RCA or RC-5) Keyboard and Mouse Controller (KBC) ❏ General-Purpose Input Events ❏ IRQs of internal logical devices — Optional routing of power-up request on IRQ, SMI and/or PWBTOUT — Battery-backed event configuration — Programmable VSB-powered output for blinking LEDs (LED1, LED2) control • Clock Sources — 48 MHz clock input — LPC clock, up to 33 MHz — On-chip low-frequency clock generator for wake-up • Power Supplies — 3.3V supply operation — Main (VDD and AVDD) — Standby (VSB) — Battery backup (VBAT) — All pins are 5V tolerant and back-drive protected, except LPC bus pins ACCESS.bus Interface (ACB) — Serial interface compatible with SMBus physical layer — — — — System Wake-Up Control (SWC) — Power-up request upon detection of Keyboard, Mouse, RI1, RI2, RING activity and General-Purpose Input Events, as follows: ❏ Preprogrammed Keyboard or Mouse sequence — 8-bit microcontroller — Software compatible with the 8042AH and PC87911 microcontrollers — 2 KB custom-designed program ROM — 256 bytes RAM for data — Five programmable dedicated open-drain I/O lines — Asynchronous access to two data registers and one status register during normal operation — Support for both interrupt and polling — 93 instructions — 8-bit timer/counter — Support for binary and BCD arithmetic — Operation at 8 MHz,12 MHz or 16 MHz (programmable option) — Can be customized by using the PC87323, which includes a RAM-based KBC as a development platform for KBC code • WATCHDOG Timer (WDT) • Compatible with Philips’ I2C® ACB master and slave Supports polling and interrupt controlled operation Optional internal pull-up on SDA and SCL pins Strap Configuration — Base Address (BADDR) strap to determine the base address of the Index-Data register pair — Test strap to force the device into test mode (reserved for National Semiconductor use) — Power Supply and LED Configuration (PSLDC0,1) straps to determine the power supply control functions and the VSB power-up defaults of LED2 — Power Supply On Polarity (PSONPOL) strap to set PSON active state and output type 3 www.national.com Datasheet Revision Record Revision Date Status Comments October 1998 Draft 0.1 Specification subject to change without notice October 1998 Draft 0.2 Specification subject to change without notice October 1998 Draft 0.21 Specification subject to change without notice November 1998 Draft 0.3 Specification subject to change without notice January 1999 Preliminary 1.0 Specification subject to change without notice; Power Supply Control and LED sections in Chapter 2 are incomplete July 2000 2.0 Release with B3 errata included November 2000 2.01 TMS/VLM characteristics updated www.national.com 4 Table of Contents Datasheet Revision Record ................................................................................................................... 4 1.0 2.0 Signal/Pin Connection and Description 1.1 CONNECTION DIAGRAM ......................................................................................................... 14 1.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY .................................................................... 15 1.3 PIN MULTIPLEXING ................................................................................................................. 19 1.4 DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................ 21 1.4.1 ACCESS.bus Interface (ACB) .................................................................................... 21 1.4.2 Bus Interface ............................................................................................................... 21 1.4.3 Clock ............................................................................................................................ 21 1.4.4 Fan Speed Control and Monitor (FSCM) ..................................................................... 21 1.4.5 Floppy Disk Controller (FDC) ...................................................................................... 22 1.4.6 General-Purpose Input/Output (GPIO) Ports ............................................................... 23 1.4.7 Infrared (IR) ................................................................................................................. 23 1.4.8 Keyboard and Mouse Controller (KBC) ..................................................................... 24 1.4.9 Parallel Port ............................................................................................................... 24 1.4.10 Power and Ground ..................................................................................................... 25 1.4.11 Protection .................................................................................................................... 26 1.4.12 Serial Port 1 and Serial Port 2 ..................................................................................... 26 1.4.13 Strap Configuration ...................................................................................................... 27 1.4.14 System Hardware Monitoring ...................................................................................... 27 1.4.15 System Wake-Up Control ............................................................................................ 28 1.4.16 WATCHDOG Timer (WDT) ......................................................................................... 28 1.5 INTERNAL PULL-UP AND PULL-DOWN RESISTORS ............................................................ 29 Device Architecture and Configuration 2.1 OVERVIEW ............................................................................................................................... 31 2.2 CONFIGURATION STRUCTURE AND ACCESS ..................................................................... 31 2.2.1 The Index-Data Register Pair ...................................................................................... 31 2.2.2 Banked Logical Device Registers Structure ................................................................ 33 2.2.3 Standard Logical Device Configuration Register Definitions ....................................... 34 2.2.4 Standard Configuration Registers ............................................................................... 36 2.2.5 Default Configuration Setup ........................................................................................ 37 2.2.6 Power States ............................................................................................................... 38 2.2.7 Address Decoding ....................................................................................................... 38 2.3 INTERRUPT SERIALIZER ........................................................................................................ 38 2.4 PROTECTION ........................................................................................................................... 39 2.4.1 Chassis Intrusion Detection ......................................................................................... 39 2.4.2 Chassis Lock and Unlock ............................................................................................ 39 2.4.3 Access Lock to I/O Ports ............................................................................................. 40 2.4.4 Pin Configuration Lock ................................................................................................ 40 2.4.5 GPIO Pin Function Lock .............................................................................................. 40 5 www.national.com Table of Contents (Continued) 2.5 POWER SUPPLY CONTROL (PSC) ......................................................................................... 40 2.6 LED OPERATION AND STATES .............................................................................................. 43 2.7 POWER SUPPLY CONTROL AND LED CONFIGURATION .................................................... 43 2.8 REGISTER TYPE ABBREVIATIONS ........................................................................................ 43 2.9 SUPERI/O CONFIGURATION REGISTERS ............................................................................. 44 2.9.1 SuperI/O ID Register (SID) .......................................................................................... 45 2.9.2 SuperI/O Configuration 1 Register (SIOCF1) .............................................................. 45 2.9.3 SuperI/O Configuration 2 Register (SIOCF2) .............................................................. 46 2.9.4 SuperI/O Configuration 3 Register (SIOCF3) .............................................................. 47 2.9.5 SuperI/O Configuration 4 Register (SIOCF4) .............................................................. 48 2.9.6 SuperI/O Configuration 5 Register (SIOCF5) .............................................................. 49 2.9.7 SuperI/O Configuration 6 Register (SIOCF6) .............................................................. 50 2.9.8 SuperI/O Revision ID Register (SRID) ........................................................................ 50 2.9.9 SuperI/O Configuration 8 Register (SIOCF8) .............................................................. 51 2.9.10 SuperI/O Configuration A Register (SIOCFA) ............................................................. 52 2.9.11 SuperI/O Configuration B Register (SIOCFB) ............................................................. 53 2.9.12 SuperI/O Configuration C Register (SIOCFC) ............................................................. 54 2.9.13 SuperI/O Configuration D Register (SIOCFD) ............................................................. 55 2.10 FLOPPY DISK CONTROLLER (FDC) CONFIGURATION ........................................................ 56 2.10.1 General Description ..................................................................................................... 56 2.10.2 Logical Device 0 (FDC) Configuration ......................................................................... 56 2.10.3 FDC Configuration Register ........................................................................................ 57 2.10.4 Drive ID Register ......................................................................................................... 58 2.11 PARALLEL PORT CONFIGURATION ...................................................................................... 59 2.11.1 General Description ..................................................................................................... 59 2.11.2 Logical Device 1 (PP) Configuration ............................................................................ 60 2.11.3 Parallel Port Configuration Register ............................................................................ 61 2.12 SERIAL PORT 2 CONFIGURATION ......................................................................................... 62 2.12.1 General Description ..................................................................................................... 62 2.12.2 Logical Device 2 (SP2) Configuration .......................................................................... 62 2.12.3 Serial Port 2 Configuration Register ............................................................................ 62 2.13 SERIAL PORT 1 CONFIGURATION ......................................................................................... 63 2.13.1 Logical Device 3 (SP1) Configuration .......................................................................... 63 2.13.2 Serial Port 1 Configuration Register ............................................................................ 63 2.14 SYSTEM WAKE-UP CONTROL (SWC) CONFIGURATION ..................................................... 64 2.14.1 Logical Device 4 (SWC) Configuration ........................................................................ 64 2.15 KEYBOARD AND MOUSE CONTROLLER (KBC) CONFIGURATION ..................................... 65 2.15.1 General Description ..................................................................................................... 65 2.15.2 Logical Devices 5 and 6 (Mouse and Keyboard) Configuration .................................. 66 2.15.3 KBC Configuration Register ........................................................................................ 67 2.16 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION .......................... 68 2.16.1 General Description ..................................................................................................... 68 2.16.2 Implementation ............................................................................................................ 68 2.16.3 Logical Device 7 (GPIO) Configuration ....................................................................... 69 2.16.4 GPIO Pin Select Register ............................................................................................ 70 www.national.com 6 Table of Contents 2.16.5 2.16.6 3.0 (Continued) GPIO Pin Configuration Register ................................................................................. 71 GPIO Event Routing Register ...................................................................................... 72 2.17 ACCESS.BUS INTERFACE (ACB) CONFIGURATION ............................................................ 73 2.17.1 General Description ..................................................................................................... 73 2.17.2 Logical Device 8 (ACB) Configuration ......................................................................... 73 2.17.3 ACB Configuration Register ........................................................................................ 74 2.18 FAN SPEED CONTROL AND MONITOR (FSCM) CONFIGURATION ..................................... 75 2.18.1 General Description ..................................................................................................... 75 2.18.2 Logical Device 9 (FSCM) Configuration ...................................................................... 75 2.18.3 Fan Speed Control and Monitor Configuration 1 Register ........................................... 76 2.18.4 Fan Speed Control and Monitor Configuration 2 Register ........................................... 77 2.18.5 Fan Speed Control OTS Configuration Register (FCOCR) ......................................... 77 2.19 WATCHDOG TIMER (WDT) CONFIGURATION ...................................................................... 78 2.19.1 Logical Device 10 (WDT) Configuration ...................................................................... 78 2.19.2 WATCHDOG Timer Configuration Register ................................................................ 78 2.20 VOLTAGE LEVEL MONITOR (VLM) CONFIGURATION .......................................................... 79 2.20.1 Logical Device 13 (VLM) Configuration ....................................................................... 79 2.21 TEMPERATURE SENSOR (TMS) CONFIGURATION ............................................................. 79 2.21.1 Logical Device 14 (TMS) Configuration ....................................................................... 79 System Wake-Up Control (SWC) 3.1 OVERVIEW ............................................................................................................................... 80 3.2 FUNCTIONAL DESCRIPTION .................................................................................................. 81 3.3 EVENT DETECTION ................................................................................................................. 82 3.3.1 Modem Ring ................................................................................................................ 82 3.3.2 Telephone Ring ........................................................................................................... 82 3.3.3 Keyboard and Mouse Activity ...................................................................................... 83 3.3.4 CEIR Address .............................................................................................................. 83 3.3.5 Standby General-Purpose Input Events ...................................................................... 83 3.3.6 GPIO-Triggered Events ............................................................................................... 83 3.3.7 Software Event ............................................................................................................ 83 3.3.8 Module IRQ Wake-Up Event ....................................................................................... 83 3.4 SWC REGISTERS ..................................................................................................................... 84 3.4.1 SWC Register Map ...................................................................................................... 85 3.4.2 Wake-Up Events Status Register 0 (WK_STS0) ......................................................... 87 3.4.3 Wake-Up Events Status Register (WK_STS1) ............................................................ 88 3.4.4 Wake-Up Events Enable Register (WK_EN0) ............................................................. 89 3.4.5 Wake-Up Events Enable Register 1 (WK_EN1) .......................................................... 90 3.4.6 Wake-Up Configuration Register (WK_CFG) .............................................................. 91 3.4.7 Wake-Up Events Routing to SMI Enable Register 0 (WK_SMIEN0) ........................... 92 3.4.8 Wake-Up Events Routing to SMI Enable Register 1 (WK_SMIEN1) ........................... 93 3.4.9 Wake-Up Events Routing to IRQ Enable Register 0 (WK_IRQEN0) ........................... 94 3.4.10 Wake-Up Events Routing to IRQ Enable Register 1 (WK_IRQEN1) ........................... 95 3.4.11 Wake-Up Extension 1 Enable Register 0 (WK_X1EN0) .............................................. 96 3.4.12 Wake-Up Extension 1 Enable Register 1 (WK_X1EN1) .............................................. 97 7 www.national.com Table of Contents 3.4.13 3.4.14 3.4.15 3.4.16 3.4.17 3.4.18 3.4.19 3.4.20 3.4.21 3.4.22 3.4.23 3.4.24 3.4.25 3.4.26 3.4.27 3.4.28 3.4.29 3.4.30 3.4.31 3.4.32 3.4.33 3.4.34 3.4.35 3.4.36 3.5 4.0 5.0 (Continued) Wake-Up Extension 2 Enable Register 0 (WK_X2EN0) .............................................. 98 Wake-Up Extension 2 Enable Register 1 (WK_X2EN1) .............................................. 99 Wake-Up Extension 3 Enable Register 0 (WK_X3EN0) ............................................ 100 Wake-Up Extension 3 Enable Register 1 (WK_X3EN1) ............................................ 101 PS/2 Keyboard and Mouse Wake-Up Events ............................................................ 102 PS/2 Protocol Control Register (PS2CTL) ................................................................. 103 Keyboard Data Shift Register (KDSR) ....................................................................... 103 Mouse Data Shift Register (MDSR) ........................................................................... 104 PS/2 Keyboard Key Data Registers (PS2KEY0 - PS2KEY7) .................................... 104 CEIR Wake-Up Control Register (IRWCR) ............................................................... 105 CEIR Wake-Up Address Register (IRWAD) .............................................................. 106 CEIR Wake-Up Address Mask Register (IRWAM) .................................................... 106 CEIR Address Shift Register (ADSR) ........................................................................ 107 CEIR Wake-Up Range 0 Registers ........................................................................... 107 CEIR Wake-Up Range 1 Registers ........................................................................... 108 CEIR Wake-Up Range 2 Registers ........................................................................... 108 CEIR Wake-Up Range 3 Registers ........................................................................... 109 Standby General-Purpose I/O (SBGPIO) Register Overview .................................... 110 Standby GPIO Pin Select Register (SBGPSEL) ........................................................ 113 Standby GPIO Pin Configuration Register (SBGPCFG) ........................................... 114 Standby GPIOE/GPIE Data Out Register 0 (SB_GPDO0) ........................................ 116 Standby GPIOE/GPIE Data In Register 0 (SB_GPDI0) ............................................ 116 Standby GPOS Data Out Register 1 (SB_GPDO1) .................................................. 117 Standby GPIS Data In Register 1 (SB_GPDI1) ......................................................... 117 SWC REGISTER BITMAP ....................................................................................................... 118 Fan Speed Control 4.1 OVERVIEW ............................................................................................................................. 121 4.2 FUNCTIONAL DESCRIPTION ................................................................................................ 121 4.3 FAN SPEED CONTROL REGISTERS .................................................................................... 122 4.3.1 Fan Speed Control Register Map .............................................................................. 122 4.3.2 Fan Speed Control Pre-Scale Register (FCPSR) ...................................................... 122 4.3.3 Fan Speed Control Duty Cycle Register (FCDCR) .................................................... 123 4.4 FAN SPEED CONTROL BITMAP ........................................................................................... 123 Fan Speed Monitor 5.1 OVERVIEW ............................................................................................................................. 124 5.2 FUNCTIONAL DESCRIPTION ................................................................................................ 124 5.3 FAN SPEED MONITOR REGISTERS ..................................................................................... 125 5.3.1 Fan Speed Monitor Register Map .............................................................................. 125 5.3.2 Fan Monitor Threshold Register (FMTHR) ................................................................ 126 5.3.3 Fan Monitor Speed Register (FMSPR) ...................................................................... 126 5.3.4 Fan Monitor Control and Status Register (FMCSR) .................................................. 126 www.national.com 8 Table of Contents 5.4 6.0 7.0 8.0 (Continued) FAN SPEED MONITOR BITMAP ............................................................................................ 127 General-Purpose Input/Output (GPIO) Port 6.1 OVERVIEW ............................................................................................................................. 128 6.2 BASIC FUNCTIONALITY ........................................................................................................ 129 6.2.1 Configuration Options ................................................................................................ 129 6.2.2 Operation ................................................................................................................... 129 6.3 EVENT HANDLING AND SYSTEM NOTIFICATION .............................................................. 130 6.3.1 Event Configuration ................................................................................................... 130 6.3.2 System Notification .................................................................................................... 130 6.4 GPIO PORT REGISTERS ....................................................................................................... 131 6.4.1 GPIO Pin Configuration (GPCFG) Register .............................................................. 132 6.4.2 GPIO Pin Event Routing (GPEVR) Register ............................................................. 133 6.4.3 GPIO Port Runtime Register Map ............................................................................. 133 6.4.4 GPIO Data Out Register (GPDO) .............................................................................. 134 6.4.5 GPIO Data In Register (GPDI) .................................................................................. 134 6.4.6 GPIO Event Enable Register (GPEVEN) .................................................................. 135 6.4.7 GPIO Event Status Register (GPEVST) .................................................................... 135 WATCHDOG Timer (WDT) 7.1 OVERVIEW ............................................................................................................................. 136 7.2 FUNCTIONAL DESCRIPTION ................................................................................................ 136 7.3 WATCHDOG TIMER REGISTERS ......................................................................................... 137 7.3.1 WATCHDOG Timer Register Map ............................................................................. 137 7.3.2 WATCHDOG Timeout Register (WDTO) .................................................................. 137 7.3.3 WATCHDOG Mask Register (WDMSK) .................................................................... 138 7.3.4 WATCHDOG Status Register (WDST) ...................................................................... 139 7.4 COUNTING DOWN IN SECONDS .......................................................................................... 139 7.5 WATCHDOG TIMER REGISTER BITMAP ............................................................................. 139 ACCESS.bus Interface (ACB) 8.1 OVERVIEW ............................................................................................................................. 140 8.2 FUNCTIONAL DESCRIPTION ................................................................................................ 140 8.2.1 Data Transactions ..................................................................................................... 140 8.2.2 Start and Stop Conditions .......................................................................................... 140 8.2.3 Acknowledge (ACK) Cycle ........................................................................................ 141 8.2.4 Acknowledge after Every Byte Rule .......................................................................... 142 8.2.5 Addressing Transfer Formats .................................................................................... 142 8.2.6 Arbitration on the Bus ................................................................................................ 142 8.2.7 Master Mode .............................................................................................................. 143 8.2.8 Slave Mode ................................................................................................................ 145 8.2.9 Configuration ............................................................................................................. 145 8.3 ACB REGISTERS .................................................................................................................... 146 8.3.1 ACB Register Map ..................................................................................................... 146 8.3.2 ACB Serial Data Register (ACBSDA) ........................................................................ 146 9 www.national.com Table of Contents 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.4 9.0 10.0 (Continued) ACB Status Register (ACBST) .................................................................................. 147 ACB Control Status Register (ACBCST) ................................................................... 148 ACB Control Register 1 (ACBCTL1) .......................................................................... 149 ACB Own Address Register (ACBADDR) ................................................................. 150 ACB Control Register 2 (ACBCTL2) .......................................................................... 150 ACB REGISTER BITMAP ........................................................................................................ 151 Voltage Level Monitor (VLM) 9.1 OVERVIEW ............................................................................................................................. 152 9.2 FUNCTIONAL DESCRIPTION ................................................................................................ 152 9.2.1 Voltage Measurement, Channels 0 through 10 ......................................................... 153 9.2.2 Power-On Reset Default States ................................................................................ 154 9.2.3 Standby Mode ........................................................................................................... 154 9.3 ANALOG SUPPLY CONNECTION ......................................................................................... 154 9.3.1 Recommendations ..................................................................................................... 154 9.3.2 Reference Voltage ..................................................................................................... 155 9.4 REGISTER BANK OVERVIEW ............................................................................................... 155 9.5 VLM REGISTERS .................................................................................................................... 156 9.5.1 VLM Register Map ..................................................................................................... 156 9.5.2 Voltage Event Status Register 0 (VEVSTS0) ............................................................ 157 9.5.3 Voltage Event Status Register 1 (VEVSTS1) ............................................................ 157 9.5.4 Voltage Event to SMI Register 0 (VEVSMI0) ............................................................ 158 9.5.5 Voltage Event to SMI Register 1 (VEVSMI1) ............................................................ 159 9.5.6 Voltage Event to IRQ Register 0 (VEVIRQ0) ............................................................ 160 9.5.7 Voltage Event to IRQ Register 1 (VEVIRQ1) ............................................................ 160 9.5.8 Voltage ID Register (VID) .......................................................................................... 160 9.5.9 Voltage Conversion Rate Register (VCNVR) ............................................................ 162 9.5.10 VLM Configuration Register (VLMCFG) .................................................................... 163 9.5.11 VLM Bank Select Register (VLMBS) ......................................................................... 163 9.5.12 Voltage Channel Configuration and Status Register (VCHCFST) ............................. 164 9.5.13 Read Channel Voltage Register (RDCHV) ................................................................ 165 9.5.14 Channel Voltage High Limit Register (CHVH) ........................................................... 165 9.5.15 Channel Voltage Low Limit Register (CHVL) ............................................................ 165 9.6 VLM REGISTER BITMAP ........................................................................................................ 166 9.6.1 VLM Control and Status Registers ............................................................................ 166 9.6.2 VLM Channel Registers ............................................................................................ 166 9.7 USAGE HINTS ........................................................................................................................ 167 9.7.1 Calculating the Channel Delay .................................................................................. 167 9.7.2 Measuring Out of Range Positive and Negative Voltages ......................................... 168 9.7.3 Obtaining the Specified VLM/TMS Accuracy ............................................................. 168 Temperature Sensor (TMS) 10.1 OVERVIEW ............................................................................................................................. 169 10.2 FUNCTIONAL DESCRIPTION ................................................................................................ 169 10.2.1 Register Bank Overview ............................................................................................ 170 www.national.com 10 Table of Contents 10.2.2 10.2.3 10.2.4 10.2.5 10.2.6 10.2.7 11.0 (Continued) TOS, THIGH and TLOW Limits, OTS and ALERT Output, IRQ and SMI ...................... 170 ALERT Response Read Sequence ........................................................................... 171 Power-On Reset Default States ................................................................................ 171 Temperature Data Format ......................................................................................... 172 Standby Mode ........................................................................................................... 172 Diode Fault Detection ................................................................................................ 172 10.3 TMS REGISTERS ................................................................................................................... 173 10.3.1 TMS Register Map ..................................................................................................... 173 10.3.2 Temperature Event Status Register (TEVSTS) ......................................................... 174 10.3.3 Temperature Event to SMI Register (TEVSMI) ......................................................... 175 10.3.4 Temperature Event to IRQ Register (TEVIRQ) ......................................................... 176 10.3.5 TMS Configuration Register (TMSCFG) .................................................................... 177 10.3.6 TMS Bank Select Register (TMSBS) ......................................................................... 177 10.3.7 Temperature Channel Configuration and Status Register (TCHCFST) .................... 178 10.3.8 Read Channel Temperature Register (RDCHT) ........................................................ 179 10.3.9 Channel Temperature High Limit Register (CHTH) ................................................... 179 10.3.10 Channel Temperature Low Limit Register (CHTL) .................................................... 179 10.3.11 Channel Overtemperature Limit Register (CHOTL) .................................................. 179 10.4 TMS REGISTER BITMAP ....................................................................................................... 180 10.4.1 TMS Control and Status Registers .......................................................................... 180 10.4.2 TMS Channel Registers ........................................................................................... 180 10.5 USAGE HINTS ........................................................................................................................ 181 10.5.1 Remote Diode Selection ............................................................................................ 181 10.5.2 ADC Noise Filtering ................................................................................................... 181 10.5.3 PC Board Layout ....................................................................................................... 181 10.5.4 Twisted Pair and Shielded Cables ............................................................................. 183 10.5.5 Obtaining the Specified VLM/TMS Accuracy ............................................................. 183 Legacy Functional Blocks 11.1 KEYBOARD AND MOUSE CONTROLLER (KBC) .................................................................. 184 11.1.1 General Description ................................................................................................... 184 11.1.2 KBC Register Map ..................................................................................................... 184 11.1.3 KBC Bitmap Summary ............................................................................................... 184 11.2 FLOPPY DISK CONTROLLER (FDC) ..................................................................................... 185 11.2.1 General Description ................................................................................................... 185 11.2.2 FDC Register Map ..................................................................................................... 185 11.2.3 FDC Bitmap Summary ............................................................................................... 186 11.3 PARALLEL PORT .................................................................................................................... 187 11.3.1 General Description ................................................................................................... 187 11.3.2 Parallel Port Register Map ......................................................................................... 187 11.3.3 Parallel Port Bitmap Summary .................................................................................. 188 11.4 UART FUNCTIONALITY (SP1 AND SP2) ............................................................................... 190 11.4.1 General Description ................................................................................................... 190 11.4.2 UART Mode Register Bank Overview ....................................................................... 190 11.4.3 SP1 and SP2 Register Maps for UART Functionality ................................................ 191 11 www.national.com Table of Contents 11.4.4 11.5 12.0 (Continued) SP1 and SP2 Bitmap Summary for UART Functionality ........................................... 193 IR FUNCTIONALITY (SP2) ..................................................................................................... 195 11.5.1 General Description ................................................................................................... 195 11.5.2 IR Mode Register Bank Overview ............................................................................. 195 11.5.3 SP2 Register Map for IR Functionality ...................................................................... 196 11.5.4 SP2 Bitmap Summary for IR Functionality ................................................................ 197 Device Characteristics 12.1 GENERAL DC ELECTRICAL CHARACTERISTICS ............................................................... 199 12.1.1 Recommended Operating Conditions ....................................................................... 199 12.1.2 Absolute Maximum Ratings ....................................................................................... 199 12.1.3 Capacitance .............................................................................................................. 199 12.1.4 Power Consumption under Recommended Operating Conditions ............................ 200 12.2 DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES ................................................ 200 12.2.1 Input, CMOS Compatible ........................................................................................... 200 12.2.2 Input, PCI 3.3V .......................................................................................................... 200 12.2.3 Input, SMBus Compatible .......................................................................................... 200 12.2.4 Input, Strap Pin .......................................................................................................... 201 12.2.5 Input, TTL Compatible ............................................................................................... 201 12.2.6 Input, TTL Compatible with Schmitt Trigger .............................................................. 201 12.2.7 Output, PCI 3.3V ....................................................................................................... 202 12.2.8 Output, Totem-Pole Buffer ......................................................................................... 202 12.2.9 Output, Open-Drain Buffer ......................................................................................... 202 12.2.10 Input, Analog ............................................................................................................. 202 12.2.11 Input, Analog ............................................................................................................. 202 12.2.12 Input, Analog ............................................................................................................. 203 12.2.13 Output, Analog ........................................................................................................... 203 12.2.14 Output, Analog ........................................................................................................... 203 12.2.15 Exceptions ................................................................................................................. 203 12.3 INTERNAL RESISTORS ......................................................................................................... 204 12.3.1 Pull-Up Resistor ......................................................................................................... 204 12.3.2 Pull-Down Resistor .................................................................................................... 204 12.4 ANALOG CHARACTERISTICS ............................................................................................... 204 12.4.1 VLM ........................................................................................................................... 204 12.4.2 TMS ........................................................................................................................... 205 12.5 AC ELECTRICAL CHARACTERISTICS .................................................................................. 206 12.5.1 AC Test Conditions .................................................................................................... 206 12.5.2 Clock Timing .............................................................................................................. 206 12.5.3 LCLK and LRESET .................................................................................................... 207 12.5.4 LPC and SERIRQ Signals ......................................................................................... 208 12.5.5 Serial Port, Sharp-IR, SIR and Consumer Remote Control Timing ........................... 209 12.5.6 Modem Control Timing .............................................................................................. 210 12.5.7 FDC Write Data Timing ............................................................................................. 210 12.5.8 FDC Drive Control Timing ......................................................................................... 211 12.5.9 FDC Read Data Timing ............................................................................................. 211 12.5.10 Standard Parallel Port Timing .................................................................................... 212 www.national.com 12 Table of Contents (Continued) 12.5.11 Enhanced Parallel Port Timing .................................................................................. 212 12.5.12 Extended Capabilities Port (ECP) Timing .................................................................. 213 12.5.13 Chassis Lock/Unlock Timing ..................................................................................... 214 13 www.national.com 1.0 CONNECTION DIAGRAM 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 TRK0 WP RDATA HDSEL DSKCHG GPIE7/IRRX1 GPIE6/IRRX2_IRSL0 GPO15/IRTX GPIO14/WDO GPIO13/SDA GPIO12/SCL GPIO11/XLOCK VDD VSS D2P D2N D1P D1N VREF AVSS AVSB AVI6 AVI5 AVI4 AVI3 AVI2 1.1 Signal/Pin Connection and Description GPIO17/DR1/IRSL3 MTR0 INDEX DRATE0 DENSEL SLCT PE BUSY_WAIT ACK PD7 PD6 PD5 VDD VSS PD4 PD3 SLIN_ASTRB PD2 INIT PD1 ERR PD0 38 37 36 35 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 34 33 32 PC87365-xxx/VLA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AVI1 SLPS5/AVI0 SLPS3 PWBTIN/GPIS2 PSON/GPOS1 PWBTOUT/GPOS0 PWUREQ VSB VBAT CHASI GPIOE5/CHASO GPIOE4/RING/ALARM GPIOE3/LED2 GPIOE2/OTS2/LED1 GPIOE1/OTS1 GPIOE0 CLKIN GPIO10/SMI VDD VSS LAD3 LAD2 LAD1 LAD0 LFRAME LDRQ SERIRQ LCLK LRESET GA20/GPIO07 KBRST/GPIO06 GPIO05/P17 GPIO04/P12 GPIO03/FANOUT0 GPIO02/FANIN0 GPIO01/FANOUT1 GPIO00/FANIN1 GPIO34/FANOUT2/CHLOCK DCD2 DSR2 SIN2 RTS2 SOUT2/PSLDC1/PSLDC1 CTS2 DTR2_BOUT2/PSONPOL RI2 KBCLK KBDAT MCLK MDAT VDD VSS GPIO20/PIRQ3 GPIO21/PIRQ4 GPIO22/PIRQ5 GPIO23/PIRQ6 GPIO24/PIRQ7 GPIO25/PIRQ9 GPIO26/PIRQ10 GPIO27/PIRQ11 GPIO30/PIRQ12 GPIO31/PIRQ14 GPIO32/PIRQ15/P16/IRSL1 GPIO33/FANIN2/CHUNLOCK AFD_DSTRB STB_WRITE DCD1 DSR1 SIN1 RTS1/TEST SOUT1/PSLDC0 CTS1 DTR1_BOUT1/BADDR RI1 65 66 67 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 WGATE WDATA STEP DIR GPIO16/MTR1/IRSL2 DR0 Plastic Quad Flatpack (PQFP), JEDEC Order Number PC87365-xxx/VLA See NS Package Number VLA128A xxx = Three-character identifier for National data and keyboard ROM and/or customer identification code. www.national.com 14 1.0 Signal/Pin Connection and Description 1.2 (Continued) BUFFER TYPES AND SIGNAL/PIN DIRECTORY Table 2 is an alphabetical list of all signals, cross-referenced to additional information for detailed functional descriptions, electrical DC characteristics and pin multiplexing. The signal DC characteristics are denoted by a buffer type symbol, described briefly below and in further detail in Section 12.2. The pin multiplexing information refers to two different types of multiplexing: ● MUX - Multiplexed, denoted by a slash (/) between pins in the diagram in Section 1.1. Pins are shared between two different functions. Each function is associated with different board connectivity. Normally, the function selection is determined by the board design and cannot be changed dynamically. The multiplexing options must be configured by the BIOS upon power-up in order to comply with the board implementation. ● MM - Multiple Mode, denoted by an underscore (_) between pins in the diagram in Section 1.1. Pins have two or more modes of operation within the same function. These modes are associated with the same external (board) connectivity. Mode selection may be controlled by the device driver through the registers of the functional block and do not require a special BIOS setup upon power-up. These pins are not considered multiplexed pins from the SuperI/O configuration perspective. The mode selection method (registers and bits), as well as the signal specification in each mode, are described within the functional description of the relevant functional block. Table 1. Buffer Types Symbol Description INAN# Input, analog type number INC Input, CMOS compatible INPCI Input, PCI 3.3V INSM Input, SMBus compatible INSTRP Input, Strap pin with weak pull-down during strap time INT Input, TTL compatible INTS Input, TTL compatible with Schmitt Trigger INULR Input, with serial UL Resistor OAN# Output, analog type number OPCI Output, PCI 3.3V Op/n Output, push-pull buffer that is capable of sourcing p mA and sinking n mA ODn Output, open-drain output buffer that is capable of sinking n mA PWR Power pin GND Ground pin Table 2. SIgnal/Pin Directory Functional Group Signal DC Characteristics Pin(s) MUX Name Section Buffer Type Section ACK 79 Parallel Port 1.4.9 INT 12.2.5 AFD_DSTRB 93 Parallel Port 1.4.9 OD14, O14/14 12.2.9, 12.2.8 MM ALARM 27 Hardware Monitoring 1.4.14 OD6 12.2.9 MUX ASTRB See SLIN_ASTRB AVI0 37 Hardware Monitoring 1.4.14 INAN1 12.2.10 MUX AVI1-6 38-43 Hardware Monitoring 1.4.14 INAN1 12.2.10 AVDD 44 Power and Ground 1.4.10 PWR N/A AVSS 45 Power and Ground 1.4.10 AGND N/A BADDR 101 Strap Configuration 1.4.13 INSTRP 12.2.4 BOUT1 See DTR1_BOUT1 15 MUX www.national.com 1.0 Signal/Pin Connection and Description (Continued) Functional Group Signal DC Characteristics Pin(s) MUX Name Section Buffer Type Section BOUT2 See DTR2_BOUT2 BUSY_WAIT 78 Parallel Port 1.4.9 INT 12.2.5 CHASI 29 Protection 1.4.11 INC 12.2.1 CHASO 28 Protection 1.4.11 OD6 12.2.9 MUX CHLOCK 1 Protection 1.4.11 O12/12 12.2.9 MUX CHUNLOCK 128 Protection 1.4.11 O12/12 12.2.9 MUX CLKIN 22 Clock 1.4.3 INT 12.2.5 CTS1 100 Serial Port 1 1.4.12 INTS 12.2.6 CTS2 108 Serial Port 2 1.4.12 INTS 12.2.6 DCD1 95 Serial Port 1 1.4.12 INTS 12.2.6 DCD2 103 Serial Port 2 1.4.12 INTS 12.2.6 DENSEL 75 FDC 1.4.5 O2/12 12.2.8 DIR 68 FDC 1.4.5 OD12, O2/12 12.2.9, 12.2.8 D1N D2N 47 49 Hardware Monitoring 1.4.14 INAN3 12.2.12 D1P D2P 48 50 Hardware Monitoring 1.4.14 INAN2 12.2.11 DR0 70 FDC 1.4.5 OD12, O2/12 12.2.9, 12.2.8 12.2.9, 12.2.8 MM DR1 71 FDC 1.4.5 OD12, O2/12 DRATE0 74 FDC 1.4.5 O3/6 12.2.8 DSKCHG 60 FDC 1.4.5 INT 12.2.5 DSR1 96 Serial Port 1 1.4.12 INTS 12.2.6 DSR2 104 Serial Port 2 1.4.12 INTS 12.2.6 DSTRB See AFD_DSTRB DTR1_BOUT1 101 1.4.12 O3/6 12.2.8 MUX, MM 1.4.12 O3/6 12.2.8 MUX, MM 1.4.9 INT 12.2.5 1.4.4 INTS 12.2.6 MUX 1.4.4 INTS 12.2.6 MUX 12.2.6 MUX DTR2_BOUT2 ERR FANIN0 FANIN1 109 91 4 2 Serial Port 1 Serial Port 2 Parallel Port Fan Speed Fan Speed MUX FANIN2 128 Fan Speed 1.4.4 INTS FANOUT0 5 Fan Speed 1.4.4 O2/14 12.2.8 MUX FANOUT1 3 Fan Speed 1.4.4 O2/14 12.2.8 MUX FANOUT2 1 Fan Speed 1.4.4 O2/14 12.2.8 MUX GA20 (P21) 9 KBC 1.4.8 INT, OD2 12.2.5, 12.2.9 MUX GPIE6-7 58-59 System Wake-Up 1.4.15 INTS 12.2.6 MUX GPIO00-07 2-9 GPIO Port 1.4.6 INTS, OD6, O3/6 12.2.6, 12.2.9, 12.2.8 MUX GPIO10 GPIO11-14 GPO15 GPIO16-17 21 53-56 57 69, 71 GPIO Port 1.4.6 INTS, OD6, O3/6 12.2.6, 12.2.9, 12.2.8 MUX GPIO20-27 117-124 GPIO Port 1.4.6 INTS, OD6, O3/6 12.2.6, 12.2.9, 12.2.8 MUX www.national.com 16 1.0 Signal/Pin Connection and Description (Continued) Functional Group Signal DC Characteristics Pin(s) MUX Name Section Buffer Type Section GPIO30-33 GPIO34 125-128 1 GPIO Port 1.4.6 INTS, OD6, O3/6 12.2.6, 12.2.9, 12.2.8 GPIOE0-1 23-24 System Wake-Up 1.4.15 INTS, OD6, O3/6 12.2.6, 12.2.9, 12.2.8 GPIOE2-5 25-28 System Wake-Up 1.4.15 INTS, OD6, O3/6 12.2.6, 12.2.9, 12.2.8 MUX GPIS2 35 System Wake-Up 1.4.15 INTS 12.2.6 MUX 1.4.15 OD6, O3/6 12.2.9, 12.2.8 MUX 1.4.5 OD12, O2/12 12.2.9, 12.2.8 1.4.5 INT 12.2.5 12.2.9, 12.2.8 GPOS0-1 HDSEL INDEX 33-34 61 73 System Wake-Up FDC FDC MUX INIT 89 Parallel Port 1.4.9 OD14, O14/14 IRRX1 59 Infrared 1.4.7 INTS 12.2.6 IRRX2_IRSL0 58 Infrared 1.4.7 INTS, O3/6 12.2.6, 12.2.8 MUX, MM IRSL1 127 Infrared 1.4.7 INT, O3/6 12.2.5, 12.2.8 MUX IRSL2 69 Infrared 1.4.7 INT, O3/6 12.2.5, 12.2.8 MUX IRSL3 71 Infrared 1.4.7 INT 12.2.5 MUX IRTX 57 Infrared 1.4.7 O6/12 12.2.8 MUX KBCLK 111 KBC 1.4.8 INTS, OD14 12.2.6, 12.2.9 KBDAT 112 KBC 1.4.8 INTS, OD14 12.2.6, 12.2.9 KBRST (P20) 8 KBC 1.4.8 INTS, OD2 12.2.6, 12.2.9 LAD0-3 15-18 Bus Interface 1.4.2 INPCI, OPCI 12.2.2, 12.2.7 LED1, LED2 25, 26 System Wake-Up 1.4.15 O12/12 12.2.8 LCLK 11 Bus Interface 1.4.2 INPCI 12.2.2 LDRQ 13 Bus Interface 1.4.2 OPCI 12.2.7 LFRAME 14 Bus Interface 1.4.2 INPCI 12.2.2 LRESET 10 Bus Interface 1.4.2 INPCI 12.2.2 MCLK 113 KBC 1.4.8 INTS, OD14 12.2.6, 12.2.9 MDAT 114 KBC 1.4.8 INTS, OD14 12.2.6, 12.2.9 MTR0 72 FDC 1.4.5 OD12, O2/12 12.2.9, 12.2.8 MTR1 69 FDC 1.4.5 OD12, O2/12 12.2.9, 12.2.8 MUX OTS1 OTS2 24 25 Hardware Monitoring 1.4.14 OD6 12.2.9 MUX P12, P16, P17 6,127, 7 KBC 1.4.8 INT, OD2 12.2.5, 12.2.9 MUX PD7-5 PD4-3, PD2, PD1 PD0 80-82 85-86 88, 90 92 Parallel Port 1.4.9 INT, O14/14 12.2.5, 12.2.9, 12.2.8 PE 77 Parallel Port 1.4.9 INT 12.2.5 PIRQ3-7 PIRQ9-12 PIRQ14-15 117-121 122-125 126-127 Bus Interface 1.4.2 INTS 12.2.6 MUX PSLDC0 99 Strap Configuration 1.4.13 INSTRP 12.2.4 MUX PSLDC1 107 Strap Configuration 1.4.13 INSTRP 12.2.4 MUX PSON 34 System Wake-Up 1.4.15 OD12, O4/4 12.2.9, 12.2.8 MUX 17 MUX MUX MUX www.national.com 1.0 Signal/Pin Connection and Description (Continued) Functional Group Signal DC Characteristics Pin(s) MUX Name Section Buffer Type Section PSONPOL 109 Strap Configuration 1.4.13 INSTRP 12.2.4 MUX PWBTIN 35 System Wake-Up 1.4.15 INTS 12.2.6 MUX PWBTOUT 33 System Wake-Up 1.4.15 OD12 12.2.9 MUX PWUREQ 32 System Wake-Up 1.4.15 OD6 12.2.9 RDATA 62 FDC 1.4.5 INT 12.2.5 RI1 102 Serial Port 1 1.4.12 INTS 12.2.6 1.4.12 INTS 12.2.6 12.2.6 MUX MUX RI2 110 Serial Port 2 RING 27 System Wake-Up 1.4.15 INTS RTS1 98 Serial Port 1 1.4.12 O3/6 12.2.8 RTS2 106 Serial Port 2 1.4.12 O3/6 12.2.8 SCL 54 ACB 1.4.1 INT, OD6, O3/6 12.2.5, 12.2.9, 12.2.8 MUX SDA 55 ACB 1.4.1 INT, OD6, O3/6 12.2.5, 12.2.9, 12.2.8 MUX SERIRQ 12 Bus Interface 1.4.2 INPCI, OPCI 12.2.2, 12.2.7 SIN1 97 Serial Port 1 1.4.12 INTS 12.2.6 SIN2 105 Serial Port 2 1.4.12 INTS 12.2.6 SLCT 76 Parallel Port 1.4.9 INT 12.2.5 SLIN_ASTRB 87 Parallel Port 1.4.9 OD14, O14/14 12.2.9, 12.2.8 SLPS3,5 36,37 System Wake-Up 1.4.15 INTS 12.2.6 MUX (SLPS3) SMI 21 Bus Interface 1.4.2 OD12 12.2.9 MUX SOUT1 99 Serial Port 1 1.4.12 O3/6 12.2.8 MUX SOUT2 107 Serial Port 2 1.4.12 O3/6 12.2.8 MUX STEP 67 FDC 1.4.5 OD12, O2/12 12.2.9, 12.2.8 STB_WRITE 94 Parallel Port 1.4.9 OD14, O14/14 12.2.9, 12.2.8 MM TEST 98 Strap Configuration 1.4.13 INSTRP 12.2.4 MUX TRK0 64 FDC 1.4.5 INT 12.2.5 VBAT 30 Power and Ground 1.4.10 INULR N/A VDD 20, 52, 83, 115 Power and Ground 1.4.10 PWR N/A VREF 46 Hardware Monitoring 1.4.14 INAN2, OAN1 12.2.11, 12.2.13 VSB 31 Power and Ground 1.4.10 PWR N/A VSS 19, 51, 84, 116 Power and Ground 1.4.10 GND N/A WAIT See BUSY_WAIT WDATA 66 FDC 1.4.5 OD12, O2/12 12.2.9, 12.2.8 WDO 56 WATCHDOG 1.4.16 OD6, O3/6 12.2.9, 12.2.8 WGATE 65 FDC 1.4.5 OD12, O2/12 12.2.9, 12.2.8 WP 63 FDC 1.4.5 INT 12.2.5 WRITE See STB_WRITE XLOCK 53 1.4.11 INT 12.2.5 www.national.com Protection 18 MM MUX MUX 1.0 Signal/Pin Connection and Description 1.3 (Continued) PIN MULTIPLEXING The multiplexing options and the associated setup configuration for all pins are described in Table 3. A multiplexing option can be chosen on one pin only per group. Table 3. Pin Multiplexing Configuration Default Alternate Pin(s) Signal I/O Configuration Signal I/O Configuration FANOUT2 O SIOCF2, Bits 1-0 = 01 CHLOCK O SIOCF2, Bits 1-0 = 10 I/O SIOCF2, Bit 2 = 0 FANIN1 I SIOCF2, Bit 2 = 1 GPIO01 I/O SIOCF2, Bit 3 = 0 FANOUT1 O SIOCF2, Bit 3 = 1 4 GPIO02 I/O SIOCF2, Bit 4 = 0 FANIN0 I SIOCF2, Bit 4 = 1 5 GPIO03 I/O SIOCF2, Bit 5 = 0 FANOUT0 O SIOCF2, Bit 5 = 1 6 GPIO04 I/O SIOCF2, Bit 6 = 0 P12 I/O SIOCF2, Bit 6 = 1 7 GPIO05 I/O SIOCF2, Bit 7 = 0 P17 I/O SIOCF2, Bit 7 = 1 8 KBRST (P20) SIOCF3, Bit 0 = 1 GPIO06 I/O SIOCF3, Bit 0 = 0 9 GA20 (P21) SIOCF3, Bit 1 = 1 GPIO07 I/O SIOCF3, Bit 1 = 0 21 GPIO10 I/O SIOCF3, Bit 2 = 0 SMI O SIOCF3, Bit 2 = 1 24 GPIOE1 I/O SIOCFA, Bit 0 = 0 OTS1 O SIOCFA, Bit 0 = 1 25 GPIOE2 I/O LED1 O SIOCFA, Bits 2-1 = 01 OTS2 O SIOCFA, Bits 2-1 = 10 26 GPIOE3 I/O SIOCFA, Bit 3 = 01 LED2 O SIOCFA, Bit 3 =1 27 GPIOE4 I/O SIOCFA, Bits 5-4 = 00 RING I SIOCFA, Bits 5-4 = 01 ALARM O SIOCFA, Bits 5-4 = 10 28 GPIOE5 I/O SIOCFA, Bit 6 = 0 CHASO O SIOCFA, Bit 6 =1 33-35, 37 PWBTOUT PSON PWBTIN SLPS5 O O I I GPOS0 GPOS1 GPIS2 AVI0 0 0 I I SIOCFA, Bit 7 = 11 53 GPIO11 I/O SIOCF3, Bit 4 = 0 XLOCK I SIOCF3, Bit 4 = 1 54 GPIO12 I/O SIOCF3, Bit 5 = 0 SCL I/O SIOCF3, Bit 5 = 1 55 GPIO13 I/O SIOCF3, Bit 5 = 0 SDA I/O SIOCF3, Bit 5 = 1 56 GPIO14 I/O SIOCF3, Bit 6 = 0 WDO O SIOCF3, Bit 6 = 1 57 GPO15 O SIOCF3, Bit 7 = 0 IRTX O SIOCF3, Bit 7 = 1 58 GPIE6 I SIOCFB, Bit 0 = 0 IRRX2_IRSL0 I/O SIOCFB, Bit 0 = 1 59 GPIE7 I SIOCFB, Bit 1 = 0 IRRX1 I SIOCFB, Bit 1 = 1 69 GPIO16 I/O SIOCF4, Bits 1-0 = 00 MTR1 O SIOCF4, Bits 1-0 = 01 IRSL2 I/O SIOCF4, Bits 1-0 = 10 71 GPIO17 I/O SIOCF4, Bits 3-2 = 00 DR1 O SIOCF4, Bits 3-2 = 01 IRSL3 I SIOCF4, Bits 3-2 = 10 117 GPIO20 I/O SIOCF4, Bits 4,P2 = 00 PIRQ3 I SIOCF4, Bits 4,P = X1 118 GPIO21 I/O SIOCF4, Bits 4,P2 = 00 PIRQ4 i SIOCF4, Bits 4,P = X1 119 GPIO22 I/O SIOCF4, Bits 4,P2 = 00 PIRQ5 I SIOCF4, Bits 4,P = X1 120 GPIO23 I/O SIOCF4, Bits 4,P2 = 00 PIRQ6 I SIOCF4, Bits 4,P = X1 1 GPIO34 I/O SIOCF2, Bits 1-0 = 00 2 GPIO00 3 SIOCFA, Bits 2-1 = 001 SIOCFA, Bit 7 = 01 19 www.national.com 1.0 Signal/Pin Connection and Description (Continued) Default Alternate Pin(s) Signal I/O Configuration Signal I/O Configuration 121 GPIO24 I/O SIOCF4, Bits 4,P2 = 00 PIRQ7 I SIOCF4, Bits 4,P = X1 122 GPIO25 I/O SIOCF4, Bits 4,P2 = 00 PIRQ9 I SIOCF4, Bits 4,P = X1 123 GPIO26 I/O SIOCF4, Bits 4,P2 = 00 PIRQ10 I SIOCF4, Bits 4,P = X1 124 GPIO27 I/O SIOCF4, Bits 4,P2 = 00 PIRQ11 I SIOCF4, Bits 4,P = X1 125 GPIO30 I/O SIOCF4, Bits 5,P = 00 PIRQ12 I SIOCF4, Bits 5,P = X1 126 GPIO31 I/O SIOCF4, Bits 5,P2 = 00 PIRQ14 I SIOCF4, Bits 5,P = X1 127 128 GPIO32 GPIO33 2 I/O SIOCF4, Bits 7,6,P2 = 000 I/O SIOCF5, Bits 1-0=0 P16 I/O SIOCF4, Bits 7,6,P2 = 010 IRSL1 I/O SIOCF4, Bits 7,6,P2 = 100 PIRQ15 I SIOCF4, Bits 7,6,P2 = XX1 FANIN2 I SIOCF5, Bits 1-0 = 10 CHUNLOCK O SIOCF5, Bits 1-0 = 11 1. The signal selected on each pin is determined during VSB power-up by the PSLDC0,1 straps. 2. P = SIOCF1, Bit 6 (Pins 117-127 Select PIRQ); see page 45. www.national.com 20 1.0 Signal/Pin Connection and Description 1.4 (Continued) DETAILED SIGNAL/PIN DESCRIPTIONS This section describes all signals. Signals are organized in functional groups. 1.4.1 ACCESS.bus Interface (ACB) Signal Pin(s) I/O Buffer Type Power Well Description SCL 54 I/O INSM/OD6 VDD ACCESS.bus Clock Signal. An internal pull-up is optional, depending upon the ACCESS.bus configuration register. SDA 55 I/O INSM/OD6 VDD ACCESS.bus Data Signal. An internal pull-up is optional, depending upon the ACCESS.bus configuration register. 1.4.2 Bus Interface Signal Pin(s) I/O Buffer Type Power Well Description I/O INPCI/OPCI VDD LPC Address-Data. Multiplexed command, address bidirectional data and cycle status. 11 I INPCI VDD LPC Clock. Practically, the PCI clock (up to 33 MHz). LDRQ 13 O OPCI VDD LPC DMA Request. Encoded DMA request for LPC I/F. LFRAME 14 I INPCI VDD LPC Frame. Low pulse indicates the beginning of new LPC cycle or termination of a broken cycle. LRESET 10 I INPCI VDD LPC Reset. Practically, the PCI system reset. I INTS VDD Parallel Interrupt. Converts Parallel Port interrupts into Serial Interrupts by means of the Interrupt Serializer. LAD0-3 15-18 LCLK PIRQ3-7 117-121 PIRQ9-12 122-125 PIRQ14-15 126-127 SERIRQ 12 I/O INPCI/OPCI VDD Serial IRQ. The interrupt requests are serialized over a single pin, where each internal IRQ signal is delivered during a designated time slot. SMI 21 OD OD12 VDD System Management Interrupt. 1.4.3 Clock Signal CLKIN 1.4.4 Pin(s) 22 I/O Buffer Type Power Well I INT VDD Description Clock In. 48 MHz clock input. Fan Speed Control and Monitor (FSCM) Signal Pin(s) I/O Buffer Type Power Well Description FANIN0 FANIN1 FANIN2 4 2 128 I INTS VDD Fan Inputs. Used to feed the fan’s tachometer pulse to the Fan Speed Monitor. The rising edge indicates the completion of a half (or full) revolution of the fan. FANOUT0 FANOUT1 FANOUT2 5 3 1 O O2/14 VDD Fan Outputs. Pulse Width Modulation (PWM) signals, used to control the speed of cooling fans by controlling the voltage supplied to the fan’s motor. 21 www.national.com 1.0 Signal/Pin Connection and Description 1.4.5 (Continued) Floppy Disk Controller (FDC) Signal Pin(s) I/O Buffer Type Power Well Description DENSEL 75 O O2/12 VDD Density Select. Indicates that a high FDC density data rate (500 Kbps or 1 Mbps) or a low density data rate (250 or 300 Kbps) is selected. DENSEL polarity is controlled by bit 5 of the FDC Configuration Register. DIR 68 O OD12, O2/12 VDD Direction. Determines the direction of the Floppy Disk Drive (FDD) head movement (active = step in, inactive = step out) during a seek operation. During reads or writes, DIR is inactive. DR0 70 O OD12, O2/12 VDD Drive Select 0. Decoded drive select output signal. DR0 is controlled by bit 0 of the Digital Output Register (DOR). DR1 71 O OD12, O2/12 VDD Drive Select 1. Decoded drive select output signal. DR0 is controlled by bit 1 of the Digital Output Register (DOR). DRATE0 74 O O3/6 VDD Data Rate 0. Reflects the value of bit 0 of the Configuration Control Register (CCR) or the Data Rate Select Register (DSR), whichever was written to last. Output from the pin is push-pull buffered. DSKCHG 60 I INT VDD Disk Change. Indicates if the drive door has been opened. The state of this pin is stored in the Digital Input Register (DIR). This pin can also be configured as the RGATE data separator diagnostic input signal via the MODE command. HDSEL 61 O OD12, O2/12 VDD Head Select. Determines which side of the FDD is accessed. Active low selects side 1, inactive selects side 0. INDEX 73 I INT VDD Index. Indicates the beginning of an FDD track. MTR0 72 O OD12, O2/12 VDD Motor Select 0. Active low, motor enable line for drives 0, controlled by bits D7-4 of the Digital Output Register (DOR). MTR1 69 O OD12, O2/12 VDD Motor Select 1. Active low, motor enable lines for drives 1, controlled by bits D7-4 of the Digital Output Register (DOR). RDATA 62 I INT VDD Read Data. Raw serial input data stream read from the FDD. STEP 67 O OD12, O2/12 VDD Step. Issues pulses to the disk drive at a software programmable rate to move the head during a seek operation. TRK0 64 I INT VDD Track 0. Indicates to the controller that the head of the selected floppy disk drive is at track 0. WDATA 66 O OD12, O2/12 VDD Write Data. Carries out the pre-compensated serial data that is written to the floppy disk drive. Pre-compensation is software selectable. WGATE 65 O OD12, O2/12 VDD Write Gate. Enables the write circuitry of the selected disk drive. WGATE is designed to prevent glitches during power up and power down. This prevents writing to the disk when power is cycled. VDD Write Protected. Indicates that the disk in the selected drive is write protected. A software programmable configuration bit (FDC configuration at Index F0h, Logical Device 0) can force an active write-protect indication to the FDC, regardless of the status of this pin. WP www.national.com 63 I INT 22 1.0 Signal/Pin Connection and Description 1.4.6 (Continued) General-Purpose Input/Output (GPIO) Ports Signal Pin/s I/O Buffer Type Power Well Description GPIO00-07 2-9 I/O INTS/ OD6, O3/6 VDD General-Purpose I/O Port 0, bits 0-7. Each pin is configured independently as input or I/O, with or without static pull-up and with either open-drain or push-pull output type. The port support interrupt assertion and each pin can be enabled or masked as an interrupt source. GPIO10 GPIO11-14 GPO15 GPIO16-17 I/O INTS/ OD6, O3/6 VDD General-Purpose I/O Port 1, bits 0-7. Same as Port 0. Bit 5 is output only with low output as default. GPIO20-27 117-124 I/O INTS/ OD6, O3/6 VDD General-Purpose I/O Port 2, bits 0-7. Similar to port 0 but without the interrupt assertion capability. INTS/ OD6, O3/6 VDD General-Purpose I/O Port 3, bits 0-4. Similar to port 0 but without the interrupt assertion capability.Bits 5, 6 and 7 are not implemented. 21 53-56 57 69, 71 GPIO30-33 125-128 GPIO34 1 I/O 1.4.7 Infrared (IR) Signal Pin/s I/O Buffer Type Power Well I INTS IRRX2_IRSL0 58 I/O INTS/O3/6 IRSL1 127 I/O INT/O3/6 IRSL2 69 I/O INT/O3/6 IRSL3 71 I INT IRTX 57 O O6/12 IRRX1 59 Description IR Receive 1. Primary input to receive serial data from the IR VDD, VSB transceiver. Monitored during power-off for wake-up event detection. VDD, VSB IRRX2 - IR Receive 2. Auxiliary IR receiver input to support a second transceiver. Monitored during power-off for wake-up event VDD detection. VDD IRSL3-0 IR Select. Output are used to control the IR transceivers. Input for PnP identification of plug-in IR transceiver (dongle). After reset, the dual-function IRSLX pins wake up in input mode. VDD After the ID is read by the IR driver, they may be put into output mode. The output mode is controlled by Serial Port 2. VDD IR Transmit. IR serial output data. 23 www.national.com 1.0 Signal/Pin Connection and Description 1.4.8 Keyboard and Mouse Controller (KBC) Signal GA20 Pin/s 9 KBCLK I/O Buffer Type Power Well INT/OD2 I/O 111 I/O Keyboard Data. Transfers the keyboard data between the SuperI/O chip and the external keyboard using the PS/2 protocol. This pin is driven by the internal, inverted KBC P27 signal and is VDD, VSB connected internally to KBC P10. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. To enable the activity during power off, it must be pulled up to Keyboard and Mouse standby voltage. I/O INTS/OD14 KBRST 8 I/O INT/OD2 113 I/O Gate A20. KBC gate A20 (P21) output. INTS/OD14 112 MCLK VDD Description Keyboard Clock. Transfers the keyboard clock between the SuperI/O chip and the external keyboard using the PS/2 protocol. This pin is driven by the internal, inverted KBC P26 signal and is VDD, VSB connected internally to the T0 signal of the KBC. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. To enable the activity during power off, it must be pulled up to Keyboard and Mouse standby voltage. KBDAT VDD KBD Reset. Keyboard Reset (P20) output. INTS/OD14 Mouse Clock. Transfers the mouse clock between the SuperI/O chip and the external keyboard using the PS/2 protocol. This pin is driven by the internal, inverted KBC P23 signal and is VDD, VSB connected internally to KBC T1. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. To enable the activity during power off, it must be pulled up to Keyboard and Mouse standby voltage. Mouse Data. Transfers the mouse data between the SuperI/O chip and the external keyboard using the PS/2 protocol. This pin is driven by the internal, inverted KBC P22 signal and is VDD, VSB connected internally to KBC P11. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. To enable the activity during power off, it must be pulled up to Keyboard and Mouse standby voltage. MDAT 114 I/O INTS/OD14 P12, P16, P17 6,127, 7 I/O INT/OD2 1.4.9 (Continued) VDD I/O Port. KBC open-drain signal for general-purpose input and output, controlled by KBC firmware. Parallel Port Signal ACK Pin/s 79 AFD_DSTRB 93 I/O Buffer Type Power Well I O INT OD14, O14/14 Description VDD Acknowledge. Pulsed low by the printer to indicate that it has received data from the Parallel Port. VDD AFD - Automatic Feed. When low, instructs the printer to automatically feed a line after printing each line. This pin is in TRI-STATE after a 0 is loaded into the corresponding control register bit. An external 4.7 KΩ pull-up resistor should be attached to this pin. DSTRB - Data Strobe (EPP). Active low, used in EPP mode to denote a data cycle. When the cycle is aborted, DSTRB becomes inactive (high). BUSY_WAIT 78 I INT VDD Busy. Set high by the printer when it cannot accept another character. Wait. In EPP mode, the Parallel Port device uses this active low signal to extend its access cycle. ERR I INT VDD Error. Set active low by the printer when it detects an error. www.national.com 91 24 1.0 Signal/Pin Connection and Description Signal Pin/s (Continued) I/O Buffer Type Power Well Description INIT 89 O OD14, O14/14 VDD Initialize. When low, initializes the printer. This signal is in TRI-STATE after a 1 is loaded into the corresponding control register bit. Use an external 4.7 KΩ pull-up resistor. PD7-5 PD4-3, PD2, PD1 PD0 80-82 85-86 88, 90 92 I/O INT, O14/14 VDD Parallel Port Data. Transfer data to and from the peripheral data bus and the appropriate Parallel Port data register. These signals have a high current drive capability. PE 77 I INT VDD Paper End. Set high by the printer when it is out of paper. This pin has an internal weak pull-up or pull-down resistor. SLCT 76 I INT VDD Select. Set active high by the printer when the printer is selected. VDD SLIN - Select Input. When low, selects the printer. This signal is in TRI-STATE after a 0 is loaded into the corresponding control register bit. Uses an external 4.7 KΩ pull-up resistor. ASTRB - Address Strobe (EPP). Active low, used in EPP mode to denote an address or data cycle. When the cycle is aborted, ASTRB becomes inactive (high). VDD STB - Data Strobe. When low, Indicates to the printer that valid data is available at the printer port. This signal is in TRISTATE after a 0 is loaded into the corresponding control register bit. An external 4.7 KΩ pull-up resistor should be employed. WRITE - Write Strobe. Active low, used in EPP mode to denote an address or data cycle. When the cycle is aborted, WRITE becomes inactive (high). SLIN_ASTRB 87 STB_WRITE 94 O O OD14, O14/14 OD14, O14/14 1.4.10 Power and Ground Signal Pin/s I/O Buffer Type Power Well Description AVSS 45 I AGND - Analog Ground. AVDD 44 I PWR - Analog 3.3V Power Supply Provides power to the analog circuits. VBAT 30 I INULR - Battery Power Supply. Provides battery back-up to the System Wake-Up Control registers when VSB is lost (power-fail). The pin is connected to the internal logic through a series resistor for UL protection. VDD 20, 52, 83, 115 I PWR - Main 3.3V Power Supply. VSB 31 I PWR - Standby 3.3V Power Supply. Provides power to the Wake-Up Control circuitry while the main power supply is turned off. VSS 19, 51, 84, 116 I GND - Ground. 25 www.national.com 1.0 Signal/Pin Connection and Description (Continued) 1.4.11 Protection Signal Pin(s) I/O Buffer Type Power Well Description CHASI 29 I INC VPP Chassis Intrusion Input. Any change of this pin sets the intrusion detection. For correct operation, this pin must be tied to VSS when it is not used. CHASO 28 O OD6 VSB Chassis Intrusion Output. When low, indicates that an intrusion indication is set. CHLOCK 1 O O12/12 VDD Chassis Hood Lock. When low, locks the chassis hood solenoid. CHUNLOCK 128 O O12/12 VDD Chassis Hood Unlock. When low, unlocks the chassis hood solenoid. XLOCK I INT VDD Access Lock. When low, this pin blocks read/write from/to the SuperI/O Configuration 6 (SIOCF6) register to prevent accidental access. 53 1.4.12 Serial Port 1 and Serial Port 2 Signal Pin/s I/O Buffer Type Power Well Description CTS1 CTS2 100 108 I INTS VDD Clear to Send. When low, indicates that the modem or other data transfer device is ready to exchange data. DCD1 DCD2 95 103 I INTS VDD Data Carrier Detected. When low, indicates that the modem or other data transfer device has detected the data carrier. DSR1 DSR2 96 104 I INTS VDD Data Set Ready. When low, indicates that the data transfer device, e.g., modem, is ready to establish a communications link. VDD Data Terminal Ready. When low, indicates to the modem or other data transfer device that the UART is ready to establish a communications link. After a system reset, these pins provide the DTR function and set these signals to inactive high. Loopback operation holds them inactive. Baud Output. Provides the associated serial channel baud rate generator output signal if test mode is selected, i.e., bit 7 of the EXCR1 Register is set. DTR1_BOUT1 is used also as BADDR. DTR1_ BOUT1 101 DTR2_ BOUT2 109 RI1 RI2 102 110 O O3/6 I INTS Ring Indicator. When low, indicates that a telephone ring signal VDD, VSB has been received by the modem. They are monitored during power-off for wake-up event detection. RTS1 RTS2 98 106 O O3/6 VDD Request to Send. When low, indicates to the modem or other data transfer device that the corresponding UART is ready to exchange data. A system reset sets these signals to inactive high, and loopback operation holds them inactive. RTS1 is used also as TEST. SIN1 SIN2 97 105 I INTS VDD Serial Input. Receive composite serial data from the communications link (peripheral device, modem or other data transfer device). SOUT1 SOUT2 99 107 O O3/6 VDD Serial Output. Send composite serial data to the communications link (peripheral device, modem or other data transfer device). These signals are set active high after a system reset. www.national.com 26 1.0 Signal/Pin Connection and Description (Continued) 1.4.13 Strap Configuration Signal BADDR PSLDC0 PSLDC1 PSONPOL TEST Pin/s I/O Buffer Type Power Well 101 I 99 107 I 109 I 98 I Description VDD Base Address. Sampled by the trailing edge of the system reset to determine the base address of the configuration Index-Data register pair. During reset, it is pulled down by internal 30 KΩ resistor. If no pull-up resistor is connected, it is sampled low, setting the Index-Data pair at 2Eh-2Fh. Connecting a 10 KΩ external pull-up resistor to VDD would make it sample high, setting the Index-Data pair at 4Eh-4Fh. INSTRP VSB1 Power Supply and LED Configuration. If no pull-up resistor is connected to these pins, pins 33-35 and 37 function as PWBTOUT, PSON, PWBTIN and SLPS5,respectively. Connecting a 10K external pull-up resistor to VSB causes these pins to function as GPOS0, GPOS1 and GPIS2 and AVI0, respectively. INSTRP VSB1 Power Supply On Polarity. If no pull-up resistor is connected to this pin, PSON is set active low with open-drain output. Connecting a 10K external pull-up resistor to VSB causes PSON to be set to active high with push-pull output. VDD Test. If sampled high on the trailing edge of system reset, this signal forces the device into test mode. This pin is for National Semiconductor use only and should be left unconnected. To put the chip in Test mode, connect an external pull-up to this pin. Otherwise, leave it unconnected or connected to the UART transceiver. INSTRP INSTRP 1. Make sure that the Serial Port driver is back-drive protected. 1.4.14 System Hardware Monitoring Signal Pin(s) I/O Buffer Type Power Well Description ALARM 27 O OD6 VSB AVI0-6 37-43 I INAN1 AVDD Analog Voltage Inputs. Analog inputs of the A/D converter. D1N D2N 47 49 I INAN3 AVDD Diode Cathode. Diodes 1 and 2 return current sink. Must be grounded when not used. D1P D2P 48 50 O OAN2 AVDD Diode Anode. Diodes 1 and 2 current source. Connected to remote discrete diodes. OTS1 OTS2 24 25 O OD6 VSB Overtemperature Shutdown. Indicates that an overtemperature was detected. See Section 2.9.10, the SuperI/O Configuration A register, bit 0, for further details on which pin/s is/are active for remote and local temperature sensing. VREF 46 I/O INAN2, OAN1 AVDD Reference Voltage. Provides reference voltage for the on-chip A/D circuits. An external reference voltage should be connected to this input. Alarm. Alerts on voltage input mismatch. 27 www.national.com 1.0 Signal/Pin Connection and Description (Continued) 1.4.15 System Wake-Up Control Signal Pin/s I/O Buffer Type Power Well Description LED1 LED2 25 26 O O12/12 VSB LED. VSB-powered pins with programmable outputs, each of which can be used to produce a 0, 0.25, 0.5, 1, 4 Hz waveform for LED control. GPIE6-7 58-59 I INTS VSB General-Purpose Input Event. GPIOE0-5 23-28 I/O INTS/ OD6, O3/6 VSB General-Purpose I/O Event. VSB-powered pins. GPIS2 35 I INTS VSB General-Purpose Input Standby. VSB-powered pin. GPOS0-1 33-34 O OD6, O3/6 VSB General-Purpose Output Standby. VSB-powered pins. PSON 34 O O4, OD12 VSB Power Supply On. Active level (low or high via PSONPOL strap) instructs the main power supply to turn the power on. PSON output signal is open-drain when active low and push-pull when active high. PWBTIN 35 I INTS VSB Power Button In. Active (low) level indicates a user request to turn the power on or off. This pin has an internal Schmitt-trigger input buffer and debounce protection of at least 16 ms. PWBTOUT 33 O OD12 VSB Power Button Out. Active (low) level serves as output to the chipset power button input. VSB Power-Up Request. Active (low) level indicates that wake-up event has occurred and causes the chipset to turn the power supply on or to exit its current sleep state. The open-drain output must be pulled up to VSB in order to function during power-off. PWUREQ 32 O OD6 RING 27 I INTS VSB Telephone Line Ring. Detection of a pulse train on the RING pin is a wake-up event that can activate the power-up request (PWUREQ). The pin has a Schmitt-trigger input buffer, powered by VSB. SLPS3 36 I INTS VSB Sleep State 3, 4 or 5. Input from this pin is assumed to be driven by the system’s ACPI controller to indicate the system’s power state. SLPS5 37 I INTS VSB Sleep State 4 or 5. Input from this pin is assumed to be driven by the system’s ACPI controller to indicate the system’s power state. 1.4.16 WATCHDOG Timer (WDT) Signal WDO www.national.com Pin/s 56 I/O Buffer Type Power Well O OD6, O3/6 VDD Description WATCHDOG Out. Low level indicates that the WATCHDOG Timer has reached its time-out period without being retriggered. The output type and an optional pull-up are configurable. 28 1.0 Signal/Pin Connection and Description 1.5 (Continued) INTERNAL PULL-UP AND PULL-DOWN RESISTORS The signals listed in Table 4 can optionally support internal pull-up (PU) and/or pull-down (PD) resistors. See Section 12.3 for the values of each resistor type. Table 4. Internal Pull-Up and Pull-Down Resistors Signal Pin/s Type Comments ACCESS.bus (ACB) SCL SDA 54 PU28 Programmable 55 PU28 Programmable General-Purpose Input/Output (GPIO) Ports GPIO00-07 2-9 PU28 GPIO10 GPIO11-14 GPO15 GPIO16-17 21 53-56 57 69, 71 PU28 GPIO20-27 117-124 PU28 Programmable GPIO30-33 GPIO34 125-128 1 PU28 Programmable Programmable Programmable Keyboard and Mouse Controller (KBC) P12, P16, P17 6,127,7 PU28 Strap Configuration BADDR 101 PD60 Strap PSLDC0 99 PD60 Strap PSLDC1 107 PD60 Strap PSONPOL 109 PD60 Strap TEST 98 PD60 Strap Parallel Port ACK 79 PU220 AFD_DSTRB 93 PU400 BUSY_WAIT 78 PD120 ERR 91 PU220 INIT 89 PU400 PE 77 SLCT 76 PD120 SLIN_ASTRB 87 PU400 STB_WRITE 94 PU400 PU220/ PD120 29 Programmable www.national.com 1.0 Signal/Pin Connection and Description Signal Pin/s (Continued) Type Comments System Wake-Up Control (SWC) GPIOE0-5 23-28 PU28 GPIS2 35 PU220 PSON/GPOS1 34 PU28 PWBTIN 35 PU220 PWBTOUT 33 PU28 RING 27 PU28 Programmable WATCHDOG Timer (WDT) WDO www.national.com 56 PU28 30 Programmable 2.0 Device Architecture and Configuration The PC87365 SuperI/O device comprises a collection of generic and proprietary functional blocks. Each functional block is described in a separate chapter in this document. However, some parameters in the implementation of each functional block may vary per SuperI/O device. This chapter describes the PC87365 structure and provides all logical device specific information, including special implementation of generic blocks, system interface and device configuration. 2.1 OVERVIEW The PC87365 consists of 13 logical devices, the host interface and a central set of configuration registers, all built around a central internal bus. The internal bus is similar to an 8-bit ISA bus protocol. See Figure 1, which illustrates the blocks and related logic. The system interface serves as a bridge between the external LPC Interface and the internal bus. It supports 8-bit I/O Read, 8-bit I/O Write and 8-bit DMA transactions, as defined in Intel’s LPC Interface Specification, Revision 1.0. The central configuration register set supports ACPI-compliant PnP configuration. The configuration registers are structured as a subset of the Plug and Play Standard registers, defined in Appendix A of the Plug and Play ISA Specification, Revision 1.0a by Intel and Microsoft. All system resources assigned to the functional blocks (I/O address space, DMA channels and IRQ lines) are configured in, and managed by, the central configuration register set. In addition, some function-specific parameters are configurable through the configuration registers and distributed to the functional blocks through special control signals. 2.2 CONFIGURATION STRUCTURE AND ACCESS The configuration structure is comprised of a set of banked registers that are accessed via a pair of specialized registers. 2.2.1 The Index-Data Register Pair Access to the SuperI/O configuration registers is via an Index-Data register pair, using only two system I/O byte locations. The base address of this register pair is determined during reset, according to the state of the hardware strapping option on the BADDR pin. Table 5 shows the selected base addresses as a function of BADDR. Table 5. BADDR Strapping Options I/O Address BADDR Index Register Data Register 0 2Eh 2Fh 1 4Eh 4Fh The Index register is an 8-bit R/W register located at the selected base address (Base+0). It is used as a pointer to the configuration register file and holds the index of the configuration register that is currently accessible via the Data register. Reading the Index register returns the last value written to it (or the default of 00h after reset). The Data register is an 8-bit virtual register, used as a data path to any configuration register. Accessing the Data register actually accesses the configuration register that is currently pointed to by the Index register. 31 www.national.com 2.0 Device Architecture and Configuration FANIN0-2 FANOUT0-2 SLCT PE BUSY_WAIT ACK SLIN_ASTRB INIT PD0-7 ERR AFD_DSTRB STB_WRITE RDATA WDATA WGATE HDSEL DIR STEP TRK0 INDEX DSKCHG WP MTR1,0 DR1,0 DENSEL DRATE0 LED1,2 GPIE6,7 GPIOE0-5 GPIS2 GPOS0,1 PSON PWBTIN PWBTOUT PWUREQ RING SLPS5 SLPS3 BADDR PSLDC0,1 TEST PSONPOL Serial Port 1 WATCHDOG Timer Fan Speed Control & Monitor Serial Port 2 with IR Parallel Port Keyboard & Mouse Controller FDC ACCESS. bus Bus Interface SIN2 SOUT2 RTS2 DTR2/BOUT2 CTS2 DSR2 DCD2 RI2 P12,P16,P17 GA20 KBCLK KBDAT KBRST MDAT MCLK SCL SDA CLKIN LRESET LCLK SERIRQ LDRQ LFRAME LAD3-0 SMI PIRQ3-7,9-12,14-15 System Wake-Up Control XLOCK CHLOCK Protection Strap Config System Hardware Monitoring Config & Control Registers Figure 1. PC87365 Detailed Block Diagram www.national.com SIN1 SOUT1 RTS1 DTR1/BOUT1 CTS1 DSR1 DCD1 RI1 IRRX1,IRRX2 IRTX IRSL0-2 IRSL3 Control Signals WDO GPIO Ports Internal Bus GPIO30-34 GPIO20-27 GPIO10-14,16,17 GPO15 GPIO00-07 (Continued) 32 CHUNLOCK CHASI CHASO ALARM AVI0-6 D1N,D2N D1P,D2P OTS1,2 VREF 2.0 Device Architecture and Configuration 2.2.2 (Continued) Banked Logical Device Registers Structure Each functional block is associated with a Logical Device Number (LDN). The configuration registers are grouped into banks, where each bank holds the standard configuration registers of the corresponding logical device. Table 6 shows the LDN values of the PC87365 functional blocks. Figure 2 shows the structure of the standard configuration register file. The SuperI/O control and configuration registers are not banked and are accessed by the Index-Data register pair only, as described above. However, the device control and device configuration registers are duplicated over 13 banks for 13 logical devices. Therefore, accessing a specific register in a specific bank is performed by two dimensional indexing, where the LDN register selects the bank (or logical device) and the Index register selects the register within the bank. Accessing the Data register while the Index register holds a value of 30h or higher results in a physical access to the Logical Device Configuration registers currently pointed to by the Index register, within the logical device currently selected by the LDN register. 07h Logical Device Number Register 20h 2Fh SuperI/O Configuration Registers 30h Logical Device Control Register 60h 63h 70h 71h 74h 75h F0h FEh Standard Logical Device Configuration Registers Special (Vendor-defined) Logical Device Configuration Registers Bank Select Banks (One per Logical Device) Figure 2. Structure of the Standard Configuration Register File Table 6. Logical Device Number (LDN) Assignments LDN Functional Block 00h Floppy Disk Controller (FDC) 01h Parallel Port (PP) 02h Serial Port 2 with IR (SP2) 03h Serial Port 1 (SP1) 04h System Wake-Up Control (SWC) 05h Keyboard and Mouse Controller (KBC) - Mouse interface 06h Keyboard and Mouse Controller (KBC) - Keyboard interface 07h General-Purpose I/O (GPIO) Ports 08h ACCESS.bus Interface (ACB) 09h Fan Speed Control and Monitor (FSCM) 0Ah WATCHDOG Timer (WDT) 0Dh Voltage Level Monitor (VLM) 0Eh Temperature Sensor (TMS) Write accesses to unimplemented registers (i.e., accessing the Data register while the Index register points to a non-existing register) are ignored and read returns 00h on all addresses except for 74h and 75h (DMA configuration registers), which returns 04h (indicating no DMA channel is active). The configuration registers are accessible immediately after reset. 33 www.national.com 2.0 Device Architecture and Configuration 2.2.3 (Continued) Standard Logical Device Configuration Register Definitions Unless otherwise noted in Tables 7 through 12: ● All registers are read/write. ● All reserved bits return 0 on reads, except where noted otherwise. They must not be modified as it may cause unpredictable results. Use read-modify-write to prevent the values of reserved bits from being changed during write. ● Write only registers should not use read-modify-write during updates. Table 7. Standard Control Registers Index Register Name 07h Logical Device Number 20h - 2Fh SuperI/O Configuration Description This register selects the current logical device. See Table 6 for valid numbers. All other values are reserved. SuperI/O configuration registers and ID registers Table 8. Logical Device Activate Register Index Register Name 30h Activate Description Bit 0 - Logical device activation control 0: Disabled 1: Enabled Bits 7-1 - Reserved Table 9. I/O Space Configuration Registers Index Register Name Description 60h I/O Port Base Address Bits (15-8) Indicates selected I/O lower limit address bits 15-8 for I/O Descriptor 0. Descriptor 0 61h I/O Port Base Address Bits (7-0) Indicates selected I/O lower limit address bits 7-0 for I/O Descriptor 0. Descriptor 0 62h I/O Port Base Address Bits (15-8) Indicates selected I/O lower limit address bits 15-8 for I/O Descriptor 1. Descriptor 1 63h I/O Port Base Address Bits (7-0) Indicates selected I/O lower limit address bits 7-0 for I/O Descriptor 1. Descriptor 1 www.national.com 34 2.0 Device Architecture and Configuration (Continued) Table 10. Interrupt Configuration Registers Index Register Name Description 70h Interrupt Number Sets IRQ, indicates the selected interrupt number and enables wake-up on IRQ. and Wake-Up on Bit 4 - Enables wake-up on the IRQ of the logical device. When enabled, IRQ IRQ Enable assertion triggers a wake-up event. 0: Disabled (default) 1: Enabled Bits 3-0 select the interrupt number. A value of 1 selects IRQL1. A value of 15 selects IRQL15. IRQL0 is not a valid interrupt selection and represent no interrupt selection. Note: If the BIOS routine that sets IRQ does not use a Read-Modify-Write sequence, it might reset bit 4. To ensure that the system wakes up, the BIOS must set bit 4 before the system goes to sleep. 71h Interrupt Request Indicates the type and level of the interrupt request level selected in the previous Type Select register. If a logical device supports only one type of interrupt, this register may be read only. Bits 7-2 - Reserved. Bit 1 - Level of the interrupt request selected in the previous register 0: Low polarity 1: High polarity Bit 0 - Type of interrupt request selected in the previous register 0: Edge 1: Level Table 11. DMA Configuration Registers Index Register Name Description 74h DMA Channel Select 0 Indicates selected DMA channel for DMA 0 of the logical device (0 - The first DMA channel in case of using more than one DMA channel). Bits 2-0 select the DMA channel for DMA 0. The valid choices are 0-3, where a value of 0 selects DMA channel 0, 1 selects channel 1, etc. A value of 4 indicates that no DMA channel is active. The values 5-7 are reserved. 75h DMA Channel Select 1 Indicates selected DMA channel for DMA 1 of the logical device (1 - The second DMA channel in case of using more than one DMA channel). Bits 2-0 select the DMA channel for DMA 1. The valid choices are 0-3, where a value of 0 selects DMA channel 0, 1 selects channel 1, etc. A value of 4 indicates that no DMA channel is active. The values 5-7 are reserved. Table 12. Special Logical Device Configuration Registers Index Register Name F0h-FEh Logical Device Configuration Description Special (vendor-defined) configuration options. 35 www.national.com 2.0 Device Architecture and Configuration 2.2.4 (Continued) Standard Configuration Registers Index SuperI/O Control and Configuration Registers Logical Device Control and Configuration Registers one per Logical Device (some are optional) Register Name 07h Logical Device Number 20h SuperI/O ID 21h SuperI/O Configuration 1 22h SuperI/O Configuration 2 23h SuperI/O Configuration 3 24h SuperI/O Configuration 4 25h SuperI/O Configuration 5 26h SuperI/O Configuration 6 27h SuperI/O Revision ID 28h SuperI/O Configuration 8 2Ah SuperI/O Configuration A 2Bh SuperI/O Configuration B 2Ch SuperI/O Configuration C 2Dh SuperI/O Configuration D 2Eh Reserved exclusively for National use 30h Logical Device Control (Activate) 60h I/O Base Address Descriptor 0 Bits 15-8 61h I/O Base Address Descriptor 0 Bits 7-0 62h I/O Base Address Descriptor 1 Bits 15-8 63h I/O Base Address Descriptor 1 Bits 7-0 70h Interrupt Number and Wake-Up on IRQ Enable (see note, p. 35) 71h IRQ Type Select 74h DMA Channel Select 0 75h DMA Channel Select 1 F0h Device Specific Logical Device Configuration 1 F1h Device Specific Logical Device Configuration 2 F2h Device Specific Logical Device Configuration 3 Figure 3. Configuration Register Map SuperI/O Control and Configuration Registers The SuperI/O Configuration registers at indexes 20h and 27h are mainly used for part identification, global power management and the selection of pin multiplexing options. For details, see Section 2.9. Logical Device Control and Configuration Registers A subset of these registers is implemented for each logical device. See functional block description in the following sections. www.national.com 36 2.0 Device Architecture and Configuration (Continued) Control The only implemented control register for each logical device is the Activate register at index 30h. Bit 0 of the Activate register controls the activation of the associated function block. Activation of the block enables access to the block’s registers and attaches its system resources, which are unused as long as the block is not activated. Other effects may apply on a function-specific basis (such as clock enable and active pinout signaling). Standard Configuration The standard configuration registers are used to manage the PnP resource allocation to the functional blocks. The I/O port base address descriptor 0 is a pair of registers at Index 60-61h, holding the (first or only) 16-bit base address for the register set of the functional block. An optional 16-bit second base-address (descriptor 1) at index 62-63h is used for logical devices with more than one continuous register set. Interrupt Number and Wake-Up on IRQ Enable (index 70h) and IRQ Type Select (index 71h) allocate an IRQ line to the block and control its type. DMA Channel Select 0 (index 74h) allocates a DMA channel to the block, where applicable. DMA Channel Select 1 (index 75h) allocates a second DMA channel, where applicable. Special Configuration The vendor-defined registers, starting at index F0h, are used to control function-specific parameters such as operation modes, power saving modes, pin TRI-STATE, clock rate selection and non-standard extensions to generic functions. 2.2.5 Default Configuration Setup The default configuration setup of the PC87365 can include four reset types, described below. See specific register descriptions for the bits affected by each reset type. • Software Reset This reset is enabled by bit 1 of the SIOCF1 register, which resets all logical devices. A software reset also resets most bits in the SuperI/O control and configuration registers (see Section 2.9 for the bits not affected). This reset does not affect register bits that are locked for write access. • Hardware Reset This reset is activated by the assertion of the LRESET input. It resets all logical devices, with the exception of the System Wake-Up Control (SWC). It also resets all SuperI/O control and configuration registers, except for those that are batterybacked. • VPP Power-Up Reset This reset is activated when either VSB or VBAT is powered up after both have been off. VPP is an internal voltage which is a combination of VSB and VBAT. VPP is taken from VSB if VSB is greater than the minimum (Min) value defined in the Device Characteristics chapter; otherwise, VBAT is used as the VPP source. This reset resets all registers whose values are retained by VPP. • VSB Power-Up Reset This is an internally generated reset that resets the SWC, excluding those SWC registers whose values are retained by VPP. This reset is activated after VSB is powered up. In the event of a hardware reset, the PC87365 wakes up with the following default configuration setup: — The configuration base address is 2Eh or 4Eh, according to the BADDR strap pin value, as shown in Table 5. — The Keyboard Controller (KBC) is active and all other logical devices are disabled, with the exception of the SWC, which remains functional but whose registers cannot be accessed. — All multiplexed GPIO pins, except for pins whose function is controlled by battery-backed registers and pins 8 and 9 (which are controlled by bits 1 and 0 of the SIOCF3 register) are configured as GPIO pins, with an internal static pullup (default direction is input). In the event of either a hardware or a software reset, the PC87365 wakes up with the following default configuration setup: — The legacy devices are assigned with their legacy system resource allocation. — The National proprietary functions are not assigned with any default resources and the default values of their base addresses are all 00h. 37 www.national.com 2.0 Device Architecture and Configuration 2.2.6 (Continued) Power States The following terminology is used in this document to describe the various possible power states: • Power On Both VSB and VDD are active. • Power Off VSB is active and VDD is inactive. • Power Fail Both VSB and VDD are inactive. Note: The following state is illegal: VDD active and VSB inactive. 2.2.7 Address Decoding A full 16-bit address decoding is applied when accessing the configuration I/O space as well as the registers of the functional blocks. However, the number of configurable bits in the base address registers varies for each logical device. The lower 1, 2, 3, 4 or 5 address bits are decoded within the functional block to determine the offset of the accessed register within the logical device’s I/O range of 2, 4, 8, 16 or 32 bytes, respectively. The rest of the bits are matched with the base address register to decode the entire I/O range allocated to the logical device. Therefore, the lower bits of the base address register are forced to 0 (read only) and the base address is forced to be 2, 4, 8, 16 or 32 byte-aligned, according to the size of the I/O range. The base address of the FDC, Serial Port 1, Serial Port 2 with IR and KBC are limited to the I/O address range of 00h to 7FXh only (bits 11-15 are forced to 0). The Parallel Port base address is limited to the I/O address range of 00h to 3F8h. The addresses of the non-legacy logical devices are configurable within the full 16-bit address range (up to FFFXh). In some special cases, other address bits are used for internal decoding (such as bit 2 in the KBC and bit 10 in the Parallel Port). The KBC has two I/O descriptors with some implied dependency between them. For more details, see the description of the base address register for each logical device. 2.3 INTERRUPT SERIALIZER The Interrupt Serializer translates parallel interrupt request (PIRQ) signals received from external devices, via the PIRQn pins, into serial interrupt request data transmitted over the SERIRQ bus. This enables the integration of devices that support only parallel IRQ in a system which supports only serial IRQs. Figure 4 shows the interrupt serialization mechanism. Internal IRQ Sources IRQ Mapping and Polarity Control Bus Interface Polarity/ Mapping Control Signals Internal Mapped IRQs Non-Shared PIRQs IRQ3 IRQ Sharing Mechanism Interrupt Serializer SERIRQ IRQ15 Shared PIRQs PIRQn Pins Figure 4. Interrupt Serialization Mechanism PIRQ signals that enter the device are fed into an IRQ sharing mechanism. This mechanism combines them with internal IRQ signals that are mapped to their associated IRQ slots. The resulting internal shared IRQs are then fed into the Interrupt Serializer, where they are translated into serial data and transmitted over the SERIRQ bus. The IRQ sharing mechanism allows an internal IRQ and an external PIRQ to share the same IRQ slot. To share an IRQ slot, all IRQ sources routed to it, including possibly a PIRQn pin, must be active low. When multiple IRQ sources are set to share an IRQ slot, the corresponding internal IRQ signal is a logic AND of all IRQ sources. When an IRQ slot is exclusively used by a PIRQ pin, each transition sensed on this PIRQ pin is translated into a new value. This value is transmitted over the SERIRQ bus during the corresponding IRQ slot. A transition on PIRQn results in a new value that is transmitted during IRQ slot “n” of the SERIRQ bus. For example, a transition on PIRQ3 is translated into the www.national.com 38 2.0 Device Architecture and Configuration (Continued) transmission of the new value of PIRQ3 during slot 3 of the SERIRQ bus. No polarity adjustment occurs during this translation process. Therefore, when the level of a PIRQn pin goes high or low, the result is transmitted with no polarity adjustment during slot “n” of the SERIRQ bus. The Interrupt Serializer is controlled by bit 6, Pins 117-127 Select PIRQ, of SuperI/O Configuration 1 register. When this bit is set to 0 (default), the Interrupt Serializer is disabled. When it is set to 1, the Interrupt Serializer is enabled and each PIRQn input function is selected on its associated pin. The PIRQn input value is then routed to the Interrupt Serializer as the IRQ value to be driven onto IRQ slot “n” when at least one of the following conditions is true: ● Slot “n” is not selected by any internal IRQ source. ● Slot “n” is selected by an internal IRQ source which is set for sharing (low polarity). Otherwise, the IRQ value driven onto IRQ slot “n” is the value of any internal IRQ that is selected. 2.4 PROTECTION The PC87365 provides features to protect the PC at mechanical and software levels. At the mechanical level, the device can detect intrusion to the chassis of the PC. It can also control the solenoids that lock and unlock the chassis. At the hardware level, the device can disable I/O port access. This protects system integrity by enabling the primary operating software to prevent other unwanted I/O operations by other software. At the software level, the device can be locked to protect configuration bits or alteration of the hardware configuration of the device, as well as internal GPIO settings and several types of configuration settings. All protection mechanisms can optionally be used. 2.4.1 Chassis Intrusion Detection The Chassis Intrusion Detection mechanism is based on the state of pin 29, CHASI. This pin reflects the status of an external switch that indicates the PC chassis state. Bits 4,5 of the SIOCFB register monitor this pin and provide two types of information. Bit 4 reports a previously detected chassis intrusion, defined as any kind of transition on the CHASI pin. Bit 5 reflects the momentary value of the CHASI pin. For further details on the SIOCFB register, see Section 2.9.11. To prevent the CHASI pin from detecting a false chassis intrusion, it is implemented with an internal noise filter. A chassis intrusion event can be reported to the host system by either software or hardware. When using software, the system must read the SIOCFB register to check if an intrusion event has occurred. When using hardware, the device provides the following means for indicating chassis intrusion: ● Dedicated output (CHASO). ● SMI assertion. To use the CHASO function, it must first be selected by setting bit 6 of the SIOCFA register to 1. Thereafter, whenever a chassis intrusion is detected, the CHASO pin reflects the value of bit 4 of the SIOCFB register. When bit 4 of this register is set to 1, the CHASO pin is asserted (driven low). It is de-asserted when this bit is cleared. To use the SMI assertion, it must either be selected on its pin or routed to interrupt request channel 2. To select SMI on its pin, set bit 2 of the SIOCF3 register to 1 (for further details, see Section 2.9.4). To route the SMI signal to interrupt request channel 2, set bit 4 of the SIOCF5 register to 1 (for further details, see Section 2.9.6). In addition, the chassis intrusion event must be routed to the SMI signal by setting bit 5 of the SIOCF8 register to 1 (for further details, see Section 2.9.9). Thereafter, whenever a chassis intrusion is detected, the SMI signal reflects bit 4 of the SIOCFB register. When bit 4 of this register is set to 1, the SMI signal and the selected target indication are asserted (driven low). The SMI signal is de-asserted when this bit 4 is cleared. 2.4.2 Chassis Lock and Unlock The Chassis Lock and Unlock mechanism is based on the output functions of pin 1, CHLOCK and pin 128, CHUNLOCK, as well as the values of bits 2, 3 of the SIOCF5 register. A lock operation is defined as the assertion of CHLOCK for approximately the next 0.75 seconds and an unlock operation as the assertion of CHUNLOCK for the same duration of time. To use this mechanism, CHLOCK and CHUNLOCK must first be selected on their respective pins. To select CHLOCK, write 10 to bits 1-0 of the SIOCF2 register. To select CHUNLOCK, write 10 to bits 1-0 of the SIOCF5 register. The CHLOCK and CHUNLOCK functions can then be operated using bits 2 and 3 of the SIOCF5 register. Bit 3 of the SIOCF5 register determines if the operation to be performed will be lock or unlock. When set to 0, unlock is selected; when set to 1, lock is selected. Writing to bit 2 of the SIOCF5 register initiates the operation set by bit 3 and reflects the status of the lock/unlock mechanism. Before initiating any lock/unlock operation, bit 2 must be verified to be 0. This indicates that the lock/unlock mechanism is idle and can be used to perform a new operation. When bit 3 is set to the desired value and bit 2 is verified to be 0, bit 2 can be set to 1 to initiate the operation determined by bit 3. 39 www.national.com 2.0 Device Architecture and Configuration (Continued) When bit 2 of the SIOCF5 register is set to 1, it causes the appropriate output function, either CHLOCK or CHUNLOCK, to be asserted for a duration of 0.75 second. Then, this output function is de-asserted. During the time the output function is asserted, and for an additional 0.25 second afterwards, bit 2 of the SIOCF5 register returns 1 on reads and no action can be initiated. This protection mechanism prevents lock/unlock operations from being performed at short intervals to protect the mechanical lock/unlock mechanism. 2.4.3 Access Lock to I/O Ports Locking access to the I/O ports of the device is based on the SIOCF6 register (for details, see Section 2.9.7). This protection feature is implemented for the following logical devices: ● FDC (Logical Device 0). ● Parallel Port (Logical Device 1). ● Serial Port 2 (Logical Device 2). ● Serial Port 1 (Logical Device 3). ● ACB (Logical Device 8). Each one of these logical devices has an associated bit in the SIOCF6 register. When one of these bits is set, the associated logical device is completely disabled. For example, when bit 0 of the SIOCF6 register is set to 1, the FDC is disabled. To lock access to the I/O ports, the SIOCF6 register must be set to read only. This can be done by either software or hardware. By software, set bit 7 of the SIOCF6 register to 1. This bit can only be cleared (read/write enabled) by a hardware reset. Alternatively, use the XLOCK input hardware-based function to set the SIOCF6 register to read only. First, select XLOCK on its pin, pin 53, by setting bit 4 of the SIOCF3 register to 1. XLOCK can then can be used to control the SIOCF6 register, as follows: ● When XLOCK is driven high, the SIOCF6 register is read/write. ● When XLOCK is driven low, the SIOCF6 register is read only. 2.4.4 Pin Configuration Lock To lock the pin configuration of the PC87365 in order to prevent unwanted changes to hardware configuration, set bit 7 of the SIOCF1 register to 1. Setting this bit causes all function select configuration bits, including those that are battery backed, to become read only bits. This bit can only be cleared by a hardware reset. 2.4.5 GPIO Pin Function Lock The PC87365 is capable of locking the attributes of each GPIO or Standby GPIO pin. The following attributes can be locked: ● Output enable. ● Output type. ● Static pull-up. ● Driven data. GPIO pins are locked per pin by setting the Lock bit in the appropriate GPIO Pin Configuration register. When the Lock bit is set, the configuration of the associated GPIO pin can only be released by a hardware reset. Standby GPIO pins are locked in the same manner by setting the Lock bit in the appropriate Standby GPIO Pin Configuration registers. However, once a Standby GPIO pin is locked, its locked attributes can only be released with a VSB power-up reset. 2.5 POWER SUPPLY CONTROL (PSC) The PC87365 includes hardware that can be used to ease the system’s control over the computer’s power supply. This hardware is implemented as a state machine that determines the required state of the power supply based on several input signals. It also connects to the system’s ACPI controller to share information about the system’s power state via specific interface signals. The PSC uses the pin functions SLPS3, SLPS5, PWBTIN, PWBTOUT and PSON. These functions are optional on their respective pins and must be selected to enable the PSC by setting the values of the PSLDC0,1 strap pins (see Table 14). Once enabled, the PSC can be operated in one of two modes, according to the value of bit 0 (Power Button Mode) of the SIOCFD register: ● ACPI mode. ● Legacy mode. www.national.com 40 2.0 Device Architecture and Configuration (Continued) ACPI Mode When the PSC is operated in ACPI mode (bit 0 of the SIOCFD register is set to 1), the ACPI controller of the system controls the system’s power supply by means of the SLPS3 state. When SLPS3 is set to 0, the power supply turns off; when it is set to 1, the power supply turns on. The state of the PSON output signal (either ON or OFF) is identical to the state of the SLPS3 input signal. The polarity of PSON is set by the PSONPOL strap. The only case in which the PSC affects the value of the PSON output is when a Crowbar condition occurs. A Crowbar condition is defined as the state in which PSON has been active for a certain period of time but the system’s power supply remains inactive. In this case, PSON is forced inactive, and the PWBTOUT output is pulsed to indicate to the ACPI controller that SLPS3 must be driven low, thus indirectly inactivating PSON and preventing a deadlock. For a detailed description of the Crowbar mechanism, see Crowbar Condition on the following page(s). In ACPI mode, during regular operation, the PWBTOUT output is pulsed when either of the following events occurs: ● PWBTIN is pulsed. ● A wake-up event that is routed to PWBTOUT. A wake-up event that is routed to the power button output can cause PWBTOUT to be pulsed in ACPI mode if one of the following conditions is met: ● SLPS5 is active. ● Enable Power Button Pulse on S3 (bit 3) of the SWC WK_CFG register is set to 1. However, when in ACPI mode, PWBTIN and PWBTOUT activity has no effect on the PSON output. The power button mechanism can have an indirect effect on PSON only if PWBTOUT is connected to the power button input of the ACPI controller, thus affecting the SLPS3 signal. Legacy Mode When the PSC is operated in Legacy mode (bit 0 of the SIOCFD register is set to 0), the PC87365 controls the system’s power supply. In this mode, the PSON output signal is set by the PC87365 according to the following factors: the state of input signals, the state of the power supply lines, power button activity and certain configuration bits. Although the ACPI controller does not control the system’s power supply, it tracks the system’s power state. For this purpose, the PC87365 manipulates the PWBTOUT so that the ACPI controller is always synchronized with the actual state of the PSON output. This synchronization mechanism assumes that PWBTOUT is connected to the power button input of the ACPI controller. See a schematic state diagram of the Legacy PSC mechanism in Figure 5. VSB Power-Up Reset Power Fail VSB Present AND Straps Sampled Resume AND Last State is ON Check Resume Mode Resume AND Last State Is OFF OR No Resume AND ACPI Is OFF No Resume AND ACPI Is ON Synchronize ACPI Synchronization Done PWBTOUT Falling Edge ON OFF PWBTOUT Falling Edge OR Software Power Supply Off Command Figure 5. Legacy Power Supply Control State Diagram 41 www.national.com 2.0 Device Architecture and Configuration (Continued) When VSB is first applied, the PSC state machine is initialized to Power Fail state. In this state, the mechanism waits for the PC87365 to be initialized according to strap options. Then the PSC enters Check Resume Mode state. In this state, the PSC checks if Resume to Last PSON state is enabled. If Resume to Last PSON is enabled, PSON immediately resumes the state it was in when VSB was lost. To enable this mechanism, set bit 2 of the SIOCFD register to 1 and program the ACPI controller to resume OFF state (SLPS3 = 0) after power fail recovery to allow the PSC to operate properly. If the last state of PSON was OFF, assuming that the ACPI controller also resumed OFF state, PSON is set to inactive and the PSC enters OFF state. If the last state was ON, under the same assumption, the ACPI controller must be notified to change its state to ON. This is done by pulsing the PWBTOUT output. This synchronization pulse is generated when the PSC is in Synchronize ACPI state. If Resume Last PSON State is disabled, the PSC enters either ON or OFF state according to the value of the SLPS3 input, as follows: ● If SLPS3 is low (active, state OFF), the PSC enters OFF state. ● If SLPS3 is high (inactive, state ON), the PSC enters ON state. Since SLPS3 reflects the state of the ACPI controller, the PSC actually resumes the current state of the ACPI controller. After entering either ON or OFF states, PSC moves between these two states on the following conditions: ● A falling edge on PWBTOUT (generated internally) changes the state from ON to OFF or vice versa. ● A Software Power Supply Off command, writing 1 to Power Supply Off (bit 1) of the SIOCFD register, changes the state from ON to OFF. Since many wake-up events can activate the PWBTOUT signal, these events can actually cause the PSC to change its state from OFF to ON, thus activating the PSON output. As in ACPI mode, the Crowbar protection mechanism is also active in Legacy mode. However, in this mode, when a Crowbar condition is detected, the PSC returns to OFF state, thus inactivating the PSON output. Also, to synchronize the APCI controller, the PWBTOUT is pulsed to bring it to the correct state. Table 13 summarizes the bit states that affect PSON VSB power-up default state. Table 13. PSON VSB Power-Up Default State Resume Last PSON State (SIOCFD, Bit 2) Last PSON State PSON VSB Power-Up Default 1 0 0 1 1 1 0 X Same as SLPS3 state Crowbar Condition A Crowbar condition is a situation in which the signal that directly controls the system’s power supply is active for a certain duration of time without a power supply response. To prevent this deadlock and enable reactivation of the power supply, a special crowbar mechanism is included in the PSC logic. Once the PSON is activated, assuming the power supply is off, a timer in the PSC logic starts counting. If this timer reaches its terminal count before the power supply becomes active, the PSC detects a Crowbar condition. In this case, PSON is deactivated and the PSC makes sure that the ACPI state of the system is changed to OFF. The time that causes a Crowbar condition is defined as the Crowbar Timeout. The Crowbar Timeout of the PSC can be programmed to values between 0.5-2.25 seconds. This Timeout value is set by writing the appropriate value to bits 4-3 of the SIOCFD register. For further details, refer to the description of this register in Section 2.9.13. www.national.com 42 2.0 Device Architecture and Configuration 2.6 (Continued) LED OPERATION AND STATES The device supports up to two LEDs, depending on Pin 25 and Pin 26 Function Select (bits 1-2 and bit 3) of the SIOCFA register. The polarity of both LEDs is determined by LED Polarity Control (bit 7) of the SIOCFD register. The device provides modes for software LED control when in power-on state. The device also provides modes for hardware LED control. This enables the LEDs to support features such as power and error indication. The LEDs may be operated in Software, Hardware1 or Hardware 2 modes. These modes are set by LED Mode Control (bits 2 and 3) of the SIOCFB register. Each LED can be set to On or Off or to blink at different rates by means of bits 0-2 (LED1) and bits 3-5 (LED2) of the SIOCFC register. When in power-on state (both VDD and VSB exist), the LEDs are software controlled. When in power-fail state (no VSB and no VDD), the LEDs are off. Note, however, that these rules are overridden when using the Hardware modes. Table 14 shows the effect of Hardware modes 1 and 2 on LED operation. Table 14. Effect of Hardware Modes 1 and 2 on LED Operation Mode System State Hardware1 (SIOCFB, bits 3-2=01) Hardware 2 (SIOCFB, bits 3-2=10) 2.7 LED1 LED2 VSB power-up reset Off 1 Hz blink, 50% duty cycle Power off (VSB, no VDD) Software controlled 1 Hz blink, 50% duty cycle ACPI mode and Sleep State 3 Software controlled Software controlled ACPI mode, Sleep State 5, bit 6 = 1 in SIOCFC register Software controlled and Power Supply Control enabled Software controlled ACPI mode, any other configuration Off Off Legacy mode and power off Off (no VDD) Off POWER SUPPLY CONTROL AND LED CONFIGURATION A combination of two strap pins (Power Supply and LED Configuration 0 and 1, PSLDC0,1, pins 99 and 107, respectively) determines the configuration of the power supply control pins and LEDs. Both pins 99 and 107 have weak pull-downs and are sampled on VSB power-up reset. Table 15 describes how they affect the chip configuration. Table 15. PSLDC0,1 Configuration Options 2.8 PSLDC0 (Pin 99) PSLDC1 (Pin 107) Power Supply Control LED2 0 0 Enabled (default) Not selected (default) 0 1 Disabled Selected 1 0 Disabled Not selected 1 1 Enabled Selected REGISTER TYPE ABBREVIATIONS The following abbreviations are used to indicate the Register Type: ● R/W = Read/Write. ● R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register. ● W = Write. ● RO = Read Only. ● R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. 43 www.national.com 2.0 Device Architecture and Configuration 2.9 (Continued) SUPERI/O CONFIGURATION REGISTERS This section describes the SuperI/O configuration and ID registers (those registers with first level indexes in the range of 20h - 2Eh). See Table 16 for a summary and directory of these registers. Table 16. SuperI/O Configuration Registers Index Mnemonic Register Name Power Well Type Section 20h SID SuperI/O ID VDD RO 2.9.1 21h SIOCF1 SuperI/O Configuration 1 VDD R/W 2.9.2 22h SIOCF2 SuperI/O Configuration 2 VDD R/W 2.9.3 23h SIOCF3 SuperI/O Configuration 3 VDD R/W 2.9.4 24h SIOCF4 SuperI/O Configuration 4 VDD R/W 2.9.5 25h SIOCF5 SuperI/O Configuration 5 VDD R/W 2.9.6 27h SRID SuperI/O Revision ID VDD RO 2.9.8 28h SIOCF8 SuperI/O Configuration 8 VDD R/W 2.9.9 2Ah SIOCFA SuperI/O Configuration A VPP R/W 2.9.10 2Bh SIOCFB SuperI/O Configuration B VPP R/W 2.9.11 2Ch SIOCFC SuperI/O Configuration C VPP R/W 2.9.12 2Dh SIOCFD SuperI/O Configuration D VPP R/W 2.9.13 2Eh Reserved exclusively for National use www.national.com 44 2.0 Device Architecture and Configuration 2.9.1 (Continued) SuperI/O ID Register (SID) This register contains the identity number of the chip. The PC87365 is identified by the value E5h. Location: Index 20h Type: RO Bit 7 6 5 4 3 2 1 0 0 0 1 0 1 4 3 2 1 0 SW Reset Global Device Enable 0 1 Name Chip ID Reset 2.9.2 1 1 1 SuperI/O Configuration 1 Register (SIOCF1) Location: Index 21h Type: R/W Bit 7 6 Name Pin Function Select Lock Pins 117-127 Function Select Reset 0 0 5 Number of DMA Wait States 0 Number of I/O Wait States 1 0 0 Bit Description 7 Pin Function Select Lock. This bit determines if the bits (located in the SIOCF1, 2, 3, 4, 5, A and B registers) that select pin functions are read only or read/write. When set to 1, this bit can only be cleared by a hardware reset. 0: Bits are R/W 1: Bits are RO 6 Pins 117-127 Function Select. 0: Pins 117-127 function set by SIOCF4 (default) 1: Pins 117-127 are PIRQ3-7, 9, 11-12, 14-15 5-4 3-2 Number of DMA Wait States. Bits 5 4 Number 0 0 1 1 Reserved Two (default) Six Twelve 0 1 0 1 Number of I/O Wait States. Bits 3 2 Number 0 0 1 1 Zero (default) Two Six Twelve 0 1 0 1 1 SW Reset. Read always returns 0. 0: Ignored (default) 1: Resets all the logical devices that are reset by hardware reset (with the exception of the lock bits) and resets the registers of the SWC, VLM and TMS 0 Global Device Enable. This bit controls the function enable of all the PC87365 logical devices, except System Wake-Up Control (SWC). With the exception of SWC, it allows all logical devices to be disabled simultaneously by writing to a single bit. 0: All logical devices in the PC87365 are disabled, except SWC, VLM and TMS 1: Each logical device is enabled according to its Activate register (Index 30h) (default) 45 www.national.com 2.0 Device Architecture and Configuration 2.9.3 (Continued) SuperI/O Configuration 2 Register (SIOCF2) Location: Index 22h Type: R/W Bit 7 6 5 4 3 2 Name Pin 7 Function Select Pin 6 Function Select Pin 5 Function Select Pin 4 Function Select Pin 3 Function Select Pin 2 Function Select Reset 0 0 0 0 0 0 Bit Description 7 Pin 7 Function Select. 0: GPIO05 (default) 1: P17 6 Pin 6 Function Select. 0: GPIO04 (default) 1: P12 5 Pin 5 Function Select. 0: GPIO03 (default) 1: FANOUT0 4 Pin 4 Function Select. 0: GPIO02 (default) 1: FANIN0 3 Pin 3 Function Select. 0: GPIO01 (default) 1: FANOUT1 2 Pin 2 Function Select. 0: GPIO00 (default) 1: FANIN1 1-0 Pin 1 Function Select. Bits 1 0 Function 0 0 1 1 GPIO34 (default) FANOUT2 CHLOCK Reserved 0 1 0 1 www.national.com 46 1 0 Pin 1 Function Select 0 0 2.0 Device Architecture and Configuration 2.9.4 (Continued) SuperI/O Configuration 3 Register (SIOCF3) Location: Index 23h Type: R/W Bit 7 6 5 4 3 2 1 0 Name Pin 57 Function Select Pin 56 Function Select Pins 54, 55 Function Select Pin 53 Function Select Reserved Pin 21 Function Select Pin 9 Function Select Pin 8 Function Select Reset 0 0 0 0 0 0 1 1 Bit Description 7 Pin 57 Function Select. 0: GPO15 (default) 1: IRTX 6 Pin 56 Function Select. 0: GPIO14 (default) 1: WDO 5 Pins 54, 55 Function Select. 0: GPIO12/GPIO13 (default) 1: SCL/SDA 4 Pin 53 Function Select. 0: GPIO11 (default) 1: XLOCK 3 Reserved. 2 Pin 21 Function Select. 0: GPIO10 (default) 1: SMI 1 Pin 9 Function Select. 0: GPIO07 1: GA20 (P21) (default) 0 Pin 8 Function Select. 0: GPIO06 1: KBRST (P20) (default) 47 www.national.com 2.0 Device Architecture and Configuration 2.9.5 SuperI/O Configuration 4 Register (SIOCF4) Location: Index 24h Type: Varies per bit Bit 7 6 Pin 127 Function Select Name Reset 0 5 4 3 Pins 125,126 Pins 117-124 Function Function Select Select 0 0 Bit 7-6 (Continued) 0 2 Pin 71 Function Select 0 Description Pin 127 Function Select. This is a R/W bit. Bits 7 6 P* Function 0 0 1 X 5 4 3-2 1-0 0 1 0 X 0 0 0 1 GPIO32 (default) P16 IRSL1 PIRQ15 Pins 125,126 Function Select. This is a RO bit. Bits 5 P* Function 0 0 1 0 X 1 GPIO30,31 (default) Reserved PIRQ12,14 Pins 117-124 Function Select. This is a RO bit. Bits 4 P* Function 0 0 1 0 X 1 GPIO20-27 (default) Reserved PIRQ3-7,9-11 Pin 71 Function Select. This is a R/W bit. Bits 3 2 Function 0 0 1 1 GPIO17 (default) DR1 IRSL3 Reserved 0 1 0 1 Pin 69 Function Select. This is a R/W bit. Bits 1 0 Function 0 0 1 1 GPIO16 (default) MTR1 IRSL2 Reserved 0 1 0 1 * Bit 6, Pins 117-127 Select PIRQ, of the SIOCF1 register (see page 45). www.national.com 48 1 0 Pin 69 Function Select 0 0 0 2.0 Device Architecture and Configuration 2.9.6 (Continued) SuperI/O Configuration 5 Register (SIOCF5) Location: Index 25h Type: Varies per bit Bit 7 6 5 Reset 0 0 3 2 1 Chassis SMI to IRQ2 Chassis Hood AcEnable Hood Lock tion/Status VID0 and VID1 Route Select Name 4 0 0 0 0 0 Pin 128 Function Select 0 0 Bit Description 7-5 VID0 and VID1 Route Select. Defines the routing of GPIO inputs to the VLM VID register. This is a R/W bit. Bits 765 000 001 010 011 100 Other Route Select VID0 and VID1 are not routed. VID4-VID0 are routed from GPIO11-13, GPIO16, GPIO17. Only CPU0 is supported. VID4-VID0 are routed from GPIO05, GPIO12-14, GPIO32. Only CPU0 is supported. When CPU0 is selected: VID4-VID0 are routed from GPIO20-24; when CPU1 is selected: VID4-VID0 are routed from GPIO25-27, GPIO30, GPIO31 VID4-VID0 are routed from GPIO11-13, GPIO16, GPIO17; processor select control is routed to GPIO14, which is configured as output. Reserved 4 SMI to IRQ2 Enable. This is a R/W bit. 0: Disabled (default) 1: Enabled 3 Chassis Hood Lock. This is a R/W bit. 0: Unlock (default) 1: Lock 2 Chassis Hood Action/Status. This is a R/W bit. Writing 1 operates the lock/unlock function determined by bit 3 of this register. Writing 0 deactivates an action in progress. Before setting this bit, the software must verify that it is set to 0. 0: Inactive/Ready (default) 1: Activate/Busy 1-0 Pin 128 Function Select. This is a R/W bit. Bits 1 0 Function 0 0 1 1 GPIO33 (default) FANIN2 CHUNLOCK Reserved 0 1 0 1 49 www.national.com 2.0 Device Architecture and Configuration 2.9.7 (Continued) SuperI/O Configuration 6 Register (SIOCF6) Write access to this register can be inhibited by either asserting XLOCK when it is selected on pin 53 or by setting bit 7 of this register. Activation of each logical device (bits 0-4) is also affected by bit 0 of the logical device Activate register, index 30h and bit 0 of the SIOCF1 register. Location: Index 26h Type: R/W Bit 7 Name SIOCF6 Software Lock Reset 0 6 5 General-Purpose Scratch 0 0 Bit 7 6-5 ACB Disable 3 2 1 Serial Port 1 Serial Port 2 Parallel Port Disable Disable Disable 0 0 0 0 Description SIOCF6 Software Lock. Once this bit is set to 1 by software, it can be cleared only by hardware reset. 0: Write access to bits 0-6 of this register is controlled by XLOCK (default) 1: Bits 0-6 of this register are RO General-Purpose Scratch. 4 ACB Disable. 0: Enabled (default) 1: Disabled 3 Serial Port 1 Disable. 0: Enabled (default) 1: Disabled 2 Serial Port 2 Disable. 0: Enabled (default) 1: Disabled 1 Parallel Port Disable. 0: Enabled (default) 1: Disabled 0 FDC Disable. 0: Enabled (default) 1: Disabled 2.9.8 4 SuperI/O Revision ID Register (SRID) This register contains the identity number of the chip revision. SRID is incremented on each revision. Location: Index 27h Type: RO www.national.com 50 0 FDC Disable 0 2.0 Device Architecture and Configuration 2.9.9 SuperI/O Configuration 8 Register (SIOCF8) Location: Index 28h Type: R/W Bit 7 Name Reset (Continued) 6 5 4 3 2 1 0 Mouse IRQ KBD IRQ to KBD P12 to GPI to SMI WDO to SMI VLM to SMI TMS to SMI CHASO to to SMI Enable Enable Enable Enable SMI Enable SMI Enable SMI Enable Enable 0 0 Bit 0 0 0 0 0 0 Description 7 VLM to SMI Enable. 0: Disabled (default) 1: Enabled 6 TMS to SMI Enable. 0: Disabled (default) 1: Enabled 5 CHASO to SMI Enable. 0: Disabled (default) 1: Enabled: 4 Mouse IRQ to SMI Enable. 0: Disabled (default) 1: Enabled 3 KBD IRQ to SMI Enable. 0: Disabled (default) 1: Enabled 2 KBD P12 to SMI Enable. 0: Disabled (default) 1: Enabled 1 GPI to SMI Enable. 0: Disabled (default) 1: Enabled 0 WDO to SMI Enable. 0: Disabled (default) 1: Enabled 51 www.national.com 2.0 Device Architecture and Configuration (Continued) 2.9.10 SuperI/O Configuration A Register (SIOCFA) This is a battery-backed register. Location: Index 2Ah Type: Varies per bit Bit 7 6 Name Pins 33-37 Function Select Pin 28 Function Select Reset Strap 0 5 4 Pin 27 Function Select 3 2 Pin 26 Function Select 0 0 0 1 Pin 25 Function Select 0 0 Pin 24 Function Select 0 0 Bit Description 7 Pins 33-37 Function Select. This is a RO bit. The function of the pin selected is determined during VSB powerup by the PSLDC0,1 straps. 0: PWBTOUT, PSON, PWBTIN, SLPS3, SLPS5 1: GPOS0, GPOS1, GPIS2, SLPS3, AVI0 6 Pin 28 Function Select. This is a R/W bit. 0: GPIOE5 (default at VPP power-up reset) 1: CHASO 5-4 3 Pin 27 Function Select. This is a R/W bit. Bits 5 4 Function 0 0 0 1 1 0 Other GPIOE4 (default at VPP power-up reset) RING ALARM Reserved Pin 26 Function Select. This is a R/W bit. 0: GPIOE3 (default at VPP power-up reset) 1: LED2 2-1 0 Pin 25 Function Select. This is a R/W bit. Bits 2 1 Function 0 0 0 1 1 0 Other GPIOE2 (default at VPP power-up reset) LED1 OTS2 (can be enabled only if OTS1 is enabled) Reserved Pin 24 Function Select. 0: GPIOE1 (default at VPP power-up reset) 1: OTS1. OTS1 functionality changes when OTS2 is enabled. The following table summarizes which OTS output is affected when an overtemperature is detected by any of the sources. A ‘Y’ indicates that the pin is active for this condition; an ‘N’ indicates that it is inactive. 1 OTS Pin 2 OTS Pins Source www.national.com OTS1 OTS1 OTS2 Remote 1 Y Y N Remote 2 Y N Y 52 2.0 Device Architecture and Configuration (Continued) 2.9.11 SuperI/O Configuration B Register (SIOCFB) This is a battery-backed register. Location: Index 2Bh Type: Varies per bit Bit 7 Name 6 Reserved Reset 0 0 5 4 Intrusion Level Intrusion Status X 1 Bit 7-6 3 2 LED Mode Control 0 0 Pin 59 Function Select Pin 58 Function Select 0 0 Reserved. Intrusion Level. This is a RO bit that reflects the value of pin 29 (CHASI)—either 0 or 1. 4 Intrusion Status. Write 0 to this bit to clear it. 0: No intrusion 1: Intrusion detected (default at VPP power-up reset) 1 0 Description 5 3-2 1 LED Mode Control. This is a R/W bit. Bits 3 2 Function 0 0 1 1 Software mode (default at VPP power-up reset) Hardware mode 1 (default when power supply control is disabled by PSLDC0,1 straps) Hardware mode 2 Reserved 0 1 0 1 Pin 59 Function Select. This is a R/W bit. 0: GPIE7 (default at VPP power-up reset) 1: IRRX1 0 Pin 58 Function Select. This is a R/W bit. 0: GPIE6 (default at VPP power-up reset) 1: IRRX2_IRSL0 53 www.national.com 2.0 Device Architecture and Configuration (Continued) 2.9.12 SuperI/O Configuration C Register (SIOCFC) This is a battery-backed register. Location: Index 2Ch Type: R/W Bit 7 6 LED Power LED Configura- Status in tion S4 or S5 Name Reset 0 0 Bit 7 5 4 3 2 LED2 Blink Rate 0 0 1 0 LED1 Blink Rate 0 0 0 0 Description LED Configuration. 0: One dual-colored LED (default at VPP power-up reset) 1: Two LEDs 6 Power LED Status in S4 or S5. This bit is active only when Hardware mode 2 is selected (bits 2-3 in the SIOCFB register). 0: Turn off (default at VDD power off) 1: Unchanged 5-3 2-0 LED2 Blink Rate. Bits 5 4 3 Rate (Hz) Duty Cycle 0 0 0 0 1 1 1 1 Off 0.25 0.5 1 2 3 4 On 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Always low 12.5% 25% 50%1 50% 50% 50% Always high (default at VPP power-up reset) LED1 Blink Rate. Bits 2 1 0 Rate (Hz) Duty Cycle 0 0 0 0 1 1 1 1 Off 0.25 0.5 1 2 3 4 On 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Always low (default at VPP power-up reset) 12.5% 25% 50% 50% 50% 50% Always high 1. When Hardware mode 1 is selected, this rate is set when VSB is powered up or when VDD becomes inactive while VSB is active. www.national.com 54 2.0 Device Architecture and Configuration (Continued) 2.9.13 SuperI/O Configuration D Register (SIOCFD) This is a battery-backed register. Location: Index 2Dh Type: Varies per bit Bit 7 6 LED Polarity Last PSON Control State Name Reset 0 0 5 PSON Polarity Strap Bit 7 4 3 Crowbar Timeout 1 1 2 1 Resume Power Last PSON Supply Off State 0 0 0 Power Button Mode 0 Description LED Polarity Control. This is a R/W bit. It determines if the LED outputs are active high or active low when they are lit. 0: Active high (default at VSB power-up reset) 1: Active low 6 Last Power Supply On State. This is a RO bit. When operating in Legacy mode (bit 0 of this register is set to 0), this bit reflects the state of the PSON pin sampled during the last power failure (no VSB), regardless of the polarity of PSON. 0: Off 1: On 5 Power Supply On Polarity. This is a RO bit. The polarity of PSON is determined during VSB power-up by the PSONPOL strap. 4-3 Crowbar Timeout. This is a R/W bit. Bits 5 4 Value (Seconds) 0 0 1 1 0.4 to 0.9 (typical 0.6) 0.9 to 1.4 (typical 1.1) 1.4 to 1.9 (typical 1.6) 1.9 to 2.5 (typical 2.1) (default at VPP power-up reset) 0 1 0 1 Note that for any specific condition, there is a minimum gap of 0.25 seconds between the actual high limit of a timeout setting and the low limit of the next time-out setting. 2 Resume Last Power Supply On State. This is a R/W bit. When it is set to 1, PSON resumes its last state, sampled during the last power failure, after power returns. When this bit is set to 0, the PSON state is determined by the SLPS3 state. 0: SLPS3 (default at VPP power-up reset) 1: Last PSON state. For correct operation, the system’s ACPI controller must be configured to resume to OFF. This enables the power supply control logic to know the state of the chipset ACPI state machine after power failure (no VDD and VSB). 1 Power Supply Off. This is a R/W bit. It always returns 0 when read. When using Legacy mode (bit 0 is set to 0) and setting this bit to 1, this bit inactivates the PSON output, thereby shutting off the power supply. 0: No action (default at VPP power-up reset) 1: Inactivate PSON in Legacy mode 0 Power Button Mode. This is a R/W bit. 0: Legacy (default at VSB power-up reset) 1: ACPI 55 www.national.com 2.0 Device Architecture and Configuration (Continued) 2.10 FLOPPY DISK CONTROLLER (FDC) CONFIGURATION 2.10.1 General Description The generic FDC is a standard FDC with a digital data separator and is DP8473 and N82077 software compatible. The PC87365 FDC supports 14 of the 17 standard FDC signals described in the generic Floppy Disk Controller (FDC) chapter, including: ● FM and MFM modes are supported. To select either mode, set bit 6 of the first command byte when writing to/reading from a diskette, where: 0 = FM mode 1 = MFM mode ● A logic 1 is returned for all floating (TRI-STATE) FDC register bits upon LPC I/O read cycles. Exceptions to standard FDC support include: ● Automatic media sense is not supported (MSEN0-1 pins are not implemented) ● DRATE1 is not supported. Table 17 lists the FDC functional block registers. Table 17. FDC Registers Offset1 Mnemonic 00h SRA Status A RO 01h SRB Status B RO 02h DOR Digital Output R/W 03h TDR Tape Drive R/W 04h MSR Main Status R DSR Data Rate Select 05h FIFO Data (FIFO) 06h Register Name Type W R/W N/A 07h X DIR Digital Input R CCR Configuration Control W 1. This is the 8-byte aligned FDC base address. 2.10.2 Logical Device 0 (FDC) Configuration Table 18 lists the Configuration registers that affect the FDC. Only the last two registers (F0h and F1h) are described here. See Sections 2.2.3 and 2.2.4 for descriptions of the others. Table 18. FDC Configuration Registers Index Configuration Register or Action Type Reset 30h Activate. See also bit 0 of the SIOCF1 register and bit 0 of the SIOCF6 register. R/W 60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. R/W 03h 61h Base Address LSB register bits 2 and 0 (for A2 and A0) are read only, 00b. R/W F2h 70h Interrupt Number and Wake-Up on IRQ Enable register (see note, p. 35). R/W 06h 71h Interrupt Type. Bit 1 is read/write; other bits are read only. R/W 03h 74h DMA Channel Select. R/W 02h 75h Report no second DMA assignment. RO 04h F0h FDC Configuration register. R/W 24h F1h Drive ID register. R/W 00h www.national.com 56 00h 2.0 Device Architecture and Configuration (Continued) 2.10.3 FDC Configuration Register This register is reset by hardware to 24h. Location: Index F0h Type: R/W Bit 7 6 5 4 3 Reserved TDR Register Mode DENSEL Polarity Control Reserved Write Protect Reset 0 0 1 0 0 Required 0 Name Bit 2 1 PC-AT or PS/2 Drive Reserved Mode Select 1 0 0 TRI-STATE Control 0 0 Description 7 Reserved. Must be 0. 6 TDR Register Mode. 0: PC-AT compatible drive mode; i.e., bits 7-2 of the TDR are 111111b (default) 1: Enhanced drive mode 5 DENSEL Polarity Control. 0: Active low for 500 Kbps or 1 Mbps data rates 1: Active high for 500 Kbps or 1 Mbps data rates (default) 4 Reserved. Must be 0. 3 Write Protect. This bit allows software to force write protect functionality. When set, writes to the floppy disk drive are disabled. This effect is identical to WP when it is active. 0: Write protected according to WP signal (default) 1: Write protected regardless of value of WP signal 2 PC-AT or PS/2 Drive Mode Select. 0: PS/2 drive mode 1: PC-AT drive mode (default) 1 Reserved. 0 TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE. 0: Disabled (default) 1: Enabled 57 www.national.com 2.0 Device Architecture and Configuration (Continued) 2.10.4 Drive ID Register This read/write register is reset by hardware to 00h. This register controls bits 5 and 4 of the TDR register in Enhanced mode. Location: Index F1h Type: R/W Bit 7 6 Name 5 4 3 Reserved Reset 0 Bit 0 2 1 Drive 1 ID 0 0 0 0 Drive 0 ID 0 0 0 Description 7-4 Reserved. 3-2 Drive 1 ID. When drive 1 is accessed, these bits are reflected on bits 5-4 of the TDR register, respectively. 1-0 Drive 0 ID. When drive 0 is accessed, these bits are reflected on bits 5-4 of the TDR register, respectively. Usage Hints: Some BIOS implementations support automatic media sense FDDs, in which case bit 5 of the TDR register in Enhanced mode is interpreted as valid media sense when it is cleared to 0. If drive 0 and/or drive 1 do not support automatic media sense, bits 1 and/or 3 of the Drive ID register should be set to 1 (to indicate non-valid media sense). When the corresponding drive (0 or 1) is selected, the Drive ID bit is reflected in bit 5 of the TDR register in Enhanced mode. www.national.com 58 2.0 Device Architecture and Configuration (Continued) 2.11 PARALLEL PORT CONFIGURATION 2.11.1 General Description The PC87365 Parallel Port supports all IEEE1284 standard communication modes: Compatibility (known also as Standard or SPP), Bi-directional (known also as PS/2), FIFO, EPP (known also as Mode 4) and ECP (with an optional Extended ECP mode). The Parallel Port includes two groups of runtime registers, as follows: • A group of 21 registers at first level offset, sharing 14 entries. Three of this registers (at offsets 403h, 404h and 405h) are used only in the Extended ECP mode. • A group of four registers, used only in the Extended ECP mode, accessed by a second level offset. The desired mode is selected by the ECR runtime register (offset 402h). The selected mode determines which runtime registers are used and which address bits are used for the base address. See Tables 19 and 20 for a listing of all registers, their offset addresses and the associated modes. Table 19. Parallel Port Registers at First Level Offset Offset Mnemonic Mode(s) Type 00h DATAR 0,1 R/W AFIFO 3 W DTR 4 R/W Data (for EPP) DSR 0,1,2,3 RO Status STR 4 RO Status (for EPP) DCR 0,1,2,3 R/W Control CTR 4 R/W Control (for EPP) 03h ADDR 4 R/W EPP Address 04h DATA0 4 R/W EPP Data Port 0 05h DATA1 4 R/W EPP Data Port 1 06h DATA2 4 R/W EPP Data Port 2 07h DATA3 4 R/W EPP Data Port 3 400h CFIFO DFIFO TFIFO CNFGA 2 3 6 7 W R/W R/W RO PP Data FIFO ECP Data FIFO Test FIFO Configuration A 401h CNFGB 7 RO Configuration B 402h ECR 0,1,2,3 R/W Extended Control 403h EIR1 0,1,2,3 R/W Extended Index 404h EDR1 0,1,2,3 R/W Extended Data 405h EAR1 0,1,2,3 R/W Extended Auxiliary Status 01h 02h Register Name Data ECP FIFO (Address) 1. These registers are extended to the standard IEEE1284 registers. They are accessible only when enabled by bit 4 of the Parallel Port Configuration register (see Section 2.11.3). Table 20. Parallel Port Registers at Second Level Offset Offset Mnemonic Type 00h Control0 R/W Extended Control 0 02h Control2 R/W Extended Control 1 04h Control4 R/W Extended Control 4 05h PP Confg0 R/W Configuration 0 59 Register Name www.national.com 2.0 Device Architecture and Configuration (Continued) 2.11.2 Logical Device 1 (PP) Configuration Table 21 lists the configuration registers that affect the Parallel Port. Only the last register (F0h) is described here. See Sections 2.2.3 and 2.2.4 for descriptions of the others. Table 21. Parallel Port Configuration Registers Index Configuration Register or Action Type Reset 30h Activate. See also bit 0 of the SIOCF1 register. R/W 00h 60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. Bit 2 (for A10) should be 0b. R/W 02h 61h Base Address LSB register. Bits 1 and 0 (A1 and A0) are read only, 00b. For ECP Mode 4 (EPP) or when using the Extended registers, bit 2 (A2) should also be 0b. R/W 78h 70h Interrupt Number and Wake-Up on IRQ Enable register (see note, p. 35). R/W 07h 71h Interrupt Type Bits 7-2 are read only. Bit 1 is a read/write bit. Bit 0 is read only. It reflects the interrupt type dictated by the Parallel Port operation mode. This bit is set to 1 (level interrupt) in Extended Mode and cleared (edge interrupt) in all other modes. R/W 02h 74h DMA Channel Select. R/W 04h 75h Report no second DMA assignment. RO 04h F0h Parallel Port Configuration register. R/W F2h www.national.com 60 2.0 Device Architecture and Configuration (Continued) 2.11.3 Parallel Port Configuration Register This register is reset by hardware to F2h. Location: Index F0h Type: R/W Bit 7 Name 6 Parallel Port Mode Select Reset 1 1 Bit 7-5 5 1 4 3 Extended Register Access 1 2 Reserved 0 0 1 0 Power Mode Control TRI-STATE Control 1 0 Description Parallel Port Mode Select. Bits 7 6 5 0 0 0 0 0 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 Function SPP-Compatible mode PD7-0 are always output signals SPP Extended mode PD7-0 direction is controlled by software EPP 1.7 mode EPP 1.9 mode ECP mode (IEEE1284 register set), with no support for EPP mode Reserved Reserved ECP mode (IEEE1284 register set), with EPP mode selectable as Mode 4 Selection of EPP 1.7 or 1.9 in ECP Mode 4 is controlled by bit 4 of the Control2 configuration register of the parallel port at offset 02h. Note: Before setting bits 7-5, enable the parallel port and set CTR/DCR (at base address + 2) to C4h. 4 3-2 Extended Register Access. 0: Registers at base (address) + 403h, base + 404h and base + 405h are not accessible (reads and writes are ignored). 1: Registers at base (address) + 403h, base + 404h and base + 405h are accessible. This option supports runtime configuration within the Parallel Port address space. Reserved. 1 Power Mode Control. When the logical device is active: 0: Parallel port clock disabled. ECP modes and EPP time-out are not functional when the logical device is active. Registers are maintained. 1: Parallel port clock enabled. All operation modes are functional when the logical device is active (default). 0 TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE. 0: Disabled (default) 1: Enabled 61 www.national.com 2.0 Device Architecture and Configuration (Continued) 2.12 SERIAL PORT 2 CONFIGURATION 2.12.1 General Description Serial Port 2 includes IR functionality as described in the Serial Port 2 with IR chapter. 2.12.2 Logical Device 2 (SP2) Configuration Table 22 lists the configuration registers that affect the Serial Port 2. Only the last register (F0h) is described here. See Sections 2.2.3 and 2.2.4 for descriptions of the others. Table 22. Serial Port 2 Configuration Registers Index Configuration Register or Action Type Reset 30h Activate. See also bit 0 of the SIOCF1 register and bit 2 of the SIOCF6 register. R/W 00h 60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. R/W 02h 61h Base Address LSB register. Bit 2-0 (for A2-0) are read only, 000b. R/W F8h 70h Interrupt Number and Wake-Up on IRQ Enable register (see note, p. 35). R/W 03h 71h Interrupt Type. Bit 1 is R/W; other bits are read only. R/W 03h 74h DMA Channel Select 0 (RX_DMA). R/W 04h 75h DMA Channel Select 1 (TX_DMA). R/W 04h F0h Serial Port 2 Configuration register. R/W 02h 2.12.3 Serial Port 2 Configuration Register This register is reset by hardware to 02h. Location: Index F0h Type: R/W Bit 7 Name Bank Select Enable Reset 0 Bit 7 6-3 6 5 4 3 Reserved 0 0 0 0 2 1 0 Busy Indicator Power Mode Control TRI-STATE Control 0 1 0 Description Bank Select Enable. Enables bank switching for Serial Port 2. 0: All attempts to access the extended registers in Serial Port 2 are ignored (default). 1: Enables bank switching for Serial Port 2. Reserved. 2 Busy Indicator. This read only bit can be used by power management software to decide when to power-down the Serial Port 2 logical device. 0: No transfer in progress (default). 1: Transfer in progress. 1 Power Mode Control. When the logical device is active in: 0: Low power mode Serial Port 2 Clock disabled. The output signals are set to their default states. The RI input signal can be programmed to generate an interrupt. Registers are maintained. (Unlike Active bit in Index 30 that also prevents access to Serial Port 2 registers.) 1: Normal power mode Serial Port 2 clock enabled. Serial Port 2 is functional when the logical device is active (default). 0 TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE. One exception is the IRTX pin, which is driven to 0 when Serial Port 2 is inactive and is not affected by this bit. 0: Disabled (default) 1: Enabled www.national.com 62 2.0 Device Architecture and Configuration (Continued) 2.13 SERIAL PORT 1 CONFIGURATION 2.13.1 Logical Device 3 (SP1) Configuration Table 23 lists the configuration registers that affect the Serial Port 2. Only the last register (F0h) is described here. See Sections 2.2.3 and 2.2.4 for descriptions of the others. Table 23. Serial Port 1 Configuration Registers Index Configuration Register or Action Type Reset 30h Activate. See also bit 0 of the SIOCF1 register and bit 3 of the SIOCF6 register. R/W 00h 60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. R/W 03h 61h Base Address LSB register. Bit 2-0 (for A2-0) are read only, 000b. R/W F8h 70h Interrupt Number and Wake-Up on IRQ Enable register (see note, p. 35). R/W 04h 71h Interrupt Type. Bit 1 is R/W; other bits are read only. R/W 03h 74h Report no DMA Assignment. RO 04h 75h Report no DMA Assignment. RO 04h F0h Serial Port 1 Configuration register. R/W 02h 2.13.2 Serial Port 1 Configuration Register This register is reset by hardware to 02h. Location: Index F0h Type: R/W Bit 7 Name 0 Bit 6-3 5 Bank Select Enable Reset 7 6 4 3 Reserved 0 0 0 0 2 1 0 Busy Indicator Power Mode Control TRI-STATE Control 0 1 0 Description Bank Select Enable. Enables bank switching for Serial Port 1. 0: Disabled (default). 1: Enabled Reserved. 2 Busy Indicator. This read only bit can be used by power management software to decide when to power-down the Serial Port 1 logical device. 0: No transfer in progress (default). 1: Transfer in progress. 1 Power Mode Control. When the logical device is active in: 0: Low power mode Serial Port 1 Clock disabled. The output signals are set to their default states. The RI input signal can be programmed to generate an interrupt. Registers are maintained. (Unlike Active bit in Index 30 that also prevents access to Serial Port 1 registers.) 1: Normal power mode Serial Port 1 clock enabled. Serial Port 1 is functional when the logical device is active (default). 0 TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE. 0: Disabled (default) 1: Enabled 63 www.national.com 2.0 Device Architecture and Configuration (Continued) 2.14 SYSTEM WAKE-UP CONTROL (SWC) CONFIGURATION 2.14.1 Logical Device 4 (SWC) Configuration Table 24 lists the configuration registers that affect the SWC. See Sections 2.2.3 and 2.2.4 for a detailed description of these registers. Table 24. System Wake-Up Control (SWC) Configuration Registers Index Configuration Register or Action Type Reset 30h Activate. When bit 0 is cleared, the registers of this logical device are not accessible.1 R/W 00h 60h Base Address MSB register. R/W 00h 61h Base Address LSB register. Bits 4-0 (for A4-0) are read only, 00000b. R/W 00h 70h Interrupt Number (see note, p. 35). R/W 00h 71h Interrupt Type. Bit 1 is read/write. Other bits are read only. R/W 03h 74h Report no DMA assignment. RO 04h 75h Report no DMA assignment. RO 04h 1. The logical device registers are maintained and all wake-up detection mechanisms are functional. www.national.com 64 2.0 Device Architecture and Configuration (Continued) 2.15 KEYBOARD AND MOUSE CONTROLLER (KBC) CONFIGURATION 2.15.1 General Description The KBC is implemented physically as a single hardware module and houses two separate logical devices: a Mouse controller (Logical Device 5) and a Keyboard controller (Logical Device 6). The hardware KBC module is integrated to provide the following pin functions: P12, P16, P17, KBRST (P20), GA20 (P21), KBDAT, KBCLK, MDAT and MCLK. KBRST and GA20 are implemented as bi-directional, open-drain pins. The Keyboard and Mouse interfaces are implemented as bi-directional, open-drain pins. Their internal connections are shown in Figure 6. P10, P11, P13-P15, P22-P27 of the KBC core are not available on dedicated pins; neither are T0 and T1. P10, P11, P22, P23, P26, P27, T0 and T1 are used to implement the Keyboard and Mouse interface. Internal pull-ups are implemented only on P12, P16 and P17. The KBC executes a program fetched from an on-chip 2Kbyte ROM. The code programmed in this ROM is user-customizable. The KBC has two interrupt request signals: one for the Keyboard and one for the Mouse. The interrupt requests are implemented using ports P24 and P25 of the KBC core. The interrupt requests are controlled exclusively by the KBC firmware, except for the type and number, which are affected by configuration registers (see Section 2.15.2 25). The interrupt requests are implemented as bi-directional signals. When an I/O port is read, all unused bits return the value latched in the output registers of the ports. For KBC firmware that implements interrupt-on-OBF schemes, it is recommended to implement it as follows: 1. Put the data in DBBOUT. 2. Set the appropriate port bit to issue an interrupt request. KBC Internal Interface Bus STATUS DBBIN DBBOUT P12 P12 P16 P16 P17 P17 P20 KBRST P21 GA20 P26 KBCLK T0 P27 KBDAT P10 P23 KBD IRQ T1 P24 Matrix Mouse IRQ MCLK P22 P25 MDAT P11 Figure 6. Keyboard and Mouse Interfaces 65 www.national.com 2.0 Device Architecture and Configuration (Continued) 2.15.2 Logical Devices 5 and 6 (Mouse and Keyboard) Configuration Tables 25 and 26 list the configuration registers that affect the Mouse and the Keyboard, respectively. Only the last register (F0h) is described here. See Sections 2.2.3 and 2.2.4 for descriptions of the others. Table 25. Mouse Configuration Registers Index Mouse Configuration Register or Action Type Reset 30h Activate. See also bit 0 of the SIOCF1. When the Mouse of the KBC is inactive, the IRQ selected by the Mouse Interrupt Number and Wake-Up on IRQ Enable register (index 70h) is not asserted. This register has no effect on host KBC commands handling the PS/2 Mouse. R/W 00h 70h Mouse Interrupt Number and Wake-Up on IRQ Enable register (see note, p. 35). R/W 0Ch 71h Mouse Interrupt Type. Bits 1,0 are read/write; other bits are read only. R/W 02h 74h Report no DMA assignment RO 04h 75h Report no DMA assignment RO 04h Type Reset R/W 01h Table 26. Keyboard Configuration Registers Index Keyboard Configuration Register or Action 30h Activate. See also bit 0 of the SIOCF1. 60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. R/W 00h 61h Base Address LSB register. Bits 2-0 are read only 000b. R/W 60h 62h Command Base Address MSB register. Bits 7-3 (for A15-11) are read only, 00000b. R/W 00h 63h Command Base Address LSB. Bits 2-0 are read only 100b. R/W 64h 70h KBD Interrupt Number and Wake-Up on IRQ Enable register (see note, p. 35). R/W 01h 71h KBD Interrupt Type. Bits 1,0 are read/write; others are read only. R/W 02h 74h Report no DMA assignment. RO 04h 75h Report no DMA assignment. RO 04h F0h KBC Configuration register. R/W 40h www.national.com 66 2.0 Device Architecture and Configuration (Continued) 2.15.3 KBC Configuration Register This register is reset by hardware to 40h. Location: Index F0h Type: R/W Bit 7 Name 6 KBC Clock Source Reset Required 0 1 Bit 7-6 5-4 3 2-1 0 5 4 Reserved 0 3 2 Swap 0 0 1 Reserved 0 0 0 0 TRI-STATE Control 0 Description KBC Clock Source. The clock source can be changed only when the KBC is inactive (disabled). Bits 7 6 Source 0 0 1 1 8 MHz 12 MHz (default) 16 MHz Reserved 0 1 0 1 Reserved. Swap. This bit swaps between the KBD and Mouse interface pins. 0: KBCLK and KBDAT are KBD interface; MCLK and MDAT are Mouse interface (default) 1: KBCLK and KBDAT are Mouse interface, MCLK and MDAT are KBD interface Reserved. TRI-STATE Control. If KBD is inactive (disabled) when this bit is set, the KBD pins (KBCLK and KBDAT) are in TRISTATE. If Mouse is inactive (disabled) when this bit is set, the Mouse pins (MCLK and MDAT) are in TRI-STATE. 0: Disabled (default) 1: Enabled Usage Hints: To change the clock frequency of the KBC: 1. Disable the KBC logical devices. 2. Change the frequency setting. 3. Enable the KBC logical devices. 4. Before swapping between the KBD and Mouse interface pins, disable the KBC logical devices and both pin sets. After swapping, the software should issue a synchronization command to the KBD and mouse through the KBC to regain synchronization with these devices. 67 www.national.com 2.0 Device Architecture and Configuration (Continued) 2.16 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION 2.16.1 General Description The GPIO functional block includes 29 pins, arranged in three 8-bit ports (ports 0, 1 and 2) and one 5-bit port (port 3). All pins in port 0 are I/O and have full event detection capability, enabling them to trigger the assertion of IRQ, SMI and PWUREQ signals. With the exception of bit 5, which is output only, port 1 pins are also I/O with full event detection capability. Pins in ports 2 and 3 are I/O but none of them has event detection capability. The 16 runtime registers associated with the five ports are arranged in the GPIO address space as shown in Table 27. The GPIO base address is 16-byte aligned. Address bits 3-0 are used to indicate the register offset. Table 27. Runtime Registers in GPIO Address Space Offset Mnemonic Register Name 00h GPDO0 GPIO Data Out 0 01h GPDI0 GPIO Data In 0 Port Type 0 R/W RO 02h GPEVEN0 GPIO Event Enable 0 R/W 03h GPEVST0 GPIO Event Status 0 R/W1C 04h 05h GPDO1 GPIO Data Out 1 GPDI1 GPIO Data In 1 06h GPEVEN1 GPIO Event Enable 1 07h GPEVST1 GPIO Event Status 1 08h GPDO2 Data Out 2 09h GPDI2 Data In 2 0Ah GPDO3 Data Out 3 0Bh GPDI3 Data In 3 1 R/W RO R/W R/W1C 2 R/W RO 3 R/W RO 2.16.2 Implementation The standard GPIO port with event detection capability (such as ports 0, 1 and 4) has four runtime registers. Each pin is associated with a GPIO Pin Configuration register that includes seven configuration bits. Ports 2 and 3 are non-standard ports that do not support event detection and therefore differ from the generic model as follows: ● They each have two runtime registers for basic functionality: GPDO2/3 and GPDI2/3. Event detection registers GPEVEN2/3 and GPEVST2/3 are not available. ● Only bits 3-0 are implemented in the GPIO Pin Configuration registers of ports 2 and 3. Bits 6-4, associated with the event detection functionality, are reserved. www.national.com 68 2.0 Device Architecture and Configuration (Continued) 2.16.3 Logical Device 7 (GPIO) Configuration Table 28 lists the configuration registers that affect the GPIO. Only the last three registers (F0h - F2h) are described here. See Sections 2.2.3 and 2.2.4 for a detailed description of the others. Table 28. GPIO Configuration Register Index Configuration Register or Action Type Reset 30h Activate. See also bit 7 of the SIOCF1 register. R/W 00h 60h Base Address MSB register. R/W 00h 61h Base Address LSB register. Bits 3-0 (for A3-0) are read only, 0000b. R/W 00h 70h Interrupt Number (see note, p. 35). R/W 00h 71h Interrupt Type. Bit 1 is read/write. Other bits are read only. R/W 03h 74h Report no DMA assignment. RO 04h 75h Report no DMA assignment. RO 04h F0h GPIO Pin Select register. R/W 00h F1h GPIO Pin Configuration register. R/W 00h F2h GPIO Pin Event Routing register. R/W 00h Figure 7 shows the organization of these registers. GPIO Pin Select Register (Index F0h) Port Select Port 0 Pin Select Pin 0 GPIO Pin Configuration Register (Index F1h) Port 3, Pin 0 Port 2, Pin 0 Port 1, Pin 0 Port 0, Pin 0 Configuration Registers Port 0, Pin 7 Port 3 Pin 7 Pin 0 Port 1, Pin 0 Port 0, Pin 0 Port 0 GPIO Pin Event Routing Register (Index F2h) Event Routing Registers Port 1 Port 0, Pin 7 Pin 7 Figure 7. Organization of GPIO Pin Registers 69 www.national.com 2.0 Device Architecture and Configuration (Continued) 2.16.4 GPIO Pin Select Register This register selects the GPIO pin (port number and bit number) to be configured (i.e., which register is accessed via the GPIO Pin Configuration register). It is reset by hardware to 00h. Location: Index F0h Type: R/W Bit 7 Name Reserved Reset 0 Bit 7 6-4 3 2-0 6 5 4 Port Select 0 0 3 2 Reserved 0 0 1 Pin Select 0 0 Description Reserved. Port Select. These bits select the GPIO port to be configured: 000: Port 0 (default) 001, 010, 011: Binary value of port numbers 1-3, respectively. All other values are reserved. Reserved. Pin Select. These bits select the GPIO pin to be configured in the selected port: 000, 001, ... 111: Binary value of the pin number, 0, 1, ... 7 respectively (default=0) www.national.com 70 0 0 2.0 Device Architecture and Configuration (Continued) 2.16.5 GPIO Pin Configuration Register This register reflects, for both read and write, the register currently selected by the GPIO Pin Select register. All the GPIO Pin registers that are accessed via this register have a common bit structure, as shown below. This register is reset by hardware to 44h, except for ports 2 and 3, which are reset to 04h. Location: Type: Index F1h R/W Ports: 0 and 1 (with event detection capability) Bit 7 6 5 4 3 2 1 0 Name Reserved Event Debounce Enable Event Polarity Event Type Lock Pull-Up Control Output Type Output Enable Reset 0 1 0 0 0 1 0 0 4 3 2 1 0 Lock Pull-Up Control Output Type Output Enable 0 1 0 0 Ports 2 and 3 (without event detection capability) Bit 7 6 Name 5 Reserved Reset 0 Bit 0 0 0 Description 7 Reserved. 6 Event Debounce Enable. (Ports 0 and 1 with event detection capability). Enables transferring the signal only after a predetermined debouncing period of time. 0: Disabled 1: Enabled (default) Reserved. (Ports 2 and 3.) Always 0. 5 Event Polarity. (Ports 0 and 1 with event detection capability). This bit defines the polarity of the signal that issues an interrupt from the corresponding GPIO pin (falling/low or rising/high). 0: Falling edge or low-level input (default) 1: Rising edge or high-level input Reserved. (Ports 2 and 3.) Always 0. 4 Event Type. (Ports 0 and 1 with event detection capability). This bit defines the type of the signal that issues an interrupt from the corresponding GPIO pin (edge or level). 0: Edge input (default) 1: Level input Reserved. (Ports 2 and 3.) Always 0. 3 Lock. This bit locks the corresponding GPIO pin. Once this bit is set to 1 by software, it can only be cleared to 0 by system reset or power-off. Pin multiplexing is functional until the Multiplexing Lock bit is 1 (bit 7 of SuperI/O Configuration 3 register, SIOCF3). 0: No effect (default) 1: Direction, output type, pull-up and output value locked 2 Pull-Up Control. This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin. It supports internal pull-ups for the open-drain output buffer type. 0: Disabled 1: Enabled (default) 1 Output Type. This bit controls the output buffer type (open-drain or push-pull) of the corresponding GPIO pin. 0: Open-drain (default) 1: Push-pull 0 Output Enable. This bit indicates the GPIO pin output state. It has no effect on the input path. 0: TRI-STATE (default) 1: Output enabled 71 www.national.com 2.0 Device Architecture and Configuration (Continued) 2.16.6 GPIO Event Routing Register This register enables the routing of the GPIO event to IRQ, SMI and/or PWUREQ signals. It is implemented only for ports 0,1 and 4, which have event detection capability. This register is reset by hardware to 00h. Location: Index F2h Type: R/W Bit 7 6 Name 4 3 0 0 Bit 0 0 Description Reserved. 2 Enable PWUREQ Routing. 0: Disabled (default) 1: Enabled 1 Enable SMI Routing. 0: Disabled (default) 1: Enabled 0 Enable IRQ Routing. 0: Disabled 1: Enabled (default) www.national.com 2 Enable PWUREQ Routing Reserved Reset 7-3 5 72 0 0 1 0 Enable SMI Enable IRQ Routing Routing 0 1 2.0 Device Architecture and Configuration (Continued) 2.17 ACCESS.BUS INTERFACE (ACB) CONFIGURATION 2.17.1 General Description The ACB is a two-wire synchronous serial interface compatible with the ACCESS.bus physical layer. The ACB uses a 24 MHz internal clock. The six runtime registers are shown below. Table 29. ACB Runtime Registers Offset Mnemonic Register Name Type 00h ACBSDA ACB Serial Data 01h ACBST ACB Status Varies per bit 02h ACBCST ACB Control Status Varies per bit 03h ACBCTL1 ACB Control 1 04h ACBADDR ACB Own Address R/W 05h ACBCTL2 R/W ACB Control 2 R/W R/W 2.17.2 Logical Device 8 (ACB) Configuration Table 30 lists the configuration registers that affect the ACB. Only the last register (F0h) is described here. See Sections 2.2.3 and 2.2.4 for a detailed description of the others. Table 30. ACB Configuration Registers Index Configuration Register or Action Type Reset 30h Activate. See also bit 0 of the SIOCF1 register. R/W 00h 60h Base Address MSB register. R/W 00h 61h Base Address LSB register. Bits 2-0 (for A2-0) are read only, 000b. R/W 00h 70h Interrupt Number and Wake-Up on IRQ Enable register (see note, p. 35). R/W 00h 71h Interrupt Type. Bit 1 is read/write. Other bits are read only. R/W 03h 74h Report no DMA assignment. RO 04h 75h Report no DMA assignment. RO 04h F0h ACB Configuration register. R/W 00h 73 www.national.com 2.0 Device Architecture and Configuration (Continued) 2.17.3 ACB Configuration Register This register is reset by hardware to 00h. Location: Index F0h Type: R/W Bit 7 6 Name 0 Bit 2 1-0 4 3 0 0 0 Description Reserved. Internal Pull-Up Enable. 0: No internal pull-up resistors on SCL and SDA (default) 1: Internal pull-up resistors on SCL and SDA Reserved. www.national.com 2 1 Internal Pull-Up Enable Reserved Reset 7-3 5 74 0 0 0 Reserved 0 0 2.0 Device Architecture and Configuration (Continued) 2.18 FAN SPEED CONTROL AND MONITOR (FSCM) CONFIGURATION 2.18.1 General Description This module includes three Fan Speed Control units and three Fan Speed Monitor units. The 15 runtime registers of the six functional blocks are arranged in the address space shown in Table 31. The base address is 16-byte aligned. Address bits 0-3 are used to indicate the register offset. Table 31. Runtime Registers in FSCM Address Space Offset Mnemonic Register Name 00h FCPSR0 Fan Control 0 Pre-Scale 01h FCDCR0 Fan Control 0 Duty Cycle 02h FCPSR1 Fan Control 1 Pre-Scale 03h FCDCR1 Fan Control 1 Duty Cycle 04h FCPSR2 Fan Control 2 Pre-Scale 05h FCDCR2 Fan Control 2 Duty Cycle 06h FMTHR0 Fan Monitor 0 Threshold 07h FMSPR0 Fan Monitor 0 Speed 08h FMCSR0 Fan Monitor 0 Control & Status 09h FMTHR1 Fan Monitor 1 Threshold 0Ah FMSPR1 Fan Monitor 1 Speed 0Bh FMCSR1 Fan Monitor 1 Control & Status 0Ch FMTHR2 Fan Monitor 2 Threshold 0Dh FMSPR2 Fan Monitor 2 Speed FMCSR2 Fan Monitor 2 Control & Status 0Eh 0Fh Function Fan Speed Control 0 Fan Speed Control 1 Fan Speed Control 2 Fan Speed Monitor 0 Fan Speed Monitor 1 Fan Speed Monitor 2 Reserved 2.18.2 Logical Device 9 (FSCM) Configuration Table 32 lists the configuration registers that affect the Fan Speed Controls and the Fan Speed Monitors. Only the last one (F0h) is described here. See Sections 2.2.3 and 2.2.4 for a detailed description of the others. Table 32. FSCM Configuration Registers Index Configuration Register or Action Type Reset 30h Activate. See also bit 0 of the SIOCF1 register. R/W 00h 60h Base Address MSB register. R/W 00h 61h Base Address LSB register. Bit 3-0 (for A3-0) are read only, 0000b. R/W 00h 70h Interrupt Number and Wake-Up on IRQ Enable register (see note, p. 35). R/W 00h 71h Interrupt Type. Bit 1 is read/write. Other bits are read only. R/W 03h 74h Report no DMA assignment. RO 04h 75h Report no DMA assignment. RO 04h F0h Fan Speed Control and Monitor Configuration 1 register. R/W 00h F1h Fan Speed Control and Monitor Configuration 2 register R/W 00h F2h Fan Speed Control OTS Configuration register R/W 00h 75 www.national.com 2.0 Device Architecture and Configuration (Continued) 2.18.3 Fan Speed Control and Monitor Configuration 1 Register This register is reset by hardware to 00h. Location: Index F0h Type: R/W Bit 7 6 5 4 3 2 Fan Speed Fan Speed Fan Speed Fan Speed Fan Speed Fan Speed Invert 1 Control 1 Monitor 1 Invert 0 Control 0 Monitor 0 Enable Enable Enable Enable Enable Enable Name Reset 0 0 Bit 0 0 0 0 1 0 Reserved TRI-STATE Control 0 0 Description 7 Fan Speed Invert 1 Enable. 0: Disabled (default) 1: Enabled 6 Fan Speed Control 1 Enable. 0: Disabled (default) 1: Enabled 5 Fan Speed Monitor 1 Enable. 0: Disabled (default) 1: Enabled 4 Fan Speed Invert 0 Enable. 0: Disabled (default) 1: Enabled 3 Fan Speed Control 0 Enable. 0: Disabled (default) 1: Enabled 2 Fan Speed Monitor 0 Enable. 0: Disabled (default) 1: Enabled 1 Reserved. 0 TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE. 0: Disabled (default) 1: Enabled www.national.com 76 2.0 Device Architecture and Configuration (Continued) 2.18.4 Fan Speed Control and Monitor Configuration 2 Register This register is reset by hardware to 00h. Location: Index F1h Type: R/W Bit 7 6 Name 5 3 0 0 0 Bit 2 1 0 Fan Speed Fan Speed Fan Speed Invert 2 Control 2 Monitor 2 Enable Enable Enable Reserved Reset 7-3 4 0 0 0 0 0 3 2 1 0 Fan 2 Enable on OTS Fan 1 Enable on OTS Fan 0 Enable on OTS 0 0 0 Description Reserved. 2 Fan Speed Invert 2 Enable. 0: Disabled (default) 1: Enabled 1 Fan Speed Control 2 Enable. 0: Disabled (default) 1: Enabled 0 Fan Speed Monitor 2 Enable. 0: Disabled (default) 1: Enabled 2.18.5 Fan Speed Control OTS Configuration Register (FCOCR) Location: Index F2h Type: R/W Bit 7 6 5 4 Name Reserved Reset 0 Bit 7-3 0 0 0 0 Description Reserved. 2 Fan 2 Enable on OTS. Enables fan 2 at 100% duty cycle when an OTS event becomes active. 0: Fan 2 operates as defined by the PWM mechanism 1: Fan 2 is forced to 100% duty cycle when the OTS output form any of the temperature measurement channels becomes active. 1 Fan 1 Enable on OTS. Enables fan 1 at 100% duty cycle when an OTS event becomes active. 0: Fan 1 operates as defined by the PWM mechanism 1: Fan 1 is forced to 100% duty cycle when the OTS output form any of the temperature measurement channels becomes active. 0 Fan 0 Enable on OTS. Enables fan 0 at 100% duty cycle when an OTS event becomes active. 0: Fan 0 operates as defined by the PWM mechanism 1: Fan 0 is forced to 100% duty cycle when the OTS output form any of the temperature measurement channels becomes active. 77 www.national.com 2.0 Device Architecture and Configuration (Continued) 2.19 WATCHDOG TIMER (WDT) CONFIGURATION 2.19.1 Logical Device 10 (WDT) Configuration Table 33 lists the configuration registers that affect the WATCHDOG Timer. Only the last register (F0h) is described here. See Sections 2.2.3 and 2.2.4 for a detailed description of the others. Table 33. WDT Configuration Registers Index Configuration Register or Action Type Reset 30h Activate. When bit 0 is cleared, the registers of this logical device are not accessible. R/W 00h 60h Base Address MSB register. R/W 00h 61h Base Address LSB register. Bits 1 and 0 (for A1 and A0) are read only, 00b. R/W 00h 70h Interrupt Number (for routing the WDO signal) and Wake-Up on IRQ Enable register (see note, p. 35). R/W 00h 71h Interrupt Type. Bit 1 is read/write. Other bits are read only. R/W 03h 74h Report no DMA assignment. RO 04h 75h Report no DMA assignment. RO 04h F0h WATCHDOG Timer Configuration register. R/W 02h 2.19.2 WATCHDOG Timer Configuration Register This register is reset by hardware to 02h. Location: Index F0h Type: R/W Bit 7 6 Name 4 Reserved Reset 0 Bit 7-4 5 0 0 3 2 1 0 Output Type Internal Pull-Up Enable Power Mode Control TRI-STATE Control 0 0 1 0 0 Description Reserved. 3 Output Type. This bit controls the buffer type (open-drain or push-pull) of the WDO pin. 0: Open-drain (default) 1: Push-pull 2 Internal Pull-Up Enable. This bit controls the internal pull-up resistor on the WDO pin. 0: Disabled (default) 1: Enabled 1 Power Mode Control. 0: Low power mode: WATCHDOG Timer clock disabled. WDO output signal is set to 1. Registers are accessible and maintained (unlike Active bit in Index 30h that also prevents access to WATCHDOG Timer registers). 1: Normal power mode: WATCHDOG Timer clock enabled. WATCHDOG Timer is functional when the logical device is active (default). 0 TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE. 0: Disabled (default) 1: Enabled www.national.com 78 2.0 Device Architecture and Configuration (Continued) 2.20 VOLTAGE LEVEL MONITOR (VLM) CONFIGURATION 2.20.1 Logical Device 13 (VLM) Configuration Table 34 lists the configuration registers that affect the VLM. See Sections 2.2.3 and 2.2.4 for a detailed description of these registers. Table 34. VLM Configuration Registers Index Configuration Register or Action Type Reset 30h Activate. When bit 0 is cleared, the registers of this logical device are not accessible. R/W 00h 60h Base Address MSB register R/W 00h 61h Base Address LSB register. Bits 3-0 (for A3-0) are read only, 0000b. R/W 00h 70h Interrupt Number R/W 00h 71h Interrupt Type. Bit 1 is read/write. Other bits are read only. R/W 03h 74h Report no DMA assignment RO 04h 75h Report no DMA assignment RO 04h 2.21 TEMPERATURE SENSOR (TMS) CONFIGURATION 2.21.1 Logical Device 14 (TMS) Configuration Table 35 lists the configuration registers that affect the TMS. See Sections 2.2.3 and 2.2.4 for a detailed description of these registers.The OTS, ALERT, IRQ and SMI signals are routed through the configuration module. OTS is routed to a pin, IRQ and SMI are routed to a designated interrupt signal and ALERT is not connected. Table 35. TMS Configuration Registers Index Configuration Register or Action Type Reset 30h Activate. When bit 0 is cleared, the registers of this logical device are not accessible. R/W 00h 60h Base Address MSB register R/W 00h 61h Base Address LSB register. Bits 3-0 (for A3-0) are read only, 0000b. R/W 00h 70h Interrupt Number R/W 00h 71h Interrupt Type. Bit 1 is read/write. Other bits are read only. R/W 03h 74h Report no DMA assignment RO 04h 75h Report no DMA assignment RO 04h 79 www.national.com 3.0 3.1 System Wake-Up Control (SWC) OVERVIEW The SWC recognizes the following maskable system events: ● Modem ring (RI1 and RI2 pins). ● Telephone ring (RING input pin). ● Keyboard activity or specific programmable key sequence. ● Mouse activity or specific programmable sequence of clicks and movements. ● Programmable Consumer Electronics IR (CEIR) address. ● Wake-up on module IRQs for FDC, Parallel Port, Serial Ports 1 and 2, Mouse, KBC, ACB, Fan Speed Control and Monitor (FSCM) and WATCHDOG Timer (WDT). ● Eight VSB-powered, general-purpose input events (via GPIOE0-5 and GPIE6-7). ● 15 VDD-powered, GPIO-triggered events (via GPIO00-07, GPIO10-14, GPIO16-17). ● Software event. The SWC notifies the device when any of these events occur by asserting one or more of the following output pins: ● Power-Up Request (PWUREQ). ● System Management Interrupt (SMI). ● Interrupt Request (via SERIRQ). ● Power Button (PWBTOUT). Figure 8 shows the block diagram of the SWC. Wake-Up Configuration and Control Registers Wake-Up Event Sources 16 Filters and Polarity Selection Logic 16 Wake-Up Mode Control (Extension) Logic Wake-Up Extension Enable Registers Power-Supplies (VDD, VSB) Status System ACPI State 16 14 100 msec Pulse Generator Internal Crowbar Indication PWBTIN 16 msec Debouncer Figure 8. SWC Block Diagram www.national.com 80 Wake-Up Event Detection and Routing Logic IRQ SMI PWUREQ ACPI Enable, Status and Routing Control Registers PWBTOUT 3.0 System Wake-Up Control (SWC) (Continued) In addition to the event detection and system notification capabilities, the SWC operates several general-purpose I/O pins powered by VSB. These pins can be used to perform various tasks while VSB is present and VDD is not. 3.2 FUNCTIONAL DESCRIPTION The SWC monitors 16 system events or activities. Upon entering the SWC, the events pass through a filter (where applicable) and polarity adjustment logic. After filtering and polarity adjustment, each event enters the Wake-Up Mode Control (Extension) Logic, which determines its effect during the various system power states. The Wake-Up Mode Control (Extension) Logic also controls the effect of each wake-up event on the power button output (PWBTOUT). See Figure 8 for an illustration of this mechanism. After the wake-up mode is determined for all events, each one of them is fed into a dedicated detector that determines when this event is active, according to predetermined (either fixed or programmable) criteria. A set of dedicated registers is used to determine the wake-up criteria, including the CEIR address and the keyboard sequence. Two Wake-Up Events Status registers (WK_STSn) hold a Status bit for each of the 16 events. Six Wake-Up Events Routing Control registers (WK_ENn WK_SMIENn and WK_IRQENn) hold three Routing Enable bits for each of the 16 events to allow selective routing of these events to PWUREQ, SMI and/or the assigned SWC interrupt request (IRQ) channel. Upon detection of any active event, the corresponding Status bit is set to 1 regardless of any Routing Enable bit. If both the Status bit and a Routing Enable bit corresponding to a specific event are set to 1 (no matter in what order), the output pin corresponding to that Routing Enable bit is asserted. The Status bit is de-asserted by writing 1 to it. Writing 0 to a Routing Enable bit of an event prevents it from issuing the corresponding system notification but does not affect the Status bit. Figure 9 show the routing scheme of detected wake-up events to the various means of system notification. Wake-Up Event i From Wake-Up Extension Logic Event i Detection WK_STSn.i PWUREQ WK_ENn.i SMI Event Routing Logic WK_SMIENn.i IRQ WK_IRQENn.i Figure 9. Wake-Up Events Routing Scheme To enable the assertion of SMI by detected wake-up events, it is necessary to either select the SMI function on a device pin or route it to an interrupt request channel via the device’s configuration registers. 81 www.national.com 3.0 System Wake-Up Control (SWC) (Continued) Six Wake-Up Extension Enable registers (WK_X1EN0,1, WK_X2EN0,1 and WK_X3EN0,1) hold three configuration bits for each of the 16 events to allow selective routing of detected events to the Power Button (PWBTOUT) pulse generator and to control the wake-up mode for each one of them. Figure 10 illustrates the Wake-Up Mode Control (Extension) mechanism. Wake-Up Raw Event i VDD Present To Event i Detection Logic Post VDD Power-On Silence Post VSB Power-On Silence Enable Power Button Pulse To Power Button Pulse Generator WK_X1ENn.i WK_X2ENn.i WK_X3ENn.i Figure 10. Wake-Up Mode Control (Extension) Mechanism To operate the power button pulse generator, the PSLDC0,1 straps must be set to enable the Power Supply Control function (see Section 2.7). In addition, one of the following conditions must be satisfied: ● SLPS5 is active (the system is in Sleep State 5), or ● Legacy Power Button is enabled, or ● Power Button operation in Sleep State 3 is enabled. The two latter conditions are determined by device configuration registers. (Refer to the Device Architecture and Configuration chapter.) In addition to monitoring various system events, the SWC operates several general-purpose I/O (GPIO) pins powered by VSB. Four runtime data registers (SB_GPDOn and SB_GPDIn) hold a Data Out bit and a Data In bit for each VSB-powered GPIO pin. In addition, each GPIO pin has a dedicated configuration register that controls its characteristics. These configuration registers are accessed via a set of Standby GPIO Pin Select and Pin Configuration registers (SBGPSEL and SBGPCFG). For a detailed description of the VSB powered GPIO pins, see Section 3.4.30. The SWC logic is powered by VSB. The SWC control and configuration registers are battery backed, powered by VPP. The setup of the wake-up events, including programmable sequences, is retained throughout power failures (no VSB) as long as the battery is connected. VPP is taken from VSB if VSB is greater than the minimum (Min) value defined in the Device Characteristics chapter; otherwise, VBAT is used as the VPP source. Hardware reset does not affect these registers. They are reset only by software reset or power-up of VPP. 3.3 3.3.1 EVENT DETECTION Modem Ring High-to-low transitions on RI1 or RI2 indicate the detection of a ring in an external modem connected to Serial Port 1 or Serial Port 2, respectively, and can be used as wake-up events. 3.3.2 Telephone Ring A telephone ring is detected by the SWC by processing the raw signal coming directly from the telephone line into the RING input pin. Detection of a pulse-train with a frequency higher than 16 Hz lasting at least 0.19 sec is used as a wake-up event. The RING pulse-train detection is achieved by monitoring the falling edges on RING in time slots of 62.5 msec (a 16 Hz cycle). A positive detection occurs if falling edges of RING are detected in three consecutive time slots, following a time slot in which no RING falling edge is detected. This detection method guarantees the detection of a RING pulse-train with frequencies higher than 16 Hz. It filters out (does not detect) pulses of less than 10 Hz and may detect pulses between 10 Hz to 16 Hz. www.national.com 82 3.0 System Wake-Up Control (SWC) 3.3.3 (Continued) Keyboard and Mouse Activity The detection of either any activity or a specific predetermined keyboard or mouse activity can be used as a wake-up event. The keyboard wake-up detection can be programmed to detect: ● Any keystroke. ● A specific programmable sequence of up to eight alphanumeric keystrokes. ● Any programmable sequence of up to 8 bytes of data received from the keyboard. The mouse wake-up detection can be programmed to detect either a mouse click or movement, a specific programmable click (left or right) or double-clicks. The keyboard or mouse event detection operates independently of the KBC (which is powered down with the rest of the system). 3.3.4 CEIR Address A CEIR transmission received on an IRRX pin in a pre-selected standard (NEC, RCA or RC-5) is matched against a programmable CEIR address. Detection of a match can be used as a wake-up event. Whenever an IR signal is detected, the receiver immediately enters the active state. When this happens, the receiver keeps sampling the IR input signal and generates a bit string where a logic 1 indicates an idle condition and a logic 0 indicates the presence of IR energy. The received bit string is de-serialized and assembled into 8-bit characters. The expected CEIR protocol of the received signal should be configured through bits 5,4 at the CEIR Wake-Up Control register (see Section 3.4.22). The CEIR Wake-Up Address register (IRWAD) holds the unique address to be compared with the address contained in the incoming CEIR message. If CEIR is enabled (bit 0 of the IRWCR register is 1) and an address match occurs, then the CEIR Event Status bit of the WK_STS0 register is set to 1 (see Section 3.4.2). The CEIR Address Shift register holds the received address, which is compared with the address contained in the IRWAD. The comparison is affected also by the CEIR Wake-Up Address Mask register (IRWAM) in which each bit determines whether to ignore the corresponding bit in the IRWAD. If CEIR routing to interrupt request is enabled, the assigned SWC interrupt request may be used to indicate that a complete address has been received. To get this interrupt when the address is completely received, the IRWAM should be written with FFh. Once the interrupt is received, the value of the address can be read from the ADSR register. Another parameter used to determine whether a CEIR signal is to be considered valid is the bit cell time width. There are four time ranges for the different protocols and carrier frequencies. Four pairs of registers define the low and high limits of each time range. (See Sections 3.4.29 through for more details regarding the recommended values for each protocol.) The CEIR address detection operates independently of the serial port with the IR (which is powered down with the rest of the system). 3.3.5 Standby General-Purpose Input Events A general-purpose event is defined as the detection of falling edge or rising edge on a specific signal. Each signal’s event is configurable via software. GPIOE0-5 and GPIE6-7 may trigger a system notification by any of the means mentioned in Section 3.1. A debouncer of 16 ms is enabled (default) on each event. It may be disabled by software. 3.3.6 GPIO-Triggered Events A GPIO-triggered event is defined as the detection of falling edge or rising edge on a specific GPIO signal whose status bit is routed to PWUREQ. Each signal’s event is configurable via software in the GPIO logical device configuration registers. GPIO00-07, GPIO10-14, GPIO16-17 may trigger a system notification only by PWUREQ. Other means of system notification triggered by GPIOs are available via the GPIO logical device configuration registers. A debouncer of 16 ms is enabled (default) on each event. It may be disabled by software. All GPIO pins are powered by VDD and therefore can cause an assertion of PWUREQ only when VDD is present. 3.3.7 Software Event A software event is defined as writing 1 to the Software Event Status bit of the WK_STS0 register. Once this bit is set to 1, it has the same effect as any other Event Status bit. Since WK_STS0 is accessible only when VDD is present, the Software Event can be activated only when VDD is present. 3.3.8 Module IRQ Wake-Up Event A module IRQ wake-up event is defined as the leading edge of the IRQ assertion of any of the following logical devices: FDC, Parallel Port, Serial Ports 1 and 2, Mouse, KBC, ACB and Fan Speed Control and Monitor (FSCM). 83 www.national.com 3.0 System Wake-Up Control (SWC) (Continued) To enable the IRQ of a specific logical device to trigger a wake-up event, the associated Enable bit must be set to 1. This is bit 4 of the Interrupt Number and Wake-Up on IRQ Enable register, located at index 70h in the configuration space of the logical device (see Table 10 in Device Architecture and Configuration chapter). When this bit is set, any IRQ assertion of the corresponding logical device activates the module IRQ wake-up event. Therefore, the module IRQ wake-up event is a combination of all IRQ signals of the logical devices for which wake-up on IRQ is enabled. Note that index 70h has two functions: it is used to set IRQ and to enable wake-up on IRQ. If the BIOS routine that sets IRQ does not use a Read-Modify-Write sequence, it might reset bit 4, which is the Wake-Up on IRQ bit. To ensure that the system wakes up, the BIOS must set bit 4 before the system goes to sleep. When the event is detected as active, its associated Status bit (bit 7 of the WK0_STS register) is set to 1. If the associated Enable bit (bit 7 of the WK_EN0 register) is also set to 1, the PWUREQ output is asserted. It remains asserted until the Status bit is cleared. Since all the logical devices listed above are powered by VDD, a module IRQ event can be activated only when VDD is present. 3.4 SWC REGISTERS The SWC registers are organized in four banks, all of which are battery-backed. The offsets are related to a base address that is determined by the SWC Base Address register in the device configuration registers. The lower 19 offsets are common to the four banks, while the upper offsets (13-1fh) are divided as follows: ● Bank 0 holds the Keyboard/Mouse Control registers. ● Bank 1 holds the CEIR Control registers. ● Bank 2 holds the Event Routing Configuration and Wake-Up Extension Control registers. ● Bank 3 holds the Standby General-Purpose I/O (GPIO) Pins Configuration registers. The active bank is selected through the Configuration Bank Select field (bits 1-0) in the Wake-Up Configuration register (WK_CFG). See Section 3.4.6. As a programming aid, the registers are described in this chapter according to the following functional groupings: ● General status, enable, configuration and routing registers. ● Extension enable registers. ● PS/2 event configuration registers. ● CEIR event configuration registers. ● Standby GPIO configuration and control registers. The following abbreviations are used to indicate the Register Type: ● R/W = Read/Write. ● R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register. ● W = Write. ● RO = Read Only. ● R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. www.national.com 84 3.0 System Wake-Up Control (SWC) 3.4.1 (Continued) SWC Register Map The following tables list the SWC registers. For the SWC register bitmap, see Section 3.5. Table 36. Banks 0, 1, 2 and 3 - The Common Control and Status Register Map Offset Mnemonic Register Name Type Section Wake-Up Events Status 0 R/W1C 3.4.2 00h WK_STS0 01h WK_STS1 Wake-Up Events Status 1 R/W1C 3.4.3 02h WK_EN0 Wake-Up Enable 0 R/W 3.4.4 03h WK_EN1 Wake-Up Enable 1 R/W 3.4.5 04h WK_CFG Wake-Up Configuration R/W 3.4.6 05h-07h Reserved R/W 3.4.33 08h SB_GPDO0 Standby GPIOE/GPIE Data Out 0 09h SB_GPDI0 Standby GPIOE/GPIE Data In 0 RO 3.4.34 0Ah SB_GPDO1 Standby GPOS Data Out 1 R/W 3.4.35 0Bh SB_GPDI1 Standby GPIS Data In 1 RO 3.4.36 0Ch-12h Reserved Table 37. Bank 0 - PS/2 Keyboard/Mouse Wake-Up Configuration and Control Register Map Offset Mnemonic 13h PS2CTL 14h-15h Reserved Register Name Type Section PS/2 Protocol Control R/W 3.4.18 RO 3.4.19 RO 3.4.20 R/W 3.4.21 16h KDSR Keyboard Data Shift 17h MDSR Mouse Data Shift 18h-1Fh PS2KEY0-PS2KEY7 PS/2 Keyboard Key Data Table 38. Bank 1 - CEIR Wake-Up Configuration and Control Register Map Offset Mnemonic Register Name Type Section CEIR Wake-Up Control R/W 3.4.22 13h IRWCR 14h Reserved 15h IRWAD CEIR Wake-Up Address R/W 3.4.23 16h IRWAM CEIR Wake-Up Address Mask R/W 3.4.24 17h ADSR CEIR Address Shift R/O 3.4.25 18h IRWTR0L CEIR Wake-Up, Range 0, Low Limit R/W 3.4.26 19h IRWTR0H CEIR Wake-Up, Range 0, High Limit R/W 3.4.26 1Ah IRWTR1L CEIR Wake-Up, Range 1, Low Limit R/W 3.4.27 1Bh IRWTR1H CEIR Wake-Up, Range 1, High Limit R/W 3.4.27 1Ch IRWTR2L CEIR Wake-Up, Range 2, Low Limit R/W 3.4.28 1Dh IRWTR2H CEIR Wake-Up, Range 2, High Limit R/W 3.4.28 1Eh IRWTR3L CEIR Wake-Up, Range 3, Low Limit R/W 3.4.29 1Fh IRWTR3H CEIR Wake-Up, Range 3, High Limit R/W 3.4.29 85 www.national.com 3.0 System Wake-Up Control (SWC) (Continued) Table 39. Bank 2 - Event Routing Configuration Register Map Offset Mnemonic Register Name Type Section 13h WK_SMIEN0 Wake-Up SMI Enable 0 R/W 3.4.7 14h WK_SMIEN1 Wake-Up SMI Enable 1 R/W 3.4.8 15h WK_IRQEN0 Wake-Up Interrupt Request Enable 0 R/W 3.4.9 16h WK_IRQEN1 Wake-Up Interrupt Request Enable 1 R/W 3.4.10 17h WK_X1EN0 Wake-Up Extension 1 Enable 0 R/W 3.4.11 18h WK_X1EN1 Wake-Up Extension 1 Enable 1 R/W 3.4.12 19h WK_X2EN0 Wake-Up Extension 2 Enable 0 R/W 3.4.13 1Ah WK_X2EN1 Wake-Up Extension 2 Enable 1 R/W 3.4.14 1Bh WK_X3EN0 Wake-Up Extension 3 Enable 0 R/W 3.4.15 1Ch WK_X3EN1 Wake-Up Extension 3 Enable 1 R/W 3.4.16 1Dh-1Fh Reserved Table 40. Bank 3 - Standby GPIO Pin Configuration Register Map Offset Mnemonic Register Name Type Section 13h SBGPSEL Standby GPIO Pin Select R/W 3.4.31 14h SBGPCFG Standby GPIO Pin Configuration R/W 3.4.32 15h-1Fh www.national.com Reserved 86 3.0 System Wake-Up Control (SWC) 3.4.2 (Continued) Wake-Up Events Status Register 0 (WK_STS0) This register is set to 00h on power-up of VPP, VSB or software reset. It indicates which of the corresponding eight wake-up events have occurred. Writing 1 to a bit clears it to 0. Writing 0 has no effect. Bit 6 of this register has a special type, as described in the table below. Location: Offset 00h Type: R/W1C Bit 7 6 5 4 3 2 1 0 Name Module IRQ Event Status Software Event Status GPIO Event Status CEIR Event Status Mouse Event Status KBD Event Status RI2 Event Status RI1 Event Status Reset 0 0 0 0 0 0 0 0 Bit Description 7 Module IRQ Event Status. This sticky bit shows the status of the module IRQ event detection. 0: Event not active (default) 1: Event active 6 Software Event Status. Writing 1 to this bit inverts its value. 0: Event not active (default) 1: Event active 5 GPIO Event Status. This sticky bit shows the status of the VDD GPIO event detection. 0: Event not detected (default) 1: Event detected 4 CEIR Event Status. 0: Event not detected (default) 1: Event detected 3 Mouse Event Status. 0: Event not detected (default) 1: Event detected 2 KBD Event Status. 0: Event not detected (default) 1: Event detected 1 RI2 Event Status. 0: Event not detected (default) 1: Event detected 0 RI1 Event Status. 0: Event not detected (default) 1: Event detected 87 www.national.com 3.0 System Wake-Up Control (SWC) 3.4.3 (Continued) Wake-Up Events Status Register (WK_STS1) This register is set to 00h on power-up of VPP, VSB or software reset. It indicates which of the corresponding eight wake-up events have occurred. Writing 1 to a bit clears it to 0. Writing 0 has no effect. Location: Offset 01h Type: R/W1C Bit 7 6 5 4 3 2 1 0 Name GPIE7 Event Status GPIE6 Event Status GPIE5 Event Status GPIE4/ RING Event Status GPIE3 Event Status GPIE2 Event Status GPIE1 Event Status GPIE0 Event Status Reset 0 0 0 0 0 0 0 0 Bit Description 7 GPIE7 Event Status. 0: Event not detected (default) 1: Event detected 6 GPIE6 Event Status. 0: Event not detected (default) 1: Event detected 5 GPIE5 Event Status. 0: Event not detected (default) 1: Event detected 4 GPIE4/RING Event Status. This sticky bit shows the status of either GPIE4 or RING event detection, according to the function currently selected on pin 27. 0: Event not detected (default) 1: Event detected 3 GPIE3 Event Status. 0: Event not detected (default) 1: Event detected 2 GPIE2 Event Status. 0: Event not detected (default) 1: Event detected 1 GPIE1 Event Status. 0: Event not detected (default) 1: Event detected 0 GPIE0 Event Status. 0: Event not detected (default) 1: Event detected www.national.com 88 3.0 System Wake-Up Control (SWC) 3.4.4 (Continued) Wake-Up Events Enable Register (WK_EN0) This register is set to 00h on power-up of VPP or software reset. Detected wake-up events that are enabled activate the PWUREQ signal. Location: Offset 02h Type: R/W Bit 7 6 5 4 3 2 1 0 Name Module IRQ Event Enable Software Event Enable GPIO Event Enable CEIR Event Enable Mouse Event Enable KBD Event Enable RI2 Event Enable RI1 Event Enable Reset 0 0 0 0 0 0 0 0 Bit Description 7 Module IRQ Event Enable. 0: Disabled (default) 1: Enabled 6 Software Event Enable. 0: Disabled (default) 1: Enabled 5 GPIO Event Enable. 0: Disabled (default) 1: Enabled 4 CEIR Event Enable. 0: Disabled (default) 1: Enabled 3 Mouse Event Enable. 0: Disabled (default) 1: Enabled 2 KBD Event Enable. 0: Disabled (default) 1: Enabled 1 RI2 Event Enable. 0: Disabled (default) 1: Enabled 0 RI1 Event Enable. 0: Disabled (default) 1: Enabled 89 www.national.com 3.0 System Wake-Up Control (SWC) 3.4.5 (Continued) Wake-Up Events Enable Register 1 (WK_EN1) This register is set to 00h on power-up of VPP or software reset. Detected wake-up events that are enabled activate the PWUREQ signal. Location: Offset 03h Type: R/W Bit 7 6 5 4 3 2 1 0 Name GPIE7 Event Enable GPIE6 Event Enable GPIE5 Event Enable GPIE4/ RING Event Enable GPIE3 Event Enable GPIE2 Event Enable GPIE1 Event Enable GPIE0 Event Enable Reset 0 0 0 0 0 0 0 0 Bit Description 7 GPIE7 Event Enable. 0: Disabled (default) 1: Enabled 6 GPIE6 Event Enable. 0: Disabled (default) 1: Enabled 5 GPIE5 Event Enable. 0: Disabled (default) 1: Enabled 4 GPIE4/RING Event Enable. 0: Disabled (default) 1: Enabled 3 GPIE3 Event Enable. 0: Disabled (default) 1: Enabled. 2 GPIE2 Event Enable. 0: Disabled (default) 1: Enabled 1 GPIE1 Event Enable. 0: Disabled (default) 1: Enabled 0 GPIE0 Event Enable. 0: Disabled (default) 1: Enabled www.national.com 90 3.0 System Wake-Up Control (SWC) 3.4.6 (Continued) Wake-Up Configuration Register (WK_CFG) This register is set to 00h on power-up of VPP or software reset. It enables access to CEIR registers, keyboard/mouse registers, Event Routing Control registers or Standby GPIO registers. Location: Offset 04h Type: R/W Bit 7 6 Name 5 0 0 Required 0 0 Bit 3 0 0 0 0 1 0 Configuration Bank Select 0 0 Description Reserved. 3 Enable Power Button Pulse on S3. 0: Disabled (default) 1: Enabled 2 Swap KBC Inputs. 0: No swapping (default) 1: KBD (KBCLK, KBDAT) and Mouse (MCLK, MDAT) inputs swapped 1-0 2 Enable Power Swap KBC Button Inputs Pulse on S3 Reserved Reset 7-4 4 Configuration Bank Select. Bits 1 0 Bank Register 0 0 1 1 0 1 0 1 0 1 2 3 Keyboard/Mouse CEIR Event Routing, Wake-Up Extension Standby GPIO 91 www.national.com 3.0 System Wake-Up Control (SWC) 3.4.7 (Continued) Wake-Up Events Routing to SMI Enable Register 0 (WK_SMIEN0) This register is set to 00h on power-up of VPP or software reset. It controls the routing of detected wake-up events to the SMI signal. Detected wake-up events that are enabled activate the SMI signal regardless of the value of the WK_EN0 register. Location: Bank 2, Offset 13h Type: R/W Bit 7 6 5 Name Reserved Software Event to SMI Enable Reserved Reset 0 0 0 Bit 4 Reserved. 6 Software Event to SMI Enable. 0: Disabled (default) 1: Enabled 5 Reserved. 4 CEIR Event to SMI Enable. 0: Disabled (default) 1: Enabled 3 Mouse Event to SMI Enable. 0: Disabled (default) 1: Enabled 2 KBD Event to SMI Enable. 0: Disabled (default) 1: Enabled 1 RI2 Event to SMI Enable. 0: Disabled (default) 1: Enabled 0 RI1 Event to SMI Enable. 0: Disabled (default) 1: Enabled www.national.com 2 1 0 RI2 RI1 CEIR Mouse KBD Event to Event to Event to Event to Event to SMI Enable SMI Enable SMI Enable SMI Enable SMI Enable 0 Description 7 3 92 0 0 0 0 3.0 System Wake-Up Control (SWC) 3.4.8 (Continued) Wake-Up Events Routing to SMI Enable Register 1 (WK_SMIEN1) This register is set to 00h on power-up of VPP or software reset. It controls the routing of detected wake-up events to the SMI signal. Detected wake-up events that are enabled activate the SMI signal regardless of the value of the WK_EN1 register. Location: Bank 2, Offset 14h Type: R/W Bit 7 Name Reset 6 5 GPIE6 GPIE5 GPIE7 Event to Event to Event to SMI Enable SMI Enable SMI Enable 0 0 Bit 0 4 3 2 1 0 GPIE4/ GPIE3 GPIE2 GPIE1 GPIE0 RING Event to Event to Event to Event to Event to SMI Enable SMI Enable SMI Enable SMI Enable SMI Enable 0 0 0 0 0 Description 7 GPIE7 Event to SMI Enable. 0: Disabled (default) 1: Enabled 6 GPIE6 Event to SMI Enable. 0: Disabled (default) 1: Enabled 5 GPIE5 Event to SMI Enable. 0: Disabled (default) 1: Enabled 4 GPIE4/RING Event to SMI Enable. 0: Disabled (default) 1: Enabled 3 GPIE3 Event to SMI Enable. 0: Disabled (default) 1: Enabled. 2 GPIE2 Event to SMI Enable. 0: Disabled (default) 1: Enabled 1 GPIE1 Event to SMI Enable. 0: Disabled (default) 1: Enabled 0 GPIE0 Event to SMI Enable. 0: Disabled (default) 1: Enabled 93 www.national.com 3.0 System Wake-Up Control (SWC) 3.4.9 (Continued) Wake-Up Events Routing to IRQ Enable Register 0 (WK_IRQEN0) This register is set to 00h on power-up of VPP or software reset. It controls the routing of detected wake-up events to the assigned SWC interrupt request (IRQ) channel. Detected wake-up events that are enabled activate the assigned IRQ channel regardless of the value of the WK_EN0 register. Location: Bank 2, Offset 15h Type: R/W Bit 7 6 5 Name Reserved Software Event to IRQ Enable Reserved Reset 0 0 0 Bit 4 Reserved. 6 Software Event to IRQ Enable. 0: Disabled (default) 1: Enabled 5 Reserved. 4 CEIR Event to IRQ Enable. 0: Disabled (default) 1: Enabled 3 Mouse Event to IRQ Enable. 0: Disabled (default) 1: Enabled 2 KBD Event to IRQ Enable. 0: Disabled (default) 1: Enabled. 1 RI2 Event to IRQ Enable. 0: Disabled (default) 1: Enabled 0 RI1 Event to IRQ Enable. 0: Disabled (default) 1: Enabled www.national.com 2 1 0 RI2 RI1 CEIR Mouse KBD Event to Event to Event to Event to Event to IRQ Enable IRQ Enable IRQ Enable IRQ Enable IRQ Enable 0 Description 7 3 94 0 0 0 0 3.0 System Wake-Up Control (SWC) (Continued) 3.4.10 Wake-Up Events Routing to IRQ Enable Register 1 (WK_IRQEN1) This register is set to 00h on power-up of VPP or software reset. It controls the routing of detected wake-up events to the assigned SWC IRQ channel. Detected wake-up events that are enabled activate the IRQ signal regardless of the value of the WK_EN1 register. Location: Bank 2, Offset 16h Type: R/W Bit 7 Name Reset 6 5 GPIE7 GPIE6 GPIE5 Event to Event to Event to IRQ Enable IRQ Enable IRQ Enable 0 0 Bit 0 4 3 2 1 0 GPIE4/ GPIE3 GPIE2 GPIE1 GPIE0 RING Event to Event to Event to Event to Event to IRQ Enable IRQ Enable IRQ Enable IRQ Enable IRQ Enable 0 0 0 0 0 Description 7 GPIE7 Event to IRQ Enable. 0: Disabled (default) 1: Enabled 6 GPIE6 Event to IRQ Enable. 0: Disabled (default) 1: Enabled 5 GPIOE5 Event to IRQ Enable. 0: Disabled (default) 1: Enabled 4 GPIE4/RING Event to IRQ Enable. 0: Disabled (default) 1: Enabled 3 GPIE3 Event to IRQ Enable. 0: Disabled (default) 1: Enabled. 2 GPIE2 Event to IRQ Enable. 0: Disabled (default) 1: Enabled 1 GPIE1 Event to IRQ Enable. 0: Disabled (default) 1: Enabled 0 GPIE0 Event to IRQ Enable. 0: Disabled (default) 1: Enabled 95 www.national.com 3.0 System Wake-Up Control (SWC) (Continued) 3.4.11 Wake-Up Extension 1 Enable Register 0 (WK_X1EN0) This register is set to 1Fh on power-up of VPP or software reset. It controls the routing of raw wake-up events to event detectors while VDD is present. Wake-up events that are enabled are routed to their event detectors while VDD is present. Location: Bank 2, Offset 17h Type: R/W Bit 7 Name 6 0 0 Bit 4 0 1 Description Reserved. 4 CEIR Event Extension 1 Enable. 0: Disabled 1: Enabled (default) 3 Mouse Event Extension 1 Enable. 0: Disabled 1: Enabled (default) 2 KBD Event Extension 1 Enable. 0: Disabled 1: Enabled (default) 1 RI2 Event Extension 1 Enable. 0: Disabled 1: Enabled (default) 0 RI1 Event Extension 1 Enable. 0: Disabled 1: Enabled (default) www.national.com 3 2 1 0 RI2 RI1 CEIR Mouse KBD Event Ex. 1 Event Ex. 1 Event Ex. 1 Event Ex. 1 Event Ex.1 Enable Enable Enable Enable Enable Reserved Reset 7-5 5 96 1 1 1 1 3.0 System Wake-Up Control (SWC) (Continued) 3.4.12 Wake-Up Extension 1 Enable Register 1 (WK_X1EN1) This register is set to FFh on power-up of VPP or software reset. It controls the routing of raw wake-up events to event detectors while VDD is present. Wake-up events that are enabled are routed to their event detectors while VDD is present. Location: Bank 2, Offset 18h Type: R/W Bit 7 Name Reset 6 5 4 3 2 1 0 GPIE4/ GPIE3 GPIE2 GPIE1 GPIE0 GPIE7 GPIE6 GPIE5 RING Event Ex. 1 Event Ex. 1 Event Ex. 1 Event Ex. 1 Event Ex. 1 Event Ex. 1 Event Ex. 1 Event Ex. 1 Enable Enable Enable Enable Enable Enable Enable Enable 1 1 1 Bit 1 1 1 1 1 Description 7 GPIE7 Event Extension 1 Enable. 0: Disabled 1: Enabled (default) 6 GPIE6 Event Extension 1 Enable. 0: Disabled 1: Enabled (default) 5 GPIE5 Event Extension 1 Enable. 0: Disabled 1: Enabled (default) 4 GPIE4/RING Event Extension 1 Enable. 0: Disabled 1: Enabled (default) 3 GPIE3 Event Extension 1 Enable. 0: Disabled 1: Enabled (default) 2 GPIE2 Event Extension 1 Enable. 0: Disabled 1: Enabled (default) 1 GPIE1 Event Extension 1 Enable. 0: Disabled 1: Enabled (default) 0 GPIE0 Event Extension 1 Enable. 0: Disabled 1: Enabled (default) 97 www.national.com 3.0 System Wake-Up Control (SWC) (Continued) 3.4.13 Wake-Up Extension 2 Enable Register 0 (WK_X2EN0) This register is set to 1Fh on power-up of VPP or software reset. It controls the routing of raw wake-up events to event detectors while VDD is not present. Wake-up events that are enabled are routed to their event detectors while VDD is not present. Location: Bank 2, Offset 19h Type: R/W Bit 7 Name 6 0 0 Bit 4 0 1 Description Reserved. 4 CEIR Event Extension 2 Enable. 0: Disabled 1: Enabled (default) 3 Mouse Event Extension 2 Enable. 0: Disabled 1: Enabled (default) 2 KBD Event Extension 2 Enable. 0: Disabled 1: Enabled (default) 1 RI2 Event Extension 2 Enable. 0: Disabled 1: Enabled (default) 0 RI1 Event Extension 2 Enable. 0: Disabled 1: Enabled (default) www.national.com 3 2 1 0 RI2 RI1 CEIR Mouse KBD Event Ex. 2 Event Ex. 2 Event Ex. 2 Event Ex. 2 Event Ex. 2 Enable Enable Enable Enable Enable Reserved Reset 7-5 5 98 1 1 1 1 3.0 System Wake-Up Control (SWC) (Continued) 3.4.14 Wake-Up Extension 2 Enable Register 1 (WK_X2EN1) This register is set to FFh on power-up of VPP or software reset. It controls the routing of raw wake-up events to event detectors while VDD is not present. Wake-up events that are enabled are routed to their event detectors while VDD is not present. Location: Bank 2, Offset 1Ah Type: R/W Bit 7 Name Reset 6 5 4 3 2 1 0 GPIE4/ GPIE3 GPIE2 GPIE1 GPIE0 GPIE7 GPIE6 GPIE5 RING Event Ex. 2 Event Ex. 2 Event Ex. 2 Event Ex. 2 Event Ex. 2 Event Ex. 2 Event Ex. 2 Event Ex. 2 Enable Enable Enable Enable Enable Enable Enable Enable 1 1 1 Bit 1 1 1 1 1 Description 7 GPIE7 Event Extension 2 Enable. 0: Disabled 1: Enabled (default) 6 GPIE6 Event Extension 2 Enable. 0: Disabled 1: Enabled (default) 5 GPIE5 Event Extension 2 Enable. 0: Disabled 1: Enabled (default) 4 GPIE4/RING Event Extension 2 Enable. 0: Disabled 1: Enabled (default) 3 GPIE3 Event Extension 2 Enable. 0: Disabled 1: Enabled (default) 2 GPIE2 Event Extension 2 Enable. 0: Disabled 1: Enabled (default) 1 GPIE1 Event Extension 2 Enable. 0: Disabled 1: Enabled (default) 0 GPIE0 Event Extension 2 Enable. 0: Disabled 1: Enabled (default) 99 www.national.com 3.0 System Wake-Up Control (SWC) (Continued) 3.4.15 Wake-Up Extension 3 Enable Register 0 (WK_X3EN0) This register is set to 00h on power-up of VPP or software reset. It controls the routing of raw wake-up events to the Power Button pulse generator. Wake-up events that are enabled are routed to the Power Button pulse generator. Location: Bank 2, Offset 1Bh Type: R/W Bit 7 Name 6 0 0 Bit 4 0 0 Description Reserved. 4 CEIR Event Extension 3 Enable. 0: Disabled (default) 1: Enabled 3 Mouse Event Extension 3 Enable. 0: Disabled (default) 1: Enabled 2 KBD Event Extension 3 Enable. 0: Disabled (default) 1: Enabled 1 RI2 Event Extension 3 Enable. 0: Disabled (default) 1: Enabled 0 RI1 Event Extension 3 Enable. 0: Disabled (default) 1: Enabled www.national.com 3 2 1 0 RI2 RI1 CEIR Mouse KBD Event Ex. 3 Event Ex. 3 Event Ex. 3 Event Ex. 3 Event Ex. 3 Enable Enable Enable Enable Enable Reserved Reset 7-5 5 100 0 0 0 0 3.0 System Wake-Up Control (SWC) (Continued) 3.4.16 Wake-Up Extension 3 Enable Register 1 (WK_X3EN1) This register is set to 00h on power-up of VPP or software reset. It controls the routing of raw wake-up events to the Power Button pulse generator. Wake-up events that are enabled are routed to the Power Button pulse generator. Location: Bank 2, Offset 1Ch Type: R/W Bit 7 Name Reset 6 5 4 3 2 1 0 GPIE3/ GPIE3 GPIE2 GPIE1 GPIE0 GPIE7 GPIE6 GPIE5 RING Event Ex. 3 Event Ex. 3 Event Ex. 3 Event Ex. 3 Event Ex. 3 Event Ex. 3 Event Ex. 3 Event Ex. 3 Enable Enable Enable Enable Enable Enable Enable Enable 0 0 0 Bit 0 0 0 0 0 Description 7 GPIE7 Event Extension 3 Enable. 0: Disabled (default) 1: Enabled 6 GPIE6 Event Extension 3 Enable. 0: Disabled (default) 1: Enabled 5 GPIE5 Event Extension 3 Enable. 0: Disabled (default) 1: Enabled 4 GPIE4/RING Event Extension 3 Enable. 0: Disabled (default) 1: Enabled 3 GPIE3 Event Extension 3 Enable. 0: Disabled (default) 1: Enabled 2 GPIE2 Event Extension 3 Enable. 0: Disabled (default) 1: Enabled 1 GPIE1 Event Extension 3 Enable. 0: Disabled (default) 1: Enabled 0 GPIE0 Event Extension 3 Enable. 0: Disabled (default) 1: Enabled 101 www.national.com 3.0 System Wake-Up Control (SWC) (Continued) 3.4.17 PS/2 Keyboard and Mouse Wake-Up Events The SWC can be configured to detect any predetermined PS/2 keyboard or mouse activity. The detection mechanisms for keyboard and mouse events are independent. Therefore, they can be operated simultaneously with no interference. Since both mechanisms are implemented by hardware, which is independent of the device’s keyboard controller, the keyboard controller itself need not be activated to detect either keyboard or mouse events. Keyboard Wake-Up Events The keyboard wake-up detection mechanism can be programmed to detect: ● Any keystroke. ● A specific programmable sequence of up to eight alphanumeric keystrokes (Password mode). ● Any programmable sequence of up to 8 bytes of data received from the keyboard (Special Key Sequence mode). To program the keyboard wake-up detection mechanism to wake-up on any keystroke, perform the following sequence: 1. Put the wake-up mechanism in Special Key Sequence mode by setting bits 3-0 of the PS2CTL register to 0001b. 2. Set the PS2KEY0 and PS2KEY1 registers to 00h. This forces the wake-up detection mechanism to ignore the values of incoming data, thus causing it to wake-up on any keystroke. In Password mode, the Make and Break bytes transmitted by the keyboard are discarded, and only the scan codes are compared against those programmed in the PS2KEYn registers. To simplify the detection mechanism, only keys with a scan code of 1 byte can be included in the sequence to be detected. To program the keyboard wake-up detection mechanism to operate in Password mode, proceed as follows: 1. Set bits 3-0 of the PS2CTL register with a value that indicates the desired number of keystrokes in the sequence. The programmed value should be the number of keystrokes + 7. For example, to wake-up on a sequence of two keys, set bits 3-0 to 9h. 2. Program the appropriate subset of the PS2KEY0-PS2KEY7 registers, in sequential order, with the scan codes of the keys in the sequence. For example, if there are three keys in the sequence and the scan codes of these keys are 05h (first), 50h (second) and 44h (third), program PS2KEY0 to 05h, PS2KEY1 to 50h and PS2KEY2 to 44h (the scan codes are only examples). In Special Key Sequence mode, all the bytes transmitted by the keyboard are compared against the ones programmed in the PS2KEYn registers. These include the Make and Break bytes. This mode enables the detection of any sequence of keystrokes, including keys such as Shift and Alt. To program the keyboard wake-up detection mechanism to operate in Special Key Sequence mode, proceed as follows: 1. Set bits 3-0 of the PS2CTL register to a value that indicates the desired number of keystrokes in the sequence. The programmed value should be the number of keystrokes + 1. For example, to wake-up on a sequence of three received bytes, set bits 3-0 of PS2CTL to 2h. 2. Program the appropriate subset of the PS2KEY0-PS2KEY7 registers in sequential order with the values of the data bytes that comprise the sequence. For example, if the number of bytes in the sequence is four and the values of these bytes are E0h (first), 5Bh (second), E0h (third) and DBh (fourth), program PS2KEY0 to E0h, PS2KEY1 to 5Bh, PS2KEY2 to E0h and PS2KEY3 to DBh (the byte values are only examples). Mouse Wake-Up Events The mouse wake-up detection mechanism can be programmed to detect either a mouse click or movement, a specific programmable click (left or right) or double-click. To program this mechanism to wake-up on a specific event, set bits 6-4 of the PS2CTL register to the required value, according to the description of these bits in Section 3.4.18. www.national.com 102 3.0 System Wake-Up Control (SWC) (Continued) 3.4.18 PS/2 Protocol Control Register (PS2CTL) This register is set to 00h on power-up of VPP or software reset. It configures the PS/2 keyboard and mouse wake-up features. Before changing bits 6-4 or 3-0, clear them to 0 and then write the new value. Location: Bank 0, Offset 13h Type: R/W Bit 7 6 Name Disable Parity Check Reset 0 5 6-4 3-0 3 Mouse Wake-Up Configuration 0 0 Bit 7 4 0 2 1 0 Keyboard Wake-Up Configuration 0 0 0 0 Description Disable Parity Check. 0: Enabled (default) 1: Disabled Mouse Wake-Up Configuration. Bits 6 5 4 Configuration 0 0 0 0 1 1 1 1 Disable mouse wake-up detection Wake-up on any mouse movement or button click Wake-up on left button click Wake-up on left button double-click Wake-up on right button click Wake-up on right button double-click Wake-up on any button single-click (left, right or middle) Wake-up on any button double-click (left, right or middle) 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Keyboard Wake-Up Configuration. Bits 3 2 1 0 Configuration 0 0 0 0 Disable keyboard wake-up detection 0 0 0 1 to 0 1 1 1 1 0 0 0 to 1 1 1 1 } } Special key sequence 2-8 PS/2 scan codes, “Make” and “Break” (including Shift and Alt keys) Password enabled with 1-8 keys “Make” code (excluding Shift and Alt keys) 3.4.19 Keyboard Data Shift Register (KDSR) This register is set to 00h on power-up of VPP or software reset. It stores the keyboard data shifted in from the keyboard during transmission only when keyboard wake-up detection is enabled. Location: Bank 0, Offset 16h Type: RO Bit 7 6 5 Name Reset 4 3 2 1 0 0 0 0 Keyboard Data 0 0 0 0 103 0 www.national.com 3.0 System Wake-Up Control (SWC) (Continued) 3.4.20 Mouse Data Shift Register (MDSR) This register is set to 00h on power-up of VSB or software reset. It stores the mouse data shifted in from the mouse during transmission only when mouse wake-up detection is enabled. Location: Bank 0, Offset 17h Type: RO Bit 7 6 Name 5 4 3 2 Reserved Reset 0 0 0 1 0 Mouse Data 0 0 0 0 0 3.4.21 PS/2 Keyboard Key Data Registers (PS2KEY0 - PS2KEY7) Eight registers (PS2KEY0-PS2KEY7) store the scan codes for the password or key sequence of the keyboard wake-up feature, as follows: ● PS2KEY0 register stores the scan code for the first key in the password/key sequence. ● PS2KEY1 register stores the scan code for the second key in the password/key sequence. ● PS2KEY2 - PS2KEY7 registers store the scan codes for the third to eighth keys in the password/key sequence. When one of these registers is set to 00h, it indicates that the value of the corresponding scan code byte is ignored (not compared). These registers are set to 00h on power-up of VPP or software reset. Location: Bank 0, Offset 18h-1Fh Type: R/W Bit 7 6 5 Name Reset www.national.com 4 3 2 1 0 0 0 0 Scan Code of Keys 0-7 0 0 0 0 104 0 3.0 System Wake-Up Control (SWC) (Continued) 3.4.22 CEIR Wake-Up Control Register (IRWCR) This register is set to 00h on power-up of VPP or software reset. Location: Bank 1, Offset 13h Type: R/W Bit 7 Name 6 Reserved Reset 0 5 4 CEIR Protocol Select 0 0 Bit 3 2 Select Invert IRRX2 Input IRRXn Input 0 0 0 1 0 Reserved CEIR Enable 0 0 Description 7-6 Reserved. 5-4 CEIR Protocol Select. Bits 5 4 0 0 0 1 1 X Protocol RC5 (default) NEC/RCA Reserved 3 Select IRRX2 Input. Selects the IRRX input. 0: IRRX1 (default) 1: IRRX2 2 Invert IRRXn Input. 0: Not inverted (default) 1: Inverted 1 Reserved. 0 CEIR Enable. 0: CEIR is disabled (default). Registers are maintained but CEIR Event Status bit (of WK0_STS) does not reflect CEIR events. (Unlike the CEIR Event Enable bit of WK0_EN that does not affect the CEIR Event Status bit.) 1: CEIR is enabled . 105 www.national.com 3.0 System Wake-Up Control (SWC) (Continued) 3.4.23 CEIR Wake-Up Address Register (IRWAD) This register holds the unique address to be compared with the address contained in the incoming CEIR message. If CEIR is enabled (bit 0 of the IRWCR register is 1) and an address match occurs, then bit 5 of the WK0_STS register is set to 1 (see Section 3.4.2). This register is set to 00h on power-up of VPP or software reset. Location: Bank 1, Offset 15h Type: R/W Bit 7 6 5 Name 4 3 2 1 0 0 0 0 CEIR Wake-Up Address Reset 0 0 0 0 0 3.4.24 CEIR Wake-Up Address Mask Register (IRWAM) Each bit in this register determines whether the corresponding bit in the IRWAD register is enabled in the address comparison. Bits 5, 6 and 7 must be set to 1 if the RC-5 protocol is selected. This register is set to E0h on power-up of VPP or software reset. Location: Bank 1, Offset 16h Type: R/W Bit 7 6 5 Name 3 2 1 0 0 0 0 CEIR Wake-Up Address Mask Reset 1 Bit 7-0 4 1 1 0 0 Description CEIR Wake-Up Address Mask. If the corresponding bit is 0, the address bit is not masked (enabled for compare). If the corresponding bit is 1, the address bit is masked (ignored during compare). www.national.com 106 3.0 System Wake-Up Control (SWC) (Continued) 3.4.25 CEIR Address Shift Register (ADSR) This register holds the received address to be compared with the address contained in the IRWAD register. This register is set to 00h on power-up of VPP or software reset. Location: Bank 1, Offset 17h Type: RO Bit 7 6 5 Name 4 3 2 1 0 0 0 0 CEIR Address Reset 0 0 0 0 0 3.4.26 CEIR Wake-Up Range 0 Registers These registers define the low and high limits of time range 0. The values are represented in units of 0.1 msec. For the RC-5 protocol, the bit cell width must fall within this range for the cell to be considered valid. The nominal cell width is 1.778 msec for a 36 KHz carrier. IRWTR0L and IRWTR0H should be set to 10h and 14h respectively (default). For the NEC protocol, the time distance between two consecutive CEIR pulses that encodes a bit value of 0 must fall within this range. The nominal distance for a 0 is 1.125 msec for a 38 KHz carrier. IRWTR0L and IRWTR0H should be set to 09h and 0Dh respectively. IRWTR0L Register This register is set to 10h on power-up of VPP or software reset. Location: Bank 1, Offset 18h Type: R/W Bit 7 Name 6 5 4 Reserved Reset 0 0 3 2 1 0 CEIR Pulse Change, Range 0, Low Limit 0 1 0 0 0 0 3 2 1 0 IRWTR0H Register This register is set to 14h on power-up of VPP or software reset. Location: Bank 1, Offset 19h Type: R/W Bit 7 Name Reset 6 5 4 Reserved 0 0 CEIR Pulse Change, Range 0, High Limit 0 1 107 0 1 0 0 www.national.com 3.0 System Wake-Up Control (SWC) (Continued) 3.4.27 CEIR Wake-Up Range 1 Registers These registers define the low and high limits of time range 1. The values are represented in units of 0.1 msec. For the RC-5 protocol, the pulse width defining a half-bit cell must fall within this range in order for the cell to be considered valid. The nominal pulse width is 0.889 for a 38 KHz carrier. IRWTR1L and IRWTR1H should be set to 07h and 0Bh, respectively (default). For the NEC protocol, the time between two consecutive CEIR pulses that encodes a bit value of 1 must fall within this range. The nominal time for a 1 is 2.25 msec for a 36 KHz carrier. IRWTR1L and IRWTR1H should be set to 14h and 19h respectively. IRWTR1L Register This register is set to 07h on power-up of VPP or software reset. Location: Bank 1, Offset 1Ah Type: R/W Bit 7 Name 6 5 4 Reserved Reset 0 0 3 2 1 0 CEIR Pulse Change, Range 1, Low Limit 0 0 0 1 1 1 3 2 1 0 IRWTR1H Register This register is set to 0Bh on power-up of VPP or software reset. Location: Bank 1, Offset 1Bh Type: R/W Bit 7 Name 6 5 4 Reserved Reset 0 0 CEIR Pulse Change, Range 1, High Limit 0 0 1 0 1 1 3.4.28 CEIR Wake-Up Range 2 Registers These registers define the low and high limits of time range 2. The values are represented in units of 0.1 msec. These registers are not used when the RC-5 protocol is selected. For the NEC protocol, the header pulse width must fall within this range in order for the header to be considered valid. The nominal value is 9 msec for a 38 KHz carrier. IRWTR2L and IRWTR2H should be set to 50h and 64h respectively (default). IRWTR2L Register This register is set to 50h on power-up of Vpp or software reset. Location: Bank 1, Offset 1Ch Type: R/W Bit 7 6 Name 5 4 3 2 1 0 CEIR Pulse Change, Range 2, Low Limit Reset 0 1 0 1 0 0 0 0 3 2 1 0 0 0 IRWTR2H Register This register is set to 64h on power-up of Vpp or software reset. Location: Bank 1, Offset 1Dh Type: R/W Bit 7 6 Name Reset www.national.com 5 4 CEIR Pulse Change, Range 2, High Limit 0 1 1 0 108 0 1 3.0 System Wake-Up Control (SWC) (Continued) 3.4.29 CEIR Wake-Up Range 3 Registers These registers define the low and high limits of time range 3. The values are represented in units of 0.1 msec. These registers are not used when the RC-5 protocol is selected. For the NEC protocol, the post header gap width must fall within this range in order for the gap to be considered valid. The nominal value is 4.5 msec for a 36 KHz carrier. IRWTR3L and IRWTR3H should be set to 28h and 32h respectively (default). IRWTR3L Register This register is set to 28h on power-up of Vpp or software reset. Location: Bank1, Offset 1Eh Type: R/WS Bit 7 6 5 Name 4 3 2 1 0 CEIR Pulse Change, Range 3, Low Limit Reset 0 0 1 0 1 0 0 0 3 2 1 0 1 0 IRWTR3H Register This register is set to 32h on power-up of Vpp or software reset. Location: Bank 1, Offset 1Fh Type: R/W Bit 7 6 5 Name Reset 4 CEIR Pulse Change, Range 3, High Limit 0 0 1 1 0 0 CEIR Recommended Values Table 41 lists the recommended time ranges limits for the different protocols and their four applicable ranges. The values are represented in hexadecimal code where the units are of 0.1 msec. Table 41. Time Range Limits for CEIR Protocols RC-5 NEC RCA Range Low Limit High Limit Low Limit High Limit Low Limit High Limit 0 10h 14h 09h 0Dh 0Ch 12h 1 07h 0Bh 14h 19h 16h 1Ch 2 − − 50h 64h B4h DCh 3 − − 28h 32h 23h 2Dh 109 www.national.com 3.0 System Wake-Up Control (SWC) (Continued) 3.4.30 Standby General-Purpose I/O (SBGPIO) Register Overview The SWC can be used to operate up to 12 VSB-powered general-purpose input/output (GPIO), input (GPI) or output (GPO) pins, eight of which support event detection. These are as follows: ● GPIOE0-5 are GPIO pins. ● GPIE6,7 and GPIS2,3 are GPI pins. ● GPOS0,1 are GPO pins. For programming convenience, these pins are associated with two SBGPIO ports. Specifically, GPIE0-5 and GPIE6,7 are associated with bits 0 to 7 of SBGPIO port 0, respectively, and GPOS0,1 and GPIS2,3 are associated with bits 0 to 3 of SBGPIO port 1, respectively. Table 42 provides a summary of the SBGPIO pin-to-port assignment and pin types. Table 42. SBGPIO Pin Types and Associated Port Pin(s) Port Type Event Detection GPIOE0-5 0 I/O Yes GPIE6,7 0 I Yes GPOS0,1 1 O No GPIS2,3 1 I No An SBGPIO port is structured as an 8-bit port, based on eight pins. It features: • • • • Software capability to manipulate and read pin levels. Controllable system notification by several means based on the pin level’s transition. Ability to capture and manipulate events and their associated status. Back-drive protected pins. SBGPIO port operation is associated with two sets of registers: • Pin configuration registers, mapped in the SWC register bank 3. These registers are used to statically set up the logical behavior of each pin. There is one 8-bit register for each SBGPIO pin. • Two 8-bit runtime registers: SBGPIO Data Out (SBGPDO) and SBGPIO Data In (SBGPDI). These registers are mapped in the SWC device I/O space (determined by the base address registers in the SWC Device Configuration). They are used to manipulate and/or read the pin values. Each runtime register corresponds to the 8-pin port described above (see Table 42). Each SBGPIO pin is associated with up to six configuration bits and the corresponding bit slice of the two runtime registers, as shown in Figure 11. The SBGPIO port has basic as well as enhanced functionality. Basic functionality includes the manipulation and reading of the SBGPIO pins, as described in Section 6.2 on page 129. Enhanced functionality includes event detection, as described in Event Detection on page 112. www.national.com 110 3.0 System Wake-Up Control (SWC) (Continued) Bit n SBGPDOX SBGPIOX Base Address SBGPDIX Runtime Registers 8 SBGPIO Pin Configuration Registers X = port number n = pin number, 0 to 7 SBGPIO Pin Configuration Register SBGPIO Port X Pin n SBGPIOXn CNFG SBGPIOXn Pin Logic x8 SBGPIO Pin Select Register Port and Pin Select Event Pending Indicator x8 x8 To Wake-Up Logic Figure 11. SBGPIO Port Architecture Basic Functionality The basic functionality of each SBGPIO pin is based on four configuration bits and a bit slice of runtime registers SBGPDO and SBGPDI. The configuration and operation of a single pin (pin n in port X) is shown in Figure 12. Read Only Data In Static Pull-Up Push-Pull=1 Pin Read/Write Data Out Internal Bus Pull-Up Enable Lock Pull-Up Control Output Type Output Enable Bit 3 Bit 2 Bit 1 Bit 0 SBGPIO Pin Configuration Register Figure 12. SBGPIO Basic Functionality 111 www.national.com 3.0 System Wake-Up Control (SWC) (Continued) Configuration Options The SBGPIO Pin Configuration register controls the following basic configuration options: • • Pin Direction - Controlled by Output Enable (bit 0). • Weak Static Pull-up - May be added to any type of port (input, open-drain or totem pole). It is controlled by Pull-Up Control (bit 2). • Pin Lock - A GPIO pin may be locked to prevent any changes in the output value and/or the output characteristics. The lock is controlled by Lock (bit 3). It disables writes to the SBGPDO register bits and to bits 0-3 of the Standby GPIO Pin Configuration register (Including the Lock bit itself). Once locked, it can be released by hardware reset only. Output Type - Push-pull vs. open-drain. It is controlled by Output Type (bit 1) by enabling/disabling the pull-up portion of the output buffer. Operation The value that is written to the SBGPDO register is driven to the pin, if the output is enabled. Reading from the SBGPDO register returns its contents, regardless of the pin value or the port configuration. The SBGPDI register is a read-only register. Reading from the SBGPDI register returns the pin value, regardless of what is driving it (the port itself, configured as an output port, or the external device when the port is configured as an input port). Writing to this register is ignored. Activation of the SBGPIO port is controlled by the same external, device-specific configuration bit (or a combination of bits) that control the activation of the SWC. When the SWC logical device is inactive, access to both the SBGPDI and SBGPDO registers is disabled. However, there is no change in the port configuration and in the SBGPDO value and hence there is no effect on the outputs of the pins. Event Detection The enhanced SBGPIO port supports input event detection. This functionality is based on three configuration bits. The configuration and operation of the event detection capability is shown in Figure 13. An SWC status register reflects the status of each input event. SWC configuration registers determine the effect of each input event on the various means of system notification available in the SWC. Event Pending Indicator Event Enable 0 Input Debouncer Rising Edge Detector 1 Status R/W 1 to Clear Detected Enabled Events from other SBGPIO Pins Pin Rising Edge =1 Event Debounce Enable Event Polarity Bit 6 Bit 5 Internal Bus SBGPIO Pin Configuration Register Figure 13. Event Detection www.national.com R/W 112 3.0 System Wake-Up Control (SWC) (Continued) Event Configuration Each pin in the SBGPIO port is a potential input event source. The event detection can trigger a system notification upon predetermined behavior of the source pin. The SBGPIO Pin Configuration register determines the event detection trigger type for the system notification. • Event Type and Polarity - One trigger type of event detection is supported: edge (Event Type, bit 4 = 0). An edge event may be detected upon a source pin transition either from high to low or low to high. The direction of the transition (i.e., edge) is determined by Event Polarity (bit 5). • Event Debounce Enable - The input signal can be debounced for about 15 msec before entering the detector. The signal state is transferred to the detector only after a debouncing period during which the signal has no transitions, to ensure that the signal is stable. The debouncer adds 15 msec delay to both assertion and de-assertion of the event pending indicator. Therefore, when working with a level event and system notification by either SMI or IRQ, it is recommended to disable the debounce if the delay in the SMI/IRQ de-assertion is not acceptable. The debounce is controlled by Event Debounce Enable (bit 6 of the SBGPIO Pin Configuration register). 3.4.31 Standby GPIO Pin Select Register (SBGPSEL) This register selects the GPIOE/GPIE pin (port number and pin number) to be configured (the register accessed by the Standby GPIO Pin Configuration register). This register is reset to 00h on VPP power-up or software reset. When port 0 is selected, bits 2-0 select between pins GPIE7,6 and GPIOE5-0. When port 1 is selected, bits 2-0 select between pins GPOS0 and GPOS1. Pins GPIS2 and GPIS3 are input only and require no configuration. Location: Bank 3, Offset 13h Type: R/W Bit 7 Name 5 Reserved Reset 0 Bit 7-5 6 0 0 4 3 Port Select Reserved 0 0 1 0 Pin Select 0 0 0 Description Reserved. 4 Port Select. This bit selects the GPIO port to be configured. 0: Port 0 (default) 1: Port 1 3 Reserved. 2-0 2 Pin Select. These bits select the GPIO pin to be configured in the selected port. 000, 001, ... 111:The binary value of the pin number, 0, 1, ... 7 respectively (default=0) 113 www.national.com 3.0 System Wake-Up Control (SWC) (Continued) 3.4.32 Standby GPIO Pin Configuration Register (SBGPCFG) This is a group of 12 configuration registers. Eight are identical for GPIOE and GPIE, two are identical for GPOS and two are identical for GPIS. Each GPIOE/GPIE register is associated with one GPIOE/GPIE pin, and each GPOS and GPIS register is associated with one GPOS or GPIS pin. The entire set is mapped to the same address. The mapping scheme is based on the Standby GPIO Pin Select (SBGPSEL) register that functions as an index register and the specific Standby GPIO Pin Configuration register that reflects the configuration of the currently selected pin. Bits 0-3 are applicable only for pins GPIOE0-5 and GPOS0,1. Bits 4-6 are applicable for all GPIOE/GPIE pins. Location: Bank 3, Offset 14h Type: R/W (bit 3 is set only) For GPIOE and GPIE: Bit 7 6 5 4 3 2 1 0 Name Reserved Event Debounce Enable Event Polarity Event Type Lock Pull-Up Control Output Type Output Enable Reset 0 1 0 0 0 1 0 0 7 6 5 4 3 2 1 0 Lock Pull-Up Control Output Type Output Enable 0 1 0 1 3 2 1 0 0 0 0 0 For GPOS: Bit Name Reserved Reset 0 0 0 0 7 6 5 4 For GPIS: Bit Name Reserved Reset 0 0 0 Bit 0 Description 7 Reserved. (For GPOS and GPIS, bits 7-4 and 7-0 are reserved, respectively). 6 Event Debounce Enable. 0: Disabled 1: Enabled (default) 5 Event Polarity. This bit defines the polarity of the signal that causes a detection of an event from the corresponding GPIO pin. 0: Falling edge input (default) 1: Rising edge input 4 Event Type. This bit defines the signal type that causes a detection of an event from the corresponding GPIO pin. 0: Edge input (default) 1: Reserved 3 Lock. This bit locks bits 2-0 of this register. These bits are associated with the GPIO pin currently selected by the SBGPSEL register. Once this bit is set to 1 by software, it can only be cleared to 0 by VSB power-up reset. 0: No effect (default at VSB power-up reset) 1: Direction, output type, pull-up and output value locked www.national.com 114 3.0 System Wake-Up Control (SWC) (Continued) Bit Description 2 Pull-Up Control. This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin. It supports open-drain output signals with internal pull-ups and TTL input signals. 0: Disabled 1: Enabled (default) 1 Output Type. This bit controls the output buffer type (open-drain or totem pole) of the corresponding GPIO pin. 0: Open-drain (default) 1: Push-pull 0 Output Enable. For GPOS, this is a R/O bit. It indicates the GPOS pin output state and is always 1. For GPIOE and GPIE, this bit indicates the GPIO pin output state. It has no effect on input. 0: TRI-STATE (default for GPIOE/GPIE) 1: Output enabled (default for GPOS) 115 www.national.com 3.0 System Wake-Up Control (SWC) (Continued) 3.4.33 Standby GPIOE/GPIE Data Out Register 0 (SB_GPDO0) This register is set to 3Fh on VPP power-up or software reset only when the Lock bit of the SBGPCFG register is set to 0. It determines the value to be driven on the GPIOE pins when configured as outputs. Location: Offset 08h Type: R/W Bit 7 Name 6 5 0 4 3 2 1 0 2 1 0 1 1 1 Data Out 0 1 Bit 5 3 Reserved Reset 7-6 4 1 1 Description Reserved. Data Out. Bits 5-0 correspond to pins GPIOE5-0 respectively. The value of each bit determines the value driven on the corresponding GPIOE pin when its output buffer is enabled. Writing to the bit latches the written data unless the bit is locked by the corresponding GPIOE Configuration Lock bit. Reading the bit returns its value, regardless of the pin value and configuration. 0: Corresponding pin level low when output enabled 1: Corresponding pin level high (according to buffer type and static pull-up selection) when output enabled 3.4.34 Standby GPIOE/GPIE Data In Register 0 (SB_GPDI0) This register reflects the values of the GPIE7-6 and GPIOE5-0 pins. Write to this register is ignored. Location: Offset 09h Type: RO Bit 7 6 5 4 Name 3 2 1 0 X X X X Data In Reset X Bit X X X Description 7 6 5 4 3 2 Data In. Bits 7-0 correspond to pins GPIE7-6 and GPIOE5-0 respectively. Reading each bit returns the value of the corresponding GPIE/GPIOE pin regardless of the pin configuration and the SB0_GPDO register value. 0: Corresponding pin level low 1: Corresponding pin level high 1 0 www.national.com 116 3.0 System Wake-Up Control (SWC) (Continued) 3.4.35 Standby GPOS Data Out Register 1 (SB_GPDO1) This register is set to 03h on VPP power-up or software reset only when the Lock bit of the SBGPCFG register is set to 0. It determines the value to be driven on the GPSO0,1 pins. Location: Offset 0Ah Type: R/W Bit 7 6 5 Name 4 3 2 1 Reserved Reset 0 0 0 Bit 0 Data Out 0 0 0 1 1 Description 7-2 Reserved. 1-0 Data Out. Bits 1-0 correspond to pins GPOS1-0 respectively. The value of each bit determines the value driven on the corresponding GPOS pin when its output buffer is enabled. Writing to the bit latches the written data unless the bit is locked by the corresponding GPOS Configuration Lock bit. Reading the bit returns its value, regardless of the pin value and configuration. 0: Corresponding pin level low 1: Corresponding pin level high (according to buffer type and static pull-up selection) 3.4.36 Standby GPIS Data In Register 1 (SB_GPDI1) This register reflects the values of the GPOS0,1 and GPIS2,3 pins. Write to this register is ignored. Location: Offset 0Bh Type: RO Bit 7 6 Name 5 4 3 2 Reserved Reset X Bit X 1 0 X X Data In X X X X Description 7-4 Reserved. 3-0 Data In. Reading each bit returns the value of the corresponding GPOS/GPIS pin. 0: Corresponding pin level low 1: Corresponding pin level high 117 www.national.com 3.0 System Wake-Up Control (SWC) 3.5 (Continued) SWC REGISTER BITMAP Table 43. Banks 0 and 1 - The Common Register Bitmap Register Bits Offset Mnemonic 7 6 5 4 3 2 1 0 00h WK_STS0 Module IRQ Event Status Software Event Status GPIO Event Status CEIR Event Status Mouse Event Status KBD Event Status RI2 Event Status RI1 Event Status 01h WK_STS1 GPIE7 Event Status GPIE6 Event Status GPIE5 Event Status GPIE4/ RING Event Status GPIE3 Event Status GPIE2 Event Status GPIE1 Event Status GPIE0 Event Status 02h WK_EN0 Module IRQ Event Enable Software Event Enable GPIO Event Enable CEIR Event Enable Mouse Event Enable KBD Event Enable RI2 Event Enable RI1 Event Enable 03h WK_EN1 GPIE7 Event Enable GPIE6 Event Enable GPIE5 Event Enable GPIE4/ RING Event Enable GPIE3 Event Enable GPIE2 Event Enable GPIE1 Event Enable GPIE0 Event Enable 04h WK_CFG Enable Power But- Swap KBC ton Pulse Inputs on S3 Reserved 05h-07h Configuration Bank Select Reserved 08h SB_GPDO0 09h SB_GPDI0 0Ah SB_GPDO1 0Bh SB_GPDI1 Reserved Data Out Data In Reserved Data Out Reserved Data In 0Ch-12h Reserved Table 44. Bank 0 - PS/2 Keyboard/Mouse Wake-Up Configuration and Control Registers Bitmap Register Bits Offset Mnemonic 7 13h PS2CTL Disable Parity 16h KDSR 17h MDSR 18h-1Fh PS2KEY0PS2KEY7 www.national.com 6 5 4 3 Mouse Wake-Up Configuration 2 1 Keyboard Wake-Up Configuration Keyboard Data Reserved Mouse Data Scan Code of Keys 0-7 118 0 3.0 System Wake-Up Control (SWC) (Continued) Table 45. Bank 1 - CEIR Wake-Up Configuration and Control Registers Bitmap Register Offset Mnemonic 13h IRWCR Bits 7 6 Reserved 5 4 CEIR Protocol Select 14h 3 2 1 0 Select IRRX2 Input Invert IRRXn Input Reserved CEIR Enable Reserved 15h IRWAD CEIR Wake-Up Address 16h IRWAM CEIR Wake-Up Address Mask 17h ADSR CEIR Address 18h IRWTR0L Reserved CEIR Pulse Change, Range 0, Low Limit 19h IRWTR0H Reserved CEIR Pulse Change, Range 0, High Limit 1Ah IRWTR1L Reserved CEIR Pulse Change, Range 1, Low Limit 1Bh IRWTR1H Reserved CEIR Pulse Change, Range 1, High Limit 1Ch IRWTR2L CEIR Pulse Change, Range 2, Low Limit 1Dh IRWTR2H CEIR Pulse Change, Range 2, High Limit 1Eh IRWTR3L CEIR Pulse Change, Range 3, Low Limit 1Fh IRWTR3H CEIR Pulse Change, Range 3, High Limit Table 46. Bank 2 - Event Routing Control Registers Bitmap Register Offset Mnemonic Bits 7 6 5 4 3 2 1 0 Software CEIR RI2 RI1 Mouse KBD Event to Reserved Event to Event to Event to Event to Event to SMI Enable SMI Enable SMI Enable SMI Enable SMI Enable SMI Enable 13h WK_SMIEN0 Reserved 14h WK_SMIEN1 15h WK_IRQEN0 Reserved 16h WK_IRQEN1 GPIE7 GPIE6 GPIE5 Event to Event to Event to IRQ Enable IRQ Enable IRQ Enable GPIE4/ GPIE3 GPIE2 GPIE1 GPIE0 RING Event to Event to Event to Event to Event to IRQ Enable IRQ Enable IRQ Enable IRQ Enable IRQ Enable 17h WK_X1EN0 Reserved CEIR Mouse KBD RI2 RI1 Event Ex. 1 Event Ex. 1 Event Ex. 1 Event Ex. 1 Event Ex. 1 Enable Enable Enable Enable Enable 18h GPIE4/ GPIE3 GPIE2 GPIE1 GPIE0 GPIE7 GPIE6 GPIE5 RING Event Ex. 1 Event Ex. 1 Event Ex. 1 Event Ex. 1 WK_X1EN1 Event Ex. 1 Event Ex. 1 Event Ex. 1 Event Ex. 1 Enable Enable Enable Enable Enable Enable Enable Enable 19h WK_X2EN0 GPIE6 GPIE5 GPIE7 Event to Event to Event to SMI Enable SMI Enable SMI Enable GPIE4/ GPIE3 GPIE2 GPIE1 GPIE0 RING Event to Event to Event to Event to Event to SMI Enable SMI Enable SMI Enable SMI Enable SMI Enable RI2 RI1 Software CEIR Mouse KBD Event to Event to Event to Reserved Event to Event to Event to IRQ Enable IRQ Enable IRQ Enable IRQ Enable IRQ Enable IRQ Enable Reserved CEIR Mouse KBD RI2 RI1 Event Ex. 2 Event Ex. 2 Event Ex. 2 Event Ex. 2 Event Ex. 2 Enable Enable Enable Enable Enable 119 www.national.com 3.0 System Wake-Up Control (SWC) (Continued) 1Ah GPIE4/ GPIE3 GPIE2 GPIE1 GPIE0 GPIE7 GPIE6 GPIE5 RING Event Ex. 2 Event Ex. 2 Event Ex. 2 Event Ex. 2 WK_X2EN1 Event Ex. 2 Event Ex. 2 Event Ex. 2 Event Ex. 2 Enable Enable Enable Enable Enable Enable Enable Enable 1Bh WK_X3EN0 1Ch GPIE4/ GPIE3 GPIE2 GPIE1 GPIE0 GPIE7 GPIE6 GPIE5 RING Event Ex. 3 Event Ex. 3 Event Ex. 3 Event Ex. 3 WK_X3EN1 Event Ex. 3 Event Ex. 3 Event Ex. 3 Event Ex. 3 Enable Enable Enable Enable Enable Enable Enable Enable 1Dh1Fh Reserved CEIR Event Ex. 3 Enable Reserved Mouse KBD RI2 RI1 Event Ex. Event Ex. 3 Event Ex. 3 Event Ex. 3 3 Enable Enable Enable Enable Table 47. Bank 3 - Standby General-Purpose I/O Configuration Registers Bitmap Register Offset Mnemonic 13h SBGPSEL 14h SBGPCFG 15h1Fh www.national.com Bits 7 6 5 Reserved Reserved Event Debounce Enable 4 3 Port Select Reserved Event Type Lock Event Polarity Reserved 120 2 1 0 Pin Select Pull-Up Control Output Type Output Enable 4.0 4.1 Fan Speed Control OVERVIEW This chapter describes a generic Fan Speed Control module. For the implementation used in this device, see the Device Architecture and Configuration chapter. The Fan Speed Control is a programmable Pulse Width Modulation (PWM) generator. The PWM generator output is used to control the fan’s power voltage, which is correlated to the fan’s speed. Converting a 0 to 100% duty cycle PWM signal to an analog voltage range is achieved by an external circuit, as shown in Figure 14. Some newer fans accept direct PWM input without any external circuitry. When an overtemperature condition is detected, the Fan speed Control forces the fan to turn on at 100% duty cycle. FANOUT Fan Speed Control External External Circuitry Circuitry Control Fan Figure 14. Fan Speed Control - System Configuration 4.2 FUNCTIONAL DESCRIPTION The PWM generator operation is based on a PWM counter and two registers: the Fan Speed Control Pre-Scale register (FCPSR), used to determine the overall cycle time (or the frequency) of the FANOUT output, and the Fan Speed Control Duty Cycle register (FCDCR), used to determine the duty cycle of the FANOUT between 0 to 100%. The PWM counter is an 8-bit, free-running counter that runs continuously in a cyclic manner, i.e., its cycle equals 256 clock periods. The PWM output is high, as long as the count is lower than the FCDCR value and it flips to low as the counter exceeds that value. The duty cycle (expressed as a percentage) is therefore (FCDCR/256)*100. In particular, the PWM output is continuously low when FCDCR=0 and continuously high when FCDCR=FFh. The FANOUT output may be inverted by an external configuration bit, in which case the FANOUT duty cycle is ([256-FCDCR]/256)*100. The PWM counter clock is generated by dividing the input clock (either 24 MHz or 200 KHz), using a clock divider. The division factor, which must be between 1 and 124, is defined as Pre-Scale Value+1, where Pre-Scale is the binary value stored in bits 6 to 0 of the FCPSR register. The resulting PWM output frequency is therefore: (24 MHz or 200 kHz/([Pre-Scale Value+1]*256). The default selection of 24 MHz input clock allows a programmable FANOUT frequency in the range of 756 Hz to 93.75 KHz. For lower frequencies, selecting the 200 KHz input clock allows a frequency range of 6 Hz to 781 Hz (see Figure 15). The FANOUT frequency must be pre-selected according to the fan type’s specific requirements prior to enabling the Fan Speed Control. The only run-time change that is required to dynamically control the fan speed is the value of the FCDCR register. Warning! The contents of the FCPSR register must not be changed when the Fan Speed Control is enabled. Enable Fans on OTS Detection When the respective Fan i Enable on OTS (bits 2-0) of the Fan Speed Control OTS Configuration register is set (see Section 2.18.5 on page 77), the fan is forced to 100% duty cycle when any of the temperature measurement channels flags an overtemperature condition. This occurs regardless of the setting of the FCDCR register in order to help protect the system from overheating. 24 MHz 0 Clock Divider (1-124) 200 KHz 1 PWM Counter Invert FANOUT PWM Output - Comparator Bit 7 FCDCR > Counter 0 Bits 6-0 O FCPSR Register FANOUT 1 FCDCR Register Figure 15. PWM Generator (FANOUT) 121 www.national.com 4.0 Fan Speed Control 4.3 (Continued) FAN SPEED CONTROL REGISTERS The following abbreviations are used to indicate the Register Type: • R/W = Read/Write. • R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register. • W = Write. • RO = Read Only. • R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. 4.3.1 Fan Speed Control Register Map Offset Mnemonic Register Name Type Section Device specific1 FCPSR Fan Speed Control Pre-Scale R/W 4.3.2 Device specific1 FCDCR Fan Speed Control Duty Cycle R/W 4.3.3 1. The location of this register is defined in the Device Architecture and Configuration chapter. 4.3.2 Fan Speed Control Pre-Scale Register (FCPSR) Location: Device specific Type: R/W Bit 7 Name Clock Select Reset 0 Bit 7 6-0 6 5 4 3 2 1 0 0 0 0 Pre-Scale Value 0 0 0 0 Description Clock Select. This bit selects the input clock for the clock divider. 0: 24 MHz 1: 200 KHz Pre-Scale Value. The clock divider for the input clock (24 MHz or 200 KHz) is Pre-Scale Value + 1. Writing 0000000b to these bits transfers the input clock directly to the counter. The maximum clock divider is 124 (7Bh +1). These bits must not be programmed with the values 7Ch, 7Dh, 7Eh and 7Fh as this may produce unpredictable results. The contents of this register should not be changed when the corresponding Fan Speed Control Enable bit of the Fan Speed Control Configuration register is 1 (see Device Architecture and Configuration chapter) as this may produce unpredictable results. www.national.com 122 4.0 Fan Speed Control 4.3.3 (Continued) Fan Speed Control Duty Cycle Register (FCDCR) Location: Device specific Type: R/W Bit 7 6 5 4 Name 3 2 1 0 1 1 1 Duty Cycle Value Reset 1 1 1 1 1 Bit Description 7-0 Duty Cycle. The binary value of this 8-bit field determines the number of clock cycles out of a 256-cycle period, during which the PWM output is high (while FANOUT is either equal to or the inverse of the PWM output, depending on the Inverse FANOUT configuration bit). 00h: PWM output is continuously low 01h - FEh: PWM output is high for [Duty Cycle Value] clock cycles and low for [256-Duty Cycle Value] clock cycles FFh: PWM output is continuously high 4.4 FAN SPEED CONTROL BITMAP Register Bits Offset Mnemonic 7 Device specific1 FCPSR Clock Select Device specific 1 FCDCR 6 5 4 3 2 1 0 Pre-Scale Value Duty Cycle Value 1. The location of this register is defined in the Device Architecture and Configuration chapter. 123 www.national.com 5.0 5.1 Fan Speed Monitor OVERVIEW This chapter describes a generic Fan Speed Monitor module. For the implementation used in this device, see the Device Architecture and Configuration chapter. The Fan Speed Monitor determines the fan’s speed by measuring the time between consecutive tachometer pulses emitted by the fan once or twice per revolution (depending on the fan type). It may provide the system with a current speed reading and/or alert the system, by interrupt, whenever the speed drops below a programmable threshold. The Fan Speed Monitor indicates whether the speed is just below the threshold or inefficiently low to consider the fan stopped. Figure 16 shows the basic system configuration of the Fan Speed Monitor. Fan Tachometer Pulse Filtering Circuitry (optional) FANIN Fan Speed Monitor Figure 16. Fan Speed Monitor - System Configuration 5.2 FUNCTIONAL DESCRIPTION The fan emits a tachometer pulse every half or full revolution (depending on the fan type). These pulses are fed into the Fan Speed Monitor through the FANIN input pin. Measuring the time between these pulses is the basis for speed monitoring. NCBTP is defined as the Number of Clock-cycles Between consecutive Tachometer Pulses. For a known clock rate (f Hz) and number of pulses per revolution (n=1,2), the Fan Speed is calculated according to the following relationship: f Fan Speed (in RPM) = 60 • -----------------------------NCBTP • n The Fan Speed Monitor consists of an 8-bit counter to measure the NCBTP and three 8-bit registers: Fan Monitor Speed register (FMSPR), Fan Monitor Threshold register (FMTHR) and Fan Monitor Control and Status register (FMCSR). Figure 17 is a general block diagram of the Fan Speed Monitor. The Up Counter and the FMSPR register are cleared to 0 while the Fan Speed Monitor is disabled (and in particular upon system reset). When the Fan Speed Monitor is enabled and there is no counter overflow, the counter runs (up-counts), clocked by the selected clock rate. Starting from the second FANIN pulse (after activation) and upon every rising edge of FANIN when the Over Threshold bit is 0, the FMSPR register is loaded with the contents of the counter, the counter is cleared to 0 and the Speed Ready bit is set to 1. Upon reading FMSPR, the Speed Ready bit of the FMCSR is cleared to 0. The above operation continually repeats itself, providing the host with the current speed reading, as long as the FMSPR register value is lower than the threshold. Once the loaded FMSPR register value exceeds the threshold, the Over Threshold bit is set to 1. Interrupt is asserted if enabled. The FMSPR register is not loaded with any new values when the Over Threshold bit is set. A new value is loaded only after clearing the Over Threshold bit (by writing 1) and reading the FMSPR register. This guarantees that the same NCBTP value that generated the interrupt remains available for the interrupt handler. If the counter passes FFh, the Overflow bit is set to 1, the FMSPR register is cleared and the interrupt is asserted, if enabled. The Overflow bit is cleared to 0 when it is written with 1, after which speed measurement resumes. The input buffer of the FANIN signal is a hysteresis buffer (Schmitt trigger). This signal passes through a digital filter when the Filter Disable bit (bit 4 of the FMCSR register) is 0. The digital filter uses a 32 KHz clock to filter out any pulses shorter than 750 µsec. This filter can be by-passed when setting bit 4 of the FMCSR register to 1. 124 www.national.com 5.0 Fan Speed Monitor (Continued) . Set Speed Ready (FMCSR, Bit 0) 16 Khz 8 Khz Clock Up Counter 4 Khz Overflow (FMCSR, Bit 2) Clear 2 Khz Clock Select (FMCSR, Bits 6-5) FMSPR Register Load Over Threshold (FMCSR, Bit 1) Interrupt Comparator Filter Pos. Edge Detector Interrupt Enable (FMCSR, Bit 3) FANIN FMTHR Register Filter Disable (FMCSR, Bit 4) Figure 17. Fan Speed Monitor 5.3 FAN SPEED MONITOR REGISTERS The FMSPR register is used to hold the current speed reading (which is represented by the latest NCBTP and refreshed upon every FANIN pulse). The FMTHR register holds the maximum allowed NCBTP value (representing the slowest speed at which the fan is allowed to operate) without causing system alert. Additional control and status bits are available through the FMCSR register. These include: • Over Threshold. A status bit that indicates that the NCBTP has exceeded the threshold (the speed has dropped below the allowed minimum). • Overflow. A status bit that indicates that the NCBTP is higher than FFh. With a proper input clock selection, this means that the speed is inefficiently low and is considered stopped. • • Speed Ready. A status bit that indicates that new, valid data has been loaded into the FMSPR register. Clock Select. A 2-bit control field that selects the counter clock rate as either 2 KHz, 4 KHz, 8 KHz or 16 KHz. The following abbreviations are used to indicate the Register Type: • R/W = Read/Write. • R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register. • W = Write. • RO = Read Only. • R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. 5.3.1 Fan Speed Monitor Register Map Offset Mnemonic Type Section Fan Monitor Threshold R/W 5.3.2 FMSPR Fan Monitor Speed RO 5.3.3 FMCSR Fan Monitor Control and Status Varies per bit 5.3.4 specific1 FMTHR Device specific1 Device specific1 Device 1. Register Name The location of this register is defined in the Device Architecture and Configuration chapter. 125 www.national.com 5.0 Fan Speed Monitor 5.3.2 (Continued) Fan Monitor Threshold Register (FMTHR) This 8-bit register contains the programmable threshold for the fan. This threshold is the maximum number of clock cycles between consecutive tachometer pulses (frequencies of 16, 8, 4 or 2 KHz). It represents the minimum fan speed permitted in the system. If the period between consecutive tachometer pulses is greater than the threshold, an interrupt (if enabled) is issued. After reset, the value of FMTHR is FFh. This register should not be changed when the corresponding Fan Monitor Enable bit is set to 1 (enabled), since this may cause unpredictable results. Location: Device specific Type: R/W Bit 7 6 5 Name 3 2 1 0 1 1 1 Threshold Value Reset 5.3.3 4 1 1 1 1 1 Fan Monitor Speed Register (FMSPR) This read-only 8-bit register holds the speed reading, represented by number of clock cycles between consecutive tachometer pulses. For details, refer to Section 5.2. When the Speed Ready bit of the FMCSR register is 1, FMSPR holds valid data that has not yet been read. It is cleared to 00h upon any of the following conditions: ● System reset. ● Fan Monitor Enable bit is set to 0. ● Overflow bit is set to 1. Location: Device specific Type: RO Bit 7 6 5 Name 3 2 1 0 0 0 0 0 4 3 2 1 0 Filter Disable Interrupt Enable Overflow Over Threshold Speed Ready 0 0 0 0 0 Fan Speed Reading Reset 5.3.4 4 0 0 0 0 Fan Monitor Control and Status Register (FMCSR) Location: Device specific Type: Varies per bit Bit 7 Name Reserved Reset 0 www.national.com 6 5 Clock Select 0 1 126 5.0 Fan Speed Monitor Bit Type 7 Description Reserved 6-5 R/W Clock Select. Selects the clock source provided to the counter. These bits must not be changed when the corresponding Fan Monitor Enable bit is 1 (enabled). 00: 16 KHz 01: 8 KHz (default) 10: 4 KHz 11: 2 KHz 4 R/W Filter Disable. When this bit is set to 1, the digital filter is disabled. When it is cleared, the filter is enabled. This bit should not be changed when the corresponding Fan Monitor Enable bit is 1 (enabled) to avoid unpredictable results. 0: Digital filter enabled (default) 1: Digital filter disabled 3 R/W Interrupt Enable. This bit controls the assertion of overflow interrupt and Over Threshold interrupt. 0: Interrupt disabled (default) 1: Interrupt enabled. Interrupt is asserted when an Over Threshold bit, Overflow bit or both are set to 1. 2 R/W1C Overflow. Indicates that the counter has passed FFh and the fan speed is inefficiently slow; i.e., slower than 60 ∗ f/(256 ∗ n). Writing 1 to this bit clears it to 0. 0: No overflow occurred since the last time this bit was cleared (by reset or by writing 1) 1: Counter passed FFh 1 R/W1C Over Threshold. Indicates that the value loaded into the FMSPR register upon detection of the rising edge of the FANIN pulse exceeded the threshold value. 0: FMSPR register value did not exceed the threshold since the last time this bit was cleared (by reset or by writing 1) 1: FMSPR register value exceeded the threshold 0 5.4 (Continued) RO Speed Ready. This bit indicates that the speed register holds new (not yet read) and valid data. It is set to 1 on each rising edge of the FANIN input (starting from the second one) if the Over Threshold bit is 0. It is cleared to 0 whenever the speed register is read or when the Overflow bit is set. 0: No new valid data in the FMSPR register (data is either invalid or has already been read) 1: FMSPR register loaded with new and valid data FAN SPEED MONITOR BITMAP Register Bits Offset Mnemonic 7 Device specific1 FMTHR Threshold Value Device specific1 FMSPR Fan Speed Reading Device specific1 FMCSR Reserved 6 5 4 Filter Disable Clock Select 3 Interrupt Enable 2 1 0 Overflow Over Threshold Speed Ready 1. The location of this register is defined in the Device Architecture and Configuration chapter. 127 www.national.com 6.0 General-Purpose Input/Output (GPIO) Port This chapter describes one 8-bit port. A device may include a combination of several ports with different implementations. For the device specific implementation, see the Device Architecture and Configuration chapter. 6.1 OVERVIEW The GPIO port is an 8-bit port, which is based on eight pins. It features: ● Software capability to manipulate and read pin levels. ● Controllable system notification by several means based on the pin level or level transition. ● Ability to capture and manipulate events and their associated status. ● Back-drive protected pins. GPIO port operation is associated with two sets of registers: ● Pin Configuration registers, mapped in the Device Configuration space. These registers are used to statically set up the logical behavior of each pin. There are two 8-bit register for each GPIO pin. ● Four 8-bit runtime registers: GPIO Data Out (GPDO), GPIO Data In (GPDI), GPIO Event Enable (GPEVEN) and GPIO Event Status (GPEVST). These registers are mapped in the GPIO device IO space (which is determined by the base address registers in the GPIO Device Configuration). They are used to manipulate and/or read the pin values and to control and handle system notification. Each runtime register corresponds to the 8-pin port, such that bit ‘n’ in each one of the four registers is associated with GPIOXn pin, where ‘X’ is the port number. Each GPIO pin is associated with ten configuration bits and the corresponding bit slice of the four runtime registers, as shown in Figure 18. The functionality of the GPIO port is divided into basic functionality (which includes the manipulation and reading of the GPIO pins) and enhanced functionality (which includes event detection and system notification). Basic functionality is described in Section 6.2. Enhanced functionality is described in Section 6.3. Bit n GPDOX GPIOX Base Address GPDIX 8 GPCFG Registers X = port number n = pin number, 0 to 7 GPIO Pin Configuration (GPCFG) Register GPEVENX Runtime Registers GPEVSTX GPIOXn Pin GPIOXn CNFG GPIOXn Port Logic x8 GPIO Pin Select (GPSEL) Register Port and Pin Select 8 GPEVR Registers x8 Event Pending Indicator x8 GPIO Pin Event Routing (GPEVR) Register GPIOXn ROUTE Figure 18. GPIO Port Architecture www.national.com 128 Event Routing Control Interrupt Request SMI PWUREQ 6.0 General-Purpose Input/Output (GPIO) Port 6.2 (Continued) BASIC FUNCTIONALITY The basic functionality of each GPIO pin is based on four configuration bits and a bit slice of runtime registers GPDO and GPDI. The configuration and operation of a single pin GPIOXn (pin n in port X) is shown in Figure 19. GPIO Device Enable Read Only Data In Static Pull-Up Push-Pull =1 Pin Read/Write Data Out Internal Bus Pull-Up Enable Lock Pull-Up Control Output Type Output Enable Bit 3 Bit 2 Bit 1 Bit 0 GPIO Pin Configuration (GPCFG) Register Figure 19. GPIO Basic Functionality 6.2.1 Configuration Options The GPCFG register controls the following basic configuration options: • • Port Direction - Controlled by the Output Enable bit (bit 0). • Weak Static Pull-up - May be added to any type of port (input, open-drain or push-pull). It is controlled by Pull-Up Control (bit 2). • Pin Lock - GPIO pin may be locked to prevent any changes in the output value and/or the output characteristics. The lock is controlled by Lock (bit 3). It disables writes to the GPDO register bits and to bits 0-3 of the GPCFG register (Including the Lock bit itself). Once locked, it can be released by hardware reset only. Output Type - Push-pull vs. open-drain. It is controlled by Output Buffer Type (bit 1) by enabling/disabling the pull-up portion of the output buffer. 6.2.2 Operation The value that is written to the GPDO register is driven to the pin if the output is enabled. Reading from the GPDO register returns its contents regardless of the pin value or the port configuration. The GPDI register is a read-only register. Reading from the GPDI register returns the pin value regardless of what is driving it (the port itself, configured as an output port, or the external device when the port is configured as an input port). Writing to this register is ignored. Activation of the GPIO port is controlled by external device specific configuration bit (or a combination of bits). When the port is inactive, access to GPDI and GPDO registers is disabled and the inputs are blocked. However, there is no change in the port configuration and in the GPDO value and hence there is no effect on the outputs of the pins. 129 www.national.com 6.0 General-Purpose Input/Output (GPIO) Port 6.3 (Continued) EVENT HANDLING AND SYSTEM NOTIFICATION The enhanced GPIO port supports system notification based on event detection. This functionality is based on six configuration bits and a bit slice of runtime registers GPEVEN and GPEVST. The configuration and operation of the event detection capability is shown in Figure 20. The operation of system notification is illustrated in Figure 21. 1 Event Pending Indicator 0 Event Enable 0 Input Debouncer Rising Edge Detector 1 Status R/W 1 to Clear Pin Rising Edge or High Level =1 Level =1 Event Debounce Enable Event Polarity Event Type Bit 6 Bit 5 Bit 4 R/W Detected Enabled Events from other GPIO Pins Internal Bus GPIO Pin Configuration Register Figure 20. Event Detection 6.3.1 Event Configuration Each pin in the GPIO port is a potential input event source. The event detection can trigger a system notification upon predetermined behavior of the source pin. The GPCFG register determines the event detection trigger type for the system notification. Event Type and Polarity Two trigger types of event detection are supported: edge and level. An edge event may be detected upon a source pin transition either from high to low or low to high. A level event may be detected when the source pin is in active level. The trigger type is determined by Event Type (bit 4 of the GPCFG register). The direction of the transition (for edge) or the polarity of the active level (for level) is determined by Event Polarity (bit 5 of the GPCFG register). Event Debounce Enable The input signal can be debounced for about 15 msec before entering the detector. To ensure that the signal is stable, the signal state is transferred to the detector only after a debouncing period, during which the signal has no transitions. The debouncer adds 15 msec delay to both assertion and de-assertion of the event pending indicator. Therefore, when working with a level event and system notification by either SMI or IRQ, it is recommended to disable the debounce if the delay in the SMI/IRQ de-assertion is not acceptable. The debounce is controlled by Event Debounce Enable (bit 6 of the GPCFG register). 6.3.2 System Notification System notification on GPIO-triggered events is by means of assertion of one or more of the following output pins: ● Interrupt Request (via the device’s Bus Interface). ● System Management Interrupt (SMI, via the device’s Bus Interface). ● Power-Up Request (PWUREQ, via the System Wake-Up Control). The system notification for each GPIO pin is controlled by the corresponding bits in the GPEVEN and GPEVR registers. System notification by a GPIO pin is enabled if the corresponding bit of the GPEVEN register is set to 1. The corresponding bits in the GPEVR register select which means of system notification the detected event is routed to. The event routing mechanism is described in Figure 21. www.national.com 130 6.0 General-Purpose Input/Output (GPIO) Port (Continued) Event Pending Indicator PWUREQ SMI Event Routing Logic Enable PWUREQ Routing Enable SMI Routing Enable IRQ Routing Bit 2 Bit 1 Bit 0 IRQ Routed Events from other GPIO Pins GPIO Pin Event Routing Register Figure 21. GPIO Event Routing Mechanism The GPEVST register is a general-purpose edge detector that may be used to reflect the event source pending status for edge-triggered events. The term active edge refers to a change in a GPIO pin level that matches the Event Polarity bit (1 for rising edge and 0 for falling edge). Active level refers to the GPIO pin level that matches the Event Polarity bit (1 for high level and 0 for low level). The corresponding bit of the GPEVST register is set by hardware whenever an active edge is detected regardless of any other bit settings. Writing 1 to the Status bit clears it to 0. Writing 0 is ignored. A GPIO pin is in event pending state if the corresponding bit of the GPEVEN register is set and either: ● The Event Type is level and the pin is in active level, or ● The Event Type is edge and the corresponding bit of the GPEVST register is set. The target means of system notification is asserted if at least one GPIO pin is in event pending state. The selection of the target means of system notification is determined by the GPEVR register. If IRQ is selected as one of the means for the system notification, the specific IRQ line is determined by the IRQ selection procedure of the device configuration. The assertion of any means of system notification is blocked when the GPIO functional block is deactivated. If the output of a GPIO pin is enabled, it may be put in event pending state by the software when writing to the GPDO register. A pending edge event may be cleared by clearing the corresponding GPEVST bit. However, a level event source may not be released by software (except for disabling the source) as long as the pin is in active level. When level event is used, it is recommended to disable the input debouncer. Upon deactivation of the GPIO port, the GPEVST register is cleared and access to both the GPEVST and GPEVEN registers is disabled. All system notification means including the target IRQ line are detached from the GPIO and de-asserted. Before enabling any system notification, it is recommended to set the desired event configuration and then verify that the status registers are cleared. 6.4 GPIO PORT REGISTERS The register maps in this chapter use the following abbreviations for Type: ● R/W = Read/Write. ● R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register. ● W = Write. ● RO = Read Only. ● R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. 131 www.national.com 6.0 General-Purpose Input/Output (GPIO) Port 6.4.1 (Continued) GPIO Pin Configuration (GPCFG) Register This is a group of eight identical configuration registers, each of which is associated with one GPIO pin. The entire set is mapped to the PnP configuration space. The mapping scheme is based on the GPSEL register, which functions as an index register and the specific GPCFG register, which reflects the configuration of the currently selected pin. For details on the GPSEL register, refer to the Device Architecture and Configuration chapter. Bits 4-6 are applicable only for the enhanced GPIO port with event detection support. In the basic port, these bits are reserved, return 0 on read and have no effect on port functionality. Location: Device specific Type: R/W (bit 3 is set only) Bit 7 6 5 4 Event DeEvent PoEvent Type Reserved bounce Enlarity able Name Reset 0 1 Bit 0 0 3 2 1 0 Lock Pull-Up Control Output Type Output Enable 0 1 0 0 Description 7 Reserved. 6 Event Debounce Enable. 0: Disabled 1: Enabled (default) 5 Event Polarity. This bit defines the polarity of the signal that causes a detection of an event from the corresponding GPIO pin (falling/low or rising/high). 0: Falling edge or low-level input (default) 1: Rising edge or high-level input 4 Event Type. This bit defines the signal type that causes a detection of an event from the corresponding GPIO pin. 0: Edge input (default) 1: Level input 3 Lock. This bit locks the corresponding GPIO pin. Once this bit is set to 1 by software, it can only be cleared to 0 by system reset or power-off. Pin multiplexing is functional until the Multiplexing Lock bit is 1. (Refer to the Device Architecture and Configuration chapter.) 0: No effect (default) 1: Direction, output type, pull-up and output value locked 2 Pull-Up Control. This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin. It supports open-drain output signals with internal pull-ups and TTL input signals. 0: Disabled 1: Enabled (default) 1 Output Type. This bit controls the output buffer type (open-drain or push-pull) of the corresponding GPIO pin. 0: Open-drain (default) 1: Push-pull 0 Output Enable. This bit indicates the GPIO pin output state. It has no effect on input. 0: TRI-STATE (default) 1: Output enabled www.national.com 132 6.0 General-Purpose Input/Output (GPIO) Port 6.4.2 (Continued) GPIO Pin Event Routing (GPEVR) Register This is a group of eight identical configuration registers, each of which is associated with one GPIO pin. The entire set is mapped to the PnP configuration space. The mapping scheme is based on the GPSEL register, which functions as an index register and the specific GPER register, which reflects the routing configuration of the currently selected pin. For details on the GPSEL register, refer to the Device Architecture and Configuration chapter. This set of registers is applicable only for the enhanced GPIO port with event detection support. In the basic port, this register set is reserved, returns 0 on read and has no effect on port functionality. Location: Device specific Type: R/W Bit 7 6 Name 5 3 0 0 0 Bit 2 1 0 GPIO Event GPIO Event GPIO Event to PWUREQ to SMI En- to IRQ EnEnable able able Reserved Reset 7-3 4 0 0 0 0 1 Description Reserved. 2 GPIO Event to PWUREQ Enable. This bit is used to enable/disable the routing of the corresponding GPIO detected event to PWUREQ. 0: Disabled (default) 1: Enabled 1 GPIO Event to SMI Enable. This bit is used to enable/disable the routing of the corresponding GIO detected event to SMI. 0: Disabled (default) 1: Enabled 0 GPIO Event to IRQ Enable. This bit is used to enable/disable the routing of the corresponding GPIO detected event to IRQ. 0: Disabled 1: Enabled (default) 6.4.3 GPIO Port Runtime Register Map Offset Device specific1 1 Mnemonic Register Name Type Section GPDO GPIO Data Out R/W 6.4.4 GPDI GPIO Data In RO 6.4.5 specific1 GPEVEN GPIO Event Enable R/W 6.4.6 Device specific1 GPEVST GPIO Event Status R/W1C 6.4.7 Device specific Device 1. The location of this register is defined in the Device Architecture and Configuration chapter in Section 2.16.1. 133 www.national.com 6.0 General-Purpose Input/Output (GPIO) Port 6.4.4 (Continued) GPIO Data Out Register (GPDO) Location: Device specific Type: R/W Bit 7 6 5 4 Name 3 2 1 0 1 1 1 1 Data Out Reset 1 1 1 Bit 1 Description 7 6 5 4 3 2 1 Data Out. Bits 7-0 correspond to pins 7-0, respectively. The value of each bit determines the value driven on the corresponding GPIO pin when its output buffer is enabled. Writing to the bit latches the written data unless the bit is locked by the GPCFG register Lock bit. Reading the bit returns its value regardless of the pin value and configuration. 0: Corresponding pin driven to low when output enabled 1: Corresponding pin driven or released to high (according to buffer type and static pull-up selection) when output enabled 0 6.4.5 GPIO Data In Register (GPDI) Location: Device specific Type: RO Bit 7 6 5 4 Name 3 2 1 0 X X X X Data In Reset X Bit X X X Description 7 6 5 4 3 2 Data In. Bits 7-0 correspond to pins 7-0, respectively. Reading each bit returns the value of the corresponding GPIO pin regardless of the pin configuration and the GPDO register value. Write is ignored. 0: Corresponding pin level low 1: Corresponding pin level high 1 0 www.national.com 134 6.0 General-Purpose Input/Output (GPIO) Port 6.4.6 (Continued) GPIO Event Enable Register (GPEVEN) Location: Device specific Type: R/W Bit 7 6 5 Name 4 3 2 1 0 0 0 0 Event Enable Reset 0 0 0 Bit 0 0 Description 7 6 5 4 3 2 Event Enable. Bits 7-0 correspond to pins 7-0, respectively. Each bit enables system notification triggering by the corresponding GPIO pin. The bit has no effect on the corresponding Status bit in the GPEVST register. 0: IRQ generation by corresponding GPIO pin masked 1: IRQ generation by corresponding GPIO pin enabled 1 0 6.4.7 GPIO Event Status Register (GPEVST) Location: Device specific Type: R/W1C Bit 7 6 5 4 Name Reset Bit 3 2 1 0 0 0 0 0 Status 0 0 0 0 Description 7 6 5 4 3 2 1 Status. Bits 7-0 correspond to pins 7-0, respectively. Each bit is an edge detector that is set to 1 by the hardware upon detection of an active edge (i.e. edge that matches the IRQ Polarity bit) on the corresponding GPIO pin. This edge detection is independent of the Event Type or the Event Enable bit in the GPEVEN register. However, the bit may reflect the event status for enabled, edge-trigger event sources. Writing 1 to the Status bit clears it to 0. 0: No active edge detected since last cleared 1: Active edge detected 0 135 www.national.com 7.0 7.1 WATCHDOG Timer (WDT) OVERVIEW The WATCHDOG Timer prompts the system via SMI or interrupt when no system activity is detected on a predefined selection of system events for a predefined period of time of between 1 and 255 minutes or seconds. The numeric value (1-255) is configured in the WDTO register (WDTO); the time unit used for counting down (minutes or seconds) is configured in the Status register (WDST). The WATCHDOG Timer monitors four maskable system events: the interrupt request lines of the Keyboard, Mouse and the two serial ports (UART1 and UART2). The system prompt is performed by asserting a special-purpose output pin (WDO), which can be attached to external SMI. Alternatively, this indication can be routed to any arbitrary IRQ line and is also available on a status bit that can be read by the host. This chapter describes the generic WATCHDOG Timer functional block. A device may include a different implementation. For device specific implementation, see the Device Architecture and Configuration chapter. 7.2 FUNCTIONAL DESCRIPTION This section describes how the WATCHDOG Timer works. By default, the WATCHDOG Timer counts down in minutes. To change the time unit from minutes to seconds, reconfigure the WDST register as defined in Section 7.4 on page 139. The WATCHDOG Timer consists of an 8-bit counter and three registers: Timeout register (WDTO), Mask register (WDMSK) and Status register (WDST). The counter is an 8-bit down counter that is clocked every minute or second and is used for the timeout period countdown. The WDTO register holds the programmable timeout, which is the period of inactivity after which the WATCHDOG Timer prompts the system (1 to 255 minutes or seconds). The WDMSK register determines which system events are enabled as WATCHDOG Timer trigger events to restart the countdown. The WDST register holds the WATCHDOG Timer status bit that reflects the value of the WDO pin and indicates that the timeout period has expired. In addition, it sets the time unit (minutes or seconds). Figure 22 shows the functionality of the WATCHDOG Timer. Enable Bits Write WDMSK Register Data Bus 1 Minute/Second Clock 3 2 1 0 WDTO Register Keyboard IRQ Load Mouse IRQ Reload Timer Serial Port 1 IRQ Zero Detector Interrupt Serial Port 2 IRQ Status Bit WDO Figure 22. WATCHDOG Timer Functional Diagram Upon reset, the Timeout register (WDTO) is initialized to zero, the timer is deactivated, the WDO is inactive (high) and all trigger events are masked. Upon writing to the WDTO register, the timer is activated while the counter is loaded with the timeout value and starts counting down every minute or second. If a trigger event (unmasked system event) occurs before the counter has expired (reached zero), the counter is reloaded with the timeout period (from WDTO register) and restarts the countdown. If no trigger event occurs before the timeout period expires, the counter reaches zero and stops counting. Consequently, the WDO pin is asserted (pulled low) and the WDO Status bit is cleared to 0. Writing to the WDTO register de-asserts the WDO output (released high) and sets the WDO Status bit to 1. If a non-zero value is written, a new countdown starts as described above. If 00h is written, the timer is deactivated. To summarize, the WDO output is de-asserted (high) and the Status bit is set to 1 (inactive) upon: ● Reset, or ● Activating the WATCHDOG Timer or ● Writing to the WDTO register. The WDO output is asserted (low) and the WDO status is set to zero (active) when the counter reaches zero. When an IRQ is assigned to the WATCHDOG Timer (through the WATCHDOG Timer device configuration), the selected IRQ level is active as long as the WDO status bit is low (active). www.national.com 136 7.0 WATCHDOG Timer (WDT) 7.3 (Continued) WATCHDOG TIMER REGISTERS The WATCHDOG Timer registers, at offsets 00h-02h relative to the WATCHDOG base address, are shown in the following register map. The base address is defined by designated registers in the WATCHDOG Timer device configuration register set. The following abbreviations are used to indicate the Register Type: • R/W = Read/Write. • R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register. • W = Write. • RO = Read Only, • R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. 7.3.1 WATCHDOG Timer Register Map Offset Mnemonic Register Name Section 00h WDTO WATCHDOG Timeout R/W 7.3.2 01h WDMSK WATCHDOG Mask R/W 7.3.3 02h WDST WATCHDOG Status RO 7.3.4 03h 7.3.2 Type Reserved WATCHDOG Timeout Register (WDTO) This register holds the programmable timeout period, which is between 1 and 255 minutes or seconds. Writing to this register de-asserts the WDO output and sets the WDO status bit to 1 (inactive). Additionally, writing to this register is interpreted as a command for starting or stopping the WATCHDOG Timer, according to the data written. If a non-zero value is written, the timer is activated (countdown starts). If a non-zero value is written when the counter is running, the timer is immediately reloaded with the new value and starts counting down from the new value. If 00h is written, the timer and its outputs are deactivated. Location: Offset 00h Type: R/W Bit 7 6 5 Name Reset 4 3 2 1 0 0 0 0 Programmed Timeout Period 0 0 0 0 0 Bit Description 7-0 Programmed Timeout Period. These bits hold the binary value of the timeout period in minutes or seconds (1 to 255). A value of 00h halts the counter and forces the outputs to inactive levels. A device reset clears the register to 00h. 00h: Timer and WDO outputs inactive 01h-FFh: Programmed timeout period (in minutes or seconds) 137 www.national.com 7.0 WATCHDOG Timer (WDT) 7.3.3 (Continued) WATCHDOG Mask Register (WDMSK) This register is used to determine which system events (IRQ) are enabled as WATCHDOG Timer trigger events. An enabled IRQ event becomes a trigger event that causes the timer to reload the WDTO and restart the countdown. This register enables or masks the trigger events that restart the WATCHDOG Timer. Location: Offset 01h Type: R/W Bit 7 6 Name 4 0 Bit 0 3 2 1 Serial Port 2 Serial Port 1 Mouse IRQ IRQ Trigger IRQ Trigger Trigger Enable Enable Enable Reserved Reset 7-4 5 0 0 0 0 0 0 KBD IRQ Trigger Enable 0 Description Reserved. 3 Serial Port 2 IRQ Trigger Enable. This bit enables the IRQ assigned to Serial Port 2 to trigger WATCHDOG Timer reloading. 0: Serial Port 2 IRQ not a trigger event 1: An active Serial Port 2 IRQ enabled as a trigger event 2 Serial Port 1 IRQ Trigger Enable. This bit enables the IRQ assigned to Serial Port 1 to trigger WATCHDOG Timer reloading. 0: Serial Port 1 IRQ not a trigger event 1: An active Serial Port 1 IRQ enabled as a trigger event 1 Mouse IRQ Trigger Enable. This bit enables the IRQ assigned to the Mouse to trigger WATCHDOG Timer reloading. 0: Mouse IRQ not a trigger event 1: An active Mouse IRQ enabled as a trigger event 0 KBD IRQ Trigger Enable. This bit enables the IRQ assigned to the Keyboard to trigger reloading of the WATCHDOG Timer. 0: Keyboard IRQ not a trigger event 1: An active Keyboard IRQ enabled as a trigger event www.national.com 138 7.0 WATCHDOG Timer (WDT) 7.3.4 (Continued) WATCHDOG Status Register (WDST) This register holds the WATCHDOG Timer status, which reflects the value of the WDO pin and indicates that the timeout period has expired. On reset or on WATCHDOG Timer activation, this register is initialized to 01h. Location: Type: Offset 02h RO Bit 7 6 Name Time Unit Reset 0 5 4 Reserved 0 0 0 Bit 7 2 1 0 Time Unit Reserved WDO Value 0 0 1 0 Description Time Unit. 0: Minutes (default) 1: Seconds (see Section 7.4) 6-3 7.4 3 Reserved. 2 Time Unit. 0: Minutes (default) 1: Seconds (see Section 7.4) 1 Reserved. 0 WDO Value. This bit reflects the value of the WDO signal (even if WDO is not configured for output). 0: WDO active 1: WDO inactive (default) COUNTING DOWN IN SECONDS To select seconds (instead of minutes) as the time unit used by the WATCHDOG Timer to countdown: 1. In the WDST register (see Section 7.3.4), write 80h to set bit 7 to ‘1’. 2. In the WDST register, write 84h to set bit 2 to ‘1’. 3. In the WDTO register (see Section Section 7.3.2), set the number of seconds to countdown (in Hexadecimal notation, for example, ‘0A’ is 10 seconds, ‘FF’ is 255 seconds). 7.5 WATCHDOG TIMER REGISTER BITMAP Register Offset Mnemonic 00h WDTO 01h WDMSK 02h WDST Bits 7 6 5 4 3 2 1 0 Programmed Timeout Period Serial Port 2 Serial Port 1 Mouse IRQ KBD IRQ IRQ IRQ Trigger Trigger Trigger Trigger Enable Enable Enable Enable Reserved Time Unit Reserved 139 Time Unit Reserved WDO Value www.national.com 8.0 ACCESS.bus Interface (ACB) The ACB is a two-wire synchronous serial interface compatible with the ACCESS.bus physical layer. The ACB is also compatible with Intel's SMBus and Philips’ I2C. The ACB can be configured as a bus master or slave and can maintain bi-directional communication with both multiple master and slave devices. As a slave device, the ACB may issue a request to become the bus master. The ACB allows easy interfacing to a wide range of low-cost memories and I/O devices, including EEPROMs, SRAMs, timers, ADC, DAC, clock chips and peripheral drivers. This chapter describes the general ACB functional block. A device may include a different implementation. For device specific implementation, see the Device Architecture and Configuration chapter. 8.1 OVERVIEW The ACCESS.bus protocol uses a two-wire interface for bi-directional communication between the devices connected to the bus. The two interface lines are the Serial Data Line (SDL) and the Serial Clock Line (SCL). These lines should be connected to a positive supply via an internal or external pull-up resistor and should remain high even when the bus is idle. Each IC has a unique address and can operate as a transmitter or a receiver (though some peripherals are only receivers). During data transactions, the master device initiates the transaction, generates the clock signal and terminates the transaction. For example, when the ACB initiates a data transaction with an attached ACCESS.bus compliant peripheral, the ACB becomes the master. When the peripheral responds and transmits data to the ACB, their master/slave (data transaction initiator and clock generator) relationship is unchanged, even though their transmitter/receiver functions are reversed. 8.2 8.2.1 FUNCTIONAL DESCRIPTION Data Transactions One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (SCL). Consequently, throughout the clock’s high period, the data should remain stable (see Figure 23). Any changes on the SDA line during the high state of the SCL and in the middle of a transaction aborts the current transaction. New data should be sent during the low SCL state. This protocol permits a single data line to transfer both command/control information and data, using the synchronous serial clock. Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a Stop Condition to terminate the transaction. Each byte is transferred with the most significant bit first. After each byte (8 bits), an Acknowledge signal must follow. The following sections provide further details of this process. During each clock cycle, the slave can stall the master while it handles the received data or prepares new data. This can be done for each bit transferred, or on a byte boundary, by the slave holding SCL low to extend the clock-low period. Typically, slaves extend the first clock cycle of a transfer if a byte read has not yet been stored or if the next byte to be transmitted is not yet ready. Some microcontrollers with limited hardware support for ACCESS.bus extend the access after each bit, thus allowing the software to handle this bit. SDA SCL Data Line Change Stable: of Data Data Valid Allowed Figure 23. Bit Transfer 8.2.2 Start and Stop Conditions The ACCESS.bus master generates Start and Stop Conditions (control codes). After a Start Condition is generated, the bus is considered busy and retains this status for a certain time after a Stop Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition (Figure 24). After a Stop Condition is issued, the data in the received buffer is not valid. In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction. This allows another device to be accessed or a change in the direction of data transfer. www.national.com 140 8.0 ACCESS.bus Interface (ACB) (Continued) SDA SCL S P Start Condition Stop Condition Figure 24. Start and Stop Conditions 8.2.3 Acknowledge (ACK) Cycle The ACK cycle consists of two signals: the ACK clock pulse sent by the master with each byte transferred and the ACK signal sent by the receiving device (see Figure 25). The master generates the ACK clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go high) to allow the receiver to send the ACK signal. The receiver must pull down the SDA line during the ACK clock pulse, signalling that it has correctly received the last data byte and is ready to receive the next byte. Figure 26 illustrates the ACK cycle. Acknowledge Signal From Receiver SDA MSB SCL 2 3-6 1 S 7 8 1 9 ACK 2 3-8 9 ACK Start Condition P Stop Condition Clock Line Held Low by Receiver While Interrupt is Serviced Byte Complete Interrupt Within Receiver Figure 25. ACCESS.bus Data Transaction Data Output by Transmitter Transmitter Stays Off Bus During Acknowledge Clock Data Output by Receiver Acknowledge Signal From Receiver SCL 1 S 2 3-6 7 8 9 Start Condition Figure 26. ACCESS.bus Acknowledge Cycle 141 www.national.com 8.0 ACCESS.bus Interface (ACB) 8.2.4 (Continued) Acknowledge after Every Byte Rule According to this rule, the master generates an acknowledge clock pulse after each byte transfer and the receiver sends an acknowledge signal after every byte received. There are two exceptions to this rule: • When the master is the receiver, it must indicate to the transmitter the end of data by not acknowledging (negative acknowledge) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down. • When the receiver is full or otherwise occupied or if a problem has occurred, the receiver sends a negative acknowledge to indicate that it cannot accept additional data bytes. 8.2.5 Addressing Transfer Formats Each device on the bus has a unique address. Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device should send an acknowledge signal on the SDA line once it recognizes its address. The address consists of the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the address, the eighth bit. A low-to-high transition during a SCL high period indicates the Stop Condition and ends the transaction of SDA (see Figure 27). When the address is sent, each device in the system compares this address with its own. If there is a match, the device considers itself addressed and sends an acknowledge signal. Depending on the state of the R/W bit (1=read, 0=write), the device acts either as a transmitter or a receiver. The I2C bus protocol allows a general call address to be sent to all slaves connected to the bus. The first byte sent specifies the general call address (00h). The second byte specifies the meaning of the general call (for example, write slave address by software only). Those slaves that require data acknowledge the call and become slave receivers; other slaves ignore the call. SDA SCL 1-7 S 8 9 Start Condition Address R/W ACK 1-7 Data 8 9 1-7 ACK Data 9 8 ACK P Stop Condition Figure 27. A Complete ACCESS.bus Data Transaction 8.2.6 Arbitration on the Bus Multiple master devices on the bus require arbitration between their conflicting bus access demands. Control of the bus is initially determined according to address bits and clock cycle. If the masters are trying to address the same slave, data comparisons determine the outcome of this arbitration. In Master mode, the device immediately aborts a transaction if the value sampled on the SDA line differs from the value driven by the device. (An exception to this rule is SDA while receiving data. The lines may be driven low by the slave without causing an abort.) The SCL signal is monitored for clock synchronization and to allow the slave to stall the bus. The actual clock period is set by the master with the longest clock period or by the slave stall period. The clock high period is determined by the master with the shortest clock high period. When an abort occurs during the address transmission, a master that identifies the conflict should give up the bus, switch to Slave mode and continue to sample SDA to check if it is being addressed by the winning master on the bus. www.national.com 142 8.0 ACCESS.bus Interface (ACB) 8.2.7 (Continued) Master Mode Requesting Bus Mastership An ACCESS.bus transaction starts with a master device requesting bus mastership. It asserts a Start Condition followed by the address of the device it wants to access. If this transaction is successfully completed, the software may assume that the device has become the bus master. For the device to become the bus master, the software should perform the following steps: 1. Configure the INTEN bit of the ACBCTL1 register to the desired operation mode (Polling or Interrupt) and set the START bit of this register. This causes the ACB to issue a Start Condition on the ACCESS.bus when the ACCESS.bus becomes free (BB bit of the ACBCST register is cleared or other conditions that can delay start). It then stalls the bus by holding SCL low. 2. If a bus conflict is detected (i.e., another device pulls down the SCL signal), the BER bit of the ACBST register is set. 3. If there is no bus conflict, the MASTER bit of the ACBST register and the SCAST of the ACBST register are set. 4. If the INTEN bit of the ACBCTL1 register is set and either the BER or SDAST bit of the ACBST register is set, an interrupt is issued. Sending the Address Byte When the device is the active master of the ACCESS.bus (the MASTER bit of the ACBST register is set), it can send the address on the bus. The address sent should not be the device’s own address, as defined by the ADDR bit of the ACBADDR register if the SAEN bit of this register is set, nor should it be the global call address if the GCMTCH bit of the ACBCST register is set. To send the address byte, use the following sequence: 1. For a receive transaction where the software wants only one byte of data, set the ACB bit of the ACBCTL1 register. If only an address needs to be sent or if the device requires stall for some other reason, set the STASTRE bit of the ACBCTL1 register. 2. Write the address byte (7-bit target device address) and the direction bit to the ACBSDA register. This causes the ACB to generate a transaction. At the end of this transaction, the acknowledge bit received is copied to the NEGACK bit of the ACBST register. During the transaction, the SDA and SCL lines are continuously checked for conflict with other devices. If a conflict is detected, the transaction is aborted, the BER bit of the ACBST register is set and the MASTER bit of this register is cleared. 3. If the STASTRE bit of the ACBCTL1 register is set and the transaction was successfully completed (i.e., both the BER and NEGACK bits of the ACBST register are cleared), the STASTR bit is set. In this case, the ACB stalls any further ACCESS.bus operations (i.e., holds SCL low). If the INTEN bit of the ACBCTL1 register is set, it also sends an interrupt request to the host. 4. If the requested direction is transmit and the start transaction was completed successfully (i.e., neither the NEGACK nor the BER bit of the ACBST register is set and no other master has accessed the device), the SDAST bit of the ACBST register is set to indicate that the ACB awaits attention. 5. If the requested direction is receive, the start transaction was completed successfully and the STASTRE bit of the ACBCTL1 register is cleared, the ACB starts receiving the first byte automatically. 6. Check that both the BER and NEGACK bits of the ACBST register are cleared. If the INTEN bit of the ACBCTL1 register is set, an interrupt is generated when either the BER or NEGACK bit of the ACBST register is set. Master Transmit After becoming the bus master, the device can start transmitting data on the ACCESS.bus. To transmit a byte in an interrupt or polling controlled operation, the software should: 1. Check that both the BER and NEGACK bits of the ACBST register are cleared and that the SDAST bit of the ACBST register is set. If the STASTRE bit of the ACBCTL1 register is set, also check that the STASTR bit of the ACBST register is cleared (and clear it if required). 2. Write the data byte to be transmitted to the ACBSDA register. When either the NEGACK or BER bit of the ACBST register is set, an interrupt is generated. When the slave responds with a negative acknowledge, the NEGACK bit of the ACBST register is set and the SDAST bit of the ACBST register remains cleared. In this case, if the INTEN bit of the ACBCTL1 register is set, an interrupt is issued. 143 www.national.com 8.0 ACCESS.bus Interface (ACB) (Continued) eive After becoming the bus master, the device can start receiving data on the ACCESS.bus. To receive a byte in an interrupt or polling operation, the software should: 1. Check that the SDAST bit of the ACBST register is set and that the BER bit is cleared. If the STASTRE bit of the ACBCTL1 register is set, also check that the STASTRE bit of the ACBST register is cleared (and clear it if required). 2. Set the ACK bit of the ACBCTL1 register to 1, if the next byte is the last byte that should be read. This causes a negative acknowledge to be sent. 3. Read the data byte from the ACBSDA register. Before receiving the last byte of data, set the ACK bit of the ACBCTL1 register. Master Stop To end a transaction, set the STOP bit of the ACBCTL1 register before clearing the current stall flag (i.e., the SDAST, NEGACK or STASTR bit of the ACBST register). This causes the ACB to send a Stop Condition immediately and to clear the STOP bit of the ACBCTL1 register. A Stop Condition may be issued only when the device is the active bus master (the MASTER bit of the ACBST register is set). Master Bus Stall The ACB can stall the ACCESS.bus between transfers while waiting for the host response. The ACCESS.bus is stalled by holding the SCL signal low after the acknowledge cycle. Note that this is interpreted as the beginning of the following bus operation. The user must make sure that the next operation is prepared before the flag that causes the bus stall is cleared. The flags that can cause a bus stall in Master mode are: ● Negative acknowledge after sending a byte (NEGACK bit of the ACBST register = 1). ● SDAST bit of the ACBST register = 1. ● STASTRE bit of the ACBCTL1 register = 1 after a successful start (STASTR bit of the ACBST register =1). Repeated Start A repeated start is performed when the device is already the bus master (MASTER bit of the ACBST register is set). In this case, the ACCESS.bus is stalled and the ACB awaits host handling due to the following states in the ACBST register: negative acknowledge (NEGACK bit = 1), empty buffer (SDAST bit = 1) and/or a stall after start (STASTR bit = 1). For a repeated start: 1. Set the START bit of the ACBCTL1 register = 1. 2. In Master Receive mode, read the last data item from ACBSDA. 3. Follow the address send sequence, as described in Sending the Address Byte. 4. If the ACB was awaiting handling (STASTR bit of the ACBST register = 1), clear it only after writing the requested address and direction to ACBSDA. Master Error Detection The ACB detects illegal Start or Stop Conditions (i.e., a Start or Stop Condition within the data transfer or the acknowledge cycle) and a conflict on the data lines of the ACCESS.bus. If an illegal condition is detected, BER is set and Master mode is exited (MASTER bit of the ACBST. register is cleared). Bus Idle Error Recovery When a request to become the active bus master or a restart operation fails, the BER bit of the ACBST register is set to indicate the error. In some cases, both the device and the other device may identify the failure and leave the bus idle. In this case, the start sequence may be incomplete and the ACCESS.bus may remain deadlocked. To recover from deadlock, use the following sequence: 1. Clear the BER and BB bits of the ACBCST register. 2. Wait for a timeout period to check that there is no other active master on the bus (the BB bit remains cleared). 3. Disable and re-enable the ACB to put it in the non-addressed Slave mode. This completely resets the functional block. At this point, some of the slaves may not identify the bus error. To recover, the ACB becomes the bus master: it asserts a Start Condition, sends an address byte and then asserts a Stop Condition that synchronizes all the slaves. www.national.com 144 8.0 ACCESS.bus Interface (ACB) 8.2.8 (Continued) Slave Mode A slave device waits in Idle mode for a master to initiate a bus transaction. Whenever the ACB is enabled and is not acting as a master (the MASTER bit of the ACBST register is cleared), it acts as a slave device. Once a Start Condition on the bus is detected, the device checks whether the address sent by the current master matches either: ● The ADDR bit value of the ACBADDR register, if the SAEN bit = 1, or ● The general call address if the GCMEN bit of the ACBCTL1 register = 1. This match is checked even when the MASTER bit is set. If a bus conflict (on SDA or SCL) is detected, the BER bit of the ACBST register is set, the MASTER bit is cleared and the device continues to search the received message for a match. If an address match or a global match is detected: 1. The device asserts its SDA pin during the acknowledge cycle. 2. The MATCH bit of the ACBCST register and the NMATCH bit of the ACBST register are set. If the XMIT bit of the ACBST register is set (Slave Transmit mode), the SDAST bit of the ACBST register is set to indicate that the buffer is empty. 3. If the INTEN bit of the ACBCTL1 register is set, an interrupt is generated the NMINTE bit is also set. 4. The software then reads the XMIT bit of the ACBST register to identify the direction requested by the master device. It clears the NMATCH bit of the ACBST register so future byte transfers are identified as data bytes. Slave Receive and Transmit Slave receive and transmit are performed after a match is detected and the data transfer direction is identified. After a byte transfer, the ACB extends the acknowledge clock until the software reads or writes the ACBSDA register. The receive and transmit sequences are identical to those used in the master routine. Slave Bus Stall When operating as a slave, the device stalls the ACCESS.bus by extending the first clock cycle of a transaction in the following cases: ● SDAST bit of the ACBST register is set. ● NMATCH bit of the ACBST register and NMINTE bit of the ACBCTL1 register are set. Slave Error Detection The ACB detects illegal Start and Stop Conditions on the ACCESS.bus (i.e., a Start or Stop Condition within the data transfer or the acknowledge cycle). When this occurs, the BER bit is set and MATCH and GMATCH are cleared, setting the ACB as an unaddressed slave. 8.2.9 Configuration SDA and SCL Signals The SDA and SCL are open-drain signals. The device permits the user to define whether to enable or disable the internal pull-up of each of these signals. ACB Clock Frequency The ACB permits the user to set the clock frequency for the ACCESS.bus clock. The clock is set by the SCLFRQ field of the ACBCTL2 register, which determines the SCL clock period used by the device. This clock low period may be extended by stall periods initiated by the ACB or by another ACCESS.bus device. In case of a conflict with another bus master, a shorter clock high period may be forced by the other bus master until the conflict is resolved. 145 www.national.com 8.0 ACCESS.bus Interface (ACB) 8.3 (Continued) ACB REGISTERS The following abbreviations are used to indicate the Register Type: • R/W = Read/Write. • R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register. • W = Write. • RO = Read Only. • R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. 8.3.1 ACB Register Map Offset Mnemonic 8.3.2 Register Name Type Section 00h ACBSDA ACB Serial Data R/W 8.3.2 01h ACBST ACB Status Varies per bit 8.3.3 02h ACBCST ACB Control Status Varies per bit 8.3.4 03h ACBCTL1 ACB Control 1 R/W 8.3.5 04h ACBADDR ACB Own Address R/W 8.3.6 05h ACBCTL2 R/W 8.3.7 ACB Control 2 ACB Serial Data Register (ACBSDA) This shift register is used to transmit and receive data. The most significant bit is transmitted (received) first and the least significant bit is transmitted (received) last. Reading or writing to the ACBSDA register is allowed only when the SDAST bit of the ACBST register is set or for repeated starts after setting the START bit. An attempt to access this register under other conditions may produce unpredictable results. Location: Offset 00h Type: R/W Bit Name 7 6 5 4 ACB Serial Data Reset www.national.com 3 146 2 1 0 8.0 ACCESS.bus Interface (ACB) 8.3.3 (Continued) ACB Status Register (ACBST) This register maintains the current ACB status. On reset, and when the ACB is disabled, ACBST is cleared (00h). Location: Offset 01h Type: Varies per bit Bit 7 6 5 4 3 2 1 0 Name SLVSTP SDAST BER NEGACK STASTR NMATCH MASTER XMIT Reset 0 0 0 0 0 0 0 0 Bit 7 6 Type Description R/W1C SLVSTP (Slave Stop). Writing 0 to SLVSTP is ignored. 0: Writing 1 or ACB disabled 1: Stop Condition detected after a slave transfer in which MATCH or GCMATCH was set RO SDAST (SDA Status). 0: Reading from the ACBSDA register during a receive or when writing to it during a transmit. When ACBCTL1.START is set, reading the ACBSDA register does not clear SDAST. This enables ACB to send a repeated start in Master Receive mode. 1: SDA Data register awaiting data (transmit - master or slave) or holds data that should be read (receive - master or slave). 5 R/W1C BER (Bus Error). Writing 0 to BER is ignored. 0: Writing 1 or ACB disabled 1: Start or Stop Condition detected during data transfer (i.e., Start or Stop Condition during the transfer of bits 2 through 8 and acknowledge cycle) or when an arbitration problem is detected. 4 R/W1C NEGACK (Negative Acknowledge). Writing 0 to NEGACK is ignored. 0: Writing 1 or ACB disabled 1: Transmission not acknowledged on the ninth clock (In this case, SDAST is not set) 3 R/W1C STASTR (Stall After Start). Writing 0 to STASTR is ignored. 0: Writing 1 or ACB disabled 1: Address sent successfully (i.e., a Start Condition sent without a bus error or Negative Acknowledge), if ACBCTL1.STASTRE is set. This bit is ignored in Slave mode. When STASTR is set, it stalls the ACCESS.bus by pulling down the SCL line and suspends any further action on the bus (e.g., receive of first byte in Master Receive mode). In addition, if ACBCTL1.INTEN is set, it also causes the ACB to send an interrupt. 2 R/W1C NMATCH (New Match). Writing 0 to NMATCH is ignored. If ACBCTL1.INTEN is set, an interrupt is sent when this bit is set. 0: Software writes 1 to this bit 1: Address byte follows a Start Condition or a repeated start, causing a match or a global-call match. 1 RO Master. 0: Arbitration loss (BER is set) or recognition of a Stop Condition 1: Bus master request succeeded and Master mode active 0 RO XMIT (Transmit). Direction bit. 0: Master/Slave Transmit mode not active 1: Master/Slave Transmit mode active 147 www.national.com 8.0 ACCESS.bus Interface (ACB) 8.3.4 (Continued) ACB Control Status Register (ACBCST) This register configures and controls the ACB functional block. It maintains the current ACB status and controls several ACB functions. On reset and when the ACB is disabled, the non-reserved bits of ACBCST are cleared. Location: Offset 02h Type: Varies per bit Bit 7 Name Reserved Reset Bit 6 0 Type 7-6 0 5 4 3 2 1 0 TGSCL TSDA GCMTCH MATCH BB BUSY 0 X 0 0 0 0 Description Reserved. 5 R/W TGSCL (Toggle SCL Line). Enables toggling the SCL line during error recovery. 0: Clock toggle completed 1: When the SDA line is low, writing 1 to this bit toggles the SCL line for one cycle. Writing 1 to TGSCL while SDA is high is ignored 4 RO TSDA (Test SDA Line). This bit reads the current value of the SDA line. It can be used while recovering from an error condition in which the SDA line is constantly pulled low by an out-of-sync slave. Data written to this bit is ignored. 3 RO GCMTCH (Global Call Match). 0: Start Condition or repeated Start and a Stop Condition (including illegal Start or Stop Condition) 1: In Slave mode, ACBCTL1.GCMEN is set and the address byte (the first byte transferred after a Start Condition) is 00h 2 RO MATCH (Address Match). 0: Start Condition or repeated Start and a Stop Condition (including illegal Start or Stop Condition) 1: ACBADDR.SAEN is set and the first seven bits of the address byte (the first byte transferred after a Start Condition) match the 7-bit address in the ACBADDR register 1 R/W1C BB (Bus Busy). 0: Writing 1, ACB disabled or Stop Condition detected 1: Bus active (a low level on either SDA or SCL) or Start Condition 0 RO www.national.com Busy. This bit should always be written 0. This bit indicates the period between detecting a Start Condition and completing receipt of the address byte. After this, the ACB is either free or enters Slave mode. 0: Completion of any state below or ACB disabled 1: ACB is in one of the following states: — Generating a Start Condition — Master mode (ACBST.MASTER is set) — Slave mode (ACBCST.MATCH or ACBCST.GCMTCH set) 148 8.0 ACCESS.bus Interface (ACB) 8.3.5 (Continued) ACB Control Register 1 (ACBCTL1) Location: Offset 03h Type: R/W Bit 7 6 5 4 3 2 1 0 Name STASTRE NMINTE GCMEN ACK Reserved INTEN STOP START Reset 0 0 0 0 0 0 0 0 Bit Description 7 STASTRE (Stall After Start Enable). 0: When cleared, ACBST.STASTR can not be set. However, if ACBST.STASTR is set, clearing STASTRE will not clear ACBST.STASTR. 1: Stall after start mechanism enabled; ACB stalls the bus after the address byte 6 NMINTE (New Match Interrupt Enable). 0: No interrupt issued on a new match 1: Interrupt issued on a new match only if ACBCTL1.INTEN set 5 GCMEN (Global Call Match Enable). 0: ACB not responding to global call 1: Global call match enabled 4 Receive Acknowledge. This bit is ignored in Transmit mode. When the device acts as a receiver (slave or master), this bit holds the stop transmitting instruction that is transmitted during the next acknowledge cycle. 0: Cleared after acknowledge cycle 1: Negative acknowledge issued on next received byte 3 Reserved. 2 Interrupt Enable. 0: ACB interrupt disabled 1: ACB interrupt enabled. An interrupt is generated in response to one of the following events: — Detection of an address match (ACBST.NMATCH=1) and NMINTE=1 — Receipt of Bus Error (ACBST.BER=1) — Receipt of Negative Acknowledge after sending a byte (ACBST.NEGACK=1) — Acknowledge of each transaction (same as the hardware set of the ACBST.SDAST bit) — In Master mode if ACBCTL1.STASTRE=1, after a successful start (ACBST.STASTR=1) — Detection of a Stop Condition while in Slave mode (ACBST.SLVSTP=1) 1 Stop. 0: Automatically cleared after STOP issued 1: Setting this bit in Master mode generates a Stop Condition to complete or abort current message transfer 0 Start. Set this bit only when in Master mode or when requesting Master mode. 0: Cleared after Start Condition sent or Bus Error (ACBST.BER=1) detected 1: Single or repeated Start Condition generated on the ACCESS.bus. If the device is not the active master of the bus (ACBST.MASTER=0), setting START generates a Start Condition when the ACCESS.bus becomes free (ACBCST.BB=0). An address transmission sequence should then be performed. If the device is the active master of the bus (ACBST.MASTER=1), setting START and then writing to the ACBSDA register generates a Start Condition. If a transmission is already in progress, a repeated Start Condition is generated. This condition can be used to switch the direction of the data flow between the master and the slave or to choose another slave device without separating them with a Stop Condition. 149 www.national.com 8.0 ACCESS.bus Interface (ACB) 8.3.6 (Continued) ACB Own Address Register (ACBADDR) This is a byte-wide register that holds the ACB ACCESS.bus address. The reset value of this register is undefined. Location: Offset 04h Type: R/W Bit 7 Name 6 5 4 SAEN 3 2 1 0 ADDR Reset Bit 7 6-0 8.3.7 Description SAEN (Slave Address Enable). 0: ACB does not check for an address match with ADDR field 1: ADDR field holds a valid address and enables the match of ADDR to an incoming address byte ADDR (Own Address). These bits hold the 7-bit device address. When in Slave mode, the first seven bits received after a Start Condition are compared with this field (the first bit received is compared with bit 6 and the last bit with bit 0). If the address field matches the received data and SAEN (bit 7) is 1, a match is declared. ACB Control Register 2 (ACBCTL2) This register enables/disables the functional block and determines the ACB clock rate. Location: Offset 05h Type: R/W Bit 7 6 5 Name 4 3 2 1 SCLFRQ Reset 0 0 0 0 0 ENABLE 0 0 0 0 Bit Description 7-1 SCLFRQ (SCL Frequency). This field defines the SCL period (low and high time) when the device serves as a bus master. The clock low and high times are defined as follows: tSCLl = tSCLh = 2*SCLFRQ*tCLK where tCLK is the module input clock cycle, as defined in the Device Architecture and Configuration chapter. SCLFRQ can be programmed to values in the range of 00010002 (810) through 11111112 (12710). Using any other value has unpredictable results. 0 Enable. 0: ACB disabled, ACBCTL1, ACBST and ACBCST cleared and clocks halted 1: ACB enabled www.national.com 150 8.0 ACCESS.bus Interface (ACB) 8.4 (Continued) ACB REGISTER BITMAP Register Bits Offset Mnemonic 7 6 00h ACBSDA 01h ACBST 02h ACBCST 03h ACBCTL1 STASTRE 04h ACBADDR SAEN 05h ACBCTL2 5 4 3 2 1 0 ACB Serial Data SLVSTP SDAST Reserved NMINTE BER NEGACK STASTR NMATCH MASTER XMIT TGSCL TSDA GCMTCH MATCH BB BUSY GCMEN ACK Reserved INTEN STOP START ADDR SCLFRQ 151 ENABLE www.national.com 9.0 9.1 Voltage Level Monitor (VLM) OVERVIEW The Voltage Level Monitor (VLM) is an A/D converter that monitors various voltages in the system, reports their values to system monitoring software and can set an alarm when any of these voltages is outside a specified range. The VLM conforms to LDCM and DMI requirements for system monitoring. The VLM can sense up to 10 voltage values. Seven sources are external and can be applied per system requirements. Four values are internal and used for VSB, VDD, VBAT and AVDD. VSB, VDD and AVDD are internally divided by 2 to allow detection of voltage both over and under the specified range. The host can query the various voltage readout values and configure the VLM to generate an ALARM signal when the voltage is outside a specified range (below ViLOW or above ViHIGH, where i is the channel number). The ALARM can generate an interrupt internally. 9.2 FUNCTIONAL DESCRIPTION The VLM incorporates an 8-bit A/D converter and a set of control, configuration and status registers and digital circuitry that controls its operation. Figure illustrates the structure of the VLM module. The VLM measures the various input voltages periodically, as defined by the conversion rate setting (see Section 9.5.9). At the beginning of each period, a measurement trigger is issued, which starts a burst of conversion operations. The burst includes scanning all enabled channels starting from channel 0. To guarantee the stability of the signal at the input of the A/D converter, a delay is added between the end of each conversion and the beginning of the next. The delay between samples should be adjusted according to the resistance and capacitance of the input source. See Section 9.7.1 for information on how to calculate the sampling delay; see Section 9.5.9 for the associated programing model. The voltage readout is an unsigned integer between 0 and 255. Section 9.2.1 describes how the readout is converted to a voltage value. The VLM is designed to preserve indication of failures by disabling the conversion whenever the SLPS3 input becomes active (i.e., VDD is expected to drop) and whenever an error is detected. The conversion and register updates resume only after power is restored and normal system operation resumes. To prevent loss of error condition flagging, the conversions for voltage measurement channels that are out of range are stopped until the ALARM status is cleared. Whenever SLPS3 is not available in the system, the SLPS3 input should be tied to 1 and the software should disable the measurements before the power fails or ignore and clear any pending error flags after power is restored. www.national.com 152 9.0 Voltage Level Monitor (VLM) AVI0 VIN0 AVI6 VLM VSB Power 11:1 Analog MUX A/D Converter A/D Converter Control Logic Internal Bus VSB VDD VBAT AVDD VIN6 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 (Continued) Status, Data & Config Registers VREF Analog Power 3.3V AVDD *(2.45 Internal ±0.05) VREF Start Delay REF Clock Divider Clock + AVss Low + Alarm Enable and Configuration Logic High ALARM IRQ SMI Figure 28. VLM Functional Diagram 9.2.1 Voltage Measurement, Channels 0 through 10 Voltage is measured relative to (2.45±0.05)*VREF (where VREF is the voltage of the VREF input or the internal reference voltage). The results are output to the Read Channel Voltage (RDCHV) register associated with the channel. The voltage measured is: Vi = (2.45±0.05)*VREF *RDCHVi / 256 VSB, VDD and AVDD are internally divided by two. Therefore, the readouts are half their actual values. When external dividers are used to scale input voltage to within the dynamic range of the A/D Converter, appropriate scale factors should be taken into account. VHIGH and VLOW Limits, ALARM Output, IRQ and SMI The voltage reading is compared to two limits: VHIGH and VLOW. If the voltage reading is outside any of these limits, the respective status bit (Channel High Limit Exceeded or Channel Low Limit Exceeded) in the VCHCFST register is set. The status bit stays active until it is cleared by the software. An ALARM status bit in the VEVSTS0 or VEVSTS1 register is set when the Channel High Limit Exceeded or the Channel Low Limit Exceeded bit for the respective channel is set. The ALARM output is used to indicate to the system that a voltage outside the high/low limits was detected. The ALARM output Enable bit in the VCHCFST register enables the ALARM output to be active when the Channel High Limit Exceeded or the Channel Low Limit Exceeded status bit in the VCHCFST register is set. The SMI output generates an interrupt if any enabled SMI event occurs. Each bit in the VEVSTS0/1 register has a corresponding SMI Enable bit in the VEVSMI0/1 register. When any status bit and its corresponding SMI Enable bit are set, the SMI output is active. The IRQ output generates an interrupt if any enabled IRQ event occurs. Each bit in the VEVSTS0/1 register has a corresponding IRQ Enable bit in the VEVIRQ0/1 register. When any status bit and its corresponding IRQ Enable bit are set, the IRQ output is active. 153 www.national.com 9.0 Voltage Level Monitor (VLM) (Continued) Alarm Response Read Sequence When the VLM activates the ALARM output, the host should respond by reading the VEVSTS0 and VEVSTS1 registers. It should then access the register of each of the channels whose bit is set in the VEVSTS0 and VEVSTS1 registers and clear these bits by writing 1 to each of them. 9.2.2 Power-On Reset Default States VLM power-on default conditions are: • • All registers are loaded with their default values. The ALARM output, IRQ and SMI are disabled. 9.2.3 Standby Mode Standby mode is enabled by setting the Standby Mode Enable bit in the VLMCFG register. Standby mode reduces power supply current by disabling new measurements, but register values are retained and the registers can be accessed by software (as usual). 9.3 ANALOG SUPPLY CONNECTION 9.3.1 Recommendations Power is supplied to the analog parts of the A/D Converter through two dedicated analog power pins: AVDD and AVSS. This ensures effective isolation of the analog parts from noise caused by the digital parts. The digital parts of the VLM are supplied via VSB. To obtain the best performance, bear in mind the following recommendations (see also details in Figure 29). Ground Connection. The analog ground pin, AVSS, should be connected at only one point to the digital ground pins. At this point, the following ground connections should also be made: • • • • The decoupling capacitors of the analog supply AVDD pin. The reference voltage VREF pin. The four digital supply VSB pins. The ground reference of the input signals to the A/D Converter. Low-impedance ground layers also improve noise isolation. Power Connection. The analog supply pin, AVDD, should be connected to a low-noise power supply, 3.3V. It is recommended to supply the AVDD pin through an external LC or RC filter. An example of an RC filter [R1 and (C2+C3)] is shown in Figure 29. Decoupling Capacitors. The following decoupling capacitors should be used: • Digital VSB: Place one capacitor of 0.1 µF on each VSB pin as close as possible to the pin (4 x C4). Also, place one 1047 µF tantalum capacitor (C5) on the common net as close as possible to the chip. • Analog AVDD: Place a 0.1 µF capacitor and a 10-47 µF tantalum capacitor on the AVDD pins (C3 and C2) as close as possible to the pin. • VREF: Place a low-leakage, non-polarized, 0.47 µF capacitor (C1) as close as possible to the VREF pin. www.national.com 154 9.0 Voltage Level Monitor (VLM) (Continued) Analog Power Power Supply R1 10 Ω 3.3 V AD0 AD6 VIN VREF VREF C1 0.47 µF + C2 22 C3 0.1 µF µF AD0 AD6 VREF AVDD VSB AVSS GND Analog Ground Layer + C4 0.1 µF C5 22 µF Digital Ground Layer Figure 29. Analog Power Supply 9.3.2 Reference Voltage Analog input voltage is measured relative to (2.45±0.05)*VREF. VREF may be either internal or external. When an internal VREF is used, a capacitor should be connected between the VREF pin and AVSS. The VREF default setting is for external. This default prevents contention between the internal and external VREF. Note that the VREF setting is common to both the VLM and the TMS modules. If either of these modules is configured to use internal reference voltage, the internal reference voltage is used by both modules. 9.4 REGISTER BANK OVERVIEW The VLM uses register banks to enable host access to its registers. The VLM has 10 common registers in addition to four registers that are located in each of the 10 banks. The common registers include configuration and status information common to all the channels. Each of the banks is associated with one channel and holds its readout, configuration and status information. All registers use the same 16-byte address space to indicate offsets 00h through 0Fh. The active bank must be selected by the software. The VLM Bank Selection (VLMBS) register, which is common to all banks, selects the active banks (see Figure 30). The default bank selection after system reset is 0. } Offset 00h . . . Common Registers for All Banks Offset 08h VLMBS (09h) Offset 0Ah Offset 0Bh BANK 10 Offset 0Eh Offset 0Fh BANK 1 BANK 0 Figure 30. Register Bank Architecture 155 www.national.com 9.0 Voltage Level Monitor (VLM) 9.5 (Continued) VLM REGISTERS The register maps in this chapter use the following abbreviations for Type: • R/W = Read/Write. • R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register. • W = Write. • RO = Read Only. • R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. 9.5.1 VLM Register Map Table 48. VLM Control and Status Register Map Offset Mnemonic Register Name Type Section 00h VEVSTS0 Voltage Event Status 0 RO 9.5.2 01h VEVSTS1 Voltage Event Status 1 RO 9.5.3 02h VEVSMI0 Voltage Event to SMI 0 R/W 9.5.4 03h VEVSMI1 Voltage Event to SMI 1 R/W 9.5.5 04h VEVIRQ0 Voltage Event to IRQ 0 R/W 9.5.6 05h VEVIRQ1 Voltage Event to IRQ 1 R/W 9.5.7 06h VID Voltage ID Varies per bit 9.5.8 07h VCNVR Voltage Conversion Rate R/W 9.5.9 08h VLMCFG VLM Configuration R/W 9.5.10 09h VLMBS VLM Bank Select R/W 9.5.11 Table 49. VLM Channel Register Map (One per Channel) Offset Mnemonic Register Name Type Section Varies per bit 9.5.12 0Ah VCHCFST Voltage Channel Configuration and Status 0Bh RDCHV Read Channel Voltage RO 9.5.13 0Ch CHVH Channel Voltage High Limit R/W 9.5.14 0Dh CHVL Channel Voltage Low Limit R/W 9.5.15 0EhReserved 0Fh www.national.com 156 9.0 Voltage Level Monitor (VLM) 9.5.2 (Continued) Voltage Event Status Register 0 (VEVSTS0) This register indicates which of the corresponding eight VLM events has occurred. Location: Offset 00h Type: RO Bit 7 6 5 4 3 2 1 0 Name VSB ALARM Event Status AVI6 ALARM Event Status AVI5 ALARM Event Status AVI4 ALARM Event Status AVI3 ALARM Event Status AVI2 ALARM Event Status AVI1 ALARM Event Status AVI0 ALARM Event Status Reset 0 0 0 0 0 0 0 0 Bit 7 Description VSB ALARM Event Status. This channel measures the internal VSB power, using VSB/2. 0: Voltage level within limits (default) 1: High or low limit exceeded 6-0 Analog Voltage Inputs 6-0 ALARM Event Status. 0: Voltage level within limits (default) 1: High or low limit exceeded 9.5.3 Voltage Event Status Register 1 (VEVSTS1) This register indicates which of the corresponding VLM events has occurred. Location: Offset 01h Type: RO Bit 7 6 Name Reset 5 4 3 Reserved 0 Bit 0 0 0 0 2 1 0 AVDD ALARM Event Status VBAT ALARM Event Status VDD ALARM Event Status 0 0 0 Description 7-3 Reserved. 2 AVDD ALARM Event Status. This channel measures the internal AVDD power, using AVDD/2. 0: Voltage level within limits (default) 1: High or low limit exceeded 1 VBAT ALARM Event Status. This channel measures the VBAT power input. 0: Voltage level within limits (default) 1: High or low limit exceeded 0 VDD ALARM Event Status. This channel measures the internal VDD power, using VDD/2. 0: Voltage level within limits (default) 1: High or low limit exceeded 157 www.national.com 9.0 Voltage Level Monitor (VLM) 9.5.4 (Continued) Voltage Event to SMI Register 0 (VEVSMI0) This register is one of two registers that controls event routing to SMI. Location: Offset 02h Type: R/W Bit 7 6 5 4 3 2 1 0 VSB Event AVI6 Event AVI5 Event AVI4 Event AVI3 Event AVI2 Event AVI1 Event AVI0 Event to SMI to SMI to SMI to SMI to SMI to SMI to SMI to SMI Enable Enable Enable Enable Enable Enable Enable Enable Name Reset 0 0 Bit 7 0 0 Description VSB Event to SMI Enable. 0: Disabled (default) 1: Enabled 6-0 AVI6-0 Event to SMI Enable. 0: Disabled (default) 1: Enabled www.national.com 158 0 0 0 0 9.0 Voltage Level Monitor (VLM) 9.5.5 (Continued) Voltage Event to SMI Register 1 (VEVSMI1) This register is one of two registers that controls event routing to SMI. Location: Offset 03h Type: R/W Bit 7 6 Name 5 4 3 0 0 Bit 0 1 0 AVDD Event VBAT Event VDD Event to SMI to SMI to SMI Enable Enable Enable Reserved Reset 2 0 0 0 0 0 Description 7-3 Reserved. 2 AVDD Event to SMI Enable. 0: Disabled (default) 1: Enabled 1 VBAT Event to SMI Enable. 0: Disabled (default) 1: Enabled 0 VDD Event to SMI Enable. 0: Disabled (default) 1: Enabled 159 www.national.com 9.0 Voltage Level Monitor (VLM) 9.5.6 (Continued) Voltage Event to IRQ Register 0 (VEVIRQ0) This register is one of two registers that controls event routing to IRQ. Location: Offset 04h Type: R/W Bit 7 6 5 4 3 2 1 0 VSB Event AVI6 Event AVI5 Event AVI4 Event AVI3 Event AVI2 Event AVI1 Event AVI0 Event to IRQ to IRQ to IRQ to IRQ to IRQ to IRQ to IRQ to IRQ Enable Enable Enable Enable Enable Enable Enable Enable Name Reset 0 0 0 Bit 7 0 0 0 0 0 3 2 1 0 Description VSB Event to IRQ Enable. 0: Disabled (default) 1: Enabled 6-0 AVI6-0 Event to IRQ Enable. 0: Disabled (default) 1: Enabled 9.5.7 Voltage Event to IRQ Register 1 (VEVIRQ1) This register is one of two registers that controls routing to IRQ. Location: Offset 05h Type: R/W Bit 7 6 Name 5 4 AVDD Event VBAT Event VDD Event to IRQ to IRQ to IRQ Enable Enable Enable Reserved Reset 0 0 Bit 0 0 0 Description 7-3 Reserved. 2 AVDD Event to IRQ Enable. 0: Disabled (default) 1: Enabled 9.5.8 1 VBAT Event to IRQ Enable. 0: Disabled (default) 1: Enabled 0 VDD Event to IRQ Enable. 0: Disabled (default) 1: Enabled Voltage ID Register (VID) This register indicates the configuration of the power supply regulator for the CPU(s). www.national.com 160 0 0 0 9.0 Voltage Level Monitor (VLM) Location: Offset 06h Type: Varies per bit Bit 7 Name 6 CPU VID Select Reset 0 Bit Type 0 (Continued) 5 4 3 Reserved 0 2 1 0 X X VID Value X X X Description 7-6 R/W CPU Voltage ID Select. This field selects which of the CPUs’ VID pins is read in the Voltage ID Value field. Bits 7 6 Voltage ID 00 CPU0 (default) 01 CPU1 Other Reserved 5 4-0 Reserved. RO Voltage ID Value. Returns the current value of the VID inputs selected by the CPU VID Select field. The pins used for the VID field are defined by VID0 and VID1 Route Select bits of the SuperI/O Configuration 5 register (See Section 2.9.6). 161 www.national.com 9.0 Voltage Level Monitor (VLM) 9.5.9 (Continued) Voltage Conversion Rate Register (VCNVR) This register indicates time related specification for the VLM. Location: Offset 07h Type: R/W Bit 7 Name 6 5 Reserved Reset 0 4 3 2 Channel Delay 0 Bit 0 0 1 0 Conversion Period 0 0 0 0 Description 7-6 Reserved. 5-3 Channel Delay. These bits define the sampling delay. The sampling delay helps guarantee the accuracy of the sampled value when switching from one channel to another. Bits 5 4 3 Delay (µsec) 0 0 0 40 (default) 0 0 1 80 0 1 0 160 Others Reserved 2-0 Conversion Period. These bits define the period of time between reconversions of all enabled channels. VBAT (channel 9) is converted at the first of every 1024 conversion periods. Bits 2 1 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 Others www.national.com Conversion Period 2 seconds (default) 1 second 0.5 seconds 0.1 seconds 0.05 seconds 0.02 seconds Reserved 162 9.0 Voltage Level Monitor (VLM) (Continued) 9.5.10 VLM Configuration Register (VLMCFG) This register selects the channels and sets global configuration (not channel specific) values. Location: Offset 08h Type: R/W Bit 7 6 5 Name 4 3 2 Reserved Reset 0 0 0 Bit 0 0 1 0 External VREF Standby Mode Enable 1 1 0 Description 7-2 Reserved. 1 External VREF. This bit selects either the internal or external reference voltage as a reference for the A/D Converter. Note that if either the VLM or TMS specify the use of an internal VREF, the internal VREF will be used by both these modules. 0: Internal VREF in use 1: External VREF in use (default) 0 Standby Mode Enable. 0: Monitoring operation enabled 1 Standby mode enabled (default) 9.5.11 VLM Bank Select Register (VLMBS) This register selects a bank and its associated channels. Location: Offset 09h Type: R/W Bit 7 Name Reset 6 5 4 3 Reserved 0 Bit 0 2 1 0 0 0 Bank Select Value 0 0 0 0 Description 7-5 Reserved. 4-0 Bank Select Value. These bits contain the binary value that selects a bank and its associated channels for configuration and viewing. 4 3 2 1 0 Bank Function 0 0 0 0 0 0 Channel 0 (default) 0 0 0 0 1 1 Channel 1 ...... 0 1 0 1 0 10 Channel 10 Other Reserved 163 www.national.com 9.0 Voltage Level Monitor (VLM) (Continued) 9.5.12 Voltage Channel Configuration and Status Register (VCHCFST) This register indicates the current channel status. Location: Offset 0Ah - Banks 0 through 10 Type: Varies per bit Bit 7 Name End of Conversion Reset 0 Bit 7 5 Reserved 0 0 3 2 1 0 ALARM Output Enable Reserved Channel High Limit Exceeded Channel Low Limit Exceeded Channel Enable 0 0 0 0 0 Description RW1C End of Conversion. This bit indicates that the RDCHV register (see next page) holds new data. It is set when new data is written into RDCHV as a result of completing a conversion for this channel. It is cleared by writing 1 to this bit. 0: No new data (default) 1: New data not yet read Reserved. R/W ALARM Output Enable. 0: Disabled (default) 1: Enabled 3 Reserved. 2 RW1C Channel High Limit Exceeded. 0: Voltage lower than limit (default) 1: Voltage higher than limit 1 RW1C Channel Low Limit Exceeded. 0: Voltage higher than limit (default) 1: Voltage lower than limit 0 4 Type 6-5 4 6 R/W Channel Enable. 0: Disabled (default) 1: Enabled www.national.com 164 9.0 Voltage Level Monitor (VLM) (Continued) 9.5.13 Read Channel Voltage Register (RDCHV) This register holds the last voltage readout for each channel. The value is an 8-bit unsigned integer of the voltage measured by the channel. Location: Offset 0Bh - Banks 0 to 10 Type: RO Bit 7 6 5 4 Name 3 2 1 0 0 0 0 2 1 0 1 1 1 2 1 0 0 0 0 Channel Voltage Value Reset 0 0 0 0 0 9.5.14 Channel Voltage High Limit Register (CHVH) This register holds the voltage high limit value that is compared with the voltage reading. Location: Offset 0Ch - Banks 0 through 10 Type: R/W Bit 7 6 5 Name 4 3 Channel Voltage High Limit Value Reset 1 1 1 1 1 9.5.15 Channel Voltage Low Limit Register (CHVL) This register holds the voltage low limit value that is compared with the voltage reading. Location: Offset 0Dh - Banks 0 through 10 Type: R/W Bit 7 6 5 Name Reset 4 3 Channel Voltage Low Limit Value 0 0 0 0 165 0 www.national.com 9.0 Voltage Level Monitor (VLM) 9.6 (Continued) VLM REGISTER BITMAP 9.6.1 VLM Control and Status Registers Register Offset Mnemonic 00h VEVSTS0 01h VEVSTS1 02h VEVSMI0 03h VEVSMI1 04h VEVIRQ0 Bits 7 6 5 4 3 2 1 0 VSB ALARM Event Status AVI6 ALARM Event Status AVI5 ALARM Event Status AVI4 ALARM Event Status AVI3 ALARM Event Status AVI2 ALARM Event Status AVI1 ALARM Event Status AVI0 ALARM Event Status AVDD ALARM Event Status VBAT ALARM Event Status VDD ALARM Event Status Reserved VSB Event AVI6 Event AVI5 Event AVI4 Event AVI3 Event AVI2 Event AVI1 Event AVI0 Event to SMI to SMI to SMI to SMI to SMI to SMI to SMI to SMI Enable Enable Enable Enable Enable Enable Enable Enable Reserved VBAT Event to SMI Enable VDD Event to SMI Enable VSB Event AVI6 Event AVI5 Event AVI4 Event AVI3 Event AVI2 Event AVI1 Event AVI0 Event to IRQ to IRQ to IRQ to IRQ to IRQ to IRQ to IRQ to IRQ Enable Enable Enable Enable Enable Enable Enable Enable 05h VEVIRQ1 06h VID CPU VID Select 07h VCNVR Reserved 08h VLMCFG 09h VLMBS 9.6.2 AVDD Event to SMI Enable Reserved AVDD Event to IRQ Enable Reserved VID Value Channel Delay VBAT Event to IRQ Enable VDD Event to IRQ Enable Conversion Period External VREF Reserved Reserved Standby Mode Enable Bank Select Value VLM Channel Registers Register Offset Mnemonic Bits 7 0Ah End of (Bank VCHCFST Conversion 0-10) 0Bh (Bank 0-10) RDCHV www.national.com 6 5 Reserved 4 3 2 1 0 ALARM Output Enable Reserved Channel High Limit Exceeded Channel Low Limit Exceeded Channel Enable Channel Voltage Value 166 9.0 Voltage Level Monitor (VLM) (Continued) Register Bits 0Ch (Bank 0-10) CHVH Channel Voltage High Limit Value 0Dh (Bank 0-10) CHVL Channel Voltage Low Limit Value 0Eh0Fh 9.7 9.7.1 Reserved USAGE HINTS Calculating the Channel Delay The channel delay is the interval between the time a new channel is selected and the time the channel voltage can be measured. The reason for this delay is to allow the voltage to charge all internal capacitors to guarantee accuracy of the measurement. This delay period depends on characteristics of the input (resistance and capacitance) and of the external circuit. Figure 31 shows the schematic of the input and its equivalent R-C circuit. The sampling time should be long enough to guarantee that the voltage settles on the capacitor CS. The voltage on CS should be stable before the measurement starts. The RAIN and CAIN values represent the input path serial resistance and parallel capacitance. RAIN is the serial resistance of the multiplexer, Sample & Hold switch and other parasitic resistors. CAIN is the parallel capacitance of the input pin, pad, leadframe, CS, etc. The required sampling time is determined by RAIN and CAIN together with the input source resistance RSOURCE and parasitic capacitance CP. Table 50 can be used as a reference for calculating the sample time. Channel Delay of the VCNVR register should be programmed accordingly. RSOURCE VIN Input Signal CP is the parasitic capacitor including the external elements (PCB capacitance etc.). AD0 AD1 AD2 AD3 AD4 AD5 AD6 Analog MUX RAIN is the equivalent serial resistance of all serial elements inside the chip (pin, bonding, MUX, Sample & Hold switch, layout). CS is the sampling capacitor. Cs CAIN is the equivalent parallel capacitance of the chip parasitic capacitances and the CS capacitor. RSOURCE VIN RAIN CP CAIN Figure 31. Analog Input Schematic Diagram and Equivalent R-C Circuit Table 50. Delay Setting Example External Elements Delay Time (ns) RSOURCE [KΩ] CP [pF] 5 0.1 15 1 110 10 900 30 3200 167 www.national.com 9.0 Voltage Level Monitor (VLM) (Continued) Table 50. Delay Setting Example External Elements RSOURCE [KΩ] CP [pF] 27.5 0.1 25 1 210 10 2220 30 7900 0.1 45 1 430 10 3350 30 11400 50 9.7.2 Delay Time (ns) Measuring Out of Range Positive and Negative Voltages Only voltages within the range of 0V to (2.45±0.05)*VREF can be measured by the module. To measure voltages out of this range, any of the external measurement pins can be used with the addition of external resistors that should be used as voltage dividers. (See Figure 32.) VIN (12V) AVDD R1 R1 AVI AVI R2 R2 AVSS VIN (-12V) AVSS Figure 32. Measurement Out of Positive and Negative Voltages 9.7.3 Obtaining the Specified VLM/TMS Accuracy To obtain the specified VLM/TMS accuracy, see Section 10.5.5 on page 183: www.national.com 168 10.0 Temperature Sensor (TMS) 10.1 OVERVIEW The Temperature Sensor (TMS) is a diode input temperature sensor that consists of a Delta-Sigma Analog to Digital (A/D) converter and a digital overtemperature detector. Both of these elements conform to Advance Configuration and Power Interface (ACPI) requirements for thermal management. The TMS senses the temperature of two target ICs by measuring the voltage drop of diode(s) placed on the target IC’s die. A host can query the TMS at any time to read the temperature of the remote diode(s). An ALERT interrupt output becomes active when the temperature goes above THIGH or below TLOW. The host may program the two thresholds for each sensing channel to define an operation window. Overtemperature Shutdown (OTS) output becomes active when the temperature exceeds the programmable limit TOS. 10.2 FUNCTIONAL DESCRIPTION The TMS incorporates a band-gap temperature sensor using remote diode(s) and an 8-bit Delta-Sigma Analog-to-Digital Converter (A/D converter). Once enabled and put in active (non-standby mode), the TMS continuously measures temperature of up to two remote diodes. TMS readings are available at all times via the host interface. When SLPS3 input becomes inactive, the conversion is stopped and no new results are generated until both SLPS3 becomes active and the internal wake up sequence is completed. TMS registers are maintained by VSB during this period. A digital comparator is also incorporated to compare temperature readings to user-programmable limits. OTS output indicates that the result of the comparison exceeds the limit preset in the Channel Overtemperature Limit register. ALERT output indicates that the result of the comparison is not within limits preset in the Channel Temperature High or Low Limit (CHTH and CHTL) registers. Figure 33 shows a simplified block diagram of the TMS. It represents only one remote diode (even though there are actually two remote diodes and one or two OTS signals, one for each diode sensor or combined). TMS Module VDD VSS VSB 8-Bit Temperature ∆−Σ Sensor Circuitry Overtemp High DPi DNi ALERT A/D Converter Low Diode Enable and Config Logic OTS IRQ SMI Selector Control Conversion Temperature Rate Logic Readout Figure 33. Overtemp. Shutdown Setpoint High and Low Limit Setpoints Enable Bits TMS Simplified Block Diagram 169 www.national.com 10.0 Temperature Sensor (TMS) (Continued) 10.2.1 Register Bank Overview Two register banks control TMS operation. The first part of each bank is a set of registers common to all banks. The second part of each bank contains registers which are specific to that bank. All registers use the same 16-byte address space to indicate offsets 00h through 0Fh. The software selects the currently active bank using the Bank Select register (TMSBS) — see Figure 34. Bank 0 is selected after reset. Offset 00h . . . Offset 08h } Common Registers for All Banks TMSBS (09h) Offset 0Ah . . . Offset 0Eh BANK 1 BANK 0 Figure 34. Register Bank Architecture 10.2.2 TOS, THIGH and TLOW Limits, OTS and ALERT Output, IRQ and SMI The temperature reading is compared to three limits: TOS, THIGH and TLOW. If the temperature reading is outside any of these limits, the respective status bit (Channel Overtemperature Limit Exceeded, Channel Temp High Limit Exceeded or Channel Temp Low Limit Exceeded) in the TCHCFST register is set. The status bit stays active until it is cleared by the software. An ALERT status bit in the TEVSTS register is set when the Channel Temp High Limit Exceeded or Channel Temp Low Limit Exceeded bit for the respective channel is set. The channel’s Overtemperature Event status in the TEVSTS register is set when the Channel Overtemperature Limit Exceeded bit is set. The OTS output is used to indicate to the system that the overtemperature limit has been exceeded. The OTS Output Enable bit in the TCHCFST register enables the OTS output to be active when the OTS status of the channel is active. In addition to the combined OTS output, there is a separate output for the remote 1 (OTS1) and remote 2 (OTS2) channels. The ALERT output is used to indicate to the system that the current temperature is outside the high/low limits. The ALERT output Enable bit in the TCHCFST register enables the ALERT output to be active when the Channel Temp High Limit Exceeded or the Channel Temp Low Limit Exceeded status bit in TCHCFST register is set. The SMI output generates an interrupt if any enabled SMI event occurs. Each bit in the TEVSTS register has a corresponding SMI Enable bit in the TEVSMI register. When any status bit and its corresponding SMI Enable bit are set, the SMI output is active. The IRQ output generates an interrupt if any enabled IRQ event occurs. Each bit in the TEVSTS register has a corresponding IRQ Enable bit in the TEVIRQ register. When any status bit and its corresponding IRQ Enable bit are set, the IRQ output is active. www.national.com 170 10.0 Temperature Sensor (TMS) (Continued) THIGH TOS1 TLOW TOS2 ALERT OTS Indicates when temperature is sampled by the A/D Converter. Indicates when temperature is sampled by the A/D Converter. b: OTS Signal a: ALERT Signal TOS1 THIGH1 TLOW1 TOS2 THIGH2 TLOW2 ALERT OTS Indicates when temperature is sampled by the A/D Converter. c: Combined ALERT and OTS Signals Figure 35. OTS and ALERT Temperature Response Diagrams 10.2.3 ALERT Response Read Sequence The Read Channel Temperature register (RDCHT) holds the temperature value most recently read from the channel. The Temperature Event Status register (TEVSTS) indicates any ALERT detected as long as VSB is maintained. ALERTs are cleared by software. When an IRQ or SMI is received, check the TEVSTS register to see which of the sensors detected an out-of-limit readout, access the channel readouts, read the current value and status information and clear any pending status bits. 10.2.4 Power-On Reset Default States TMS always powers up in a known state. TMS power-up default conditions are: 1. Local temperature set to 0°C. 2. Remote temperature set to 0°C until the TMS senses a diode present on D+ and D- input pins. 3. Status register set to 00h. 4. Command register set to 00h; ALERT and OTS enabled and Standby mode deactivated. 5. Local and Remote TOS set to 127°C. 6. Local and Remote THIGH set to 127°C. 7. Local and Remote TLOW set to -55°C. 171 www.national.com 10.0 Temperature Sensor (TMS) (Continued) 10.2.5 Temperature Data Format Temperature data is stored in the RDCHT, CHTH, CHTL and CHOTL registers as an 8-bit, 2’s complement word with a Least Significant Bit (LSB) equal to 1° C. Table 51. Temperature Formats Digital Output Temperature (°C) Binary Hex +125 0111 1101 7Dh +25 0001 1001 19h +1 0000 0001 01h 0 0000 0000 00h -1 1111 1111 FFh -25 1110 0111 E7h Output Code 0111,1101 +25°C +1°C 0001,1001 0000,0001 0000,0000 Temperature 0°C -55°C 1111,1111 -1°C -25°C +125°C 1110,0111 1100,1001 Figure 36. Temperature-to-Digital Transfer Function (Non-linear scale for clarity) 10.2.6 Standby Mode Standby mode is enabled by setting the Standby Mode bit in the TMSCFG register to 1 (default). Standby mode disables the conversion process to reduce power supply current. During standby mode, all registers retain their values and can be accessed by software (as usual). 10.2.7 Diode Fault Detection At the beginning of each conversion, the TMS goes through a diode fault detection sequence. If the DxP input is shorted to VDD or floating, the temperature reading will be +127° C and the Open bit of the TCHCFST register is set, which activates the ALERT and OTS outputs on completion of a conversion. If DxP is shorted to GND or DxN, the temperature reading is O° C and the Temperature Low Limit bit of the TCHCFST register is not set. www.national.com 172 10.0 Temperature Sensor (TMS) (Continued) 10.3 TMS REGISTERS The TMS registers are divided into two groups: TMS Control and Status registers and TMS channel registers. The TMS channel registers are duplicated for each channel. The register maps in this chapter use the following abbreviations for Type: • R/W = Read/Write. • R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register. • W = Write. • RO = Read Only. • R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. 10.3.1 TMS Register Map Table 52. TMS Control and Status Register Map Offset Mnemonic 00h TEVSTS 01h Reserved 02h TEVSMI 03h Reserved 04h TEVIRQ Register Name Type Section Temperature Event Status RO 10.3.2 Temperature Event to SMI R/W 10.3.3 Temperature Event to IRQ R/W 10.3.4 05hReserved 07h 08h TMSCFG TMS Configuration R/W 10.3.5 09h TMSBS TMS Bank Select R/W 10.3.6 Table 53. TMS Channel Register Map (One per Channel) Offset Mnemonic Register Name Type Section 0Ah TCHCFST Temperature Channel Configuration and Status Varies per bit 10.3.7 0Bh RDCHT Read Channel Temperature RO 10.3.8 0Ch CHTH Channel Temperature High Limit R/W 10.3.9 0Dh CHTL Channel Temperature Low Limit R/W 10.3.10 0Eh CHOTL Channel Overtemperature Limit R/W 10.3.11 0Fh Reserved 173 www.national.com 10.0 Temperature Sensor (TMS) (Continued) 10.3.2 Temperature Event Status Register (TEVSTS) This register is set to 00h on power-up of AVDD. It indicates which of the corresponding three TMS events has occurred. Location: Offset 00h Type: RO Bit 7 6 Name 5 4 Reserved Reset 0 0 0 Bit 3 2 1 0 Remote 2 Overtemp Event Status Remote 2 ALERT Event Status Remote 1 Overtemp Event Status Remote 1 ALERT Event Status 0 0 0 0 0 Description 7-4 Reserved. 3 Remote 2 Overtemperature Event Status. 0: Event not detected (default) 1: Event detected 2 Remote 2 ALERT Event Status. 0: Event not detected (default) 1: Event detected 1 Remote 1 Overtemperature Event Status. 0: Event not detected (default) 1: Event detected 0 Remote 1 ALERT Event Status. 0: Event not detected (default) 1: Event detected www.national.com 174 10.0 Temperature Sensor (TMS) (Continued) 10.3.3 Temperature Event to SMI Register (TEVSMI) This register controls temperature event routing to the SMI. Location: Offset 02h Type: R/W Bit 7 6 Name 5 4 0 0 2 1 0 Remote 2 Remote 2 Remote 1 Remote 1 Overtemp ALERT ALERT Overtemp Event to Event to Event to Event to SMI Enable SMI Enable SMI Enable SMI Enable Reserved Reset 3 0 Bit 0 0 0 0 0 Description 7-4 Reserved. 3 Remote 2 Overtemperature Event to SMI Enable. 0: Disabled (default) 1: Enabled 2 Remote 2 ALERT Event to SMI Enable. 0: Disabled (default) 1: Enabled 1 Remote 1 Overtemperature Event to SMI Enable. 0: Disabled (default) 1: Enabled 0 Remote 1 ALERT Event to SMI Enable. 0: Disabled (default) 1: Enabled 175 www.national.com 10.0 Temperature Sensor (TMS) (Continued) 10.3.4 Temperature Event to IRQ Register (TEVIRQ) This register controls temperature event routing to the IRQ. Location: Offset 04h Type: R/W Bit 7 6 Name 5 4 0 0 0 Bit 0 Description 7-4 Reserved. 3 Remote 2 Overtemperature Event to IRQ Enable. 0: Disabled (default) 1: Enabled 2 Remote 2 ALERT Event to IRQ Enable. 0: Disabled (default) 1: Enabled 1 Remote 1 Overtemperature Event to IRQ Enable. 0: Disabled (default) 1: Enabled 0 Remote 1 ALERT Event to IRQ Enable. 0: Disabled (default) 1: Enabled www.national.com 2 1 0 Remote 2 Remote 2 Remote 1 Remote 1 Overtemp ALERT ALERT Overtemp Event to Event to Event to Event to IRQ Enable IRQ Enable IRQ Enable IRQ Enable Reserved Reset 3 176 0 0 0 0 10.0 Temperature Sensor (TMS) (Continued) 10.3.5 TMS Configuration Register (TMSCFG) This register selects channels and sets global configuration (not channel-specific) values. Location: Offset 08h Type: R/W Bit 7 6 5 Name 4 3 2 Reserved Reset 0 0 0 Bit 0 0 0 1 0 External VREF Standby Mode 1 1 Description 7-2 Reserved. 1 External VREF. This bit selects either internal or external reference voltage for conversion. Note that if either the VLM or TMS are configured to use the internal VREF, the internal VREF will be used by both. 0: Internal VREF in use 1: External VREF in use (default) 0 Standby Mode. 0: Monitoring operation enabled 1: Standby mode (default) 10.3.6 TMS Bank Select Register (TMSBS) This register selects banks and sets global configuration (not bank specific) values. Location: Offset 09h Type: R/W Bit 7 6 Name Reset 5 4 3 Reserved 0 0 2 1 0 Bank Select 0 Bit 0 0 0 0 0 Description 7-4 Reserved. 3-0 Bank Select. Bits 3 2 1 0 0 0 0 0 0 0 0 1 Other These bits select the bank for configuration and viewing. Bank Function 0 Remote diode 1 1 Remote diode 2 Reserved 177 www.national.com 10.0 Temperature Sensor (TMS) (Continued) 10.3.7 Temperature Channel Configuration and Status Register (TCHCFST) This register is set to 00h on power-up of AVDD. Bits 3-1 indicate which of three temperature limits has been exceeded. Write 1 to clear any of these bits. Writing 0 has no effect. Location: Offset 0Ah Type: Varies per bit Bit 7 6 5 4 3 Name End of Conversion Open OTS Output Enable ALERT Output Enable Channel Overtemp Limit Exceeded Reset 0 0 0 0 0 Bit Type 2 1 Channel Channel Temp High Temp Low Limit Limit Exceeded Exceeded 0 0 0 Channel Enable 0 Description 7 R/W1C End of Conversion. This bit reflects the data in the RDCHT register (see next page). It is cleared by writing 1 to this bit. It is set when new data is written to the RDCHT register. 0: No new data (default) 1: New data not yet read 6 R/W1C Open. 0: No fault (default) 1: Remote diode continuity (open circuit) fault 5 R/W OTS Output Enable. 0: Disabled (default) 1: Enabled 4 R/W ALERT Output Enable. 0: Disabled (default) 1: Enabled 3 R/W1C Channel Overtemperature Limit Exceeded. 0: Overtemperature lower than limit (default) 1: Overtemperature higher than limit 2 R/W1C Channel Temperature High Limit Exceeded. 0: Temperature lower than limit (default) 1: Temperature higher than limit 1 R/W1C Channel Temperature Low Limit Exceeded. This bit is set whenever a value lower than the value specified in CHTL is written into RDCHT. It is cleared by writing 1 to it. 0: Temperature higher than limit (default) 1: Temperature lower than limit 0 R/W Channel Enable. 0: Disabled (default) 1: Enabled www.national.com 178 10.0 Temperature Sensor (TMS) (Continued) 10.3.8 Read Channel Temperature Register (RDCHT) This register holds the last temperature readout for each channel. The value is an 8-bit, 2’s complement word with a Least Significant Bit (LSB) equal to 1° C of the temperature measured by the channel. Location: Offset 0Bh Type: RO Bit 7 6 5 Name 4 3 2 1 0 0 0 0 1 0 1 1 1 0 0 1 1 0 1 1 Channel Temperature Value Reset 0 0 0 0 0 10.3.9 Channel Temperature High Limit Register (CHTH) This register holds the temperature high limit value that is compared with the temperature reading. Location: Offset 0Ch Type: R/W Bit 7 6 Name 5 4 3 2 Channel Temperature High Limit Value Reset 0 1 1 1 1 1 10.3.10 Channel Temperature Low Limit Register (CHTL) This register holds the temperature low limit value that is compared with the temperature reading. Location: Offset 0Dh Type: R/W Bit 7 6 Name 5 4 3 2 Channel Temperature Low Limit Value Reset 1 1 0 0 1 0 10.3.11 Channel Overtemperature Limit Register (CHOTL) This register holds the overtemperature limit value that is compared with the temperature reading. Location: Offset 0Eh Type: R/W Bit 7 6 Name Reset 5 4 3 2 Channel Overtemperature Limit Value 0 1 1 1 179 1 1 www.national.com 10.0 Temperature Sensor (TMS) (Continued) 10.4 TMS REGISTER BITMAP 10.4.1 TMS Control and Status Registers Register Offset Mnemonic 00h Bits 7 6 TEVSTS 5 4 Reserved 01h 02h 2 1 0 Remote 2 Overtemp Event Status Remote 2 ALERT Event Status Remote 1 Overtemp Event Status Remote 1 ALERT Event Status Remote 2 Overtemp Event to SMI Enable Remote 2 ALERT Event to SMI Enable Remote 1 Overtemp Event to SMI Enable Remote 1 ALERT Event to SMI Enable Remote 2 Overtemp Event to IRQ Enable Remote 2 ALERT Event to IRQ Enable Remote 1 Overtemp Event to IRQ Enable Remote 1 ALERT Event to IRQ Enable External VREF Standby Mode Reserved TEVSMI Reserved 03h 04h 3 Reserved TEVIRQ Reserved 05h07h Reserved 08h TMSCFG 09h TMSBS Reserved Reserved Bank Select 10.4.2 TMS Channel Registers Register Offset Mnemonic 0Ah TCHCFST Bits 7 End of Conversion 6 5 4 Open OTS Output Enable ALERT Output Enable 3 2 Channel Channel Channel Overtemp Temp High Temp Low Limit Limit Limit Exceeded Exceeded Exceeded 0Bh RDCHT 0Ch CHTH Channel Temperature High Limit Value 0Dh CHTL Channel Temperature Low Limit Value 0Eh CHOTL Channel Overtemperature Limit Value 0Fh www.national.com Channel Temperature Value Reserved 180 1 0 Channel Enable 10.0 Temperature Sensor (TMS) (Continued) 10.5 USAGE HINTS 10.5.1 Remote Diode Selection Temperature accuracy depends on a good quality transistor, used as a diode-connected small-signal transistor. Accuracy has been experimentally verified for the Motorola and other devices listed in Table 54. A temperature sensor can directly measure the die temperature of CPUs with on-board temperature-sensing diodes. The transistor must be a small-signal type with a relatively high forward voltage; otherwise, the A/D input voltage range may be violated. The forward voltage must be greater than 0.25V at 10µA at the highest expected temperature. The forward voltage must be less than 0.95V at 100µA at the lowest expected temperature. Power transistors do not work. In addition, the base resistance must be less than 100Ω. Tight specifications for forward-current gain (+50 to +150, for example) indicate devices with consistent VBE characteristics. Thermal mass can seriously degrade the temperature sensor’s effective accuracy. The use of smaller packages for remote sensors, such as SOT23s, improves the situation. Table 54. Remote Sensor Transistor Manufacturers Manufacturer Model Central Semiconductor (USA) CMPT3904 Motorola (USA) MMBT3904 National Semiconductor (USA) MMBT3904 Rohm Semiconductor (Japan) SST3904 Samsung (Korea) KST3904-TF Siemens (Germany) SMBT3904 Zetex (England) FMMT3904CT-ND 10.5.2 ADC Noise Filtering The ADC is an integrating type with inherently good noise rejection, especially of low-frequency signals such as power supply hum. Micropower operation places constraints on high-frequency noise rejection; therefore, careful PC board layout and proper external noise filtering are required for high-accuracy remote measurements in electrically noisy environments. High-frequency EMI is best filtered at DXP and DXN with an external 2200 pF capacitor. This value can be increased to about 3300pF (max), including cable capacitance. Capacitance higher than 3300 pF introduces errors due to the rise time of the switched current source. Nearly all noise sources tested cause the ADC measurements to be higher than the actual temperature, depending on the frequency and amplitude. 10.5.3 PC Board Layout 1. Place the temperature sensor as close as practical to the remote diode. In a noisy environment, such as a computer motherboard, this distance can be 4 in. to 8 in. (typical) or more as long as the worst noise sources (such as CRTs, clock generators, memory buses and ISA/PCI buses) are avoided. 2. Do not route the DXP DXN lines next to high-inductance signals. Also, do not route the traces across a fast memory bus, which can easily introduce +30˚C error, even with good filtering. Otherwise, most noise sources are fairly benign. 3. Route the DXP and DXN traces in parallel and in close proximity to each other and away from any high-voltage traces such as +12VDC. Beware of leakage currents from PC board contamination; e.g., a 20M leakage path from DXP to ground causes about +1˚C error. 4. Connect guard traces to GND on either side of the DXP DXN traces (Figure 37). With guard traces in place, routing near high-voltage traces is not a problem. 5. Route through as few vias and crossunders as possible to minimize copper/solder thermocouple effects. 6. When introducing a thermocouple, make sure that both the DXP and the DXN paths have matching thermocouples. In general, PC board-induced thermocouples are not a serious problem. A copper-solder thermocouple exhibits 3V/˚C, and it takes about 200V of voltage error at DXP DXN to cause a +1˚C measurement error. So, most parasitic thermocouple errors are swamped out. 7. Use wide traces. Narrow ones are more inductive and tend to pick up radiated noise. The 10 mil widths and spacings recommended in Figure 37 are not absolutely necessary (as they offer only a minor improvement in leakage and noise), but try to use them where practical. 181 www.national.com 10.0 Temperature Sensor (TMS) • (Continued) Keep in mind that copper cannot be used as an EMI shield, and only ferrous materials such as steel work well. Placing a copper ground plane between the DXP-DXN traces and traces carrying high-frequency noise signals does not help reduce EMI. GND 10 mil 10 mil DXP Minimum 10 mil DXN 10 mil GND Figure 37. DXP/DXN PC Traces DXP DXN 2N3904 2200 pF Figure 38. Typical Operating Circuit www.national.com 182 10.0 Temperature Sensor (TMS) (Continued) 10.5.4 Twisted Pair and Shielded Cables For remote sensor distances longer than 8 in. or in particularly noisy environments, a twisted pair is recommended. Its practical length is 6 feet to 12 feet (typical) before noise becomes a problem, as tested in a noisy electronics laboratory. For longer distances, the best solution is a shielded twisted pair like that used for audio microphones. Connect the twisted pair to DXP and DXN and the shield to GND and leave the shield’s remote end unterminated. Excess capacitance at DX_ limits practical remote sensor distances. For very long cable runs, the cable’s parasitic capacitance often provides noise filtering, so the 2200 pF capacitor can often be removed or reduced in value. Cable resistance also affects remote sensor accuracy: 1Ω series resistance introduces about +1/2˚C error. 10.5.5 Obtaining the Specified VLM/TMS Accuracy To obtain the specified VLM/TMS accuracy, use the following sequence on VSB power-up: 1. Set the TMS Logical Device base address. 2. Enable the TMS Logical Device. 3. Write 00h to index 08h of the TMS Logical Device. 4. Write 0Fh to index 09h of the TMS Logical Device. 5. Write 08h to index 0Ah of the TMS Logical Device. 6. Write 04h to index 0Bh of the TMS Logical Device. 7. Write 35h to index 0Ch of the TMS Logical Device. 8. Write 05h to index 0Dh of the TMS Logical Device. 9. Write 05h to index 0Eh of the TMS Logical Device. 183 www.national.com 11.0 Legacy Functional Blocks This chapter briefly describes the following blocks that provide legacy device functions: ● Keyboard and Mouse Controller (KBC). ● Floppy Disk Controller (FDC). ● Parallel Port. ● Serial Port 1 (SP1), UART Functionality for both Serial Port 1 and Serial Port 2. ● Serial Port 2 (SP2), Infrared Functionality. The description of each Legacy block includes the sections listed below. For more information about legacy blocks, contact your National representative. ● General Description. ● Register Map table(s). ● Bitmap table(s). The register maps in this chapter use the following abbreviations for Type: ● R/W = Read/Write. ● R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register. ● W = Write. ● RO = Read Only. ● R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. 11.1 KEYBOARD AND MOUSE CONTROLLER (KBC) 11.1.1 General Description The KBC is implemented physically as a single hardware module and houses two separate logical devices: a Mouse controller and a Keyboard controller. The KBC is functionally equivalent to the industry standard 8042A Keyboard controller, which may serve as a detailed technical reference for the KBC. 11.1.2 KBC Register Map Offset Mnemonic Register Name Type DBBOUT Read KBC Data 00h DBBIN R Write KBC Data W STATUS Read Status 04h DBBIN R Write KBC Command W 11.1.3 KBC Bitmap Summary Register Offset Mnemonic Bits 7 6 5 4 3 DBBOUT KBC Data Bits (For Read cycles) DBBIN KBC Data Bits (For Write cycles) 2 1 0 F0 IBF OBF 00h STATUS General Purpose Flags F1 04h DBBIN www.national.com KBC Command Bits (For Write cycles) 184 11.0 Legacy Functional Blocks (Continued) 11.2 FLOPPY DISK CONTROLLER (FDC) 11.2.1 General Description The generic FDC is a standard FDC with a digital data separator and is DP8473 and N82077 software compatible. The FDC is implemented in this device as follows: ● FM and MFM modes are supported. To select either mode, set bit 6 of the first command byte when writing to/reading from a diskette, where: 0 = FM mode 1 = MFM mode ● Automatic media sense is not supported (MSEN0-1 pins are not implemented). ● DRATE1 is not supported. ● A logic 1 is returned for all floating (TRI-STATE) FDC register bits upon LPC I/O read cycles. 11.2.2 FDC Register Map Offset Mnemonic 00h SRA Status A RO 01h SRB Status B RO 02h DOR Digital Output R/W 03h TDR Tape Drive R/W MSR Main Status R 04h 05h Register Name DSR Data Rate Select FIFO Data (FIFO) DIR Digital Input R CCR Configuration Control W 06h 07h Type W R/W Reserved 185 www.national.com 11.0 Legacy Functional Blocks (Continued) 11.2.3 FDC Bitmap Summary The FDC supports two system operation modes: PC-AT mode and PS/2 mode (MicroChannel systems). Unless specifically indicated otherwise, all fields in all registers are valid in both drive modes. Register Bits Offset Mnemonic 7 6 5 4 3 2 1 0 00h SRA1 IRQ Pending Reserved Step TRK0 Head Select INDEX WP Head Direction 01h SRB1 Drive Select 0 Status WDATA RDATA WGATE MTR1 MTR0 02h DOR Motor Enable 1 Motor Enable 0 DMAEN Reset Controller Reserved Motor Enable 3 Motor Enable 2 TDR 03h TDR2 Reserved Reserved MSR RQM DSR Software Reset Data I/O Direction 04h 05h Tape Drive Select 1,0 Logical Drive Exchange Drive ID Information Non-DMA Execution Low Power Reserved Command in Progress Drive 3 Busy Drive 2 Busy Precompensation Delay Select FIFO Drive Select Tape Drive Select 1,0 Drive 1 Busy Data Transfer Rate Select Data Bits DIR3 DSKCHG DIR1 DSKCHG Reserved 07h 07h 1. 2. 3. CCR Reserved Reserved Applicable only in PS/2 Mode. Applicable only in Enhanced TDR Mode. Applicable only in PC-AT Compatible Mode. www.national.com Drive 0 Busy 186 DRATE 1,0 Status High Density DRATE1,0 11.0 Legacy Functional Blocks (Continued) 11.3 PARALLEL PORT 11.3.1 General Description The Parallel Port supports all IEEE1284 standard communication modes: Compatibility (known also as Standard or SPP), Bidirectional (known also as PS/2), FIFO, EPP (known also as Mode 4) and ECP (with an optional Extended ECP mode). 11.3.2 Parallel Port Register Map The Parallel Port functional block register maps are grouped according to first and second level offsets. EPP and second level offset registers are available only when base address is 8-byte aligned. Table 55. Parallel Port Register Map for First Level Offset First Level Offset Mnemonic 000h DATAR 000h AFIFO 001h DSR Modes (ECR Bits) 765 Type PP Data 000 001 R/W ECP Address FIFO 011 W Status All Modes RO Control Register Name 002h DCR All Modes R/W 003h ADDR EPP Address 100 R/W 004h DATA0 EPP Data Port 0 100 R/W 005h DATA1 EPP Data Port 1 100 R/W 006h DATA2 EPP Data Port 2 100 R/W 007h DATA3 EPP Data Port 3 100 R/W 400h CFIFO PP Data FIFO 010 W 400h DFIFO ECP Data FIFO 011 R/W 400h TFIFO Test FIFO 110 R/W 400h CNFGA Configuration A 111 RO 401h CNFGB Configuration B 111 RO 402h ECR Extended Control All Modes R/W 403h EIR Extended Index All Modes R/W 404h EDR Extended Data All Modes R/W 405h EAR Extended Auxiliary Status All Modes R/W Table 56. Parallel Port Register Map for Second Level Offset Second Level Offset Register Name Type 00h Control0 R/W 02h Control2 R/W 04h Control4 R/W 05h PP Confg0 R/W 187 www.national.com 11.0 Legacy Functional Blocks (Continued) 11.3.3 Parallel Port Bitmap Summary The Parallel Port functional block bitmaps are grouped according to first and second level offsets. Table 57. Parallel Port Bitmap Summary for First Level Offset Register Offset Mnemonic Bits 7 6 5 4 3 DATAR Data Bits AFIFO Address Bits 2 1 0 000h Printer Status ACK Status PE Status SLCT Status ERR Status Reserved EPP Timeout Status Direction Control Interrupt Enable PP Input Control Printer Automatic Initialization Line Feed Control Control Data Strobe Control 001h DSR 002h DCR 003h ADDR EPP Device or Register Selection Address Bits 004h DATA0 EPP Device or R/W Data 005h DATA1 EPP Device or R/W Data 006h DATA2 EPP Device or R/W Data 007h DATA3 EPP Device or R/W Data 400h CFIFO Data Bits 400h DFIFO Data Bits 400h TFIFO Data Bits 400h CNFGA 401h CNFGB 402h ECR 403h EIR 404h EDR 405h EAR www.national.com Reserved Bit 7 of PP Confg0 Reserved Reserved Interrupt Request Value Interrupt Select Reserved DMA Channel Select ECP Mode Control ECP Interrupt Mask ECP Interrupt Service FIFO Full Reserved ECP DMA Enable Reserved FIFO Empty Second Level Offset Data Bits FIFO Tag Reserved 188 11.0 Legacy Functional Blocks (Continued) Table 58. Parallel Port Bitmap Summary for Second Level Offset Register Second Level Mnemonic Offset Bits 7 6 Reserved 5 4 DCR Register Live Freeze Bit Reserved Revision 1.7 or 1.9 Select 00h Control0 02h Control2 SPP Compatibility Channel Address Enable 04h Control4 Reserved PP DMA Request Inactive Time 05h PP Confg0 Bit 3 of CNFGA Demand DMA Enable 3 1 0 EPP Timeout Interrupt Mask Reserved Reserved Reserved ECP IRQ Channel Number 189 2 PP DMA Request Active Time PE Internal Pull-up or Pull-down ECP DMA Channel Number www.national.com 11.0 Legacy Functional Blocks (Continued) 11.4 UART FUNCTIONALITY (SP1 AND SP2) 11.4.1 General Description Both SP1 and SP2 provide UART functionality. The generic SP1 and SP2 support serial data communication with remote peripheral device or modem using a wired interface. The functional blocks can function as a standard 16450 or 16550 or as an Extended UART. 11.4.2 UART Mode Register Bank Overview Four register banks, each containing eight registers, control UART operation. All registers use the same 8-byte address space to indicate offsets 00h through 07h. The BSR register selects the active bank and is common to all banks. See Figure 39. BANK 3 BANK 2 BANK 1 BANK 0 Offset 07h Common Register Throughout All Banks Offset 06h Offset 05h Offset 04h LCR/BSR Offset 02h Offset 01h Offset 00h 16550 Banks Figure 39. UART Mode Register Bank Architecture www.national.com 190 11.0 Legacy Functional Blocks (Continued) 11.4.3 SP1 and SP2 Register Maps for UART Functionality Table 59. Bank 0 Register Map Offset Mnemonic 00h RXD 00h TXD Transmitter Data Port 01h IER Interrupt Enable R/W 02h 03h Register Name Type Receiver Data Port RO W EIR Event Identification (Read Cycles) RO FCR FIFO Control (Write Cycles) W LCR1 Line Control BSR1 Bank Select R/W 04h MCR Modem/Mode Control R/W 05h LSR Link Status RO MSR Modem Status 06h 07h 1. RO SPR/ASCR Scratchpad/Auxiliary Status and Control R/W When bit 7 of this Register is set to 1, bits 6-0 of BSR select the bank, as shown in Table 60. Table 60. Bank Selection Encoding BSR Bits 6 5 4 3 2 1 0 Bank Selected 0 x x x x x x x 0 1 0 x x x x x x 1 1 1 x x x x 1 x 1 1 1 x x x x x 1 1 1 1 1 0 0 0 0 0 2 1 1 1 0 0 1 0 0 3 1 1 1 0 1 0 0 0 4 1 1 1 0 1 1 0 0 5 1 1 1 1 0 0 0 0 6 1 1 1 1 0 1 0 0 7 7 Functionality UART + IR (SP1 + SP2) IR Only (SP2) Table 61. Bank 1 Register Map Offset Mnemonic Register Name Type 00h LBGD(L) Legacy Baud Generator Divisor Port (Low Byte) R/W 01h LBGD(H) Legacy Baud Generator Divisor Port (High Byte) R/W 02h 03h 04h - 07h Reserved LCR/BSR Line Control/Bank Select R/W Reserved 191 www.national.com 11.0 Legacy Functional Blocks (Continued) Table 62. Bank 2 Register Map Offset Mnemonic Register Name 00h BGD(L) 01h BGD(H) Baud Generator Divisor Port (High Byte) R/W 02h EXCR1 Extended Control1 R/W 03h LCR/BSR Line Control/Bank Select R/W 04h EXCR2 Extended Control 2 R/W Baud Generator Divisor Port (Low Byte) 05h Type R/W Reserved 06h TXFLV TX_FIFO Level R/W 07h RXFLV RX_FIFO Level R/W Table 63. Bank 3 Register Map Offset 00h MRID 01h SH_LCR Register Name Type Module Revision ID RO Shadow of LCR (Read Only) RO 02h SH_FCR Shadow of FIFO Control (Read Only) RO 03h LCR/BSR Line Control/Bank Select R/W 04h-07h www.national.com Mnemonic Reserved 192 11.0 Legacy Functional Blocks (Continued) 11.4.4 SP1 and SP2 Bitmap Summary for UART Functionality Table 64. Bank 0 Bitmap Register Offset Mnemonic Bits 7 6 5 4 3 RXD Receiver Data Bits TXD Transmitter Data Bits 2 1 0 00h IER1 Reserved 01h IER2 EIR1 02h EIR2 Reserved FEN1 TXEMP_IE FEN0 Reserved Reserved3/ DMA_IE4 Reserved MS_IE LS_IE TXLDL_IE RXHDL_IE MS_IE LS_IE TXLDL_IE RXHDL_IE RXFT IPR1 TXEMP_EV Reserved3/ DMA_EV4 MS_EV IPR0 IPF LS_EV or TXLDL_EV RXHDL_EV TXHLT_EV FCR RXFTH1 RXFTH0 TXFTH1 TXFTH0 Reserved TXSR RXSR FIFO_EN LCR5 BKSE SBRK STKP EPS PEN STB WLS1 WLS0 BSR5 BKSE ISEN or DCDLP RILP RTS DTR TX_DFR Reserved RTS DTR 03h MCR1 Bank Select Reserved LOOP 04h MCR2 Reserved 05h LSR ER_INF TXEMP TXRDY BRK FE PE OE RXDA 06h MSR DCD RI DSR CTS DDCD TERI DDSR DCTS SPR1 Scratch Data 07h ASCR2 1. 2. 3. 4. 5. Reserved TXUR4 RXACT 4 RXWDG4 Reserved S_OET4 Reserved RXF_TOUT Non-Extended Mode. Extended Mode. In SP1 only. In SP2 only. When bit 7 of this register is set to 1, bits 6-0 of BSR select the bank, as shown in Table 60. 193 www.national.com 11.0 Legacy Functional Blocks (Continued) Table 65. Bank 1 Bitmap Register Bits Offset Mnemonic 7 6 5 00h LBGD(L) Legacy Baud Generator Divisor (Least Significant Bits) 01h LBGD(H) Legacy Baud Generator Divisor (Most Significant Bits) 02h 03h 4 3 2 1 0 1 0 Reserved LCR/BSR Same as Bank 0 04h07h Reserved Table 66. Bank 2 Bitmap Register Bits Offset Mnemonic 7 00h BGD(L) Baud Generator Divisor Low (Least Significant Bits) 01h BGD(H) Baud Generator Divisor High (Most Significant Bits) 02h EXCR1 03h LCR/BSR 04h EXCR2 05h Reserved BTEST 6 Reserved 5 ETDLBK 4 3 LOOP 2 Reserved EXT_SL Same as Bank 0 LOCK Reserved PRESL1 PRESL0 Reserved 06h TXFLV Reserved TFL4 TFL3 TFL2 TFL1 TFL0 07h RXFLV Reserved RFL4 RFL3 RFL2 RFL1 RFL0 3 2 1 0 Table 67. Bank 3 Bitmap Register Bits Offset Mnemonic 00h MRID 01h SH_LCR BKSE SBRK STKP EPS PEN STB WLS1 WLS0 02h SH_FCR RXFTH1 RXFTH0 TXFHT1 TXFTH0 Reserved TXSR RXSR FIFO_EN 03h LCR/BSR 04h07h www.national.com 7 6 5 4 Module ID (MID 7-4) Revision ID(RID 3-0) Same as Bank 0 Reserved 194 11.0 Legacy Functional Blocks (Continued) 11.5 IR FUNCTIONALITY (SP2) 11.5.1 General Description This section describes the IR support registers of Serial Port 2 (SP2). The UART support registers for both SP1 and SP2 are described in Section 11.4. The IR functional block provides advanced, versatile serial communications features with IR capabilities. SP2 supports also two DMA channels; the functional block can use either one or both of them. One channel is required for IR-based applications because IR communication works in half duplex fashion. Two channels would normally be needed to handle high-speed full-duplex UART based applications. 11.5.2 IR Mode Register Bank Overview Eight register banks, each containing eight registers, control SP2 operation. Banks 0-3 are used to control both UART and IR modes of operation; banks 4-7 are used to control and configure the IR modes of operation only. All registers use the same 8-byte address space to indicate offsets 00h through 07h. The BSR register selects the active bank and is common to all banks. See Figure 40. BANK 7 BANK 6 BANK 5 BANK 4 BANK 3 BANK 2 BANK 1 Common Register Throughout All Banks BANK 0 Offset 07h Offset 06h Offset 05h Offset 04h LCR/BSR IR Special Banks (Banks 4-7) Offset 02h Offset 01h Offset 00h Figure 40. SP2 Register Bank Architecture 195 www.national.com 11.0 Legacy Functional Blocks (Continued) 11.5.3 SP2 Register Map for IR Functionality . Table 68. Bank 4 Register Map Offset Mnemonic Register Name 00h-01h Type Reserved 02h IRCR1 03h LCR/BSR IR Control 1 R/W Line Control/Bank Select R/W 04h - 07h Reserved Table 69. Bank 5 Register Map Offset Mnemonic Register Name 00h-02h Type Reserved 03h LCR/BSR 04h IRCR2 Line Control/Bank Select R/W IR Control 2 R/W 05h - 07h Reserved Table 70. Bank 6 Register Map Offset Mnemonic 00h IRCR3 01h Register Name IR Control 3 Type R/W Reserved 02h SIR_PW SIR Pulse Width Control (≤ 115 Kbps) R/W 03h LCR/BSR Line Control/Bank Select R/W 04h-07h Reserved Table 71. Bank 7 Register Map Offset Mnemonic 00h IRRXDC 01h 02h 03h LCR/BSR 04h IRCFG1 Type IR Receiver Demodulator Control RO IRTXMC IR Transmitter Modulator Control RO RCCFG CEIR Configuration RO Line Control/Bank Select R/W IR Interface Configuration 1 R/W 05h www.national.com Register Name Reserved 06h IRCFG3 IR Interface Configuration 3 R/W 07h IRCFG4 IR Interface Configuration 4 R/W 196 11.0 Legacy Functional Blocks (Continued) 11.5.4 SP2 Bitmap Summary for IR Functionality Table 72. Bank 4 Bitmap Register Offset Mnemonic Bits 7 6 5 00h01h 4 3 2 1 IR_SL1 IR_SL0 0 Reserved 02h EIR 03h LCR/BSR Reserved Reserved Same as Bank 0 04h07h Reserved Table 73. Bank 5 Bitmap Register Offset Mnemonic Bits 7 6 5 00h02h 4 3 2 1 0 IRMSSL IR_FDPLX 1 0 Reserved 03h LCR/BSR 04h IRCR2 Same as Bank 0 Reserved AUX_IRRX 05h07h Reserved Reserved Table 74. Bank 6 Bitmap Register Offset Mnemonic 00h IRCR3 Bits 7 6 5 SHDM_DS SHMD_DS 01h 3 2 Reserved Reserved 02h SIR_PW 03h LCR/BSR 04h07h 4 Reserved SPW (3-0) Same as Bank 0 Reserved 197 www.national.com 11.0 Legacy Functional Blocks (Continued) Table 75. Bank 7 Bitmap Register Bits Offset Mnemonic 7 00h IRRXDC DBW (2-0) DFR (4-0) 01h IRTXMC MCPW (2-0) MCFR (4-0) 02h RCCFG 03h LCR/BSR 04h IRCFG1 R_LEN 6 T_OV 5 RXHSC 4 RCDM_DS 3 Reserved 2 TXHSC 1 RC_MND1 RC_MMD0 Same as Bank 0 STRV_MS SIRC (2-0) 05h IRID3 IRIC (2-0) Reserved RCLC (2-0) IRSL21_DS Reserved Reserved 06h IRCFG3 Reserved 07h IRCFG4 AMCFG www.national.com RCH (2-0) Reserved IRSL0_DS RXINV 198 0 12.0 Device Characteristics 12.1 GENERAL DC ELECTRICAL CHARACTERISTICS 12.1.1 Recommended Operating Conditions Symbol Parameter Min Typ Max Unit AVDD Analog Supply Voltage (only one) 3.0 3.3 3.6 V VDD Supply Voltage 3.0 3.3 3.6 V VSB Standby Voltage 3.0 3.3 3.6 V VBAT Battery Backup Supply Voltage 2.4 3.0 3.6 V +70 °C TA 0 Operating Temperature 12.1.2 Absolute Maximum Ratings Absolute maximum ratings are values beyond which damage to the device may occur. Unless otherwise specified, all voltages are relative to ground. Symbol Parameter Conditions Min Max Unit AVDD Analog Supply Voltage -0.5 TBD VDD Supply Voltage −0.5 +6.5 V VI Input Voltage −0.5 VDD + 0.5 V VO Output Voltage −0.5 VDD + 0.5 V Storage Temperature −65 +165 °C 1 W +260 °C TSTG PD Power Dissipation TL Lead Temperature Soldering (10 s) CZAP = 100 pF ESD Tolerance 1. 2000 RZAP = 1.5 KΩ1 V Value based on test complying with RAI-5-048-RA human body model ESD testing. 12.1.3 Capacitance Symbol Parameter Min Typ Max Unit 5 7 pF 8 12 pF CIN Input Pin Capacitance CIN1 Clock Input Capacitance CIO I/O Pin Capacitance 10 12 pF CO Output Pin Capacitance 6 8 pF 5 TA = 25°C, f = 1 MHz 199 www.national.com 12.0 Device Characteristics (Continued) 12.1.4 Power Consumption under Recommended Operating Conditions Symbol Conditions Typ Max Unit VDD Average Main Supply Current VIL = 0.5V, VIH = 2.4V No Load 32 50 mA ICCLP VDD Quiescent Main Supply Current in Low Power Mode VIL = VSS, VIH = VDD No Load 1.3 1.7 mA IASB AVDD Average Main Supply Current TBD TBD mA ISB VSB Average Main Supply Current VIL = 0.5V, VIH = 2.4V No Load 15 mA ISBLP VSB Quiescent Main Supply Current in Low Power Mode VIL = VSS, VIH = VSB No Load 3 mA IBAT VBAT Battery Supply Current VDD, VSB = 0 V, VBAT = 3V 250 nA ICC Parameter 12.2 DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES The following tables summarize the DC characteristics of all device pins described in the Signal/Pin Connection and Description chapter. The characteristics describe the general I/O buffer types defined in Table 1. For exceptions, refer to Section 12.2.15 on page 203. The DC characteristics of the system interface meet the PCI2.1 3.3V DC signaling. 12.2.1 Input, CMOS Compatible Symbol: INC Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 0.7 VDD 5.51 V VIL Input Low Voltage −0.51 0.3 VDD V IIL VIN = VDD 50 nA Input Leakage Current VIN = VSS −50 nA 1. Not tested. Guaranteed by design. 12.2.2 Input, PCI 3.3V Symbol: INPCI Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 0.5VDD VDD + 0.5 V VIL Input Low Voltage −0.5 0.3 VDD V lIL1 Input Leakage Current ±10 µA 1. 0 < Vin < VDD Input leakage currents include hi-Z output leakage for all bi-directional buffers with TRI-STATE outputs. 12.2.3 Input, SMBus Compatible Symbol: INSM Symbol VIH www.national.com Parameter Conditions Input High Voltage 200 Min Max Unit 1.4 5.51 V 12.0 Device Characteristics Symbol Parameter VIL Input Low Voltage IIL Input Leakage Current 1. (Continued) Conditions Min Max Unit −0.5 0.8 V VIN = VDD 10 µA VIN = VSS −10 µA 1 Not tested. Guaranteed by design. 12.2.4 Input, Strap Pin Symbol: INSTRP Symbol Parameter VIH Input High Voltage IIL Input Leakage Current 1. Conditions Min Max Unit 5.5 V During Reset: VIN = VDD 150 µA VIN = VSS −10 µA Min Max Unit 0.6 VDD1 1 Not tested. Guaranteed by design. 12.2.5 Input, TTL Compatible Symbol: INT Symbol Parameter Conditions VIH Input High Voltage 2.0 5.51 V VIL Input Low Voltage −0.51 0.8 V IIL VIN = VDD 10 Input Leakage Current µA VIN = VSS −10 µA 1. Not tested. Guaranteed by design. 12.2.6 Input, TTL Compatible with Schmitt Trigger Symbol: INTS Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 2.0 5.51 V VIL Input Low Voltage −0.5 1 0.8 V IIL VIN = VDD 10 Input Leakage Current µA VIN = VSS −10 µA VH Input Hysteresis 1. 250 mV Not tested. Guaranteed by design. 201 www.national.com 12.0 Device Characteristics (Continued) 12.2.7 Output, PCI 3.3V Symbol: OPCI Symbol Parameter Conditions Min 0.9 VDD VOH Output High Voltage lout = -500 µA VOL Output Low Voltage lout =1500 µA Max Unit V 0.1 VDD V 12.2.8 Output, Totem-Pole Buffer Symbol: Op/n Output, Totem-Pole buffer that is capable of sourcing p mA and sinking n mA Symbol Parameter Conditions Min 2.4 VOH Output High Voltage IOH = −p mA VOL Output Low Voltage IOL = n mA Max Unit V 0.4 V 12.2.9 Output, Open-Drain Buffer Symbol: ODn Output, Open-Drain output buffer, capable of sinking n mA. Output from these signals is open-drain and cannot be forced high. Symbol VOL Parameter Conditions Min Max Unit 0.4 V IOL = n mA Output Low Voltage 12.2.10 Input, Analog Symbol: INAN1 Input, analog to VLM. Symbol Conditions1 Parameter Min Typ Max Unit ±1 µA RAIN Analog Input Resistance2 250 Ω CAIN Analog Input Capacitance 15 pF Analog Input Leakage Current IAL 1. 2. All parameters specified for 0° C ≤ TA ≤ 70° C. AVCC= 3.3V ± 10%, unless otherwise specified and VREF = 1.235 or AVDD. The resistance between the device input and the internal analog input capacitance. 12.2.11 Input, Analog Symbol: INAN2 Input, analog to reference voltage. Symbol VREFE Conditions1 Parameter External Reference Voltage 2 RVREFE V REF Input DC resistance 1. 2. Typ Max Unit TBD 1.235 TBD V 36 KΩ 5 All parameters specified for 0° C ≤ TA ≤ 70° C. AVCC= 3.3V ± 10%, unless otherwise specified and VREF = 1.235 or AVDD. Valid only for external VREF; value changes during the conversion. www.national.com Min 202 12.0 Device Characteristics (Continued) 12.2.12 Input, Analog Symbol: INAN3 Input, analog to TMS. Symbol VDN Parameter Conditions Min D- Source Voltage Typ Max Unit 0.7 V 12.2.13 Output, Analog Symbol: OAN1 Output, analog to reference voltage. Symbol VREFE Parameter Conditions External Reference Voltage 1 RVREFE V REF Input DC resistance 1. Min Typ Max Unit 1.233 1.235 1.237 V 36 KΩ Max Unit 5 Valid only for external VREF; value changes during the conversion. 12.2.14 Output, Analog Symbol: OAN2 Output, analog to TMS. Symbol IDPH Parameter Diode Source Current IDPL Conditions Min Typ D+ = D- + 0.65V; High Level 80 120 µA Low Level 8 12 µA 12.2.15 Exceptions 1. All pins are back-drive protected, except for the output pins with PCI Buffer Type. 2. The following pins have a static pull-up resistor and therefore may have input leakage current (when VIN = VSS) of about (-)160µA: ACK, AFD_DSTRB, ERR, GPIO40-47, GPIO30-34, GPIO20-27, GPIO16-17, GPIO10-14. GPIO00-07, INIT, P12, P16, P17, PE, SLIN_ASTRB, STB_WRITE. 3. The following pins have a static pull-down resistor and therefore may have input leakage current (when VIN = VDD) of about 130µA: BUSY_WAIT, PE, SLCT. 4. Output from SLCT, BUSY_WAIT (and PE if bit 2 of PP Confg0 Register is “0”) is open-drain in all SPP modes, except in SPP-Compatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel port register is 1. Otherwise, output from these signals is level 2. External 4.7 KW pull-up resistors should be used. 5. Output from ACK, ERR (and PE if bit 2 of PP Confg0 Register is set to 1) is open-drain in all SPP modes, except in SPPCompatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel port register is set to 1. Otherwise, output from these signals is level 2. External 4.7 KW pull-up resistors should be used. 6. Output from STB, AFD, INIT, SLIN is open-drain in all SPP modes, except in SPP-Compatible mode when the setup mode is ECP-based (FIFO). Otherwise, output from these signals is level 2. External 4.7 KΩ pull-up resistors should be used. 7. Output from PD7-0 is open-drain in all SPP modes, except in SPP-Compatible mode when the setup mode is ECP-based (FIFO) and bit 4 of the Control2 parallel port register is 1. Otherwise, output from these signals is Level 2. External 4.7 KΩ pull-up resistors should be used. 8. IOH is valid for a GPIO pin only when it is not configured as open-drain. 9. P12, P16 and P17 are driven high for about 100 ns after a low-to-high transition, during which it is capable of sourcing 2 mA. 203 www.national.com 12.0 Device Characteristics (Continued) 12.3 INTERNAL RESISTORS 12.3.1 Pull-Up Resistor Symbol: PUnn. Symbol Parameter RPU Pull-up equivalent resistance Conditions Typical VDD = 3.3V nn Conditions Typical VDD = 3.3V nn Min Max nn−30% nn+30% Unit KΩ 12.3.2 Pull-Down Resistor Symbol: PDnn. Symbol Parameter RPD Pull-down equivalent resistance Min Max nn−30% nn+30% Unit KΩ 12.4 ANALOG CHARACTERISTICS 12.4.1 VLM Symbol Parameter VRES Resolution VIREF Internal Reference Voltage VDNL Differential (non-linearity) Error2 VREF Reference Voltage Input4 Accuracy5 ACU VFS Full Scale Voltage VIN Input Voltage Range tACT VLM Activation Time6 1. 2. 3. 4. 5. 6. Conditions1 Min Typical Max 8 1.208 1.211 Unit bit 1.216 V ±0.53 LSB 1.211 V 0V ≤ VIN ≤ 1.2V ±2 LSB 1.2V ≤ VIN ≤ 2V ±2 LSB 2V ≤ VIN ≤ 0.95 VFS ±4 LSB 2.967 0 V 2.45*VREF V 100 µs All parameters specified for 0° C ≤ TA ≤ 70° C and AVCC= 3.3V ± 5% unless otherwise specified and external VREF = 1.211V. The maximum difference between an ideal step size of 1 LSB and any actual step size. No missing codes. The voltage connected to this input serves as the reference voltage used to calculate the actual input voltatge. Total unadjusted error (incoludes the offset, gain, integral n0on-linearity and quantization (0.5 LSB) errors). Time from when the VLMCFG register Standby Mode Enable bit = 0 until valid conversions are possible. www.national.com 204 12.0 Device Characteristics (Continued) 12.4.2 TMS Symbol TRAC1 Parameter Accuracy Using Remote Diode TRAC2 TRESB Conditions1 tCONV Temperature Conversion Time (per channel) 1. 2. Max Unit -5 +5 C TA = +40°C to +100°C -3 +3 C TRESC Reference Voltage Input2 Typ TA = -40°C to +125°C Resolution VREF Min 8 bits 1 °C 1.211 V 100 ms All parameters specified for 0° C ≤ TA ≤ 70° C. AVCC= 3.3V ± 10% unless otherwise specified and external VREF = 1.211V. When using input with value other than specified, temperature reading accuracy is affected. 205 www.national.com 12.0 Device Characteristics (Continued) 12.5 AC ELECTRICAL CHARACTERISTICS 12.5.1 AC Test Conditions Load Circuit (Notes 1, 2, 3) AC Testing Input, Output Waveform VDD S1 2.4 0.1 µf 2.0 0.8 0.4 Test Points 2.0 0.8 RL Input Device Under Test Output CL Figure 41. AC Test Conditions, TA = 0 °C to 70 °C, VDD = 5.0V ±10% Notes: 1. CL = 100 pF for all output pins except OPCI, and CL = 50pF for outputs of type OPCI. These values include both jig and scope capacitance. 2. S1 = Open for push-pull output pins. S1 = VDD for high impedance to active low and active low to high-impedance measurements. S1 = GND for high impedance to active high and active high to high-impedance measurements. RL = 1.0KΩ for µP interface pins. 3. For the FDC open-drive interface pins, S1 = VDD and RL = 150Ω. 12.5.2 Clock Timing 48 MHz Symbol Parameter Min Max Unit tCH Clock High Pulse Width1 8.4 ns tCL Clock Low Pulse Width1 8.4 ns tCP Clock Period1 20 21.5 ns 1. Not tested. Guaranteed by design. . tCP tCH CLKIN tCL www.national.com 206 12.0 Device Characteristics (Continued) 12.5.3 LCLK and LRESET Symbol Parameter Min Max Units tCYC1 LCLK Cycle Time 30 ns tHIGH LCLK High Time 11 ns tLOW LCLK Low Time 11 ns - LCLK Slew Rate2 1 - LRESET Slew Rate3 50 4 V/ns mV/ns 1. The PCI may have any clock frequency between nominal DC and 33 MHz. Device operational parameters at frequencies under 16 MHz may be guaranteed by design rather than by testing. The clock frequency may be changed at any time during the operation of the system as long as the clock edges remain “clean” (monotonic) and the minimum cycle and high and low times are not violated. The clock may only be stopped in a low state. 2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock wavering as shown below. 3. The minimum LRESET slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures that system noise cannot make an otherwise monotonic signal appear to bounce in the switching range. 3.3V Clock tHIGH 0.5 VDD tLOW 0.6 VDD 0.4 VDD p-to-p (minimum) 0.4 VDD 0.3 VDD 0.2 VDD tCYC 207 www.national.com 12.0 Device Characteristics (Continued) 12.5.4 LPC and SERIRQ Signals Symbol Figure Description Reference Conditions tVAL Output Output Valid Delay After RE CLK tON Output Float to Active Delay After RE CLK tOFF Output Active to Float Delay After RE CLK tSU Input Input Setup Time Before RE CLK 7 ns tHI Input Input Hold Time After RE CLK 0 ns Output LCLK tVAL tON LPC Signals/ SERIRQ tOFF Input LCLK tSU LPC Signals/ SERIRQ www.national.com tHI Input Valid 208 Min Max Unit 11 ns 2 ns 28 ns 12.0 Device Characteristics (Continued) 12.5.5 Serial Port, Sharp-IR, SIR and Consumer Remote Control Timing Symbol Parameter tBT Single Bit Time in Serial Port and Sharp-IR tCMW Modulation Signal Pulse Width in Sharp-IR and Consumer Remote Control Conditions Min Max Unit Transmitter tBTN − 251 tBTN + 25 ns Receiver tBTN − 2% tBTN + 2% ns Transmitter tCWN − 252 tCWN + 25 ns Receiver 500 Transmitter tCPN − 25 Receiver ns 3 tCPN + 25 ns tMMIN4 tMMAX4 ns Transmitter, Variable (3/16) x tBTN − 151 (3/16) x tBTN + 151 ns SIR Signal Pulse Width Transmitter, Fixed 1.48 1.78 µs Receiver 1 SDRT SIR Data Rate Tolerance. % of Nominal Data Rate. Transmitter ± 0.87% Receiver ± 2.0% tSJT SIR Leading Edge Jitter. % of Nominal Bit Duration. Transmitter ± 2.5% Receiver ± 6.5% tCMP tSPW 1. 2. 3. 4. Modulation Signal Period in Sharp-IR and Consumer Remote Control µs tBTN is the nominal bit time in Serial Port, Sharp-IR, SIR and Consumer Remote Control modes. It is determined by the setting of the Baud Generator Divisor registers. tCWN is the nominal pulse width of the modulation signal for Sharp-IR and Consumer Remote Control modes. It is determined by the MCPW field (bits 7-5) of the IRTXMC register and the TXHSC bit (bit 2) of the RCCFG register. tCPN is the nominal period of the modulation signal for Sharp-IR and Consumer Remote Control modes. It is determined by the MCFR field (bits 4-0) of the IRTXMC register and the TXHSC bit (bit 2) of the RCCFG register. tMMIN and tMMAX define the time range within which the period of the incoming subcarrier signal has to fall in order for the signal to be accepted by the receiver. These time values are determined by the contents of the IRRXDC register and the setting of the RXHSC bit (bit 5) of the RCCFG register. tBT Serial Port tCMW tCMP Sharp-IR Consumer Remote Control tSPW SIR 209 www.national.com 12.0 Device Characteristics (Continued) 12.5.6 Modem Control Timing Symbol Parameter Min Max Unit tL RI2,1 Low Time 10 ns tH RI2,1 High Time 10 ns tSIM Delay to Set IRQ from Modem Input CTS, DSR, DCD tSIM 40 ns tSIM INTERRUPT (Read MSR) (Read MSR) tSIM tL tH RI 12.5.7 FDC Write Data Timing Symbol Parameter Min Max Unit tHDH HDSEL Hold from WGATE Inactive1 100 µs tHDS HDSEL Setup to WGATE Active1 100 µs tWDW Write Data Pulse Width 1. See tDRP, tICP and tWDW values in table below Not tested. Guaranteed by design. HDSEL WGATE tHDS tHDH tWDW WDATA tDRP tICP tWDW Values Data Rate tDRP tICP tICP Nominal tWDW tWDW Minimum Unit 1 Mbps 1000 6 x tCP1 125 2 x tICP 250 ns 500 Kbps 2000 6 x tCP1 125 2 x tICP 250 ns 300 Kbps 3333 10 x tCP1 208 2 x tICP 375 ns 250 Kbps 4000 12 x tCP1 250 2 x tICP 500 ns 1. tCP is the clock period defined in the Clock Timing section on page 206. www.national.com 210 12.0 Device Characteristics (Continued) 12.5.8 FDC Drive Control Timing Symbol Parameter tDST DIR Setup to STEP Active1 tIW Index Pulse Width tSTD DIR Hold from STEP Inactive tSTP tSTR Min 1 STEP Active High Pulse Width STEP Rate Time 1 Max Unit 6 µs 100 ns tSTR ms 8 µs 0.5 ms 1. Not tested. Guaranteed by design. DIR tSTD tDST STEP tSTP tSTR INDEX tIW 12.5.9 FDC Read Data Timing Symbol tRDW Parameter Min 50 Read Data Pulse Width Max Unit ns tRDW RDATA 211 www.national.com 12.0 Device Characteristics (Continued) 12.5.10 Standard Parallel Port Timing Symbol Parameter Conditions Typ Max Unit tPDH Port Data Hold These times are system dependent and are therefore not tested. 500 ns tPDS Port Data Setup These times are system dependent and are therefore not tested. 500 ns tSW Strobe Width These times are system dependent and are therefore not tested. 500 ns Typical Data Exchange BUSY ACK tPDH tPDS PD7-0 tSW STB 12.5.11 Enhanced Parallel Port Timing Symbol Parameter Min Max EPP 1.7 EPP 1.9 Unit tWW19a WRITE Active from WAIT Low 45 ✔ ns tWW19ia WRITE Inactive from WAIT Low 45 ✔ ns tWST19a DSTRB or ASTRB Active from WAIT Low 65 ✔ ns tWEST DSTRB or ASTRB Active after WRITE Active 10 ✔ ✔ ns tWPDH PD7-0 Hold after WRITE Inactive 0 ✔ ✔ ns tWPDS PD7-0 Valid after WRITE Active ✔ ✔ ns tEPDW PD7-0 Valid Width 80 ✔ ✔ ns tEPDH PD7-0 Hold after DSTRB or ASTRB Inactive 0 ✔ ✔ ns 15 tWW19a WRITE DSTRB or ASTRB tWST19a tWEST tWPDH PD7-0 tWPDS tWW19ia WAIT www.national.com 212 tWST19a tEPDH Valid tEPDW 12.0 Device Characteristics (Continued) 12.5.12 Extended Capabilities Port (ECP) Timing Forward Mode Symbol Parameter Min Max Unit tECDSF Data Setup before STB Active 0 ns tECDHF Data Hold after BUSY Inactive 0 ns tECLHF BUSY Active after STB Active 75 ns tECHHF STB Inactive after BUSY Active 0 1 s tECHLF BUSY Inactive after STB Active 0 35 ms tECLLF STB Active after BUSY Inactive 0 ns tECDHF PD7-0 AFD tECDSF tECLLF STB tECHLF tECLHF BUSY tECHHF Reverse Mode Symbol Parameter Min Max Unit tECDSR Data Setup before ACK Active 0 ns tECDHR Data Hold after AFD Active 0 ns tECLHR AFD Inactive after ACK Active 75 ns tECHHR ACK Inactive after AFD Inactive 0 35 ms tECHLR AFD Active after ACK Inactive 0 1 s tECLLR ACK Active after AFD Active 0 ns tECDHR PD7-0 BUSY tECDSR ACK tECLLR tECLHR AFD tECHLR tECHHR 213 www.national.com 12.0 Device Characteristics (Continued) 12.5.13 Chassis Lock/Unlock Timing Symbol Parameter tCLPW Max Unit Chassis Lock Pulse Width1 0.75 sec tCULPW Chassis Unlock Pulse Width1 0.75 sec tCLRCV Chassis Lock Recovery1 0.25 sec tCULRCV Chassis Unlock Recovery1 0.25 sec 1. Min Not tested. Guaranteed by design. tCLPW,tCULPW CHLOCK CHUNLOCK www.national.com 214 tCLRCV,tCULRCV PC87365 128-Pin LPC SuperI/O with System Hardware Monitoring Physical Dimensions All dimensions are in millimeters. Plastic Quad Flatpack (PQFP), JEDEC Order Number PC87365-xxx/VLA NS Package Number VLA128A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Email: [email protected] 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: +49 (0) 1 80 530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 87 90 National Semiconductor Asia Pacific Fax: 65-250-4466 Email: [email protected] Tel: 65-254-4466 National Semiconductor Japan Fax: 81-3-5639-7507 Email: [email protected] Tel: 81-3-5639-7560 www.national.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.