WOLFSON WM9093

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WM9093
Ultra Low Power Audio Subsystem
DESCRIPTION
[1]
The WM9093 is a high performance low power audio
subsystem, including headphone driver and Class AB/D
earpiece/speaker driver. The Class D speaker driver
supports 650mW output power at 3.6V, 1%THD.
The unique dual mode charge pump architecture provides
ground referenced headphone outputs removing the
requirement for external coupling capacitors. Class G
technology is integrated to increase the efficiency and
extend playback time by optimizing the headphone driver
supply voltages according to the volume control.
The flexible input configuration allows single ended or
differential stereo inputs. Mixers allow highly flexible routing
to the outputs. A ‘Voice Bypass’ path is also available for
low-power voice applications.
The WM9093 is controlled using a two-wire I2C interface.
An integrated oscillator generates all internal clocks,
removing the need to provide any external clock.
Separate mixer and volume controls are provided for each
headphone and speaker driver. Automatic Gain Control
limits the speaker output signal in order to prevent clipping.
DC offset correction to less than 1mV guarantees a
pop/click-free headphone start up.
The WM9093 is available in a 2.0mm x 2.5mm 20-bump
CSP package.
FEATURES
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Mono Class D speaker driver
2W at 5V SVDD @1%THD+N into 4Ω
650mW at 3.6V SVDD @1%THD+N into 8Ω
92dB SNR
Ground referenced stereo headphone driver
34mW into 16Ω load @ 1% THD+N
96dB SNR
80dB THD+N
Mono Class AB earpiece driver
40mW into 8Ω load
Differential and single ended analogue input configurations
Integrated oscillator for clocking requirements
2
I C 2-wire software control interface
Automatic gain control (AGC) for Class D speaker output
Pop and click suppression, < 1mV DC offset
<50ms start up time
Excellent RF and TDMA noise immunity
Ultra low power consumption
4mW quiescent for headphone driver
5mW quiescent for speaker driver (Class D)
Shutdown current < 1uA
Supply voltage
SVDD = 2.7V to 5.5V
HPVDD = 1.8V
1.8V to 2.7V control interface compatibility
20-bump CSP package
APPLICATIONS

Mobile handsets
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
Production Data, March 2012, Rev 4.2
[1] This product is protected by US Patents 7,622,984 and 7,626,445
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Copyright 2012 Wolfson Microelectronics plc
WM9093
Production Data
TABLE OF CONTENTS
DESCRIPTION ....................................................................................................... 1 FEATURES ............................................................................................................ 1 APPLICATIONS..................................................................................................... 1 BLOCK DIAGRAM ................................................................................................ 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION .......................................................................................... 4 ORDERING INFORMATION .................................................................................. 4 PIN DESCRIPTION ................................................................................................ 5 ABSOLUTE MAXIMUM RATINGS ........................................................................ 6 RECOMMENDED OPERATING CONDITIONS ..................................................... 6 ELECTRICAL CHARACTERISTICS ..................................................................... 7 TERMINOLOGY ............................................................................................................. 10 PERFORMANCE PLOTS ............................................................................................... 11 TYPICAL PERFORMANCE ................................................................................. 12 POWER CONSUMPTION .............................................................................................. 12 AUDIO SIGNAL PATHS DIAGRAM .................................................................... 13 CONTROL INTERFACE TIMING......................................................................... 14 DEVICE DESCRIPTION ...................................................................................... 15 INTRODUCTION ............................................................................................................ 15 INPUT SIGNAL PATH .................................................................................................... 16 LINE INPUTS............................................................................................................................................. 17 INPUT PGA ENABLE ................................................................................................................................ 17 INPUT PGA CONFIGURATION ................................................................................................................ 18 INPUT PGA VOLUME CONTROL ............................................................................................................. 18 OUTPUT SIGNAL PATH ................................................................................................ 21 OUTPUT SIGNAL PATHS ENABLE .......................................................................................................... 21 SPEAKER MIXER CONTROL ................................................................................................................... 22 SPEAKER OUTPUT VOLUME CONTROL................................................................................................ 23 SPEAKER BOOST MIXER CONTROL ..................................................................................................... 24 HEADPHONE MIXER CONTROL ............................................................................................................. 24 HEADPHONE OUTPUT VOLUME CONTROL .......................................................................................... 27 AUTOMATIC GAIN CONTROL (AGC) ........................................................................... 29 AGC CONTROL ........................................................................................................................................ 29 AGC ANTI-CLIP ......................................................................................................................................... 29 AGC POWER LIMITING ............................................................................................................................ 31 ANALOGUE OUTPUTS ................................................................................................. 33 SPEAKER OUTPUT CONFIGURATIONS ................................................................................................. 33 HEADPHONE OUTPUT CONFIGURATIONS ........................................................................................... 34 CLOCKING CONTROL .................................................................................................. 35 CONTROL INTERFACE................................................................................................. 37 CONTROL WRITE SEQUENCER.................................................................................. 40 INITIATING A SEQUENCE........................................................................................................................ 40 PROGRAMMING A SEQUENCE .............................................................................................................. 41 DEFAULT SEQUENCES ........................................................................................................................... 43 POWER SEQUENCES AND POP SUPPRESSION CONTROL .................................... 45 INPUT VMID CLAMPS .............................................................................................................................. 45 HEADPHONE ENABLE/DISABLE ............................................................................................................. 46 RECOMMENDED HEADPHONE START UP SEQUENCE....................................................................... 48 w
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WM9093
CHARGE PUMP ............................................................................................................. 49 DC SERVO ..................................................................................................................... 50 DC SERVO ENABLE AND START-UP...................................................................................................... 50 DC SERVO ACTIVE MODES .................................................................................................................... 52 DC SERVO READBACK ........................................................................................................................... 53 REFERENCE VOLTAGES AND MASTER BIAS ........................................................... 54 POWER MANAGEMENT ............................................................................................... 55 THERMAL SHUTDOWN ................................................................................................ 57 SOFTWARE RESET AND CHIP ID ............................................................................... 57 REGISTER MAP .................................................................................................. 58 REGISTER BITS BY ADDRESS .................................................................................... 60 APPLICATIONS INFORMATION ........................................................................ 77 RECOMMENDED EXTERNAL COMPONENTS ............................................................ 77 AUDIO INPUT PATHS ............................................................................................................................... 77 POWER SUPPLY DECOUPLING ............................................................................................................. 78 HEADPHONE OUTPUT PATH .................................................................................................................. 78 CLASS D SPEAKER CONNECTIONS ...................................................................................................... 78 RECOMMENDED EXTERNAL COMPONENTS DIAGRAM ...................................................................... 80 PCB LAYOUT CONSIDERATIONS ............................................................................... 81 CLASS D LOUDSPEAKER CONNECTION............................................................................................... 81 PACKAGE DIMENSIONS .................................................................................... 82 IMPORTANT NOTICE ......................................................................................... 83 ADDRESS: ..................................................................................................................... 83 REVISION HISTORY ........................................................................................... 84 w
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PIN CONFIGURATION
20-bump CSP package; Top View
ORDERING INFORMATION
ORDER CODE
TEMPERATURE RANGE
PACKAGE
-40C to +85C
20-ball W-CSP
(Pb-free, Tape and reel)
WM9093ECS/R
MOISTURE
SENSITIVITY LEVEL
PEAK SOLDERING
TEMPERATURE
MSL1
260C
Note:
Reel quantity = 5000
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PIN DESCRIPTION
PIN NO
NAME
TYPE
A1
HPR
Analogue Output
Right headphone output
A2
HPL
Analogue Output
Left headphone output
A3
CPVSS
Analogue Output
Charge pump negative rail decoupling pin
A4
CP
Analogue Output
Charge pump flyback capacitor pin
A5
CN
Analogue Output
Charge pump flyback capacitor pin
B1
BIAS
Analogue Output
Mid-rail voltage decoupling pin
B2
SDA
Digital Input / Output
Control interface data
B3
SCL
Digital Input
Control interface clock
B4
HPVDD
Supply
B5
CPVDD
Analogue Output
C1
IN1+
Analogue Input
IN1 positive analogue input
C2
IN1-
Analogue Input
IN1 negative analogue input
C3
IN3+
Analogue Input
Positive analogue input for bypass path
C4
GND
Supply
C5
OUT+
Analogue Output
D1
IN2+
Analogue Input
IN2 positive analogue input
D2
IN2-
Analogue Input
IN2 negative analogue input
D3
IN3-
Analogue Input
Negative analogue input for bypass path
D4
SVDD
Supply
D5
OUT-
Analogue Output
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DESCRIPTION
Analogue supply
Charge pump positive rail decoupling pin
Ground for speaker and charge pump
Speaker positive output
Speaker supply
Speaker negative output
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
Supply voltages (HPVDD)
Supply voltages (SVDD)
MIN
MAX
-0.3V
+2.5V
-0.3V
+7.0V
Voltage range digital inputs (SCL, SDA)
GND -0.3V
+3.3V
Voltage range analogue inputs
GND -0.3V
+3.3V
Operating temperature range, TA
-40ºC
+85ºC
Junction temperature, TJMAX
-40ºC
+150ºC
Storage temperature after soldering
-65ºC
+150ºC
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Charge Pump supply range
HPVDD
1.71
1.8
2.0
V
Speaker supply range
SVDD
2.7
3.6
5.5
V
Ground
GND
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0
V
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ELECTRICAL CHARACTERISTICS
Test Conditions
o
SVDD = 3.6V, HPVDD=1.8V, GND=0V, TA = +25 C, 1kHz signal, PGA gain = 0dB unless otherwise stated
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analogue Input Pin Maximum Signal Levels
Maximum Full-Scale Input Signal
Level for inputs IN1+/- and IN2+/-
Single-ended input
1.0
Vrms
Differential input
1.0
Vrms
Maximum Full-Scale Input Signal
Level for inputs IN3+/-
Differential input
0.56
Vrms
15
k
Analogue Input Pin Resistance
Line Input Resistance
Differential or Single- Ended Mode
8
10
IN1+/- and IN2+/Line Input Resistance
Speaker Boost = +12dB
42
IN3+/- Differential Mode
Speaker Boost = +9dB
60
k
Speaker Boost = +7.5dB
71
k
Note that gain is controlled by
SKOUTLBOOST[2:0] and
SPK_ATTN_FB
k
Speaker Boost = +6dB
85
k
Speaker Boost = +4.5dB
101
k
Speaker Boost = +3dB
120
k
Speaker Boost = +1.5dB
143
k
Speaker Boost = 0dB (SPK_ATTN_FB=0)
170
k
Speaker Boost = 0dB (SPK_ATTN_FB=1)
42
k
Speaker Boost = -3dB
60
k
Speaker Boost = -4.5dB
71
k
Speaker Boost = -6dB
85
k
Speaker Boost = -7.5dB
101
k
Speaker Boost = -9dB
120
k
Speaker Boost = -10.5dB
143
k
Speaker Boost = -12dB
170
k
Minimum Programmable Gain
-6
dB
Maximum Programmable Gain
+18
dB
Mute Attenuation
80
dB
45
dB
Minimum Programmable Gain
-57
dB
Maximum Programmable Gain
+6
dB
Guaranteed monotonic
1
dB
HPOUT1LVOL and HPOUT1RVOL
75
dB
SPKVOL
66
dB
Input Programmable Gain Amplifiers (PGAs) IN1A, IN1B, IN2A and IN2B
Common Mode Rejection Ratio
Differential Mode (217Hz input)
Output Programmable Gain Amplifiers (PGAs) SPKVOL, HPOUT1LVOL and HPOUT1RVOL
Programmable Gain Step Size
Mute Attenuation
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Test Conditions
o
SVDD = 3.6V, HPVDD=1.8V, GND=0V, TA = +25 C, 1kHz signal, PGA gain = 0dB unless otherwise stated
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SPKOUTLBOOST=111,SPK_ATTN_FB=0
11.5
12
12.5
dB
SPKOUTLBOOST=110,SPK_ATTN_FB=0
8.5
9
9.5
dB
SPKOUTLBOOST=101,SPK_ATTN_FB=0
7
7.5
8
dB
SPKOUTLBOOST=100,SPK_ATTN_FB=0
5.5
6
6.5
dB
SPKOUTLBOOST=011,SPK_ATTN_FB=0
4
4.5
5
dB
SPKOUTLBOOST=010,SPK_ATTN_FB=0
2.5
3
3.5
dB
SPKOUTLBOOST=001,SPK_ATTN_FB=0
1
1.5
2
dB
SPKOUTLBOOST=000,SPK_ATTN_FB=0
-0.75
0
0.75
dB
SPKOUTLBOOST=111,SPK_ATTN_FB=1
-0.75
0
0.75
dB
SPKOUTLBOOST=110,SPK_ATTN_FB=1
-3.5
-3
-2.5
dB
SPKOUTLBOOST=101,SPK_ATTN_FB=1
-5
-4.5
-4
dB
SPKOUTLBOOST=100,SPK_ATTN_FB=1
-6.5
-6
-5.5
dB
SPKOUTLBOOST=011,SPK_ATTN_FB=1
-8
-7.5
-7
dB
SPKOUTLBOOST=010,SPK_ATTN_FB=1
-9.5
-9
-8.5
dB
SPKOUTLBOOST=001,SPK_ATTN_FB=1
-11
-10.5
-10
dB
SPKOUTLBOOST=000,SPK_ATTN_FB=1
-12.5
-12
-11.5
dB
Speaker Output Programmable Gain SPKOUTLBOOST
Programmable Gain
Headphone Driver Audio Performance (RL = 16)
SNR (A-weighted)
96
dB
THD (PO=20mW)
Path from IN1+/- or IN2+/-
90
-82
dB
THD+N (PO=20mW)
-80
-72
dB
THD (PO=5mW)
-81
dB
THD+N (PO=5mW)
-79
dB
Crosstalk (L/R)
PSRR
DC Offset
Output Power
Minimum Headphone Resistance
Headphone Capacitance
Quiescent Current
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Single-ended mode
72
dB
HPVDD with 100mVpk-pk at 217Hz (Note 1)
82
dB
SVDD with 100mVpk-pk at 217Hz
85
Magnitude after DC Servo calibration
0.3
dB
2
mV
0.1% THD+N
31
mW
1% THD+N
34
mW
Normal operation
15

Device survival with load indefinitely applied
1

2
With zobel network
4
nF
mA
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Test Conditions
o
SVDD = 3.6V, HPVDD=1.8V, GND=0V, TA = +25 C, 1kHz signal, PGA gain = 0dB unless otherwise stated
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Speaker Driver Class D Audio Performance (RL=8 + 10H BTL)
SNR (A-weighted)
Speaker Boost = 6dB
92
dB
THD (PO=500mW)
Speaker Boost = 6dB
-75
dB
THD+N (PO=500mW)
Speaker Boost = 6dB
-73
dB
HPVDD with 100mVpk-pk at 217Hz (Note 1)
75
dB
SVDD with 100mVpk-pk at 217Hz
70
dB
5
mV
PSRR
82
DC Offset at Load
Efficiency
Output Power
Speaker Boost = 6dB, 0dBFS input
80
SVDD=5.0V, THD+N ≤ 1%,
89
%
1300
mW
950
mW
650
mW
3
mA
98
dB
Speaker Boost = 12dB
SVDD=4.2V, THD+N ≤ 1%,
Speaker Boost = 9dB
SVDD=3.6V, THD+N ≤ 1%,
Speaker Boost = 6dB
Quiescent Current
IN3 Differential Voice Bypass to Earpiece Driver Class AB (RL=8 + 10H BTL)
SNR (A-weighted)
0.56Vrms input with Speaker Boost = 0dB gain
THD (PO=30mW)
-68
dB
THD+N (PO=30mW)
-66
dB
HPVDD with 100mVpk-pk at 217Hz (Note 1)
90
dB
SVDD with 100mVpk-pk at 217Hz
85
dB
2
mV
160
mW
1
mA
PSRR
DC Offset at Load
Output Power
THD+N ≤ 1%
Quiescent Current
Leakage Currents
SVDD Leakage Current
HPVDD Leakage Current
VMID_ENA = 0, VMID_BUF_ENA = 0, and
0.2
A
1
A
TSHUT_ENA = 0
Analogue Reference Levels
BIAS Midrail Reference Voltage
-3%
HPVDD
+3%
V
500
s
/2
Charge Pump
Start-up Time
Supply Voltage
CPVDD
1.71
2.0
V
Normal mode
HPVDD
V
Low power mode
HPVDD
V
/2
CPVSS
Normal mode
-HPVDD
V
Low power mode
-HPVDD
V
/2
at 2V
1
2.2
F
CPVDD Capacitor
at 2V
2
2.2
F
CPVSS Capacitor
at 2V
2
2.2
F
Flyback Capacitor
(between CP and CN)
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Test Conditions
o
SVDD = 3.6V, HPVDD=1.8V, GND=0V, TA = +25 C, 1kHz signal, PGA gain = 0dB unless otherwise stated
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Input / Output
0.7 
HPVDD
Input HIGH Level
V
0.3 
HPVDD
Input LOW Level
Output HIGH Level
IOL=1mA
Output LOW Level
IOH=-1mA
0.7 
HPVDD
V
0.3 
HPVDD
Maximum Signal Level
2.7
Input capacitance
10
Input leakage
V
-0.9
V
V
pF
0.9
uA
Start-Up Time
Start up time
Speaker and Headphone
35
ms
Note 1: Total system PSRR with external DC-DC or LDO will be higher.
TERMINOLOGY
1.
Signal-to-Noise Ratio (dB) – SNR is a measure of the difference in level between the maximum full scale output signal
and the output with no input signal applied.
2.
Total Harmonic Distortion (dB) – THD is the level of the rms value of the sum of harmonic distortion products relative
to the amplitude of the measured output signal.
3.
Total Harmonic Distortion plus Noise (dB) – THD+N is the level of the rms value of the sum of harmonic distortion
products plus noise in the specified bandwidth relative to the amplitude of the measured output signal.
4.
Crosstalk (L/R) (dB) – left-to-right and right-to-left channel crosstalk is the measured signal level in the idle channel at
the test signal frequency relative to the signal level at the output of the active channel. The active channel is
configured and supplied with an appropriate input signal to drive a full scale output, with signal measured at the output
of the associated idle channel.
5.
Mute Attenuation – This is a measure of the difference in level between the full scale output signal and the output with
mute applied.
6.
All performance measurements carried out with 20kHz low pass filter, and where noted an A-weighted filter. Failure to
use such a filter will result in higher THD and lower SNR readings than are found in the Electrical Characteristics. The
low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values.
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PERFORMANCE PLOTS
WM9093
WM9093
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TYPICAL PERFORMANCE
POWER CONSUMPTION
Mode
Other settings
SVDD
(V)
HPVDD
(V)
iSVDD
(A)
iHPVDD
(A)
Total Power
(W)
3.6
0.0
0.2
0.0
0.72
3.6
1.8
0.2
2
4.3
Battery Leakage
All supplies except SVDD disabled
Shutdown Leakage
All supplies enabled
Mode
VMID_ENA = 0, VMID_BUF_ENA =
0,
Other settings
SPKKVDD LDO1VDD iSPKVDD iLDO1VDD Total Power
(V)
(V)
(mA)
(mA)
(mW)
Headphone
IN1+/IN1- Stereo to Headphone
16ohm load
3.6
1.8
0.00
3.36
6.0
IN2+/IN2- Differential to Speaker Class D
8ohm + 10H, +6dB boost
3.6
1.8
2.54
1.56
12.0
IN3+/IN3- Differential Bypass to Speaker Class
AB
8ohm + 10H, +6dB boost
3.6
1.8
0.97
0.28
4.0
Speaker
Notes:
1.
2.
Power in the load is included
All figures are quoted at TA = 25C
3.
All figures are quoted as quiescent current unless otherwise stated
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WM9093
AUDIO SIGNAL PATHS DIAGRAM
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CONTROL INTERFACE TIMING
Figure 1 Control Interface Timing
Test Conditions
o
SVDD = 3.6V, HPVDD=1.8V, GND=0V, TA = +25 C, 1kHz signal, PGA gain = 0dB unless otherwise stated
PARAMETER
SYMBOL
MIN
SCLK Frequency
TYP
MAX
UNIT
400
kHz
SCLK Low Pulse-Width
t1
1300
ns
SCLK High Pulse-Width
t2
600
ns
Hold Time (Start Condition)
t3
600
ns
Setup Time (Start Condition)
t4
600
ns
Data Setup Time
t5
100
SDAT, SCLK Rise Time
t6
300
ns
SDAT, SCLK Fall Time
t7
300
ns
Setup Time (Stop Condition)
t8
Data Hold Time
t9
Pulse width of spikes that will be suppressed
tps
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ns
600
0
ns
900
ns
5
ns
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DEVICE DESCRIPTION
INTRODUCTION
The WM9093 is an ultra-low power, high quality audio subsystem, including a headphone and
speaker driver. Its flexible architecture is designed to interface with a wide range of analogue
components. The small 2.0 x 2.5mm footprint makes it ideal for portable applications such as mobile
handsets.
Four flexible analogue input pins allow interfacing to up to four single-ended or two differential input
sources. Connection to an external voice CODEC, FM radio, melody IC or generic line input are all
fully supported. Signal routing to the output mixers provides maximum flexibility to support a wide
variety of usage modes. An additional differential ‘Voice Bypass’ path direct to the Earpiece output
driver is also included.
Three analogue output drivers are integrated, including a high quality Class D/AB switchable speaker
driver supporting 650mW output power at 3.6V in Class D mode. In Class AB mode, the driver is
suitable for driving an earpiece via the low-power differential ‘Voice Bypass’ path. A configurable
automatic gain control (AGC) is provided on the speaker output path, to prevent clipping or power
overload at the loudspeaker.
Ground-referenced stereo headphone outputs are also provided; these are powered from an
integrated Charge Pump, enabling high quality, power efficient headphone playback. The groundreferenced design reduces power consumption, improves bass response, and enables direct
headphone connection without any DC blocking capacitors. A DC Servo circuit is provided for DC
offset measurement and correction, thereby suppressing pops and reducing power consumption.
Internal differential signal routing and amplifier configurations have been optimised to provide the
lowest possible power consumption for a wide range of usage scenarios, including voice calls and
music playback. The speaker drivers offer low leakage and high PSRR; this enables direct connection
to a Lithium battery. The speaker driver provides eight levels of boost gain to allow output signal
levels to be maximised for many commonly-used SVDD/HPVDD combinations.
An integrated oscillator is provided to support all the WM9093 clocking requirements, including the
Class D switching clock, Headphone Charge Pump and DC Servo control.
The WM9093 is controlled via a standard 2-wire I2C interface, providing full software control of all
features, together with device register readback. The interface provides support for I/O voltages up to
2.7V. An integrated Control Write Sequencer enables automatic scheduling of control sequences;
commonly-used signal configurations may be selected using ready-programmed sequences,
including time-optimised control of the WM9093 pop suppression features. Unused circuitry can be
disabled under software control, in order to save power; low leakage currents enable extended
standby/off time in portable battery-powered applications.
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INPUT SIGNAL PATH
The WM9093 three differential analogue input channels, configurable in a number of combinations:

Up to two differential line inputs to analogue mixers

Up to four single-ended line inputs to analogue mixers

One differential line routed directly to the Speaker output
These inputs may be mixed together or independently routed to different combinations of output
drivers. The WM9093 input signal paths and control registers are illustrated in Figure 2.
Figure 2 Control Registers for Input Signal Path
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LINE INPUTS
All of the analogue input pins are designed as line inputs. Four of these pins (IN1+/- and IN2+/-) can
be configured as single-ended or differential inputs, with flexible routing options and gain controls
suitable for many different usage cases. The remaining inputs (IN3+ and IN3-) provide a low-power
signal path direct to the speaker output driver.
The line input pins IN1+ and IN1- provide a differential input path to PGA IN1A. These inputs provide
a high gain path if required for low input signal levels. If required, these input pins can be configured
as two separate single-ended inputs to PGAs IN1A and IN1B respectively. Single ended configuration
is selected by writing a 0 to the IN1_DIFF register bit.
The line input pins IN2+ and IN2- provide a differential input path to PGA IN2A. These inputs provide
a high gain path if required for low input signal levels. If required, these input pins can be configured
as two separate single-ended inputs to PGAs IN2A and IN2B respectively. Single ended configuration
is selected by writing a 0 to the IN2_DIFF register bit.
The line input pins IN3+ and IN3- provide a mono differential ‘voice bypass’ input (eg. From an
external voice CODEC) to the speaker drivers. This provides a low-power option, bypassing the input
and output mixer circuits.
Signal path configuration to the input PGAs is detailed later in this section. Signal path configuration
to the output mixers and speaker mixers is described in “Output Signal Path”.
Note that, by default, the analogue input pins are clamped to VMID in order to prevent audible pops
caused by enabling the input paths. When one or more analogue input path is in use, the respective
input clamp(s) must be disabled using the register bits described under “Power Sequences and Pop
Suppression Control”.
INPUT PGA ENABLE
The Input PGAs are enabled using register bits IN1A_ENA, IN1B_ENA, IN2A_ENA and IN2B_ENA,
as described in Table 1. The Input PGAs must be enabled for line input on the respective input pins.
Note that, for differential input on IN1+ and IN1-, it is not necessary to enable PGA IN1B.
Note that, for differential input on IN2+ and IN2-, it is not necessary to enable PGA IN2B.
REGISTER
ADDRESS
R2 (02h)
Power
Management
(2)
BIT
7
LABEL
IN1A_ENA
DEFAULT
0
DESCRIPTION
IN1A Input PGA Enable
0 = Disabled
1 = Enabled
6
IN1B_ENA
0
IN1B Input PGA Enable
0 = Disabled
1 = Enabled
(Note this is only required for single-ended
input on the IN1- pin)
5
IN2A_ENA
0
IN2A Input PGA Enable
0 = Disabled
1 = Enabled
4
IN2B_ENA
0
IN2B Input PGA Enable
0 = Disabled
1 = Enabled
(Note this is only required for single-ended
input on the IN2- pin)
Table 1 Input PGA Enable
For normal operation of the input PGAs, the reference voltage VMID and the bias current must also
be enabled. See “Reference Voltages and Master Bias” for details of the associated controls
VMID_RES and BIAS_ENA.
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INPUT PGA CONFIGURATION
The input PGAs can be configured in single-ended mode or differential mode, using the IN1_DIFF
and IN2_DIFF register bits described in Table 2.
In single-ended mode, an input pin is routed to each individual PGA. In differential mode, a pair of
input pins is routed to PGA IN1A or IN2A.
REGISTER
ADDRESS
R22 (16h)
BIT
1
LABEL
DEFAULT
IN1_DIFF
1
IN1 Line
Control
R23 (17h)
DESCRIPTION
PGA IN1A and IN1B configuration
0 = Single-ended mode
1 = Differential mode
1
IN2_DIFF
1
IN2 Line
Control
PGA IN2A and IN2B configuration
0 = Single-ended mode
1 = Differential mode
Table 2 Input PGA Configuration
INPUT PGA VOLUME CONTROL
Each of the four input PGAs has an independently controlled gain range of -6dB to +18dB. The gains
on the inverting and non-inverting inputs to the PGAs are always equal. Each Input PGA can be
independently muted using the PGA mute bits as described in Table 3.
Note that, in differential mode, PGA IN1B and/or IN2B is not used, and the volume control is provided
on IN1A only (for pins IN1+ and IN1-) or IN2A only (for pins IN2+ and IN2-).
Note also that in single-ended mode there is an additional +6dB gain which must be factored into the
volume control. For example a 0dB volume setting provides 0dB gain in differential mode, but in
single-ended mode it will apply +6dB gain. Therefore in single-ended mode the input PGAs have a
controlled gain range of 0dB to +24dB
To prevent “zipper noise”, a zero-cross function is provided on the input PGAs. When this feature is
enabled, volume updates will not take place until a zero-crossing is detected. In the case of a long
period without zero-crossings, a timeout function is provided. When the zero-cross function is
enabled, the volume will update after the timeout period if no earlier zero-cross has occurred. The
timeout clock is enabled using TOCLK_ENA, the timeout period is set by TOCLK_RATE. See
“Clocking Control” for more information on these fields.
The IN1_VU and IN2_VU bits control the loading of the input PGA volume data. When IN1_VU and
IN2_VU are set to 0, the PGA volume data will be loaded into the respective control register, but will
not actually change the gain setting. The IN1A and IN1B volume settings are both updated when a 1
is written to IN1_VU; the IN2A and IN2B volume settings are both updated when a 1 is written to
IN2_VU. This makes it possible to update the gain of two single-ended input paths simultaneously.
Note that, in differential input modes, the Volume Update control bits IN1_VU and/or IN2_VU should
always be set to 1.
The Input PGA Volume Control register fields are described in Table 3.
REGISTER
ADDRESS
R24 (18h)
BIT
8
LABEL
IN1_VU
DEFAULT
N/A
DESCRIPTION
IN1 Volume Update
Writing a 1 to this bit will cause IN1A and
IN1B input PGA volumes to be updated
simultaneously
IN1 Line Input
A Volume
7
IN1A_MUTE
1
IN1A PGA Mute
0 = Un-Mute
1 = Mute
6
IN1A_ZC
0
IN1A PGA Zero Cross Control
0 = Change gain immediately
1 = Change gain on zero cross only
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REGISTER
ADDRESS
BIT
LABEL
2:0
IN1A_VOL
[2:0]
DEFAULT
011
DESCRIPTION
IN1A Volume (differential mode)
000 = -6dB
001 = -3.5dB
010 = 0dB
011 = +3.5dB
100 = +6dB
101 = +12dB
110 = +18dB
111 = +18dB
IN1A Volume (single-ended mode)
000 = 0dB
001 = +2.5dB
010 = +6dB
011 = +9.5dB
100 = +12dB
101 = +18dB
110 = +24dB
111 = +24dB
R25 (19h)
8
IN1_VU
N/A
IN1 Line Input
B Volume
IN1 Volume Update
Writing a 1 to this bit will cause IN1A and
IN1B input PGA volumes to be updated
simultaneously
7
IN1B_MUTE
1
IN1B PGA Mute
0 = Un-Mute
1 = Mute
6
IN1B_ZC
0
IN1B PGA Zero Cross Control
0 = Change gain immediately
1 = Change gain on zero cross only
2:0
IN1B_VOL
[2:0]
011
IN1B Volume (differential mode)
000 = -6dB
001 = -3.5dB
010 = 0dB
011 = +3.5dB
100 = +6dB
101 = +12dB
110 = +18dB
111 = +18dB
IN1B Volume (single-ended mode)
000 = 0dB
001 = +2.5dB
010 = +6dB
011 = +9.5dB
100 = +12dB
101 = +18dB
110 = +24dB
111 = +24dB
R26 (1Ah)
IN2 Line Input
A Volume
w
8
IN2_VU
N/A
Input PGA Volume Update
Writing a 1 to this bit will cause IN2A and
IN2B input PGA volumes to be updated
simultaneously
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
7
IN2A_MUTE
1
DESCRIPTION
IN2A PGA Mute
0 = Un-Mute
1 = Mute
6
IN2A_ZC
0
IN2A PGA Zero Cross Control
0 = Change gain immediately
1 = Change gain on zero cross only
2:0
IN2A_VOL
[2:0]
011
IN2A Volume (differential mode)
000 = -6dB
001 = -3.5dB
010 = 0dB
011 = +3.5dB
100 = +6dB
101 = +12dB
110 = +18dB
111 = +18dB
IN2A Volume (single-ended mode)
000 = 0dB
001 = +2.5dB
010 = +6dB
011 = +9.5dB
100 = +12dB
101 = +18dB
110 = +24dB
111 = +24dB
R27 (1Bh)
8
IN2_VU
N/A
Input PGA Volume Update
Writing a 1 to this bit will cause IN2A and
IN2B input PGA volumes to be updated
simultaneously
IN2 Line Input
B Volume
7
IN2B_MUTE
1
IN2B PGA Mute
0 = Un-Mute
1 = Mute
6
IN2B_ZC
0
IN2B PGA Zero Cross Control
0 = Change gain immediately
1 = Change gain on zero cross only
2:0
IN2B_VOL
[2:0]
011
IN2B Volume (differential mode)
000 = -6dB
001 = -3.5dB
010 = 0dB
011 = +3.5dB
100 = +6dB
101 = +12dB
110 = +18dB
111 = +18dB
IN2B Volume (d single-ended mode)
000 = 0dB
001 = +2.5dB
010 = +6dB
011 = +9.5dB
100 = +12dB
101 = +18dB
110 = +24dB
111 = +24dB
Table 3 Input PGA Volume Control
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OUTPUT SIGNAL PATH
The WM9093 output mixers provide a high degree of flexibility, allowing configurable operation of
multiple signal paths through the device to a variety of analogue outputs. The outputs comprise a
ground referenced headphone driver and Class D/AB loudspeaker driver. See “Analogue Outputs” for
further details of these outputs.
The WM9093 output signal paths and control registers are illustrated in Figure 3.
Figure 3 Control Registers for Output Signal Path
OUTPUT SIGNAL PATHS ENABLE
The output mixers and drivers can be independently enabled and disabled as described in Table 4.
See “Power Sequences and Pop Suppression Control” for details of additional control bits relating to
the Headphone Output configuration.
Note that, when using the ‘Voice Bypass’ inputs on pins IN3+ and IN3-, these signals can be routed to
the Speaker output without enabling the Speaker mixer or the Speaker PGA. This provides a lowpower configuration, bypassing the input and output mixer circuits.
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REGISTER
ADDRESS
R1 (01h)
Power
Management
(1)
BIT
12
LABEL
SPKOUTL_ENA
DEFAULT
0
DESCRIPTION
Speaker Output Enable
0 = Disabled
1 = Enabled
9
HPOUT1L_ENA
0
Headphone Output (HPL) input
stage enable
0 = Disabled
1 = Enabled
8
HPOUT1R_ENA
0
Headphone Output (HPR) input
stage enable
0 = Disabled
1 = Enabled
R3 (03h)
Power
Management
(3)
8
SPKLVOL_ENA
0
Speaker PGA Enable
0 = Disabled
1 = Enabled
5
MIXOUTL_ENA
0
MIXOUTL Headphone Mixer Enable
0 = Disabled
1 = Enabled
4
MIXOUTR_ENA
0
MIXOUTR Headphone Mixer
Enable
0 = Disabled
1 = Enabled
3
SPKMIX_ENA
0
SPKMIX Speaker Mixer Enable
0 = Disabled
1 = Enabled
Table 4 Output Signal Paths Enable
SPEAKER MIXER CONTROL
The signal path configuration registers for the Speaker Mixer are described in Table 5. Each of the
input PGAs IN1A, IN1B, IN2A and IN2B is independently selectable as an input to the Speaker Mixer.
Care should be taken when enabling more than one path to a Speaker Mixer in order to avoid
clipping. The gain of each input path is adjustable using a selectable volume control in each path to
facilitate this.
The Speaker Mixer output can be muted or enabled using the SPKMIX_MUTE register bit. The
Speaker Mixer volume is also controlled by the Speaker Output PGA, as defined in Table 6.
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REGISTER
ADDRESS
R54 (36h)
BIT
6
LABEL
DEFAULT
IN1A_TO_SPKMIX
0
Speaker Mixer
DESCRIPTION
IN1A to SPKMIX enable
0 = Disabled
1 = Enabled
4
IN1B_TO_SPKMIX
0
IN1B to SPKMIX enable
0 = Disabled
1 = Enabled
2
IN2A_TO_SPKMIX
0
IN2A to SPKMIX enable
0 = Disabled
1 = Enabled
0
IN2B_TO_SPKMIX
0
IN2B to SPKMIX enable
0 = Disabled
1 = Enabled
R34 (22h)
8
SPKMIX_MUTE
1
SPKMIXL
Attenuation
SPKMIX Output mute
0 = Un-Mute
1 = Mute
7:6
IN1A_SPKMIX_VOL
00
IN1A to SPKMIX volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
5:4
IN1B_SPKMIX_VOL
00
IN1B to SPKMIX volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
3:2
IN2A_SPKMIX_VOL
00
IN2A to SPKMIX volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
1:0
IN2B_SPKMIX_VOL
[1:0]
00
IN2B to SPKMIX volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
Table 5 Speaker Mixer (SPKMIX) Control
SPEAKER OUTPUT VOLUME CONTROL
The speaker output PGA controls are shown in Table 6.
Note that the Speaker Output PGA is bypassed when the ‘Voice Bypass’ path is selected as the
speaker output source, as described in the following section (“Speaker Boost Mixer Control”). In this
case, the SPKMIX mixer and the Speaker Output PGA can be disabled, providing a low-power signal
path for ‘Voice Bypass’ applications.
A zero-cross function is provided on the speaker output PGA. Note that the timeout clock TOCLK
must be enabled when using the zero-cross function. See “Clocking Control” for more information on
the TOCLK control fields.
The SPKOUT_VU bit controls the loading of the speaker PGA volume data. This bit should be set to
1 whenever the SPKOUTL_VOL register is updated.
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REGISTER
ADDRESS
R38 (26h)
BIT
8
LABEL
SPKOUT_VU
DEFAULT
N/A
Speaker
Volume Left
DESCRIPTION
Speaker Output PGA Volume
Update
Writing a 1 to this bit will update the
SPKOUTL volume.
7
SPKOUTL_ZC
0
Speaker Output PGA Zero Cross
Control
0 = Change gain immediately
1 = Change gain on zero cross only
6
SPKOUTL_MUTE
0
Speaker Output PGA Mute
0 = Un-mute
1 = Mute
5:0
SPKOUTL_VOL [5:0]
39h
(0dB)
Speaker Output PGA Volume
-57dB to +6dB in 1dB steps
(See Table 11 for output PGA
volume control range)
Table 6 Speaker Output PGA Control
SPEAKER BOOST MIXER CONTROL
The Class D/AB speaker driver has its own boost mixer which performs a dual role.
The boost mixer allows the output from the speaker mixer or from the ‘Voice Bypass’ path to be
routed to the speaker driver. The ‘Voice Bypass’ path is the differential input, IN3+/IN3-, routed
directly to the speaker driver, providing a low power differential path from baseband voice to
loudspeakers.
It is recommended that no more than one of the available signal paths is enabled in the speaker boost
mixer at any time. The signal path configuration registers for the speaker boost mixer are described in
Table 7.
The second function of the speaker boost mixer is to provide an additional AC gain (boost) function to
shift signal levels between the HPVDD and SVDD voltage domains for maximum output power. The
AC gain (boost) function is described in the “Analogue Outputs” section.
REGISTER
ADDRESS
R36 (24h)
BIT
5
LABEL
IN3_TO_SPKOUTL
DEFAULT
0
SPKOUT
Mixers
DESCRIPTION
Voice Bypass (IN3 Differential) to
Speaker Output enable
0 = Disabled
1 = Enabled
4
SPKMIXL_TO_SPKOU
TL
1
SPKMIX to Speaker Output enable
0 = Disabled
1 = Enabled
Table 7 Speaker Boost Mixer Control
HEADPHONE MIXER CONTROL
The Headphone Mixer configuration registers are described in Table 8 for the Left Channel
(MIXOUTL) and Table 9 for the Right Channel (MIXOUTR). Each of the input PGAs IN1A, IN1B, IN2A
and IN2B is independently selectable as an input to each of the Headphone Mixers.
Care should be taken when enabling more than one path to a Headphone Mixer in order to avoid
clipping. The gain of each input path is adjustable using a selectable volume control in each path to
facilitate this.
The Headphone Mixer outputs can be muted or enabled using the MIXOUTL_MUTE and
MIXOUTR_MUTE register bits. The Headphone Mixer volume is also controlled by the Headphone
Output PGAs, as defined in Table 10.
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REGISTER
ADDRESS
R45 (2Dh)
BIT
6
LABEL
IN1A_TO_MIXOUTL
DEFAULT
0
Output Mixer1
DESCRIPTION
IN1A to MIXOUTL enable
0 = Disabled
1 = Enabled
4
IN1B_TO_MIXOUTL
0
IN1B to MIXOUTL enable
0 = Disabled
1 = Enabled
2
IN2A_TO_MIXOUTL
0
IN2A to MIXOUTL enable
0 = Disabled
1 = Enabled
0
IN2B_TO_MIXOUTL
0
IN2B to MIXOUTL enable
0 = Disabled
1 = Enabled
R47 (2Fh)
8
MIXOUTL_MUTE
1
Output Mixer3
MIXOUTL Output mute
0 = Un-Mute
1 = Mute
7:6
IN1A_MIXOUTL_VOL
[1:0]
00
IN1A to MIXOUTL volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
5:4
IN1B_MIXOUTL_VOL
[1:0]
00
IN1B to MIXOUTL volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
3:2
IN2A_MIXOUTL_VOL
[1:0]
00
IN2A to MIXOUTL volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
1:0
IN2B_MIXOUTL_VOL
[1:0]
00
IN2B to MIXOUTL volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
Table 8 Left Output Mixer (MIXOUTL) Control
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REGISTER
ADDRESS
R46 (2Eh)
BIT
6
LABEL
IN1A_TO_MIXOUTR
DEFAULT
0
Output Mixer2
DESCRIPTION
IN1A to MIXOUTR enable
0 = Disabled
1 = Enabled
4
IN1B_TO_MIXOUTR
0
IN1B to MIXOUTR enable
0 = Disabled
1 = Enabled
2
IN2A_TO_MIXOUTR
0
IN2A to MIXOUTR enable
0 = Disabled
1 = Enabled
0
IN2B_TO_MIXOUTR
0
IN2B to MIXOUTR enable
0 = Disabled
1 = Enabled
R48 (30h)
8
MIXOUTR_MUTE
1
Output Mixer4
MIXOUTR Output mute
0 = Un-Mute
1 = Mute
7:6
IN1A_MIXOUTR_VOL
[1:0]
00
IN1A to MIXOUTR volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
5:4
IN1B_MIXOUTR_VOL
[1:0]
00
IN1B to MIXOUTR volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
3:2
IN2A_MIXOUTR_VOL
[1:0]
00
IN2A to MIXOUTR volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
1:0
IN2B_MIXOUTR_VOL
[1:0]
00
IN2B to MIXOUTR volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
Table 9 Right Output Mixer (MIXOUTR) Control
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HEADPHONE OUTPUT VOLUME CONTROL
The headphone output PGA controls are shown in Table 10.
The HPOUT1_VU bits control the loading of the headphone PGA volume data. When HPOUT1_VU is
set to 0, the volume control data will be loaded into the respective control register, but will not actually
change the gain setting. The headphone PGA volume settings are both updated when a 1 is written to
either HPOUT1_VU bit. This makes it possible to update the gain of the left and right output paths
simultaneously.
A zero-cross function is provided on the headphone output PGAs. Note that the timeout clock TOCLK
must be enabled when using the zero-cross function. See “Clocking Control” for more information on
the TOCLK control fields.
When the zero-cross function is enabled (using HPOUT1L_ZC or HPOUT1R_ZC), it will only become
effective after the respective PGA gain (or mute) has been changed in two or more subsequent
register writes.
To guarantee zero cross functionality, it is recommended to enable zero cross and toggle the
respective mute (HPOUT1L_MUTE or HPOUT1R_MUTE) before enabling the headphone output.
Alternatively, the zero-cross function can be ensured by updating the PGA gain register
(HPOUT1L_VOL or HPOUT1R_VOL) in two successive register writes - decrementing then
incrementing the setting by 1 gain step – after the zero-cross enable bits have been set.
REGISTER
ADDRESS
R28 (1Ch)
BIT
8
LABEL
HPOUT1_VU
DEFAULT
N/A
Left Output
Volume
DESCRIPTION
Headphone Output PGA Volume
Update
Writing a 1 to this bit will update
HPOUT1LVOL and HPOUT1RVOL
volumes simultaneously.
7
HPOUT1L_ZC
0
Left Headphone Output PGA Zero
Cross Control
0 = Change gain immediately
1 = Change gain on zero cross only
6
HPOUT1L_MUTE
0
Left Headphone Output PGA Mute
0 = Un-mute
1 = Mute
5:0
HPOUT1L_VOL [5:0]
2Dh
(-12dB)
Left Headphone Output PGA
Volume
-57dB to +6dB in 1dB steps
(See Table 11 for output PGA
volume control range)
R29 (1Dh)
8
HPOUT1_VU
N/A
Right Output
Volume
Headphone Output PGA Volume
Update
Writing a 1 to this bit will update
HPOUT1LVOL and HPOUT1RVOL
volumes simultaneously.
7
HPOUT1R_ZC
0
Right Headphone Output PGA Zero
Cross Control
0 = Change gain immediately
1 = Change gain on zero cross only
6
HPOUT1R_MUTE
0
Right Headphone Output PGA Mute
0 = Un-mute
1 = Mute
5:0
HPOUT1R_VOL [5:0]
2Dh
(-12dB)
Right Headphone Output PGA
Volume
-57dB to +6dB in 1dB steps
(See Table 11 for output PGA
volume control range)
Table 10 Headphone Output PGA Control
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PGA GAIN SETTING
VOLUME (dB)
PGA GAIN SETTING
VOLUME (dB)
0h
-57
20h
-25
1h
-56
21h
-24
2h
-55
22h
-23
3h
-54
23h
-22
4h
-53
24h
-21
5h
-52
25h
-20
6h
-51
26h
-19
7h
-50
27h
-18
8h
-49
28h
-17
9h
-48
29h
-16
Ah
-47
2Ah
-15
Bh
-46
2Bh
-14
Ch
-45
2Ch
-13
Dh
-44
2Dh
-12
Eh
-43
2Eh
-11
Fh
-42
2Fh
-10
10h
-41
30h
-9
11h
-40
31h
-8
12h
-39
32h
-7
13h
-38
33h
-6
14h
-37
34h
-5
15h
-36
35h
-4
16h
-35
36h
-3
17h
-34
37h
-2
18h
-33
38h
-1
19h
-32
39h
0
1Ah
-31
3Ah
+1
1Bh
-30
3Bh
+2
1Ch
-29
3Ch
+3
1Dh
-28
3Dh
+4
1Eh
-27
3Eh
+5
1Fh
-26
3Fh
+6
Table 11 Output PGA Volume Range
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AUTOMATIC GAIN CONTROL (AGC)
The Speaker Output PGA incorporates an Automatic Gain Control (AGC) circuit. This feature
provides an automatic reduction in the speaker path gain in order to prevent clipping or power
overload at the loudspeaker. The AGC circuit provides two separate detection mechanisms to identify
clipping or power overload respectively. Each of these two mechanisms can be independently
configured to suit the loudspeaker characteristics and the desired audio response. The two control
mechanisms operate together to provide a flexible and effective automatic gain control feature.
Note that the ‘Voice Bypass’ path is routed directly to the speaker output driver and is not affected by
the Speaker Output PGA or by the AGC function.
AGC CONTROL
AGC is enabled by setting the AGC_ENA register bit, as defined in Table 12.
The AGC can provide attenuation in the speaker output path – note that it can never apply additional
gain to boost the signal level. The maximum extent of the AGC attenuation can be controlled by
setting the AGC_MINGAIN register. This field sets the lowest gain level that can be selected by the
AGC under signal clipping or power limiting conditions.
When the signal conditions trigger the AGC to apply attenuation, the Speaker PGA gain is controlled
automatically by the AGC. In order to prevent ‘zipper noise’ from the gain adjustment, the PGA gain is
only changed when a signal zero-cross is detected. When AGC_RAMP = 1, then the gain adjustment
is restricted to a single gain step on each zero-cross. When AGC_RAMP = 0, then multiple gain steps
may be applied, if necessary, on each zero-cross.
Selecting single gain steps only will result in a more gradual gain adjustment, but the AGC may also
be slower to remove signal clipping under this selection. Note that the AGC attenuation has a step
size of 0.5dB, providing a high resolution of signal level control.
REGISTER
ADDRESS
R3 (03h)
BIT
14
LABEL
AGC_ENA
DEFAULT
0
Power
Management
(3)
R100 (64h)
DESCRIPTION
AGC Enable
0 = Disabled
1 = Enabled
8
AGC_RAMP
0
AGC Ramp Control
Selects how the AGC gain
adjustment is applied
AGC Control
2
0 = Multiple gains steps per zerocross
1 = Single gain step per zero-cross
5:0
AGC_MINGAIN [5:0]
00000
AGC Minimum Gain
-57dB to +6dB in 1dB steps
(See Table 11 for AGC Minimum
Gain range)
Table 12 AGC Control
AGC ANTI-CLIP
The AGC incorporates two mechanisms for monitoring the signal conditions. One of these is the anticlip threshold detection. The anti-clip function measures the speaker supply voltage, SVDD, and
compares this with the output signal level. The difference between these voltages is referred to as the
headroom; to avoid clipping, the signal level must always be less than the supply voltage. If the
headroom is small (ie. The signal level is very close to the supply voltage), then clipping and distortion
will occur.
The anti-clip function can be disabled using the AGC_CLIP_ENA bit. It is enabled by default.
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The headroom threshold at which the AGC will apply attenuation is set using the AGC_CLIP_THR
register. Values in the range -200mV to 800mV can be selected. When the signal headroom is
300mV, the distortion (THD) is approximately 1%. Therefore, if the anti-clip threshold is set to 300mV,
then the AGC would aim to limit the distortion to be no worse than 1% under maximum signal
conditions. Selecting a larger headroom threshold will avoid clipping across a wider range of
operating conditions.
When the AGC applies signal attenuation triggered by the anti-clip threshold, the signal gain is
reduced at a rate that is set by the AGC_CLIP_ATK register. When the anti-clip threshold is no longer
met (due to the signal level reduction), then the AGC increases the signal gain at a rate set by the
AGC_CLIP_DCY register.
Note that, when the anti-clip and power limiting thresholds are both triggered concurrently, then the
signal gain is reduced at the rate set by the AGC_CLIP_ATK register and is increased at the rate set
by AGC_PWR_DCY. These fields are defined in Table 13 and Table 14 respectively.
REGISTER
ADDRESS
R98 (62h)
BIT
15
LABEL
AGC_CLIP_ENA
DEFAULT
1
AGC Control
0
DESCRIPTION
Enable AGC Anti-Clip Mode
0 = Disabled
1 = Enabled
11:8
AGC_CLIP_THR [3:0]
0110
AGC Anti-Clip Threshold
Sets the headroom between
SPKPGA output and SVDD at
which Anti-Clip limiting will be
applied
0000 = -200mV
0001 = -150mV
0010 = -100mV
0011 = -50mV
0100 = 0mV
0101 = 50mV
0110 = 100mV
0111 = 150mV
1000 = 200mV
1001 = 250mV
1010 = 300mV
1011 = 400mV
1100 = 500mV
1101 = 600mV
1110 = 700mV
1111 = 800mV
6:4
AGC_CLIP_ATK [2:0]
100
AGC Anti-Clip Attack Rate
Sets the rate of AGC gain reduction
when clipping is detected
000 = 0.6ms/6dB
001 = 5.4ms/6dB
010 = 10.2ms/6dB
011 = 15.0ms/6dB
100 = 19.8ms/6dB
101 = 24.6ms/6dB
110 = 29.4ms/6dB
111 = 34.1ms/6dB
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REGISTER
ADDRESS
BIT
LABEL
DEFAULT
2:0
AGC_CLIP_DCY [2:0]
000
DESCRIPTION
AGC Anti-Clip Decay Rate
Sets the rate of AGC gain
increments after a period of clipping
000 = 120ms/6dB
001 = 480ms/6dB
010 = 820ms/6dB
011 = 1170ms/6dB
100 = 1640ms/6dB
101 = 2050ms/6dB
110 = 2730ms/6dB
111 = 4100ms/6dB
Table 13 AGC Anti-Clip Control
AGC POWER LIMITING
The second mechanism used by the AGC to monitor signal conditions is the power limit function. The
speaker output voltage is measured, and the corresponding power output is determined. The power
limiting function can be disabled using the AGC_PWR_ENA bit. It is enabled by default.
The power output threshold at which the AGC will apply attenuation is set using the AGC_PWR_THR
register. Power levels in the range 300mW and 1050mW can be selected. Note that these are RMS
power levels, assuming an 8 speaker.
The power output threshold is also controlled by the AGC_PWR_AVG register. When
AGC_PWR_AVG = 1, then the AGC responds to the RMS power level as quoted above. When
AGC_PWR_AVG = 0, then the AGC responds to the instantaneous voltage at the speaker output.
Selecting the RMS power level is recommended, as this represents the average signal level.
When the AGC applies signal attenuation triggered by the power limit threshold, the signal gain is
reduced at a rate that is set by the AGC_PWR_ATK register. When the power limit threshold is no
longer met (due to the signal level reduction), then the AGC increases the signal gain at a rate set by
the AGC_PWR_DCY register.
Note that, when the anti-clip and power limiting thresholds are both triggered concurrently, then the
signal gain is reduced at the rate set by the AGC_CLIP_ATK register and is increased at the rate set
by AGC_PWR_DCY. These fields are defined in Table 13 and Table 14 respectively.
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REGISTER
ADDRESS
R99 (63h)
BIT
15
LABEL
AGC_PWR_ENA
DEFAULT
1
DESCRIPTION
Enable AGC Power Limit Mode
0 = Disabled
AGC Control
1
1 = Enabled
12
AGC_PWR_AVG
0
AGC Power Measurement mode
0 = Instantaneous power
1 = RMS power
11:8
AGC_PWR_THR [2:0]
0000
AGC Power Limit Threshold
Sets the output level at which
Power limiting will be applied.
Assumes RMS power mode and
8ohm speaker.
0000 = 300mW
0001 = 350mW
0010 = 400mW
0011 = 450mW
0100 = 500mW
0101 = 550mW
0110 = 600mW
0111 = 650mW
1000 = 700mW
1001 = 750mW
1010 = 800mW
1011 = 850mW
1100 = 900mW
1101 = 950mW
1110 = 1000mW
1111 = 1050mW
6:4
AGC_PWR_ATK [2:0]
000
AGC Power Limiting Attack Rate
Sets the rate of AGC gain reduction
when power limiting is applied
000 = 120ms/6dB
001 = 480ms/6dB
010 = 840ms/6dB
011 = 1200ms/6dB
100 = 1680ms/6dB
101 = 2040ms/6dB
110 = 2760ms/6dB
111 = 4080ms/6dB
2:0
AGC_PWR_DCY [2:0]
000
AGC Power Limiting Decay Rate
Sets the rate of AGC gain
increments after a period of power
limiting
000 = 1080ms/6dB
001 = 1200ms/6dB
010 = 1320ms/6dB
011 = 1680ms/6dB
100 = 2040ms/6dB
101 = 2760ms/6dB
110 = 4080ms/6dB
111 = 8160ms/6dB
Table 14 AGC Power Limit Control
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ANALOGUE OUTPUTS
The speaker, headphone and earpiece outputs are highly configurable and may be used in many
different ways.
SPEAKER OUTPUT CONFIGURATIONS
The speaker output can be driven by the speaker mixer, SPKMIX, or by the low power differential
‘Voice Bypass’ path from IN3+ and IN3-. Fine volume control is available on the speaker mixer path
using the Speaker Output PGA. A boost function is available on the speaker mixer path and on the
Voice Bypass path. See the “Output Signal Path” section for more information on the speaker mixing
options.
The speaker output operates in a BTL configuration in Class AB or Class D amplifier modes; the
selected mode is determined by the SPKOUT_CLASSAB_MODE register bit, as defined in Table 15.
When the speaker mixer (SPKMIX) output is selected as the speaker output source, then Class D
mode should be selected in the output driver. When the ‘Voice Bypass’ signal is selected as the
speaker output source, then Class AB mode should be selected. Note that only one of these signal
paths should be selected at any time – see “Speaker Boost Mixer Control”.
A selectable 12dB attenuation is available at the speaker output driver in Class AB mode. This is
controlled using the SPK_ATTN_FB register. The 12dB attenuation can be used in conjunction with
the boost (gain) described below to provide a wider range of signal level control for the ‘Voice Bypass’
path. Note that this bit has no effect in Class D mode.
Eight levels of signal boost are provided in order to deliver maximum output power for many
commonly-used SVDD/HPVDD combinations. These boost options are available in both Class AB
and Class D modes. The boost level from 0dB to +12dB is selected using the SPKOUTL_BOOST
register field. To prevent pop noise, the SPKOUTL_BOOST register should not be modified while the
speaker output is enabled. Figure 4 illustrates the speaker output and the mixing and gain/boost
options available.
Ultra-low leakage and high PSRR allow the speaker supply SVDD to be directly connected to a
lithium battery. Note that an appropriate SVDD supply voltage must be provided to prevent waveform
clipping when speaker boost is used.
DC gain is applied automatically in both class AB and class D modes with a shift from VMID to
SVDD/2. This provides optimum signal swing for maximum output power. In class AB mode, an ultrahigh PSRR mode is available, in which the DC reference for the speaker driver is fixed at VMID. This
mode is selected by enabling the SPK_VREF_AB_CTRL bit (see Table 15). In this mode, the output
power is limited but the driver will still be capable of driving more than 500mW in 8 while maintaining
excellent suppression of noise on SVDD (for example, TDMA noise in a GSM phone application).
Figure 4 Speaker Output Configuration and Boost Operation
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REGISTER
ADDRESS
R34 (22h)
BIT
LABEL
DEFAULT
12
SPKOUT_CLASSAB
_MODE
0
SPKMIXL
Attenuation
DESCRIPTION
Speaker Class AB Mode Enable
0 = Class D mode (for SPKMIX
source)
1 = Class AB mode (for Voice
Bypass source)
R37 (25h)
7
SPK_ATTN_FB
0
ClassD3
Speaker Amplifier Gain
0 = 0dB
1 = -12dB
Note – this bit has no effect in Class
D mode; the 0dB setting is always
implemented in Class D mode.
6
SPK_VREF_AB_CT
RL
0
Selects Reference for Speaker in
Class AB mode
0 = SVDD/2
1 = VMID
5:3
SPKOUTL_BOOST
[2:0]
000
(1.0x)
Speaker Output Gain Boost
000 = 1.00x boost (+0dB)
001 = 1.19x boost (+1.5dB)
010 = 1.41x boost (+3.0dB)
011 = 1.68x boost (+4.5dB)
100 = 2.00x boost (+6.0dB)
101 = 2.37x boost (+7.5dB)
110 = 2.81x boost (+9.0dB)
111 = 3.98x boost (+12.0dB)
Table 15 Speaker Mode and Boost Control
HEADPHONE OUTPUT CONFIGURATIONS
The headphone output pins HPL and HPR are driven by the headphone output PGAs. Each PGA has
its own dedicated volume control, as described in the “Output Signal Path” section. The inputs to
these PGAs come from the respective output mixers MIXOUTL or MIXOUTR.
The headphone output driver is capable of driving up to 35mW into a 16Ω load such as a stereo
headset or headphones. The outputs are ground-referenced, eliminating any requirement for AC
coupling capacitors. This is achieved by having separate positive and negative supply rails powered
by an on-chip charge pump. A DC Servo circuit removes any DC offset from the headphone outputs,
suppressing ‘pop’ noise and minimising power consumption. The Charge Pump and DC Servo are
described separately (see “Charge Pump” and “DC Servo” respectively).
The zobel network components should be connected to the headphone output pins HPL and HPR for
best audio performance in all applications. The components of the zobel network have the effect of
dampening high frequency oscillations and instabilities that can arise outside the audio band under
certain conditions. Possible sources of these instabilities include the inductive load of a headphone
coil or an active load in the form of an external line amplifier. The capacitance of lengthy cables or
PCB tracks can also lead to amplifier instability. The zobel network should comprise of a 20 resistor
and 100nF capacitor in series with each other, as illustrated in Figure 5.
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Figure 5 Zobel Network Components for HPL and HPR
CLOCKING CONTROL
The internal clocks for the WM9093 are derived from a common internal clock source, CLK_SYS.
This clock is the reference for the Control Write Sequencer, Class D switching amplifier, DC servo
control and other internal functions.
CLK_SYS is derived from an internal oscillator; this is controlled by the OSC_ENA register. The
frequency of CLK_SYS is nominally 6MHz; internal dividers generate the other required clocks from
this reference.
A slow clock, TOCLK, is used to set the timeout period for volume updates when zero-cross detect is
used. This clock is derived from CLK_SYS and is enabled by TOCLK_ENA. The slow clock frequency
is selected using the programmable dividers TOCLK_RATE, TOCLK_RATE_X4 and
TOCLK_RATE_DIV16. See Table 17 for a list of possible TOCLK rates.
The clocking configuration is illustrated in Figure 6. The control registers associated with WM9093
Clocking are defined in Table 16.
Internal
Oscillator
f/N
DC Servo clock
f/N
Class D switching clock
CLK_SYS
OSC_ENA
256kHz clock to
Charge Pump, Control
Write Sequencer and
other circuits
f/N
TOCLK_ENA
f/1024
f/N
TOCLK_RATE_DIV16
0=f/1
1 = f / 16
f.N
TOCLK_RATE_X4
0=fx1
1=fx4
f/N
Volume update timeout
TOCLK_RATE
0=f/2
1=f/1
Figure 6 Clocking Scheme
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REGISTER
ADDRESS
R1 (01h)
BIT
LABEL
DEFAULT
OSC_ENA
3
0
CLK_SYS Oscillator Enable
0 = Disabled
Power
Management
(1)
R6 (06h)
DESCRIPTION
1 = Enabled
15
TOCLK_RATE
0
Clocking 1
TOCLK Rate Divider (/2)
0=f/2
1=f/1
14
TOCLK_ENA
0
TOCLK Enable
0 = Disabled
1 = Enabled
R66 (42h)
TOCLK_RATE_DIV16
8
0
Clocking 4
TOCLK Rate Divider (/16)
0=f/1
1 = f / 16
TOCLK_RATE_X4
7
0
TOCLK Rate Multiplier
0=fx1
1=fx4
Table 16 Clocking Control
TOCLK_RATE
TOCLK_RATE_X4
TOCLK_RATE_DIV16
1
1
0
TOCLK
FREQ (Hz)
PERIOD (ms)
0
1000
1
1
0
500
2
1
0
0
250
4
0
0
0
125
8
1
1
1
62.5
16
0
1
1
31.25
32
1
0
1
15.625
64
0
0
1
7.8125
128
Table 17 TOCLK Rates
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CONTROL INTERFACE
The WM9093 is controlled by writing to registers through a 2-wire serial control interface. Readback is
available for all registers, including Chip ID and power management status.
The WM9093 is a slave device on the control interface; SCL is a clock input, while SDA is a bidirectional data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the same
interface, the WM9093 transmits logic 1 by tri-stating the SDA pin, rather than pulling it high. An
external pull-up resistor is required to pull the SDA line high so that the logic 1 can be recognised by
the master. Note that the control interface can support I/O levels up to 2.7V.
In order to allow many devices to share a single 2-wire control bus, every device on the bus has a
unique 7-bit device ID (this is not the same as the 8-bit address of each register in the WM9093). The
WM9093 device ID is 1101_1100 (DCh). The LSB of the device ID is the Read/Write bit; this bit is set
to logic 1 for “Read” and logic 0 for “Write”.
The WM9093 operates as a slave device only. The controller indicates the start of data transfer with a
high to low transition on SDA while SCL remains high. This indicates that a device ID, register
address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in
the next eight bits on SDA (7-bit device ID + Read/Write bit, MSB first). If the device ID received
matches the device ID of the WM9093, then the WM9093 responds by pulling SDA low on the next
clock pulse (ACK). If the device ID is not recognised or the R/W bit is ‘1’ when operating in write only
mode, the WM9093 returns to the idle condition and waits for a new start condition and valid address.
If the device ID matches the device ID of the WM9093, the data transfer continues as described
below. The controller indicates the end of data transfer with a low to high transition on SDA while SCL
remains high. After receiving a complete address and data sequence the WM9093 returns to the idle
state and waits for another start condition. If a start or stop condition is detected out of sequence at
any point during data transfer (i.e. SDA changes while SCL is high), the device returns to the idle
condition.
The WM9093 supports the following read and write operations:
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Single write

Single read

Multiple write using auto-increment

Multiple read using auto-increment
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The sequence of signals associated with a single register write operation is illustrated in Figure 7.
Figure 7 Control Interface Register Write
The sequence of signals associated with a single register read operation is illustrated in Figure 8.
Figure 8 Control Interface Register Read
The Control Interface also supports other register operations, as listed above. The interface protocol
for these operations is summarised below. The terminology used in the following figures is detailed in
Table 18.
Note that multiple write and multiple read operations are supported using the auto-increment mode.
This feature enables the host processor to access sequential blocks of the data in the WM9093
register map faster than is possible with single register operations.
TERMINOLOGY
DESCRIPTION
S
Start Condition
Sr
Repeated start
A
Acknowledge (SDA Low)
¯¯
A
Not Acknowledge (SDA High)
P
Stop Condition
R/W
¯¯
ReadNotWrite
0 = Write
1 = Read
[White field]
Data flow from bus master to WM9093
[Grey field]
Data flow from WM9093 to bus master
Table 18 Control Interface Terminology
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WM9093
Figure 9 Single Register Write to Specified Address
Figure 10 Single Register Read from Specified Address
Figure 11 Multiple Register Write to Specified Address using Auto-increment
Figure 12 Multiple Register Read from Specified Address using Auto-increment
Figure 13 Multiple Register Read from Last Address using Auto-increment
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CONTROL WRITE SEQUENCER
The Control Write Sequencer is a programmable unit that forms part of the WM9093 control interface
logic. It provides the ability to perform a sequence of register write operations with the minimum of
demands on the host processor – the sequence may be initiated by a single operation from the host
processor and then left to execute independently.
Default sequences for Start-Up of each output driver and Shut-Down are provided (see “Default
Sequences” section). It is recommended that these default sequences are used unless changes
become necessary.
When a sequence is initiated, the sequencer performs a series of pre-defined register writes. The
host processor informs the sequencer of the start index of the required sequence within the
sequencer’s memory. At each step of the sequence, the contents of the selected register fields are
read from the sequencer’s memory and copied into the WM9093 control registers. This continues
sequentially through the sequencer’s memory until an “End of Sequence” bit is encountered; at this
point, the sequencer stops and an Interrupt status flag is asserted. For cases where the timing of the
write sequence is important, a programmable delay can be set for specific steps within the sequence.
Note that the Control Write Sequencer’s internal clock is derived from the internal clock CLK_SYS
which must be enabled by setting OSC_ENA (see “Clocking Control”). The clock division from
CLK_SYS is handled transparently by the WM9093 without user intervention.
INITIATING A SEQUENCE
The Register fields associated with running the Control Write Sequencer are described in Table 19.
Note that the operation of the Control Write Sequencer also requires the internal clock CLK_SYS to
be enabled via the OSC_ENA control bit (see “Clocking Control”).
The Write Sequencer is enabled by setting the WSEQ_ENA bit. The start index of the required
sequence must be written to the WSEQ_START_INDEX field. Setting the WSEQ_START bit initiates
the sequencer at the given start index.
The Write Sequencer can be interrupted by writing a logic 1 to the WSEQ_ABORT bit.
The current status of the Write Sequencer can be read using two further register fields – when the
WSEQ_BUSY bit is asserted, this indicates that the Write Sequencer is busy. Note that, whilst the
Control Write Sequencer is running a sequence (indicated by the WSEQ_BUSY bit), normal
read/write operations to the Control Registers cannot be supported. The index of the current step in
the Write Sequencer can be read from the WSEQ_CURRENT_INDEX field; this is an indicator of the
sequencer’s progress. On completion of a sequence, this field holds the index of the last step within
the last commanded sequence.
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REGISTER
ADDRESS
R70 (46h)
BIT
8
LABEL
WSEQ_ENA
DEFAULT
0
Write
Sequencer 0
R73 (49h)
DESCRIPTION
Write Sequencer Enable
0 = Disabled
1 = Enabled
9
WSEQ_ABORT
0
Writing a 1 to this bit aborts the
current sequence and returns control
of the device back to the serial
control interface.
8
WSEQ_START
0
Writing a 1 to this bit starts the write
sequencer at the memory location
indicated by the
WSEQ_START_INDEX field. The
sequence continues until it reaches
an “End of sequence” flag. At the end
of the sequence, this bit will be reset
by the Write Sequencer.
5:0
WSEQ_START_
INDEX [5:0]
00_0000
Sequence Start Index. This is the
memory location of the first command
in the selected sequence.
Write
Sequencer 3
0 to 15 = RAM addresses
16 to 58 = ROM addresses
59 to 63 = Reserved
R74 (4Ah)
0
Write
Sequencer 4
WSEQ_BUSY
0
(read only)
Sequencer Busy flag (Read Only).
0 = Sequencer idle
1 = Sequencer busy
Note: it is not possible to write to
control registers via the control
interface while the Sequencer is
Busy.
R75 (4Bh)
Write
Sequencer 5
5:0
WSEQ_CURRE
NT_INDEX [5:0]
00_0000
(read only)
Sequence Current Index. This is the
location of the most recently
accessed command in the write
sequencer memory.
Table 19 Write Sequencer Control – Initiating a Sequence
PROGRAMMING A SEQUENCE
A sequence consists of write operations to data bits (or groups of bits) within the control registers.
The Register fields associated with programming the Control Write Sequencer are described in Table
20.
For each step of the sequence being programmed, the Sequencer Index must be written to the
WSEQ_WRITE_INDEX field. The values 0 to 15 correspond to all the available RAM addresses
within the Write Sequencer memory. (Note that memory addresses 16 to 58 also exist, but these are
ROM addresses, which are not programmable.)
Having set the Index as described above, Register R71 must be written to (containing the Control
Register Address, the Start Bit Position and the Field Width applicable to this step of the sequence).
Also, Register R72 must be written to (containing the Register Data, the End of Sequence flag and
the Delay time required after this step is executed). After writing to these two registers, the next step
in the sequence may be programmed by updating WSEQ_WRITE_INDEX and repeating the
procedure.
WSEQ_ADDR is an 8-bit field containing the Control Register Address in which the data should be
written.
WSEQ_DATA_START is a 4-bit field which identifies the LSB position within the selected Control
Register to which the data should be written. For example, setting WSEQ_DATA_START = 0100 will
select bit 4 as the LSB position; in this case, 4-bit data would be written to bits 7:4 and so on.
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WSEQ_DATA_WIDTH is a 3-bit field which identifies the width of the data block to be written. This
enables selected portions of a Control Register to be updated without any concern for other bits within
the same register, eliminating the need for read-modify-write procedures. Values of 0 to 7 correspond
to data widths of 1 to 8 respectively. For example, setting WSEQ_DATA_WIDTH = 010 will cause a
3-bit data block to be written. Note that the maximum value of this field corresponds to an 8-bit data
block; writing to register fields greater than 8 bits wide must be performed using two separate
operations of the Control Write Sequencer.
WSEQ_DATA is an 8-bit field which contains the data to be written to the selected Control Register.
The WSEQ_DATA_WIDTH field determines how many of these bits are written to the selected
register; the most significant bits (above the number indicated by WSEQ_DATA_WIDTH) are ignored.
WSEQ_DELAY is a 4-bit field which controls the waiting time between the current step and the next
step in the sequence i.e. the delay occurs after the write in which it was called. The total delay time
per step (including execution) is given by:
T = k × (2
WSEQ_DELAY
+ 8)
where k = 62.5s (under recommended operating conditions)
This gives a useful range of execution/delay times from 562s up to 2.048s per step.
WSEQ_EOS is a 1-bit field which indicates the End of Sequence. If this bit is set, then the Control
Write Sequencer will automatically stop after this step has been executed.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R70 (46h)
Write
Sequencer 0
3:0
WSEQ_WRIT
E_INDEX [3:0]
0000
Sequence Write Index. This is the
memory location to which any updates to
R71 and R72 will be copied.
R71 (47h)
Write
Sequencer 1
14:12
WSEQ_DATA
_WIDTH [2:0]
000
0 to 15 = RAM addresses
11:8
WSEQ_DATA
_START [3:0]
0000
Width of the data block written in this
sequence step.
000 = 1 bit
001 = 2 bits
010 = 3 bits
011 = 4 bits
100 = 5 bits
101 = 6 bits
110 = 7 bits
111 = 8 bits
Bit position of the LSB of the data block
written in this sequence step.
0000 = Bit 0
…
1111 = Bit 15
R72 (48h)
Write
Sequencer 2
7:0
WSEQ_ADDR
[7:0]
14
WSEQ_EOS
0000_0000
Control Register Address to be written to
in this sequence step.
0
End of Sequence flag. This bit indicates
whether the Control Write Sequencer
should stop after executing this step.
0 = Not end of sequence
1 = End of sequence (Stop the
sequencer after this step).
11:8
7:0
WSEQ_DELA
Y [3:0]
0000
WSEQ_DATA
[7:0]
0000_0000
Time delay after executing this step.
Total time per step (including execution)
WSEQ_DELAY
= 62.5µs × (2
+ 8)
Data to be written in this sequence step.
When the data width is less than 8 bits,
then one or more of the MSBs of
WSEQ_DATA are ignored. It is
recommended that unused bits be set to
0.
Table 20 Write Sequencer Control – Programming a Sequence
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Note that a ‘Dummy’ write can be inserted into a control sequence by commanding the sequencer to
write a value of 0 to bit 0 of Register R255 (FFh). This is effectively a write to a non-existent register
location. This can be used in order to create placeholders ready for easy adaptation of the sequence.
For example, a sequence could be defined to power-up a mono signal path from IN1+ and IN1- to
headphone, with a ‘dummy’ write included to leave space for easy modification to a stereo signal path
configuration. Dummy writes can also be used in order to implement additional time delays between
register writes. Dummy writes are included in the Headphone Start-Up sequence – see Table 21.
In summary, the Control Register to be written is set by the WSEQ_ADDR field. The data bits that are
written are determined by a combination of WSEQ_DATA_START, WSEQ_DATA_WIDTH and
WSEQ_DATA. This is illustrated below for an example case of writing to the VMID_RES field within
Register R1 (01h).
In this example, the Start Position is bit 01 (WSEQ_DATA_START = 0001b) and the Data width is 2
bits (WSEQ_DATA_WIDTH = 0001b). With these settings, the Control Write Sequencer would update
the Control Register R1 [2:1] with the contents of WSEQ_DATA [1:0].
Figure 14 Control Write Sequencer Example
DEFAULT SEQUENCES
When the WM9093 is powered up, a number of Control Write Sequences are available through
default settings in both RAM and ROM memory locations. The pre-programmed default settings
comprise a Headphone Start-Up and a Generic Shut-Down sequence.
Note that the start-up sequence does not include audio signal path or gain setting configuration; this
must be implemented prior to scheduling the sequence. Also, the start-up sequence does not include
configuration of the master bias. The user must enable the clock and the master bias by setting
OSC_ENA and VMID_ENA prior to executing the start-up control sequence. These registers may be
reset to 0 after executing the shut-down sequence.
Index addresses 0 to 15 may be programmed to users’ own settings at any time, as described in
“Programming a Sequence”. Users’ own settings remain in memory regardless of WSEQ_ENA, and
are not affected by software resets (i.e. writing to Register R0). However, any non-default sequences
are lost when the device is powered down.
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The following default control sequences are provided:
1.
Headphone Start-Up – This sequence powers up the headphone driver and charge pump. It
commands the DC Servo to perform offset correction. This sequence is intended for enabling the
headphone output after initial power-on, when DC offset correction has not previously been run.
2.
Generic Shut-Down – This sequence shuts down all of the WM9093 output drivers, DC Servo
and charge pump circuits.
Specific details of these sequences are provided below. Note that the timings noted are typical values
only.
Headphone Start-Up
The Headphone Start-Up sequence is initiated by writing 0100h to Register 73 (49h). This single
operation starts the Control Write Sequencer at Index Address 0 (00h) and executes the sequence
defined in Table 21.
This sequence takes approximately 40ms to run.
WSEQ
INDEX
REGISTER
ADDRESS
WIDTH
START
DATA
DELAY
EOS
DESCRIPTION
0 (00h)
R76 (4Ch)
1 bit
Bit 15
01h
6h
0b
CP_ENA = 1
1 (01h)
R1 (01h)
3 bits
Bit 7
07h
0h
0b
HPOUT1R_ENA = 1
(delay = 4.5ms)
HPOUT1L_ENA = 1
(delay = 0.5ms)
2 (02h)
R96 (60h)
5 bits
Bit 1
11h
0h
0b
HPOUT1R_DLY = 1
HPOUT1L_DLY = 1
(delay = 0.5ms)
3 (03h)
R84 (54h)
7 bits
Bit 0
33h
9h
0b
DCS_ENA_CHAN_0 = 1
DCS_ENA_CHAN_1 = 1
DCS_TRIG_STARTUP_0 = 1
DCS_TRIG_STARTUP_1 = 1
(delay = 32.5ms)
4 (04h)
R255 (FFh)
1 bit
Bit 0
00h
5h
0b
Dummy Write for additional delay
(delay = 2.5ms)
5 (05h)
R255 (FFh)
1 bit
Bit 0
00h
0h
0b
Dummy Write for expansion
(delay = 0.5ms)
6 (06h)
R255 (FFh)
1 bits
Bit 0
00h
0h
0b
Dummy Write for expansion
(delay = 0.5ms)
7 (07h)
R96 (60h)
6 bits
Bit 2
3Bh
0h
1b
HPOUT1L_RMV_SHORT = 1
HPOUT1L_OUTP = 1
HPOUT1L_DLY = 1
HPOUT1R_RMV_SHORT =1
HPOUT1R_OUTP = 1
(delay = 0.5ms)
Table 21 Headphone Start-Up Default Sequence
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Generic Shut-Down
The Generic Shut-Down sequence can be initiated by writing 0110h to Register 73 (49h). This single
operation starts the Control Write Sequencer at Index Address 16 (10h) and executes the sequence
defined in Table 22.
This sequence takes approximately 2.8ms to run.
WSEQ
INDEX
REGISTER
ADDRESS
WIDTH
START
DATA
DELAY
EOS
16 (10h)
R96 (60h)
7 bits
Bit 1
00h
0h
0b
DESCRIPTION
HPOUT1R_DLY = 0
HPOUT1R_OUTP = 0
HPOUT1R_RMV_SHORT = 0
HPOUT1L_DLY = 0
HPOUT1L_OUTP = 0
HPOUT1L_RMV_SHORT = 0
(delay = 0.5ms)
17 (11h)
R84 (54h)
2 bits
Bit 0
00h
0h
0b
DCS_ENA_CHAN_0 = 0
DCS_ENA_CHAN_1 = 0
(delay = 0.5ms)
18 (12h)
R1 (01h)
2 bits
Bit 8
00h
0h
0b
HPOUT1R_ENA = 0
HPOUT1L_ENA = 0
(delay = 0.5ms)
19 (13h)
R76 (4Ch)
1 bit
Bit 15
00h
0h
0b
CP_ENA = 0
20 (14h)
R1 (01h)
2 bits
Bit 12
00h
0h
1b
SPKOUTL_ENA = 0
(delay = 0.5ms)
(delay = 0.5ms)
Table 22 Generic Shut-Down Default Sequence
POWER SEQUENCES AND POP SUPPRESSION CONTROL
The WM9093 incorporates a number of features, including Wolfson’s SilentSwitch™ technology,
designed to suppress pops normally associated with Start-Up, Shut-Down or signal path control. To
achieve maximum benefit from these features, careful attention is required to the sequence and
timing of these controls. Note that, under the recommended usage conditions of the WM9093, these
features will be configured by running the default Start-Up and Shut-Down sequences as described in
the “Control Write Sequencer” section. In these cases, the user does not need to set these register
fields directly. Additional bias controls, also pre-programmed into Control Write Sequencer, are
described in the “Reference Voltages and Master Bias” section.
INPUT VMID CLAMPS
The analogue inputs are biased to VMID in normal operation. In order to avoid audible pops caused
by enabling the inputs, the WM9093 can clamp the input pins to VMID when the relevant input stage
is disabled. This allows pre-charging of the input AC coupling capacitors during power-up.
The Input VMID Clamps connect the input pins to a buffered VMID reference. The buffered VMID
reference is enabled by setting VMID_BUF_ENA. The VMID Clamp is enabled on each pair of input
pins independently using the register bits defined in Table 23.
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REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
ADDRESS
R21 (15h)
0
IN3_CLAMP
1
IN3 Line Control
IN3+ and IN3- input pad VMID clamp
0 = Clamp de-activated
1 = Clamp activated
R22 (16h)
0
IN1_CLAMP
1
IN1 Line Control
IN1+ and IN1- input pad VMID clamp
0 = Clamp de-activated
1 = Clamp activated
R23 (17h)
0
IN2_CLAMP
1
IN2 Line Control
IN2+ and IN2- input pad VMID clamp
0 = Clamp de-activated
1 = Clamp activated
R57 (39h)
3
VMID_BUF_ENA
1
AntiPOP2
VMID Buffer Enable
0 = Disabled
1 = Enabled
Table 23 Input VMID Clamps
HEADPHONE ENABLE/DISABLE
The ground-referenced headphone outputs implement Wolfson’s SilentSwitch™ technology to
minimise pop noise associated with enabling and disabling. The output pins HPL and HPR are
shorted to GND by default while the individual driver stages are enabled. As a final step the short
circuit is then removed on each of these paths by setting the applicable fields
HPOUT1L_RMV_SHORT and HPOUT1R_RMV_SHORT.
The ground-referenced Headphone output drivers are designed to suppress pops and clicks when
enabled or disabled. However, it is necessary to control the drivers in accordance with a defined
sequence in start-up and shut-down to achieve the pop suppression. It is also necessary to schedule
the DC Servo offset correction at the appropriate point in the sequence (see “DC Servo”). Table 24
and Table 25 describe the recommended sequences for enabling and disabling these output drivers.
SEQUENCE
HEADPHONE ENABLE
Step 1
HPOUT1L_ENA = 1
Step 2
HPOUT1L_DLY = 1
HPOUT1R_ENA = 1
HPOUT1R_DLY = 1
Step 3
DC offset correction
Step 4
HPOUT1L_OUTP = 1
HPOUT1L_RMV_SHORT = 1
HPOUT1R_OUTP = 1
HPOUT1R_RMV_SHORT = 1
Table 24 Headphone Output Enable Sequence
SEQUENCE
Step 1
HEADPHONE DISABLE
HPOUT1L_RMV_SHORT = 0
HPOUT1L_DLY = 0
HPOUT1L_OUTP = 0
HPOUT1R_RMV_SHORT = 0
HPOUT1R_DLY = 0
HPOUT1R_OUTP = 0
Step 2
HPOUT1L_ENA = 0
HPOUT1R_ENA = 0
Table 25 Headphone Output Disable Sequence
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The register bits relating to pop suppression control are defined in Table 26.
REGISTER
ADDRESS
R1 (01h)
BIT
9
LABEL
HPOUT1L_ENA
DEFAULT
0
Power
Management
(1)
DESCRIPTION
Headphone Output (HPL) input stage
enable
0 = Disabled
1 = Enabled
8
HPOUT1R_ENA
0
Headphone Output (HPR) input stage
enable
0 = Disabled
1 = Enabled
R96 (60h)
7
Analogue HP
0
HPOUT1L_RMV_
SHORT
0
Removes HPOUT1L short
0 = HPOUT1L short enabled
1 = HPOUT1L short removed
Note: Remove short after output stage
has been enabled.
6
HPOUT1L_OUTP
0
Enables HPOUT1L output stage
0 = Disabled
1 = Enabled
Note: Set after offset correction is
complete
5
HPOUT1L_DLY
0
Enables HPOUT1L intermediate stage
0 = Disabled
1 = Enabled
Note: Set with at least 20us delay after
HPOUT1L_ENA has been set.
3
HPOUT1R_RMV_
SHORT
0
Removes HPOUT1R short
0 = HPOUT1R short enabled
1 = HPOUT1R short removed
Note: Remove short after output stage
has been enabled.
2
HPOUT1R_OUTP
0
Enables HPOUT1R output stage
0 = Disabled
1 = Enabled
Note: Set after offset correction is
complete
1
HPOUT1R_DLY
0
Enables HPOUT1R intermediate stage
0 = Disabled
1 = Enabled
Note: Set with at least 20us delay after
HPOUT1R_ENA has bee set.
Table 26 Pop Suppression Control
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RECOMMENDED HEADPHONE START UP SEQUENCE
Below is a recommended headphone start up sequence for suppressing pops.
Firstly program the following sequence into the Control Write Sequencer. For further details refer to
the ‘Programming a Sequence’ section.
WSEQ
INDEX
REGISTER
ADDRESS
WIDTH
START
DATA
DELAY
EOS
DESCRIPTION
0
(00h)
R76 (4Ch)
1 bits
Bit 15
01h
0h
0b
Enable Charge Pump
1
(01h)
R3 (03h)
2 bits
Bit 4
03h
0h
0b
Enable Output Mixers
2
(02h)
R46 (2Dh)
1 bits
Bit 6
01h
0h
0b
Enable path from IN1A
TO MIXOUTL
3
(03h)
R47 (2Eh)
1 bits
Bit 4
01h
0h
0b
Enable path from IN1B
TO MIXOUTR
4
(04h)
R48 (2Fh)
1 bits
Bit 8
00h
0h
0b
Un-mute MIXOUTL
5
(05h)
R49 (30h)
1 bits
Bit 8
00h
0h
0b
Un-mute MIXOUTR
6
(06h)
R28 (1Ch)
1 bits
Bit 8
01h
0h
0b
HPOUT1L_VOL=-12dB
and update
7
(07h)
R29 (1Dh)
1 bits
Bit 8
01h
0h
0b
HPOUT1R_VOL=-12dB
and update
8
(08h)
R1 (01h)
2 bits
Bit 8
03h
0h
0b
Enable HPOUTL/R
9
(0Ah)
R96 (60h)
6 bits
Bit 0
22h
0h
0b
Enable HP DLY
10
(0Bh)
R84 (54h)
6 bits
Bit 0
33h
9h
(32.5ms)
0b
Enable DC Servo and
Start Calibration
11
(0Ch)
R96 (60h)
8 bits
Bit 0
EEh
0h
1b
Enable Headphone
Output
Secondly, initiate the sequence by performing the following set of register writes.
REGISTER
DATA
DESCRIPTION
ADDRESS
R1 (01h)
0x000B
OSC_ENA=1, VMID_RES=01,
BIAS_ENA=1
0x60C0
Enable input PGAs
0x0000
IN1+/- to s/e mode and disable input
clamp
0x0100
IN1A Volume=-6dB and update
0x0100
IN1B Volume=-6dB and update
0x0100
Write Sequencer enable
0x0100
WSEQ_START=1
Power Management (1)
R2 (02h)
Power Management (2)
R22 (16h)
IN1 Line Control
R24 (18h)
IN1 Line Input A Volume
R25 (19h)
IN1 Line Input B Volume
R70 (46h)
Write Sequencer 0
R71 (47h)
Write Sequencer 0
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CHARGE PUMP
The WM9093 incorporates a dual-mode Charge Pump which generates the supply rails for the
headphone output drivers, HPOUT1L and HPOUT1R. The Charge Pump has a single supply input,
HPVDD, and generates split rails CPVDD and CPVSS according to the selected mode of operation.
The Charge Pump connections are illustrated in Figure 15 (see “Electrical Characteristics” for external
component values). An input decoupling capacitor may also be required at HPVDD, depending upon
the system configuration.
CP
CN
HPVDD
CPVDD
Charge Pump
CPVSS
WM9093
GND
Figure 15 Charge Pump External Connections
The Charge Pump is enabled by setting the CP_ENA bit. When enabled, the charge pump adjusts the
output voltages (CPVDD and CPVSS) as well as the switching frequency in order to optimise the
power consumption according to the operating conditions.
The Charge Pump mode of operation is selected automatically according to the HPOUT1L_VOL and
HPOUT1R_VOL register settings.
Under the recommended usage conditions of the WM9093, the Charge Pump will be enabled by
running the default headphone Start-Up sequence as described in the “Control Write Sequencer”
section. (Similarly, it will be disabled by running the Shut-Down sequence.) In these cases, the user
does not need to write to the CP_ENA bit.
Note that the charge pump clock is derived from internal clock CLK_SYS which must be enabled by
setting OSC_ENA (see “Clocking Control”). The clock division from CLK_SYS is handled
transparently by the WM9093 without user intervention.
The CP_ENA register bit is defined in Table 27.
REGISTER
ADDRESS
R76 (4Ch)
BIT
15
LABEL
CP_ENA
Charge Pump
1
DEFAULT
0
DESCRIPTION
Charge Pump Control
0 = Disabled
1 = Enabled
Table 27 Charge Pump Control
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DC SERVO
The WM9093 provides a DC servo circuit on the headphone outputs HPOUT1L and HPOUT1R in
order to remove DC offset from these ground-referenced outputs. When enabled, the DC servo
ensures that the DC level of these outputs remains within 1mV of ground. Removal of the DC offset is
important because any deviation from GND at the output pin will cause current to flow through the
load under quiescent conditions, resulting in increased power consumption. Additionally, the presence
of DC offsets can result in audible pops and clicks at power up and power down.
The recommended usage of the DC Servo is initialised by running the default Start-Up sequence as
described in the “Control Write Sequencer” section. The default Start-Up sequence executes a series
of DC offset corrections, after which the measured offset correction is maintained on the headphone
output channels. If a different usage is required, eg. If a periodic DC offset correction is required, then
the default Start-Up sequence may be modified according to specific requirements. The relevant
control fields are described in the following paragraphs and are defined in Table 28.
DC SERVO ENABLE AND START-UP
The DC Servo circuit is enabled on HPOUT1L and HPOUT1R by setting DCS_ENA_CHAN_0 and
DCS_ENA_CHAN_1 respectively. When the DC Servo is enabled, the DC offset correction can be
commanded in a number of different ways, including single-shot and periodically recurring events.
Writing a logic 1 to DCS_TRIG_STARTUP_n initiates a series of DC offset measurements and
applies the necessary correction to the associated output; (‘n’ = 0 for Left channel, 1 for Right
channel). On completion, the headphone output will be within 1mV of AGND. This is the DC Servo
mode selected by the default Start-Up sequence. Completion of the DC offset correction triggered in
this way is indicated by the DCS_STARTUP_COMPLETE field, as described in Table 28. Typically,
this operation takes 25ms per channel.
Writing a logic 1 to DCS_TRIG_DAC_WR_n causes the DC offset correction to be set to the value
contained in the DCS_DAC_WR_VAL_n fields in Register R87. This mode is useful if the required
offset correction has already been determined and stored; it is faster than the
DCS_TRIG_STARTUP_n mode, but relies on the accuracy of the stored settings. Completion of the
DC offset correction triggered in this way is indicated by the DCS_DAC_WR_COMPLETE field, as
described in Table 28. Typically, this operation takes 2ms per channel.
When using either of the DC Servo options above, the status of the DC offset correction process is
indicated by the DCS_CAL_COMPLETE field; this is the logical OR of the
DCS_STARTUP_COMPLETE and DCS_DAC_WR_COMPLETE fields.
The DC Servo control fields associated with start-up operation are described in Table 28. It is
important to note that, to minimise audible pops/clicks, the Start-Up and DAC Write modes of DC
Servo operation should be commanded as part of a control sequence which includes muting and
shorting of the headphone outputs; a suitable sequence is defined in the default Start-Up sequence.
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REGISTER
ADDRESS
R84 (54h)
BIT
LABEL
DEFAULT
DESCRIPTION
5
DCS_TRIG_START
UP_1
0
Writing 1 to this bit selects StartUp DC Servo mode for
HPOUT1R.
DC Servo 0
In readback, a value of 1
indicates that the DC Servo
Start-Up correction is in
progress.
4
DCS_TRIG_START
UP_0
0
Writing 1 to this bit selects StartUp DC Servo mode for
HPOUT1L.
In readback, a value of 1
indicates that the DC Servo
Start-Up correction is in
progress.
3
DCS_TRIG_DAC_W
R_1
0
Writing 1 to this bit selects DAC
Write DC Servo mode for
HPOUT1R.
In readback, a value of 1
indicates that the DC Servo DAC
Write correction is in progress.
2
DCS_TRIG_DAC_W
R_0
0
Writing 1 to this bit selects DAC
Write DC Servo mode for
HPOUT1L.
In readback, a value of 1
indicates that the DC Servo DAC
Write correction is in progress.
1
DCS_ENA_CHAN_1
0
DC Servo enable for HPOUT1R
0 = Disabled
1 = Enabled
0
DCS_ENA_CHAN_0
0
DC Servo enable for HPOUT1L
0 = Disabled
1 = Enabled
R87 (57h)
15:8
DC Servo 3
DCS_DAC_WR_VA
L1 [7:0]
0000 0000
DC Offset value for HPOUT1Rin
DAC Write DC Servo mode.
Two’s complement format.
LSB is 0.25mV.
Range is -32mV to +31.75mV
7:0
DCS_DAC_WR_VA
L0 [7:0]
0000 0000
DC Offset value for HPOUT1Lin
DAC Write DC Servo mode.
Two’s complement format.
LSB is 0.25mV.
Range is -32mV to +31.75mV
R88 (58h)
9:8
DC Servo
Readback 0
DCS_CAL_COMPL
ETE [1:0]
00
DC Servo Complete status
0 = DAC Write or Start-Up DC
Servo mode not completed.
1 = DAC Write or Start-Up DC
Servo mode complete.
Bit [1] = HPOUT1R
Bit [0] = HPOUT1L
5:4
DCS_DAC_WR_CO
MPLETE [1:0]
00
DC Servo DAC Write status
0 = DAC Write DC Servo mode
not completed.
1 = DAC Write DC Servo mode
complete.
Bit [1] = HPOUT1R
Bit [0] = HPOUT1L
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REGISTER
ADDRESS
BIT
1:0
LABEL
DCS_STARTUP_C
OMPLETE [1:0]
DEFAULT
00
DESCRIPTION
DC Servo Start-Up status
0 = Start-Up DC Servo mode not
completed.
1 = Start-Up DC Servo mode
complete.
Bit [1] = HPOUT1R
Bit [0] = HPOUT1L
Table 28 DC Servo Enable and Start-Up Modes
DC SERVO ACTIVE MODES
The DC Servo modes described above are suitable for initialising the DC offset correction circuit on
the Headphone outputs as part of a controlled start-up sequence which is executed before the signal
path is fully enabled. Additional modes are available for use whilst the signal path is active; these
modes may be of benefit following a large change in signal gain, which can lead to a change in DC
offset level. Periodic updates may also be desirable to remove slow drifts in DC offset caused by
changes in parameters such as device temperature.
The DC Servo circuit is enabled on HPOUT1L and HPOUT1R by setting DCS_ENA_CHAN_0 and
DCS_ENA_CHAN_1 respectively, as described earlier in Table 28.
Writing a logic 1 to DCS_TRIG_SINGLE_n initiates a single DC offset measurement and adjustment
to the associated output; (‘n’ = 0 for Left channel, 1 for Right channel). This will adjust the DC offset
correction on the selected channel by no more than 1LSB (0.25mV).
Setting DCS_TIMER_PERIOD_01 to a non-zero value will cause a single DC offset measurement
and adjustment to be scheduled on a periodic basis. Periodic rates ranging from every 0.52s to in
excess of 2hours can be selected.
Writing a logic 1 to DCS_TRIG_SERIES_n initiates a series of DC offset measurements and applies
the necessary correction to the associated output. The number of DC Servo operations performed is
determined by DCS_SERIES_NO_01. A maximum of 128 operations may be selected, though a
much lower value will be sufficient in most applications.
The DC Servo control fields associated with active modes (suitable for use on a signal path that is in
active use) are described in Table 29.
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REGISTER
ADDRESS
R84 (54h)
BIT
LABEL
DEFAULT
13
DCS_TRIG_SINGLE
_1
0
DC Servo 0
DESCRIPTION
Writing 1 to this bit selects a
single DC offset correction for
HPOUT1R.
In readback, a value of 1
indicates that the DC Servo
single correction is in progress.
12
DCS_TRIG_SINGLE
_0
0
Writing 1 to this bit selects a
single DC offset correction for
HPOUT1L.
In readback, a value of 1
indicates that the DC Servo
single correction is in progress.
9
DCS_TRIG_SERIES
_1
0
Writing 1 to this bit selects a
series of DC offset corrections
for HPOUT1R.
In readback, a value of 1
indicates that the DC Servo DAC
Write correction is in progress.
8
DCS_TRIG_SERIES
_0
0
Writing 1 to this bit selects a
series of DC offset corrections
for HPOUT1L.
In readback, a value of 1
indicates that the DC Servo DAC
Write correction is in progress.
R85 (55h)
11:5
DC Servo 1
DCS_SERIES_NO_
01 [6:0]
010 1010
Number of DC Servo updates to
perform in a series event.
0 = 1 updates
1 = 2 updates
...
127 = 128 updates
3:0
DCS_TIMER_PERI
OD_01 [3:0]
1010
Time between periodic updates.
Time is calculated as
0.256s x (2^PERIOD)
0000 = Off
0001 = 0.52s
1010 = 266s (4min 26s)
1111 = 8519s (2hr 22s)
Table 29 DC Servo Active Modes
DC SERVO READBACK
The current DC offset value for each Headphone output channel can be read from Registers R89 and
R90, as described in Table 30. Note that these values may form the basis of settings that are
subsequently used by the DC Servo in DAC Write mode.
REGISTER
ADDRESS
R89 (59h)
BIT
LABEL
DEFAULT
7:0
DCS_DAC_WR_VA
L_1_RD
0000 0000
DCS_DAC_WR_VA
L_0_RD
0000 0000
DC Servo
Readback 1
R90 (5Ah)
DC Servo
Readback 2
7:0
DESCRIPTION
Readback value for HPOUT1R.
Two’s complement format.
LSB is 0.25mV.
Range is -32mV to +31.75mV
Readback value for HPOUT1L.
Two’s complement format.
LSB is 0.25mV.
Range is -32mV to +31.75mV
Table 30 DC Servo Readback
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WM9093
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REFERENCE VOLTAGES AND MASTER BIAS
This section describes the analogue reference voltage and bias current controls. It also describes the
VMID soft-start circuit for pop suppressed start-up and shut-down.
The analogue circuits in the WM9093 require a mid-rail analogue reference voltage, VMID. This
reference is generated from HPVDD via a programmable resistor chain. Together with the external
decoupling capacitor (connected to the BIAS pin), the programmable resistor chain results in a slow,
normal or fast charging characteristic on VMID.
VMID is enabled by setting the VMID_ENA register bit. The programmable resistor chain is
configured by VMID_RES[1:0], and can be used to optimise the reference for normal operation, low
power standby or for fast start-up as described in Table 31.
When VMID is enabled using VMID_ENA, the WM9093 automatically controls VMID using a popsuppression circuit to avoid a step change in VMID; this suppresses pop/click noise which could
otherwise occur.
By default, the 2 x 5k VMID divider is selected in order to allow fast start-up. For normal operation
and lower power consumption, the VMID_RES register should be updated after start-up to select
another resistor value.
The analogue circuits in the WM9093 require a bias current. The normal bias current is enabled by
setting BIAS_ENA. Note that the normal bias current source requires VMID to be enabled also.
REGISTER
ADDRESS
R1 (01h)
BIT
2:1
Power
Management
(1)
LABEL
VMID_RES
[1:0]
DEFAULT
11
DESCRIPTION
VMID Divider Enable and Select
00 = VMID disabled (for OFF mode)
01 = 2 x 50k divider (for normal operation)
10 = 2 x 250k divider (for low power standby)
11 = 2 x 5k divider (for fast start-up)
0
BIAS_ENA
0
Enables the Normal bias current generator (for
all analogue functions)
0 = Disabled
1 = Enabled
R57 (39h)
AntiPOP2
0
VMID_ENA
0
Enable VMID master bias current source
0 = Disabled
1 = Enabled
Table 31 Reference Voltages and Master Bias Enable
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WM9093
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POWER MANAGEMENT
The WM9093 provides control registers that allow users to select which functions are active. For
minimum power consumption, unused functions should be disabled. To minimise pop or click noise, it
is important to enable or disable functions in the correct order. See “Power Sequences and Pop
Suppression Control” for further details of recommended control sequences.
REGISTER
ADDRESS
R1 (1h)
Power
Management
(1)
BIT
12
LABEL
SPKOUTL_ENA
DEFAULT
0
DESCRIPTION
Speaker Output Enable
0 = Disabled
1 = Enabled
9
HPOUT1L_ENA
0
Headphone Output (HPL) input stage
enable
0 = Disabled
1 = Enabled
8
HPOUT1R_ENA
0
Headphone Output (HPR) input stage
enable
0 = Disabled
1 = Enabled
2:1
VMID_RES
00
[1:0]
VMID Divider Enable and Select
00 = VMID disabled (for OFF mode)
01 = 2 x 50k divider (for normal
operation)
10 = 2 x 250k divider (for low power
standby)
11 = 2 x 5k divider (for fast start-up)
0
BIAS_ENA
0
Enables the Normal bias current
generator (for all analogue functions)
0 = Disabled
1 = Enabled
R2 (02h)
Power
Management
(2)
14
TSHUT_ENA
0
Thermal Sensor Enable
0 = Disabled
1 = Enabled
13
TSHUT_OPDIS
1
Thermal Shutdown Control
(Causes audio outputs to be disabled if
an over-temperature occurs. The thermal
sensor must also be enabled.)
0 = Disabled
1 = Enabled
7
IN1A_ENA
0
IN1A Input PGA Enable
0 = Disabled
1 = Enabled
6
IN1B_ENA
0
IN1B Input PGA Enable
0 = Disabled
1 = Enabled
(Note this is only required for singleended input on the IN1- pin)
5
IN2A_ENA
0
IN2A Input PGA Enable
0 = Disabled
1 = Enabled
4
IN2B_ENA
0
IN2B Input PGA Enable
0 = Disabled
1 = Enabled
(Note this is only required for singleended input on the IN2- pin)
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WM9093
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REGISTER
ADDRESS
R3 (03h)
Power
Management
(3)
BIT
8
LABEL
SPKLVOL_ENA
DEFAULT
0
DESCRIPTION
Speaker PGA Enable
0 = Disabled
1 = Enabled
5
MIXOUTL_ENA
0
MIXOUTL Headphone Mixer Enable
0 = Disabled
1 = Enabled
4
MIXOUTR_ENA
0
MIXOUTR Headphone Mixer Enable
0 = Disabled
1 = Enabled
3
SPKMIX_ENA
0
SPKMIX Speaker Mixer Enable
0 = Disabled
1 = Enabled
R57 (39h)
2
AntiPOP2
STARTUP_BIAS_
ENA
0
Enables the Start-Up bias current
generator
0 = Disabled
1 = Enabled
R70 (46h)
8
WSEQ_ENA
0
Write
Sequencer 0
R76 (4Ch)
0 = Disabled
1 = Enabled
15
CP_ENA
0
Charge Pump
1
R84 (54h)
Write Sequencer Enable
Charge Pump Control
0 = Disabled
1 = Enabled
1
DC Servo 0
DCS_ENA_CHAN
_1
0
DCS_ENA_CHAN
_0
0
DC Servo enable for HPOUT1R
0 = Disabled
1 = Enabled
0
DC Servo enable for HPOUT1L
0 = Disabled
1 = Enabled
Table 32 Power Management
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WM9093
Production Data
THERMAL SHUTDOWN
The WM9093 incorporates a temperature sensor which detects when the device temperature is within
normal limits or if the device is approaching a hazardous temperature condition.
The temperature status can be polled at any time by reading the TSHUT register bit. The temperature
sensor can be configured to automatically disable the audio outputs of the WM9093 in response to an
over-temperature condition (approximately 150ºC).
The temperature sensor is enabled by setting the TSHUT_ENA register bit. When the TSHUT_OPDIS
is also set, then a device over-temperature condition will cause the speaker output (OUT+ and OUT-)
to be disabled; this response is likely to prevent any damage to the device attributable to the large
currents of the speaker output driver.
When the temperature sensor is enabled, the temperature status can be read from the TSHUT
register bit.
Note that, to prevent pops and clicks, TSHUT_ENA and TSHUT_OPDIS should only be updated
whilst the speaker and headphone outputs are disabled.
REGISTER
ADDRESS
BIT
R2 (02h)
15
Power
Management
(2)
LABEL
DEFAULT
TSHUT
0
(read only)
DESCRIPTION
Thermal shutdown status
0 = Normal temperature
1 = Over temperature
14
TSHUT_ENA
1
Thermal sensor enable
0 = Disabled
1 = Enabled
13
TSHUT_OPDIS
1
Thermal shutdown control
(Causes audio outputs to be disabled
if an overtemperature occurs. The
thermal sensor must also be enabled.)
0 = Disabled
1 = Enabled
Table 33 Thermal Shutdown
SOFTWARE RESET AND CHIP ID
A Software Reset can be commanded by writing to Register R0. This is a read-only register field and
the contents will not be affected by writing to this Register.
The Chip ID can be read back from Register R0.
REGISTER
ADDRESS
BIT
LABEL
R0 (00h)
15:0
SW_RESET
Software
Reset
[15:0]
DEFAULT
DESCRIPTION
9093h
Writing to this register causes a Software
Reset.
Reading from this register will indicate
Chip ID.
Table 34 Chip Reset and ID
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w
39
36
54
42
30
48
66
2F
47
57
2E
46
25
37
26
24
36
2D
23
35
45
22
34
38
1D
19
29
18
24
25
1C
16
17
22
23
28
15
21
1A
06
6
1B
03
3
26
IN1 Line Input A Volume
02
2
27
IN2 Line Control
01
1
Clocking 4
AntiPOP2
Speaker Mixer
Output Mixer4
Output Mixer3
Output Mixer2
Output Mixer1
Speaker Volume Left
ClassD3
SPKOUT Mixers
RESERVED
SPKMIXL Attenuation
Right Output Volume
Left Output Volume
IN2 Line Input B Volume
IN2 Line Input A Volume
IN1 Line Input B Volume
IN1 Line Control
IN3 Line Control
Clocking 1
Power Management (3)
Power Management (2)
Power Management (1)
Software Reset
00
0
Name
Hex Addr
Dec Addr
0
13
AGC_ENA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TSHUT_OP
TSHUT_ENA
DIS
0
14
TOCLK_RAT
TOCLK_ENA
E
0
TSHUT
0
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SPKOUT_CLAS
SAB_MODE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
11
0
0
0
0
0
0
0
0
0
0
0
0
SPKOUTL_ENA
12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
10
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
IN2B_MUTE
IN2A_MUTE
IN1B_MUTE
IN1A_MUTE
0
0
0
IN2B_ZC
IN2A_ZC
IN1B_ZC
IN1A_ZC
0
0
0
1
0
IN1B_ENA
0
6
IN2B_ENA
0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IN2A_SPKMIX_VOL[1:0]
HPOUT1R_VOL[5:0]
HPOUT1L_VOL[5:0]
0
0
0
0
0
0
0
0
1
IN2_CLAMP
IN1_CLAMP
IN3_CLAMP
0
0
0
BIAS_ENA
0
0
0
IN2B_SPKMIX_VOL[1:0]
IN2B_VOL[2:0]
IN2A_VOL[2:0]
IN1B_VOL[2:0]
IN1A_VOL[2:0]
IN2_DIFF
IN1_DIFF
0
0
0
0
VMID_RES[1:0]
2
0
1
1
1
1
0
0000_0000_0101_1110
0
0000_0000_0000_1101
1
0000_0000_0000_0000
0000_0001_0000_0000
0000_0001_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_000P_0011_1001
0000_0001_0100_0000
0000_0000_0001_0000
0000_0000_0000_0000
0000_0001_0000_0000
0000_000P_0010_1101
0000_000P_0010_1101
0000_000P_1000_0011
0000_000P_1000_0011
0000_000P_1000_0011
0000_000P_1000_0011
0000_0000_0000_0011
0000_0000_0000_0011
0000_0000_0000_0001
0000_0001_1100_0000
0000_0000_0000_0000
0110_0000_0000_0000
0000_0000_P000_0110
TOCLK_RAT TOCLK_RAT
E_X4
E_DIV16
SPK_ATTN_FB
Bin Default
1001_0000_1001_0011
MIXOUTR_M
IN1A_MIXOUTR_VOL[1:0] IN1B_MIXOUTR_VOL[1:0] IN2A_MIXOUTR_VOL[1:0] IN2B_MIXOUTR_VOL[1:0]
UTE
IN2A_TO_SPK
IN1B_TO_S
IN2B_TO_S
IN1A_TO_S
0
0
0
0
0
PKMIX
MIX
PKMIX
PKMIX
VMID_BUF_
0
0
0
0
0
1
0
VMID_ENA
ENA
1
0
IN3_TO_SP SPKMIXL_T
0
0
0
0
0
KOUTL
O_SPKOUT
SPK_VREF_
SPKOUTL_BOOST[2:0]
0
0
0
AB CTRL
SPKOUT_V SPKOUTL_Z SPKOUTL_
SPKOUTL_VOL[5:0]
MUTE
U
C
IN1A_TO_MI
IN1B_TO_MI
IN2A_TO_MI
IN2B_TO_MI
0
0
0
0
0
XOUTL
XOUTL
XOUTL
XOUTL
IN1A_TO_MI
IN1B_TO_MI
IN2A_TO_MI
IN2B_TO_MI
0
0
0
0
0
XOUTR
XOUTR
XOUTR
XOUTR
MIXOUTL_M
IN1A_MIXOUTL_VOL[1:0] IN1B_MIXOUTL_VOL[1:0] IN2A_MIXOUTL_VOL[1:0] IN2B_MIXOUTL_VOL[1:0]
UTE
0
0
OSC_ENA
3
MIXOUTL_E MIXOUTR_E SPKMIX_EN
NA
NA
A
IN2A_ENA
0
5
HPOUT1_V HPOUT1L_Z HPOUT1L_M
U
C
UTE
HPOUT1_V HPOUT1R_Z HPOUT1R_
U
C
MUTE
SPKMIX_MU
IN1A_SPKMIX_VOL[1:0]
IN1B_SPKMIX_VOL[1:0]
TE
IN2_VU
IN2_VU
IN1_VU
IN1_VU
0
0
0
1
0
SPKLVOL_E
NA
1
IN1A_ENA
0
0
SW_RESET[15:0]
HPOUT1L_E HPOUT1R_
ENA
NA
9
WM9093
Production Data
REGISTER MAP
PD, March 2012, Rev 4.2
58
w
4B
4C
54
55
56
57
58
59
5A
60
75
76
84
85
86
87
88
89
90
96
64
4A
74
100
49
73
62
48
72
63
47
71
98
46
70
99
Hex Addr
Dec Addr
Name
AGC Control 2
AGC Control 1
AGC Control 0
Analogue HP 0
DC Servo Readback 2
DC Servo Readback 1
DC Servo Readback 0
DC Servo 3
DC Servo 2
DC Servo 1
DC Servo 0
Charge Pump 1
Write Sequencer 5
Write Sequencer 4
Write Sequencer 3
Write Sequencer 2
Write Sequencer 1
Write Sequencer 0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
1
0
0
0
0
11
7
0
0
1
0
0
0
0
0
1
AGC_RAMP
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
4
0
3
0
0
0
0
0
0
2
0
1
WSEQ_CURRENT_INDEX[5:0]
0
WSEQ_START_INDEX[5:0]
0
1
0
0
WSEQ_WRITE_INDEX[3:0]
0
0
AGC_CLIP_ATK[2:0]
AGC_PWR_ATK[2:0]
0
0
AGC_MINGAIN[5:0]
0
0
1
DCS_ENA_
CHAN_0
1
AGC_CLIP_DCY[2:0]
AGC_PWR_DCY[2:0]
0
DCS_STARTUP_COMPLE
TE[1:0]
1
HPOUT1R_ HPOUT1R_ HPOUT1R_
RMV_SHOR
OUTP
DLY
DCS_DAC_WR_VAL_0_RD[7:0]
DCS_DAC_WR_VAL_1_RD[7:0]
0
1
0
WSEQ_BUS
Y
DCS_TIMER_PERIOD_01[3:0]
DCS_DAC_WR_VAL_0[7:0]
0
DCS_DAC_WR_COMPLE
TE[1:0]
0
DCS_TRIG_ DCS_TRIG_ DCS_TRIG_ DCS_TRIG_ DCS_ENA_
STARTUP_1 STARTUP_0 DAC_WR_1 DAC_WR_0
CHAN_1
1
0
0
HPOUT1L_R HPOUT1L_O HPOUT1L_D
MV_SHORT
UTP
LY
DCS_SERIES_NO_01[6:0]
DCS_CAL_COMPLETE[1:
0]
0
DCS_TRIG_ DCS_TRIG_
SERIES_1 SERIES_0
1
0
0
WSEQ_ABO WSEQ_STA
RT
RT
AGC_CLIP_THR[3:0]
0
0
0
0
0
0
1
0
0
0
0
6
0
WSEQ_DATA[7:0]
0
WSEQ_ADDR[7:0]
AGC_PWR_THR[3:0]
0
8
WSEQ_ENA
WSEQ_DELAY[3:0]
0
0
0
0
0
0
9
0
WSEQ_DATA_START[3:0]
0
10
AGC_PWR_
AVG
0
0
0
0
DCS_DAC_WR_VAL_1[7:0]
0
0
DCS_TRIG_ DCS_TRIG_
SINGLE_1 SINGLE_0
0
0
0
0
0
0
0
0
AGC_CLIP_
ENA
AGC_PWR_
ENA
0
0
0
0
0
0
0
0
0
0
0
0
CP_ENA
0
0
0
0
0
0
0
WSEQ_EOS
0
0
WSEQ_DATA_WIDTH[2:0]
12
0
0
0
0
13
14
15
Bin Default
0000_0010_0000_0000
1100_0000_0000_0000
1000_0000_0100_0000
0000_0001_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_1000_0000_0111
0000_0101_0100_1010
00PP_00PP_00PP_PP00
0001_1111_0010_0101
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
0000_0000_0000_0000
Production Data
WM9093
PD, March 2012, Rev 4.2
59
WM9093
Production Data
REGISTER BITS BY ADDRESS
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R0 (00h)
Software
Reset
15:0
SW_RESET[15:0] 1001_0000 Writing to this register causes a Software Reset.
_1001_001 Reading from this register will indicate Chip ID.
1
Register 00h Software Reset
REGISTER
BIT
LABEL
DEFAULT
12
SPKOUTL_ENA
0
DESCRIPTION
REFER TO
ADDRESS
R1 (01h)
Power
Managemen
t (1)
Speaker Output Enable
0 = Disabled
1 = Enabled
9
HPOUT1L_ENA
0
Headphone Output (HPL) input stage enable
0 = Disabled
1 = Enabled
8
HPOUT1R_ENA
0
Headphone Output (HPR) input stage enable
0 = Disabled
1 = Enabled
3
OSC_ENA
0
CLK_SYS Oscillator Enable
0 = Disabled
1 = Enabled
2:1
VMID_RES[1:0]
11
VMID Divider Enable and Select
00 = VMID disabled (for OFF mode)
01 = 2 x 50k divider (for normal operation)
10 = 2 x 250k divider (for low power standby)
11 = 2 x 5k divider (for fast start-up)
0
BIAS_ENA
0
Enables the Normal bias current generator (for all
analogue functions)
0 = Disabled
1 = Enabled
Register 01h Power Management (1)
REGISTER
BIT
LABEL
DEFAULT
15
TSHUT
0
DESCRIPTION
REFER TO
ADDRESS
R2 (02h)
Power
Managemen
t (2)
Thermal shutdown status
0 = Normal temperature
1 = Over temperature
14
TSHUT_ENA
1
Thermal sensor enable
0 = Disabled
1 = Enabled
13
TSHUT_OPDIS
1
Thermal shutdown control
(Causes audio outputs to be disabled if an
overtemperature occurs. The thermal sensor must also
be enabled.)
0 = Disabled
1 = Enabled
7
IN1A_ENA
0
IN1A Input PGA Enable
0 = Disabled
1 = Enabled
6
IN1B_ENA
0
IN1B Input PGA Enable
0 = Disabled
1 = Enabled
(Note this is only required for single-ended input on the
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PD, March 2012, Rev 4.2
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WM9093
Production Data
REGISTER
BIT
LABEL
DEFAULT
5
IN2A_ENA
0
DESCRIPTION
REFER TO
ADDRESS
IN1- pin)
IN2A Input PGA Enable
0 = Disabled
1 = Enabled
4
IN2B_ENA
0
IN2B Input PGA Enable
0 = Disabled
1 = Enabled
(Note this is only required for single-ended input on the
IN2- pin)
Register 02h Power Management (2)
REGISTER
BIT
LABEL
DEFAULT
14
AGC_ENA
0
DESCRIPTION
REFER TO
ADDRESS
R3 (03h)
Power
Managemen
t (3)
AGC Enable
0 = Disabled
1 = Enabled
8
SPKLVOL_EN
A
0
Speaker PGA Enable
0 = Disabled
1 = Enabled
Note that SPKMIXL and SPKLVOL are also enabled
when SPKOUTL_ENA is set.
5
MIXOUTL_EN
A
0
MIXOUTR_EN
A
0
SPKMIX_ENA
0
MIXOUTL Headphone Mixer Enable
0 = Disabled
1 = Enabled
4
MIXOUTR Headphone Mixer Enable
0 = Disabled
1 = Enabled
3
SPKMIX Speaker Mixer Enable
0 = Disabled
1 = Enabled
Register 03h Power Management (3)
REGISTER
BIT
LABEL
DEFAULT
15
TOCLK_RATE
0
DESCRIPTION
REFER TO
ADDRESS
R6 (06h)
Clocking 1
TOCLK Rate Divider (/2)
0=f/2
1=f/1
14
TOCLK_ENA
0
TOCLK Enable
0 = Disabled
1 = Enabled
Register 06h Clocking 1
REGISTER
BIT
LABEL
DEFAULT
0
IN3_CLAMP
1
DESCRIPTION
REFER TO
ADDRESS
R21 (15h)
IN3 Line
Control
IN3+ and IN3- input pad VMID clamp
0 = Clamp de-activated
1 = Clamp activated
Register 15h IN3 Line Control
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WM9093
REGISTER
Production Data
BIT
LABEL
DEFAULT
1
IN1_DIFF
1
DESCRIPTION
REFER TO
ADDRESS
R22 (16h)
IN1 Line
Control
PGA IN1A and IN1B configuration
0 = Single-ended mode
1 = Differential mode
0
IN1_CLAMP
1
IN1+ and IN1- input pad VMID clamp
0 = Clamp de-activated
1 = Clamp activated
Register 16h IN1 Line Control
REGISTER
BIT
LABEL
DEFAULT
1
IN2_DIFF
1
DESCRIPTION
REFER TO
ADDRESS
R23 (17h)
IN2 Line
Control
PGA IN2A and IN2B configuration
0 = Single-ended mode
1 = Differential mode
0
IN2_CLAMP
1
IN2+ and IN2- input pad VMID clamp
0 = Clamp de-activated
1 = Clamp activated
Register 17h IN2 Line Control
REGISTER
BIT
LABEL
DEFAULT
8
IN1_VU
N/A
DESCRIPTION
REFER TO
ADDRESS
R24 (18h)
IN1 Line
Input A
Volume
IN1 Volume Update
Writing a 1 to this bit will cause IN1A and IN1B input
PGA volumes to be updated simultaneously
7
IN1A_MUTE
1
IN1A PGA Mute
0 = Un-Mute
1 = Mute
6
IN1A_ZC
0
IN1A PGA Zero Cross Control
0 = Change gain immediately
1 = Change gain on zero cross only
2:0
IN1A_VOL[2:0]
011
IN1A Volume (differential mode)
000 = -6dB
001 = -3.5dB
010 = 0dB
011 = +3.5dB
100 = +6dB
101 = +12dB
110 = +18dB
111 = +18dB
IN1A Volume (single-ended mode)
000 = 0dB
001 = +2.5dB
010 = +6dB
011 = +9.5dB
100 = +12dB
101 = +18dB
110 = +24dB
111 = +24dB
Register 18h IN1 Line Input A Volume
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WM9093
Production Data
REGISTER
BIT
LABEL
DEFAULT
8
IN1_VU
N/A
DESCRIPTION
REFER TO
ADDRESS
R25 (19h)
IN1 Line
Input B
Volume
IN1 Volume Update
Writing a 1 to this bit will cause IN1A and IN1B input
PGA volumes to be updated simultaneously
7
IN1B_MUTE
1
IN1B PGA Mute
0 = Un-Mute
1 = Mute
6
IN1B_ZC
0
IN1B PGA Zero Cross Control
0 = Change gain immediately
1 = Change gain on zero cross only
2:0
IN1B_VOL[2:0]
011
IN1B Volume (differential mode)
000 = -6dB
001 = -3.5dB
010 = 0dB
011 = +3.5dB
100 = +6dB
101 = +12dB
110 = +18dB
111 = +18dB
IN1B Volume (single-ended mode)
000 = 0dB
001 = +2.5dB
010 = +6dB
011 = +9.5dB
100 = +12dB
101 = +18dB
110 = +24dB
111 = +24dB
Register 19h IN1 Line Input B Volume
REGISTER
BIT
LABEL
DEFAULT
8
IN2_VU
N/A
DESCRIPTION
REFER TO
ADDRESS
R26 (1Ah)
IN2 Line
Input A
Volume
Input PGA Volume Update
Writing a 1 to this bit will cause IN2A and IN2B input
PGA volumes to be updated simultaneously
7
IN2A_MUTE
1
IN2A PGA Mute
0 = Un-Mute
1 = Mute
6
IN2A_ZC
0
IN2A PGA Zero Cross Control
0 = Change gain immediately
1 = Change gain on zero cross only
2:0
IN2A_VOL[2:0]
011
IN2A Volume (differential mode)
000 = -6dB
001 = -3.5dB
010 = 0dB
011 = +3.5dB
100 = +6dB
101 = +12dB
110 = +18dB
111 = +18dB
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WM9093
REGISTER
Production Data
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
IN2A Volume (single-ended mode)
000 = 0dB
001 = +2.5dB
010 = +6dB
011 = +9.5dB
100 = +12dB
101 = +18dB
110 = +24dB
111 = +24dB
Register 1Ah IN2 Line Input A Volume
REGISTER
BIT
LABEL
DEFAULT
8
IN2_VU
N/A
DESCRIPTION
REFER TO
ADDRESS
R27 (1Bh)
IN2 Line
Input B
Volume
Input PGA Volume Update
Writing a 1 to this bit will cause IN2A and IN2B input
PGA volumes to be updated simultaneously
7
IN2B_MUTE
1
IN2B PGA Mute
0 = Un-Mute
1 = Mute
6
IN2B_ZC
0
IN2B PGA Zero Cross Control
0 = Change gain immediately
1 = Change gain on zero cross only
2:0
IN2B_VOL[2:0]
011
IN2B Volume (differential mode)
000 = -6dB
001 = -3.5dB
010 = 0dB
011 = +3.5dB
100 = +6dB
101 = +12dB
110 = +18dB
111 = +18dB
IN2B Volume (single-ended mode)
000 = 0dB
001 = +2.5dB
010 = +6dB
011 = +9.5dB
100 = +12dB
101 = +18dB
110 = +24dB
111 = +24dB
Register 1Bh IN2 Line Input B Volume
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WM9093
Production Data
REGISTER
BIT
LABEL
DEFAULT
8
HPOUT1_VU
N/A
DESCRIPTION
REFER TO
ADDRESS
R28 (1Ch)
Left Output
Volume
Headphone Output PGA Volume Update
Writing a 1 to this bit will update HPOUT1LVOL and
HPOUT1RVOL volumes simultaneously.
7
HPOUT1L_ZC
0
Left Headphone Output PGA Zero Cross Control
0 = Change gain immediately
1 = Change gain on zero cross only
6
HPOUT1L_MU
TE
0
HPOUT1L_VO
L[5:0]
10_1101
Left Headphone Output PGA Mute
0 = Un-mute
1 = Mute
5:0
Left Headphone Output PGA Volume
-57dB to +6dB in 1dB steps
Register 1Ch Left Output Volume
REGISTER
BIT
LABEL
DEFAULT
8
HPOUT1_VU
N/A
DESCRIPTION
REFER TO
ADDRESS
R29 (1Dh)
Right Output
Volume
Headphone Output PGA Volume Update
Writing a 1 to this bit will update HPOUT1LVOL and
HPOUT1RVOL volumes simultaneously.
7
HPOUT1R_ZC
0
Right Headphone Output PGA Zero Cross Control
0 = Change gain immediately
1 = Change gain on zero cross only
6
HPOUT1R_MU
TE
0
HPOUT1R_VO
L[5:0]
10_1101
Right Headphone Output PGA Mute
0 = Un-mute
1 = Mute
5:0
Right Headphone Output PGA Volume
-57dB to +6dB in 1dB steps
Register 1Dh Right Output Volume
REGISTER
BIT
LABEL
DEFAULT
12
SPKOUT_CLA
SSAB_MODE
0
SPKMIX_MUT
E
1
IN1A_SPKMIX
_VOL[1:0]
00
DESCRIPTION
REFER TO
ADDRESS
R34 (22h)
SPKMIXL
Attenuation
Speaker Class AB Mode Enable
0 = Class D mode (for SPKMIX source)
1 = Class AB mode (for Voice Bypass source)
8
SPKMIX Output mute
0 = Un-Mute
1 = Mute
7:6
IN1A to SPKMIX volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
5:4
IN1B_SPKMIX
_VOL[1:0]
00
IN1B to SPKMIX volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
3:2
IN2A_SPKMIX
_VOL[1:0]
00
IN2A to SPKMIX volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
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WM9093
REGISTER
Production Data
BIT
LABEL
DEFAULT
1:0
IN2B_SPKMIX
_VOL[1:0]
00
DESCRIPTION
REFER TO
ADDRESS
IN2B to SPKMIX volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
Register 22h SPKMIXL Attenuation
REGISTER
BIT
LABEL
DEFAULT
5
IN3_TO_SPKO
UTL
0
DESCRIPTION
REFER TO
ADDRESS
R36 (24h)
SPKOUT
Mixers
Voice Bypass (IN3 Differential) to Speaker Output
enable
0 = Disabled
1 = Enabled
4
SPKMIXL_TO_
SPKOUTL
1
SPKMIX to Speaker Output enable
0 = Disabled
1 = Enabled
Register 24h SPKOUT Mixers
REGISTER
BIT
LABEL
DEFAULT
7
SPK_ATTN_FB
0
DESCRIPTION
REFER TO
ADDRESS
R37 (25h)
ClassD3
Speaker Amp Gain
0 = 0dB
1 = -12dB
Note – this bit has no effect in Class D mode; the 0dB
setting is always implemented in Class D mode.
6
SPK_VREF_A
B_CTRL
1
SPKOUTL_BO
OST[2:0]
000
Selects Reference for Speaker in Class AB mode
0 = SVDD/2
1 = VMID
5:3
Speaker Output Gain Boost
000 = 1.00x boost (+0dB)
001 = 1.19x boost (+1.5dB)
010 = 1.41x boost (+3.0dB)
011 = 1.68x boost (+4.5dB)
100 = 2.00x boost (+6.0dB)
101 = 2.37x boost (+7.5dB)
110 = 2.81x boost (+9.0dB)
111 = 3.98x boost (+12.0dB)
Register 25h ClassD3
REGISTER
BIT
LABEL
DEFAULT
8
SPKOUT_VU
N/A
7
SPKOUTL_ZC
0
DESCRIPTION
REFER TO
ADDRESS
R38 (26h)
Speaker
Volume Left
Speaker Output PGA Volume Update
Writing a 1 to this bit will update the SPKOUTL volume.
Speaker Output PGA Zero Cross Control
0 = Change gain immediately
1 = Change gain on zero cross only
6
SPKOUTL_MU
TE
0
SPKOUTL_VO
11_1001
Speaker Output PGA Mute
0 = Un-mute
1 = Mute
5:0
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Speaker Output PGA Volume
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WM9093
Production Data
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
L[5:0]
-57dB to +6dB in 1dB steps
Register 26h Speaker Volume Left
REGISTER
BIT
LABEL
DEFAULT
6
IN1A_TO_MIX
OUTL
0
IN1B_TO_MIX
OUTL
0
IN2A_TO_MIX
OUTL
0
IN2B_TO_MIX
OUTL
0
DESCRIPTION
REFER TO
ADDRESS
R45 (2Dh)
Output
Mixer1
IN1A to MIXOUTL enable
0 = Disabled
1 = Enabled
4
IN1B to MIXOUTL enable
0 = Disabled
1 = Enabled
2
IN2A to MIXOUTL enable
0 = Disabled
1 = Enabled
0
IN2B to MIXOUTL enable
0 = Disabled
1 = Enabled
Register 2Dh Output Mixer1
REGISTER
BIT
LABEL
DEFAULT
6
IN1A_TO_MIX
OUTR
0
IN1B_TO_MIX
OUTR
0
IN2A_TO_MIX
OUTR
0
IN2B_TO_MIX
OUTR
0
DESCRIPTION
REFER TO
ADDRESS
R46 (2Eh)
Output
Mixer2
IN1A to MIXOUTR enable
0 = Disabled
1 = Enabled
4
IN1B to MIXOUTR enable
0 = Disabled
1 = Enabled
2
IN2A to MIXOUTR enable
0 = Disabled
1 = Enabled
0
IN2B to MIXOUTR enable
0 = Disabled
1 = Enabled
Register 2Eh Output Mixer2
REGISTER
BIT
LABEL
DEFAULT
8
MIXOUTL_MU
TE
1
IN1A_MIXOUT
L_VOL[1:0]
00
DESCRIPTION
REFER TO
ADDRESS
R47 (2Fh)
Output
Mixer3
MIXOUTL Output mute
0 = Un-Mute
1 = Mute
7:6
IN1A to MIXOUTL volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
5:4
IN1B_MIXOUT
L_VOL[1:0]
00
IN1B to MIXOUTL volume control
00 = 0dB
01 = -6dB
10 = -9dB
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WM9093
REGISTER
Production Data
BIT
LABEL
DEFAULT
3:2
IN2A_MIXOUT
L_VOL[1:0]
00
DESCRIPTION
REFER TO
ADDRESS
11 = -12dB
IN2A to MIXOUTL volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
1:0
IN2B_MIXOUT
L_VOL[1:0]
00
IN2B to MIXOUTL volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
Register 2Fh Output Mixer3
REGISTER
BIT
LABEL
DEFAULT
8
MIXOUTR_MU
TE
1
IN1A_MIXOUT
R_VOL[1:0]
00
DESCRIPTION
REFER TO
ADDRESS
R48 (30h)
Output
Mixer4
MIXOUTR Output mute
0 = Un-Mute
1 = Mute
7:6
IN1A to MIXOUTR volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
5:4
IN1B_MIXOUT
R_VOL[1:0]
00
IN1B to MIXOUTR volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
3:2
IN2A_MIXOUT
R_VOL[1:0]
00
IN2A to MIXOUTR volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
1:0
IN2B_MIXOUT
R_VOL[1:0]
00
IN2B to MIXOUTR volume control
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
Register 30h Output Mixer4
REGISTER
BIT
LABEL
DEFAULT
6
IN1A_TO_SPK
MIX
0
IN1B_TO_SPK
MIX
0
IN2A_TO_SPK
MIX
0
DESCRIPTION
REFER TO
ADDRESS
R54 (36h)
Speaker
Mixer
IN1A to SPKMIX enable
0 = Disabled
1 = Enabled
4
IN1B to SPKMIX enable
0 = Disabled
1 = Enabled
2
IN2A to SPKMIX enable
0 = Disabled
1 = Enabled
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WM9093
Production Data
REGISTER
BIT
LABEL
DEFAULT
0
IN2B_TO_SPK
MIX
0
DESCRIPTION
REFER TO
ADDRESS
IN2B to SPKMIX enable
0 = Disabled
1 = Enabled
Register 36h Speaker Mixer
REGISTER
BIT
LABEL
DEFAULT
3
VMID_BUF_EN
A
1
VMID_ENA
1
DESCRIPTION
REFER TO
ADDRESS
R57 (39h)
AntiPOP2
VMID Buffer Enable
0 = Disabled
1 = Enabled
0
Enable VMID master bias current source
0 = Disabled
1 = Enabled
Register 39h AntiPOP2
REGISTER
BIT
LABEL
DEFAULT
8
WSEQ_ENA
0
DESCRIPTION
REFER TO
ADDRESS
R70 (46h)
Write
Sequencer 0
Write Sequencer Enable.
0 = Disabled
1 = Enabled
3:0
WSEQ_WRITE
_INDEX[3:0]
0000
Sequence Write Index. This is the memory location to
which any updates to R71 and R72 will be copied.
0 to 15 = RAM addresses
Register 46h Write Sequencer 0
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
14:12
WSEQ_DATA_
WIDTH[2:0]
000
Width of the data block written in this sequence step.
000 = 1 bit
001 = 2 bits
010 = 3 bits
011 = 4 bits
100 = 5 bits
101 = 6 bits
110 = 7 bits
111 = 8 bits
11:8
WSEQ_DATA_
START[3:0]
0000
Bit position of the LSB of the data block written in this
sequence step.
ADDRESS
R71 (47h)
Write
Sequencer 1
0000 = Bit 0
…
1111 = Bit 15
7:0
WSEQ_ADDR[ 0000_0000 Control Register Address to be written to in this
sequence step.
7:0]
Register 47h Write Sequencer 1
REGISTER
BIT
LABEL
DEFAULT
14
WSEQ_EOS
0
DESCRIPTION
REFER TO
ADDRESS
R72 (48h)
Write
Sequencer 2
End of Sequence flag. This bit indicates whether the
Control Write Sequencer should stop after executing
this step.
0 = Not end of sequence
1 = End of sequence (Stop the sequencer after this
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WM9093
REGISTER
Production Data
BIT
LABEL
DEFAULT
11:8
WSEQ_DELAY
[3:0]
0000
DESCRIPTION
REFER TO
ADDRESS
7:0
step).
Time delay after executing this step.
Total time per step (including execution) = 62.5us ×
(2^WSEQ_DELAY + 8)
WSEQ_DATA[ 0000_0000 Data to be written in this sequence step. When the data
width is less than 8 bits, then one or more of the MSBs
7:0]
of WSEQ_DATA are ignored. It is recommended that
unused bits be set to 0.
Register 48h Write Sequencer 2
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
9
WSEQ_ABOR
T
0
Writing a 1 to this bit aborts the current sequence and
returns control of the device back to the serial control
interface.
8
WSEQ_START
0
Writing a 1 to this bit starts the write sequencer at the
memory location indicated by the
WSEQ_START_INDEX field. The sequence continues
until it reaches an “End of sequence” flag. At the end of
the sequence, this bit will be reset by the Write
Sequencer.
5:0
WSEQ_START
_INDEX[5:0]
00_0000
ADDRESS
R73 (49h)
Write
Sequencer 3
Sequence Start Index. This is the memory location of
the first command in the selected sequence.
0 to 15 = RAM addresses
16 to 58 = ROM addresses
59 to 63 = Reserved
Register 49h Write Sequencer 3
REGISTER
BIT
LABEL
DEFAULT
0
WSEQ_BUSY
0
DESCRIPTION
REFER TO
ADDRESS
R74 (4Ah)
Write
Sequencer 4
Sequencer Busy flag (Read Only).
0 = Sequencer idle
1 = Sequencer busy
Note: it is not possible to write to control registers via
the control interface while the Sequencer is Busy.
Register 4Ah Write Sequencer 4
REGISTER
BIT
LABEL
DEFAULT
5:0
WSEQ_CURR
ENT_INDEX[5:
0]
00_0000
DESCRIPTION
REFER TO
ADDRESS
R75 (4Bh)
Write
Sequencer 5
Sequence Current Index. This is the location of the
most recently accessed command in the write
sequencer memory.
Register 4Bh Write Sequencer 5
REGISTER
BIT
LABEL
DEFAULT
15
CP_ENA
0
DESCRIPTION
REFER TO
ADDRESS
R76 (4Ch)
Charge
Pump 1
Charge Pump Control
0 = Disabled
1 = Enabled
Register 4Ch Charge Pump 1
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WM9093
Production Data
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
13
DCS_TRIG_SI
NGLE_1
0
Writing 1 to this bit selects a single DC offset correction
for HPOUT1R.
ADDRESS
R84 (54h)
DC Servo 0
In readback, a value of 1 indicates that the DC Servo
single correction is in progress.
12
DCS_TRIG_SI
NGLE_0
0
Writing 1 to this bit selects a single DC offset correction
for HPOUT1L.
In readback, a value of 1 indicates that the DC Servo
single correction is in progress.
9
DCS_TRIG_SE
RIES_1
0
Writing 1 to this bit selects a series of DC offset
corrections for HPOUT1R.
In readback, a value of 1 indicates that the DC Servo
DAC Write correction is in progress.
8
DCS_TRIG_SE
RIES_0
0
Writing 1 to this bit selects a series of DC offset
corrections for HPOUT1L.
In readback, a value of 1 indicates that the DC Servo
DAC Write correction is in progress.
5
DCS_TRIG_ST
ARTUP_1
0
Writing 1 to this bit selects Start-Up DC Servo mode for
HPOUT1R.
In readback, a value of 1 indicates that the DC Servo
Start-Up correction is in progress.
4
DCS_TRIG_ST
ARTUP_0
0
Writing 1 to this bit selects Start-Up DC Servo mode for
HPOUT1L.
In readback, a value of 1 indicates that the DC Servo
Start-Up correction is in progress.
3
DCS_TRIG_DA
C_WR_1
0
Writing 1 to this bit selects DAC Write DC Servo mode
for HPOUTR.
In readback, a value of 1 indicates that the DC Servo
DAC Write correction is in progress.
2
DCS_TRIG_DA
C_WR_0
0
Writing 1 to this bit selects DAC Write DC Servo mode
for HPOUTL.
In readback, a value of 1 indicates that the DC Servo
DAC Write correction is in progress.
1
DCS_ENA_CH
AN_1
0
DCS_ENA_CH
AN_0
0
DC Servo enable for HPOUT1R
0 = Disabled
1 = Enabled
0
DC Servo enable for HPOUT1L
0 = Disabled
1 = Enabled
Register 54h DC Servo 0
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WM9093
REGISTER
Production Data
BIT
LABEL
DEFAULT
11:5
DCS_SERIES_
NO_01[6:0]
010_1010
DESCRIPTION
REFER TO
ADDRESS
R85 (55h)
DC Servo 1
Number of DC Servo updates to perform in a series
event.
0 = 1 updates
1 = 2 updates
...
127 = 128 updates
3:0
DCS_TIMER_P
ERIOD_01[3:0]
1010
Time between periodic updates. Time is calculated as
0.256s x (2^PERIOD)
0000 = Off
0001 = 0.52s
1010 = 266s (4min 26s)
1111 = 8519s (2hr 22s)
Register 55h DC Servo 1
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R87 (57h)
DC Servo 3
15:8
DCS_DAC_WR 0000_0000 DC Offset value for HPOUT1R in DAC Write DC Servo
mode.
_VAL_1[7:0]
Two’s complement format.
LSB is 0.25mV.
Range is -32mV to +31.75mV
7:0
DCS_DAC_WR 0000_0000 DC Offset value for HPOUT1L in DAC Write DC Servo
mode.
_VAL_0[7:0]
Two’s complement format.
LSB is 0.25mV.
Range is -32mV to +31.75mV
Register 57h DC Servo 3
REGISTER
BIT
LABEL
DEFAULT
9:8
DCS_CAL_CO
MPLETE[1:0]
00
DESCRIPTION
REFER TO
ADDRESS
R88 (58h)
DC Servo
Readback 0
DC Servo Complete status
0 = DAC Write or Start-Up DC Servo mode not
completed.
1 = DAC Write or Start-Up DC Servo mode complete.
Bit [1] = HPOUT1R
Bit [0] = HPOUT1L
5:4
DCS_DAC_WR
_COMPLETE[1
:0]
00
DC Servo DAC Write status
0 = DAC Write DC Servo mode not completed.
1 = DAC Write DC Servo mode complete.
Bit [1] = HPOUT1R
Bit [0] = HPOUT1L
1:0
DCS_STARTU
P_COMPLETE[
1:0]
00
DC Servo Start-Up status
0 = Start-Up DC Servo mode not completed.
1 = Start-Up DC Servo mode complete.
Bit [1] = HPOUT1R
Bit [0] = HPOUT1L
Register 58h DC Servo Readback 0
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WM9093
Production Data
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R89 (59h)
DC Servo
Readback 1
7:0
DCS_DAC_WR 0000_0000 Readback value for HPOUT1R.
_VAL_1_RD[7:
Two’s complement format.
0]
LSB is 0.25mV.
Range is -32mV to +31.75mV
Register 59h DC Servo Readback 1
REGISTER
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
ADDRESS
R90 (5Ah)
DC Servo
Readback 2
7:0
DCS_DAC_WR 0000_0000 Readback value for HPOUT1L.
_VAL_0_RD[7:
Two’s complement format.
0]
LSB is 0.25mV.
Range is -32mV to +31.75mV
Register 5Ah DC Servo Readback 2
REGISTER
BIT
LABEL
DEFAULT
7
HPOUT1L_RM
V_SHORT
0
DESCRIPTION
REFER TO
ADDRESS
R96 (60h)
Analogue
HP 0
Removes HPOUT1L short
0 = HPOUT1L short enabled
1 = HPOUT1L short removed
Note: Remove short after output stage has been
enabled.
6
HPOUT1L_OU
TP
0
Enables HPOUT1L output stage
0 = Disabled
1 = Enabled
Note: Set after offset correction is complete
5
HPOUT1L_DL
Y
0
Enables HPOUT1L intermediate stage
0 = Disabled
1 = Enabled
Note: Set with at least 20us delay after HPOUT1L_ENA
has been set.
3
HPOUT1R_RM
V_SHORT
0
Removes HPOUT1R short
0 = HPOUT1R short enabled
1 = HPOUT1R short removed
Note: Remove short after output stage has been
enabled.
2
HPOUT1R_OU
TP
0
Enables HPOUT1R output stage
0 = Disabled
1 = Enabled
Note: Set after offset correction is complete
1
HPOUT1R_DL
Y
0
Enables HPOUT1R intermediate stage
0 = Disabled
1 = Enabled
Note: Set with at least 20us delay after HPOUT1R_ENA
has been set.
Register 60h Analogue HP 0
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WM9093
REGISTER
Production Data
BIT
LABEL
DEFAULT
15
AGC_CLIP_EN
A
1
AGC_CLIP_TH
R [3:0]
0110
DESCRIPTION
REFER TO
ADDRESS
R98 (62h)
AGC Control
0
Enable AGC Anti-Clip Mode
0 = Disabled
1 = Enabled
11:8
AGC Anti-Clip Threshold
Sets the headroom between SPKPGA output and
SVDD at which Anti-Clip limiting will be applied
0000 = -200mV
0001 = -150mV
0010 = -100mV
0011 = -50mV
0100 = 0mV
0101 = 50mV
0110 = 100mV
0111 = 150mV
1000 = 200mV
1001 = 250mV
1010 = 300mV
1011 = 400mV
1100 = 500mV
1101 = 600mV
1110 = 700mV
1111 = 800mV
6:4
AGC_CLIP_AT
K[2:0]
100
AGC Anti-Clip Attack Rate
Sets the rate of AGC gain reduction when clipping is
detected
000 = 0.6ms/6dB
001 = 5.4ms/6dB
010 = 10.2ms/6dB
011 = 15.0ms/6dB
100 = 19.8ms/6dB
101 = 24.6ms/6dB
110 = 29.4ms/6dB
111 = 34.1ms/6dB
2:0
AGC_CLIP_DC
Y[2:0]
000
AGC Anti-Clip Decay Rate
Sets the rate of AGC gain increments after a period of
clipping
000 = 120ms/6dB
001 = 480ms/6dB
010 = 820ms/6dB
011 = 1170ms/6dB
100 = 1640ms/6dB
101 = 2050ms/6dB
110 = 2730ms/6dB
111 = 4100ms/6dB
Register 62h AGC Control 0
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REGISTER
BIT
LABEL
DEFAULT
15
AGC_PWR_EN
A
1
AGC_PWR_AV
G
0
AGC_PWR_TH
R [2:0]
0000
DESCRIPTION
REFER TO
ADDRESS
R99 (63h)
AGC Control
1
Enable AGC Power Limit Mode
0 = Disabled
1 = Enabled
12
AGC Power Measurement mode
0 = Instantaneous power
1 = RMS power
11:8
AGC Power Limit Threshold
Sets the output level at which Power limiting will be
applied. Assumes RMS power mode and 8ohm
speaker.
0000 = 300mW
0001 = 350mW
0010 = 400mW
0011 = 450mW
0100 = 500mW
0101 = 550mW
0110 = 600mW
0111 = 650mW
1000 = 700mW
1001 = 750mW
1010 = 800mW
1011 = 850mW
1100 = 900mW
1101 = 950mW
1110 = 1000mW
1111 = 1050mW
6:4
AGC_PWR_AT
K[2:0]
000
AGC Power Limiting Attack Rate
Sets the rate of AGC gain reduction when power
limiting is applied
000 = 120ms/6dB
001 = 480ms/6dB
010 = 840ms/6dB
011 = 1200ms/6dB
100 = 1680ms/6dB
101 = 2040ms/6dB
110 = 2760ms/6dB
111 = 4080ms/6dB
2:0
AGC_PWR_D
CY[2:0]
000
AGC Power Limiting Decay Rate
Sets the rate of AGC gain increments after a period of
power limiting
000 = 1080ms/6dB
001 = 1200ms/6dB
010 = 1320ms/6dB
011 = 1680ms/6dB
100 = 2040ms/6dB
101 = 2760ms/6dB
110 = 4080ms/6dB
111 = 8160ms/6dB
Register 63h AGC Control 1
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REGISTER
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BIT
LABEL
DEFAULT
8
AGC_RAMP
0
DESCRIPTION
REFER TO
ADDRESS
R100 (64h)
AGC Control
2
AGC Ramp Control
Selects how the AGC gain adjustment is applied
0 = Multiple gains steps per zero-cross
1 = Single gain step per zero-cross
5:0
AGC_MINGAIN
[5:0]
00_0000
AGC Minimum Gain
-57dB to +6dB in 1dB steps
Register 64h AGC Control 2
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APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
AUDIO INPUT PATHS
The WM9093 provides 6 analogue audio inputs. Each of these inputs is referenced to the internal DC
reference, VMID. A DC blocking capacitor is required for each input pin used in the target application.
The choice of capacitor is determined by the filter that is formed between that capacitor and the input
impedance of the input pin. The circuit is illustrated in Figure 16.
Figure 16 Audio Input Path DC Blocking Capacitor
If the input impedance is known, and the cut-off frequency is known, then the minimum capacitor
value may be derived easily. However, it can be seen from the representation in Figure 16 that the
input impedance is not fixed in all applications but can vary with gain and boost amplifier settings. The
choice of capacitor for a 20Hz cut-off frequency is shown in Table 35 for different input impedance
conditions. The applicable input impedance can be found in the “Electrical Characteristics” section of
this datasheet.
INPUT IMPEDANCE
MINIMUM CAPACITANCE
FOR 20HZ PASS BAND
2k
4 F
15k
0.5 F
30k
0.27 F
60k
0.13 F
Table 35 Audio Input DC Blocking Capacitors
Using the figures in Table 35, it follows that a 1F capacitance for all input connections will give good
results in most cases. Tantalum electrolytic capacitors are particularly suitable as they offer high
stability in a small package size.
Ceramic equivalents are a cost effective alternative to the superior tantalum packages, but care must
be taken to ensure the desired capacitance is maintained at the HPVDD operating voltage. Also,
ceramic capacitors may show microphonic effects, where vibrations and mechanical conditions give
rise to electrical signals. This is particularly problematic for microphone input paths where a large
signal gain is required.
A single capacitor is required for a line input or single-ended microphone connection. In the case of a
differential connection, a DC blocking capacitor is required on both input pins.
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POWER SUPPLY DECOUPLING
Electrical coupling exists particularly in digital logic systems where switching in one sub-system
causes fluctuations on the power supply. This effect occurs because the inductance of the power
supply acts in opposition to the changes in current flow that are caused by the logic switching. The
resultant variations (or ‘spikes’) in the power supply voltage can cause malfunctions and unintentional
behavior in other components. A decoupling (or ‘bypass’) capacitor can be used as an energy storage
component which will provide power to the decoupled circuit for the duration of these power supply
variations, protecting it from malfunctions that could otherwise arise.
Coupling also occurs in a lower frequency form when ripple is present on the power supply rail
caused by changes in the load current or by limitations of the power supply regulation method. In
audio components such as the WM9093, these variations can alter the performance of the signal
path, leading to degradation in signal quality. A decoupling (or ‘bypass’) capacitor can be used to filter
these effects, by presenting the ripple voltage with a low impedance path that does not affect the
circuit to be decoupled.
These coupling effects are addressed by placing a capacitor between the supply rail and the
corresponding ground reference. In the case of systems comprising multiple power supply rails,
decoupling should be provided on each rail.
The recommended power supply decoupling capacitors for WM9093 are listed below in Table 36.
POWER SUPPLY
DECOUPLING CAPACITOR
HPVDD
2.2F ceramic
SVDD
0.1F ceramic (see Note)
Table 36 Power Supply Decoupling Capacitors
Note: 0.1F is required with 2.2F a guide to the total required power rail capacitance.
All decoupling capacitors should be placed as close as possible to the WM9093 device. The
connection between GND, the HPVDD decoupling capacitor and the main system ground should be
made at a single point as close as possible to the AGND ball of the WM9093.
The BIAS capacitor is not, technically, a decoupling capacitor. However, it does serve a similar
purpose in filtering noise on the VMID reference. The connection between GND, the BIAS decoupling
capacitor and the main system ground should be made at a single point as close as possible to the
GND ball of the WM9093.
Due to the wide tolerance of many types of ceramic capacitors, care must be taken to ensure that the
selected components provide the required capacitance across the required temperature and voltage
ranges in the intended application. For most application the use of ceramic capacitors with capacitor
dielectric X5R is recommended.
HEADPHONE OUTPUT PATH
The headphone output on WM9093 is ground referenced and therefore does not require the large,
expensive capacitors necessary for VMID-referenced solutions. For best audio performance, it is
recommended to connect a zobel network to the audio output pins. This network should comprise of a
100nF capacitor and 20ohm resistor in series with each other (see “Analogue Outputs” section).
These components have the effect of dampening high frequency oscillations or instabilities that can
arise outside the audio band under certain conditions. Possible sources of these instabilities include
the inductive load of a headphone coil or an active load in the form of an external line amplifier.
CLASS D SPEAKER CONNECTIONS
The WM9093 incorporates a Class D speaker driver. By default, the speaker driver operates in Class
D mode, which offers high amplifier efficiency at large signal levels. As the Class D output is a pulse
width modulated (PWM) signal, the choice of speakers and tracking of signals is critical for ensuring
good performance and reducing EMI in this mode.
The efficiency of the speaker drivers is affected by the series resistance between the WM9093 and
the speaker (e.g. PCB track loss and inductor ESR) as shown in Figure 17. This resistance should be
as low as possible to maximise efficiency.
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Figure 17 Speaker Connection Losses
The Class D output requires external filtering in order to recreate the audio signal. This may be
nd
st
implemented using a 2 order LC or 1 order RC filter, or else may be achieved by using a
loudspeaker whose internal inductance provides the required filter response. An LC or RC filter
should be used if the loudspeaker characteristics are unknown or unsuitable, or if the length of the
loudspeaker connection is likely to lead to EMI problems.
nd
In applications where it is necessary to provide Class D filter components, a 2 order LC filter is the
recommended solution as it provides more attenuation at higher frequencies and minimises power
dissipated in the filter when compared to a first order RC filter (lower ESR). This maximises both
rejection of unwanted switching frequencies and overall speaker efficiency. A suitable implementation
is illustrated in Figure 18.
Figure 18 Class D Output Filter Components
A simple equivalent circuit of a loudspeaker consists of a serially connected resistor and inductor, as
shown in Figure 19. This circuit provides a low pass filter for the speaker output. If the loudspeaker
characteristics are suitable, then the loudspeaker itself can be used in place of the filter components
described earlier. This is known as ‘filterless’ operation.
Figure 19 Speaker Equivalent Circuit for Filterless Operation
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For filterless Class D operation, it is important to ensure that a speaker with suitable inductance is
chosen. For example, if we know the speaker impedance is 8Ω and the desired cut-off frequency is
20kHz, then the optimum speaker inductance may be calculated as:
8 loudspeakers typically have an inductance in the range 20H to 100H, however, it should be
noted that a loudspeaker inductance will not be constant across the relevant frequencies for Class D
operation (up to and beyond the Class D switching frequency). Care should be taken to ensure that
the cut-off frequency of the loudspeaker’s filtering is low enough to suppress the high frequency
energy of the Class D switching and, in so doing, to prevent speaker damage. The Class D outputs of
the WM9093 operate at much higher frequencies than is recommended for most speakers and it must
be ensured that the cut-off frequency is low enough to protect the speaker.
RECOMMENDED EXTERNAL COMPONENTS DIAGRAM
Figure 20 below provides a summary of recommended external components for WM9093. Note that
the diagram does not include any components that are specific to the end application e.g. they do not
include filtering on the speaker outputs (assume filterless class D operation), RF decoupling, or RF
filtering for pins which connect to the external world i.e. headphone or speaker outputs.
Figure 20 Recommended External Components
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PCB LAYOUT CONSIDERATIONS
Poor PCB layout will degrade the performance and be a contributory factor in EMI, ground bounce
and resistive voltage losses. All external components should be placed as close to the WM9093
device as possible, with current loop areas kept as small as possible. Specific factors relating to
Class D loudspeaker connection are detailed below.
CLASS D LOUDSPEAKER CONNECTION
Long, exposed PCB tracks or connection wires will emit EMI. The distance between the WM9093 and
the loudspeaker should therefore be kept as short as possible. Where speakers are connected to the
PCB via a cable form, it is recommended that a shielded twisted pair cable is used. The shield should
be connected to the main system, with care taken to ensure ground loops are avoided.
Further reduction in EMI can be achieved using PCB ground (or VDD) planes and also by using
passive LC components to filter the Class D switching waveform. When passive filtering is used, low
ESR components should be chosen in order to minimise the series resistance between the WM9093
and the speaker, maximising the power efficiency.
LC passive filtering will usually be effective at reducing EMI at frequencies up to around 30MHz. To
reduce emissions at higher frequencies, ferrite beads can also be used. These should be positioned
as close to the device as possible.
These techniques for EMI reduction are illustrated in Figure 21.
Figure 21 EMI Reduction Techniques
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PACKAGE DIMENSIONS
B: 20 BALL W-CSP PACKAGE 2.500 X 2.000 X 0.7mm BODY, 0.50 mm BALL PITCH
DM086.A
6
D
DETAIL 1
A
2
g
3
4
5
A2
2
1
A
A1
CORNER
4
B
e
5
E
E1
C
D
2X
DETAIL 2
2X
e
0.10 Z
0.10 Z
TOP VIEW
D1
BOTTOM VIEW
f1
SOLDER BALL
f2
bbb Z
h
1
Z
A1
DETAIL 1
DETAIL 2
Symbols
A
A1
A2
D
D1
E
E1
e
f1
MIN
0.646
0.219
0.391
f2
0.250
0.270
g
0.036
h
Dimensions (mm)
NOM
MAX
0.700
0.754
0.244
0.269
0.441
0.416
2.500
2.560
2.000 BSC
2.000
2.100
1.500 BSC
0.500 BSC
0.040
NOTE
5
0.044
0.314 BSC
NOTES:
1. PRIMARY DATUM -Z- AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.
2. THIS DIMENSION INCLUDES STAND-OFF HEIGHT ‘A1’ AND BACKSIDE COATING.
3. A1 CORNER IS IDENTIFIED BY INK/LASER MARK ON TOP PACKAGE.
4. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY.
5. ‘e’ REPRESENTS THE BASIC SOLDER BALL GRID PITCH.
6. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
7. FOLLOWS JEDEC DESIGN GUIDE MO-211-C.
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WM9093
IMPORTANT NOTICE
Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,
delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the
right to make changes to its products and specifications or to discontinue any product or service without notice. Customers
should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.
Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating
safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer
product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for
such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where
malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage.
Any use of products by the customer for such purposes is at the customer’s own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other
intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or
services might be or are used. Any provision or publication of any third party’s products or services does not constitute
Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document
belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is
accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is
not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in
this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or
accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any
reliance placed thereon by any person.
ADDRESS:
Wolfson Microelectronics plc
26 Westfield Road
Edinburgh
EH11 2QB
United Kingdom
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: [email protected]
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REVISION HISTORY
DATE
REV
08/03/12
4.2
DESCRIPTION OF CHANGES
Labelling corrected in performance plots.
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