WM8192 (8 + 8) Bit Output 16-bit CIS/CCD AFE/Digitiser Product Preview, June 2000, Rev 1.0 DESCRIPTION FEATURES The WM8192 is a 16-bit analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors (CIS) at pixel sample rates of up to 6MSPS. The device includes three analogue signal processing channels each of which contains Reset Level Clamping, Correlated Double Sampling and Programmable Gain and Offset adjust functions. Three multiplexers allow single channel processing. The output from each of these channels is time multiplexed into a single high-speed 16-bit Analogue to Digital Converter. The digital output data is available in 8 or 4-bit wide multiplexed format. An internal 4-bit DAC is supplied for internal reference level generation. This may be used during CDS to reference CIS signals or during Reset Level Clamping to clamp CCD signals. An external reference level may also be supplied. ADC references are generated internally, ensuring optimum performance from the device. Using an analogue supply voltage of 5V and a digital interface supply of either 5V or 3.3V, the WM8192 typically only consumes 240mW when operating from a single 5V supply. • • • • • • • • • • • • • 16-bit ADC 6MSPS conversion rate Low power – 240mW typical 5V single supply or 5V/3.3V dual supply operation Single or 3 channel operation Correlated double sampling Programmable gain (8-bit resolution) Programmable offset adjust (8-bit resolution) Programmable clamp voltage 8 or 4-bit wide multiplexed data output formats Internally generated voltage references 28-pin SOIC package Serial control interface APPLICATIONS • • • • Flatbed and sheetfeed scanners USB compatible scanners Multi-function peripherals High-performance CCD sensor interface BLOCK DIAGRAM VRLC/VBIAS (26) VSMP (5) CL RS VS G B RLC M U X RLC 8 G + RLC DAC OFFSET DAC CDS OFFSET DAC + I/P SIGNAL POLARITY ADJUST PGA 8 + 8 PGA 8 CDS RLC (4) OEB M U X 8 BINP (27) OFFSET DAC + R WM8192 VREF/BIAS M U X CDS B GINP (28) VRT VRX VRB (24) (25) (23) DVDD1 DVDD2 (10) (3) AVDD (21) TIMING CONTROL R RINP (1) MCLK (7) + WOLFSON MICROELECTRONICS LTD Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: [email protected] http://www.wolfson.co.uk (2) AGND2 DATA I/O PORT + I/P SIGNAL POLARITY ADJUST 4 (22) AGND1 16BIT ADC I/P SIGNAL POLARITY ADJUST PGA 8 M U X (13) OP[0] (14) OP[1] (15) OP[2] (16) OP[3] (17) OP[4] (18) OP[5] (19) OP[6] (20) OP[7]/SDO CONFIGURABLE SERIAL CONTROL INTERFACE (9) SEN (12) SCK (11) SDI (6) RLC/ACYC (8) DGND Product Preview data sheets contain specifications for products in the formative phase of development. These products may be changed or discontinued without notice. 2000 Wolfson Microelectronics Ltd. WM8192 Product Preview PIN CONFIGURATION ORDERING INFORMATION RINP 1 28 GINP AGND2 2 27 BINP DVDD1 3 26 VRLC/VBIAS OEB 4 25 VRX VSMP 5 24 VRT RLC/ACYC 6 23 VRB MCLK 7 22 AGND1 DGND 8 21 AVDD SEN 9 20 OP[7]/SDO DVDD2 10 19 OP[6] SDI 11 18 OP[5] SCK 12 17 OP[4] OP[0] 13 16 OP[3] OP[1] 14 15 OP[2] DEVICE TEMP. RANGE PACKAGE XWM8192CDW/V 0 to 70oC 28-pin SOIC PIN DESCRIPTION PIN NAME TYPE 1 RINP Analogue input DESCRIPTION 2 AGND2 Supply Analogue ground (0V). 3 DVDD1 Supply Digital supply (5V) for logic and clock generator. This must be operated at the same potential as AVDD. 4 OEB Digital input Output Hi-Z control, all digital outputs disabled when OEB = 1. 5 VSMP Digital input Video sample synchronisation pulse. 6 RLC/ACYC Digital input RLC (active high) selects reset level clamp on a pixel-by-pixel basis – tie high if used on every pixel. ACYC autocycles between R, G, B inputs. 7 MCLK Digital input Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or any multiple of 2 thereafter depending on input sample mode). 8 DGND Supply 9 SEN Digital input 10 DVDD2 Supply 11 SDI Digital input Serial data input. 12 SCK Digital input Serial clock. Red channel input video. Digital ground (0V). Enables the serial interface when high. Digital supply (5V/3.3V), all digital I/O pins. Digital multiplexed output data bus. ADC output data (d15:d0) is available in two multiplexed formats as shown, under the control of register bit MUXOP. See ‘Output Formats’ description in Device Description section for further details. 8+8-bit 4+4+4+4-bit A B A B C D 13 OP[0] Digital output d8 d0 14 OP[1] Digital output d9 d1 15 OP[2] Digital output d10 d2 16 OP[3] Digital output d11 d3 17 OP[4] Digital output d12 d4 d12 d8 d4 d0 18 OP[5] Digital output d13 d5 d13 d9 d5 d1 19 OP[6] Digital output d14 d6 d14 d10 d6 d2 20 OP[7] Digital output d15 d7 d15 d11 d7 d3 Alternatively, pin OP[7]/SDO may be used to output register read-back data when OEB = 0 and SEN has been pulsed high. See Serial Interface description in Device Description section for further details. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 June 2000 2 WM8192 Product Preview PIN NAME TYPE DESCRIPTION 21 AVDD Supply Analogue supply (5V). This must be operated at the same potential as DVDD1. 22 AGND1 Supply Analogue ground (0V). 23 VRB Analogue output Lower reference voltage. This pin must be connected to AGND via a decoupling capacitor. 24 VRT Analogue output Upper reference voltage. This pin must be connected to AGND via a decoupling capacitor. 25 VRX Analogue output Input return bias voltage. This pin must be connected to AGND via a decoupling capacitor. 26 VRLC/VBIAS Analogue I/O Selectable analogue output voltage for RLC or single-ended bias reference. This pin would typically be connected to AGND via a decoupling capacitor. VRLC can be externally driven if programmed Hi-Z. 27 BINP Analogue input Blue channel input video. 28 GINP Analogue input Green channel input video. ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. As per JEDEC specifications A112-A and A113-B, this product requires specific storage conditions prior to surface mount assembly. It is anticipated as having a Moisture Sensitivity Level of 2 and as such will be supplied in vacuum-sealed moisture barrier bags. CONDITION MIN MAX Analogue supply voltage: AVDD GND - 0.3V GND + 7V Digital supply voltages: DVDD1 − 2 GND - 0.3V GND + 7V Digital ground: DGND GND - 0.3V GND + 0.3V Analogue grounds: AGND1 − 2 GND - 0.3V GND + 0.3V Digital inputs, digital outputs and digital I/O pins GND - 0.3V DVDD2 + 0.3V Analogue inputs (RINP, GINP, BINP) GND - 0.3V AVDD + 0.3V Other pins GND - 0.3V AVDD + 0.3V 0°C +70°C -65°C +150°C Operating temperature range: TA Storage temperature Package body temperature (soldering, 10 seconds) +240°C Package body temperature (soldering, 2 minutes) +183°C Notes: 1. 2. GND denotes the voltage of any ground pin. AGND1, AGND2 and DGND pins are intended to be operated at the same potential. Differential voltages between these pins will degrade performance. RECOMMENDED OPERATING CONDITIONS CONDITION SYMBOL MIN TA 0 Analogue supply voltage AVDD 4.75 5.0 5.25 V Digital core supply voltage DVDD1 4.75 5.0 5.25 V 5V I/O DVDD2 4.75 5.0 5.25 V 3.3V I/O DVDD2 2.97 3.3 3.63 V Operating temperature range Digital I/O supply voltage WOLFSON MICROELECTRONICS LTD TYP MAX UNITS 70 °C PP Rev 1.0 June 2000 3 WM8192 Product Preview ELECTRICAL CHARACTERISTICS Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions) Full-scale input voltage range (see Note 1) Max Gain Min Gain Input signal limits (see Note 2) VIN 0.4 4.08 0 Vp-p Vp-p AVDD V Full-scale transition error Gain = 0dB; PGA[7:0] = 4B(hex) 20 mV Zero-scale transition error Gain = 0dB; PGA[7:0] = 4B(hex) 20 mV Differential non-linearity DNL TBD LSB Integral non-linearity INL TBD LSB 1 % Channel to channel gain matching References Upper reference voltage VRT 2.85 V Lower reference voltage VRB 1.35 V Input return bias voltage VRX 0.65 V Diff. reference voltage (VRT-VRB) VRTB 1.5 V 1 Ω Output resistance VRT, VRB, VRX VRLC/Reset-Level Clamp (RLC) RLC switching impedance 50 Ω VRLC short-circuit current 5 mA VRLC output resistance Ω 2 VRLC Hi-Z leakage current VRLC = 0 to AVDD 1 RLCDAC resolution µA 4 bits RLCDAC step size, RLCDAC = 0 VRLCSTEP 0.24 V/step RLCDAC step size, RLCDAC = 1 VRLCSTEP 0.16 V/step RLCDAC output voltage at code 0(hex), RLCDACRNG = 0 VRLCBOT 0.40 V RLCDAC output voltage at code 0(hex), RLCDACRNG = 1 VRLCBOT 0.25 V RLCDAC output voltage at code F(hex) RLCDACRNG, = 0 VRLCTOP 4.20 V RLCDAC output voltage at code F(hex), RLCDACRNG = 1 VRLCTOP 2.85 V VRLC deviation -50 +50 mV 0.1 0.5 LSB 0.25 1 Offset DAC, Monotonicity Guaranteed Resolution 8 Differential non-linearity DNL Integral non-linearity INL Step size Output voltage Code 00(hex) Code FF(hex) bits LSB 2.04 mV/step -260 +260 mV mV Notes: 1. Full-scale input voltage denotes the maximum amplitude of the input signal at the specified gain. 2. Input signal limits are the limits within which the full-scale input voltage signal must lie. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 June 2000 4 WM8192 Product Preview Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Programmable Gain Amplifier Resolution Gain 8 bits 208 283 − PGA[7 : 0] V/V Max gain, each channel GMAX 7.4 V/V Min gain, each channel GMIN 0.74 V/V 1 % Gain error, each channel DIGITAL SPECIFICATIONS Digital Inputs 0.8 ∗ DVDD2 High level input voltage VIH Low level input voltage VIL 0.2 ∗ DVDD2 V High level input current IIH 1 µA Low level input current IIL 1 µA Input capacitance CI V 5 pF Digital Outputs High level output voltage VOH IOH = 1mA Low level output voltage VOL IOL = 1mA High impedance output current IOZ DVDD2 - 0.5 V 0.5 V 1 µA 0.2 ∗ DVDD2 V 0.5 V Digital IO Pins 0.8 ∗ DVDD2 Applied high level input voltage VIH Applied low level input voltage VIL High level output voltage VOH IOH = 1mA Low level output voltage VOL IOL = 1mA V DVDD2 - 0.5 V Low level input current IIL 1 µA High level input current IIH 1 µA Input capacitance CI High impedance output current IOZ 1 µA 5 pF Supply Currents Total supply current − active 48 mA 45 mA Digital core supply current, DVDD1 − active 2 mA Digital I/O supply current, DVDD2 − active 1 mA 100 µA Total analogue supply current − active IAVDD Supply current − full power down mode WOLFSON MICROELECTRONICS LTD PP Rev 1.0 June 2000 5 WM8192 Product Preview INPUT VIDEO SAMPLING tPER tMCLKH tMCLKL MCLK tVSMPSU tVSMPH VSMP INPUT tVSU tVH tRSU tRH VIDEO Figure 1 Input Video Timing Note: 1. See Page 14 (Programmable VSMP Detect Circuit) for video sampling description. Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated PARAMETER SYMBOL MCLK period tPER 83.3 ns MCLK high period tMCLKH 37.5 ns MCLK low period tMCLKL 37.5 ns VSMP set-up time tVSMPSU 10 ns VSMP hold time tVSMPH 5 ns tVSU 15 ns Video level set-up time TEST CONDITIONS MIN TYP MAX UNITS Video level hold time tVH 5 ns Reset level set-up time tRSU 15 ns Reset level hold time tRH 5 ns Notes: 1. 2. tVSU and tRSU denote the set-up time required after the input video signal has settled. Parameters are measured at 50% of the rising/falling edge. OUTPUT DATA TIMING MCLK tPD OP[7:0] Figure 2 Output Data Timing WOLFSON MICROELECTRONICS LTD PP Rev 1.0 June 2000 6 WM8192 Product Preview OEB tPZE tPEZ OP[7:0] Hi-Z Hi-Z Figure 3 Output Data Enable Timing Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated SYMBOL TEST CONDITIONS Output propagation delay PARAMETER tPD IOH = 1mA, IOL = 1mA Output enable time Output disable time MIN TYP MAX UNITS 75 ns tPZE 50 ns tPEZ 25 ns SERIAL INTERFACE tSPER tSCKL tSCKH SCK tSSU tSH SDI tSCE tSEW tSEC SEN tSERD tSCRD t SCRDZ ADC DATA ADC DATA SDO MSB LSB REGISTER DATA Figure 4 Serial Interface Timing Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS SCK period tSPER 83.3 ns SCK high tSCKH 37.5 ns SCK low tSCKL 37.5 ns SDI set-up time tSSU 10 ns SDI hold time tSH 10 ns SCK to SEN set-up time tSCE 20 ns SEN to SCK set-up time tSEC 20 ns SEN pulse width tSEW 50 ns SEN low to SDO = Register data tSERD 35 ns SCK low to SDO = Register data tSCRD 35 ns SCK low to SDO = ADC data tSCRDZ 25 ns Note: 1. Parameters are measured at 50% of the rising/falling edge WOLFSON MICROELECTRONICS LTD PP Rev 1.0 June 2000 7 WM8192 Product Preview DEVICE DESCRIPTION INTRODUCTION A block diagram of the device showing the signal path is presented on Page 1. The WM8192 samples up to three inputs (RINP, GINP and BINP) simultaneously. The device then processes the sampled video signal with respect to the video reset level or an internally/externally generated reference level using either one or three processing channels. Each processing channel consists of an Input Sampling block with optional Reset Level Clamping (RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and an 8-bit Programmable Gain Amplifier (PGA). The ADC then converts each resulting analogue signal to a 16-bit digital word. The digital output from the ADC is presented on an 8-bit wide bi-directional bus, with optional 8 or 4-bit multiplexed formats. On-chip control registers determine the configuration of the device, including the offsets and gains applied to each channel. These registers are programmable via a serial interface. INPUT SAMPLING The WM8192 can sample and process one to three inputs through one or three processing channels as follows: Colour Pixel-by-Pixel: The three inputs (RINP, GINP and BINP) are simultaneously sampled for each pixel and a separate channel processes each input. The signals are then multiplexed into the ADC, which converts all three inputs within the pixel period. Monochrome: A single chosen input (RINP, GINP, or BINP) is sampled, processed by the corresponding channel, and converted by the ADC. The choice of input and channel can be changed via the control interface, e.g. on a line-by-line basis if required. Colour Line-by-Line: A single chosen input (RINP, GINP, or BINP) is sampled and multiplexed into the red channel for processing before being converted by the ADC. The input selected can be switched in turn (RINP → GINP → BINP → RINP…) together with the PGA and Offset DAC control registers by pulsing the RLC/ACYC pin. This is known as auto-cycling. Alternatively, other sampling sequences can be generated via the control registers. This mode causes the blue and green channels to be powered down. Refer to the Line-by-Line Operation section for more details. RESET LEVEL CLAMPING (RLC) To ensure that the signal applied to the WM8192 lies within its input range (0V to AVDD) the CCD output signal is usually level shifted by coupling through a capacitor, CIN. The RLC circuit clamps the WM8192 side of this capacitor to a suitable voltage during the CCD reset period. A typical input configuration is shown in Figure 5. A clamp pulse, CL, is generated from MCLK and VSMP by the Timing Control Block. When CL is active the voltage on the WM8192 side of CIN, at RINP, is forced to the VRLC/VBIAS voltage (VVRLC ) by switch 1. When the CL pulse turns off, the voltage at RINP initially remains at VVRLC but any subsequent variation in sensor voltage (from reset to video level) will couple through CIN to RINP. RLC is compatible with both CDS and non-CDS operating modes, as selected by switch 2. Refer to the CDS/non-CDS Processing section. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 June 2000 8 WM8192 Product Preview MCLK RLC/ACYC VSMP TIMING CONTROL CL RS FROM CONTROL INTERFACE VS CIN S/H RINP + + 2 S/H RLC CDS EXTERNAL VRLC TO OFFSET DAC - 1 INPUT SAMPLING BLOCK FOR RED CHANNEL CDS VRLC/ VBIAS 4-BIT RLC DAC FROM CONTROL INTERFACE VRLCEXT Figure 5 Reset Level Clamping and CDS Circuitry If auto-cycling is not required, RLC can be selected by pin RLC/ACYC. Figure 6 illustrates control of RLC for a typical CCD waveform, with CL applied during the reset period. The input signal applied to the RLC pin is sampled on the positive edge of MCLK that occurs during each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the internal CL pulse on the next reset level. The position of CL can be adjusted by using control bits CDSREF[1:0] (Figure 7). If auto-cycling is required, pin RLC/ACYC is no longer available for this function and control bit RLCINT determines whether clamping is applied. MCLK VSMP RLC/ACYC 1 X X 0 X X 0 Programmable Delay CL (CDSREF = 01) INPUT VIDEO RGB RGB RLC on this Pixel RGB No RLC on this Pixel Figure 6 Relationship of RLC Pin, MCLK and VSMP to Internal Clamp Pulse, CL The VRLC/VBIAS pin can be driven internally by a 4-bit DAC (RLCDAC) by writing to control bits RLCV[3:0]. The RLCDAC range and step size may be increased by writing to control bit RLCDACRNG. Alternatively, the VRLC/VBIAS pin can be driven externally by writing to control bit VRLCEXT to disable the RLCDAC and then applying a d.c. voltage to the pin. CDS/NON-CDS PROCESSING For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel common mode noise. For CDS operation, the video level is processed with respect to the video reset level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must be set to 1 (default), this controls switch 2 (Figure 5) and causes the signal reference to come from the video reset level. The time at which the reset level is sampled, by clock Rs/CL, is adjustable by programming control bits CDSREF[1:0], as shown in Figure 7. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 June 2000 9 WM8192 Product Preview MCLK VSMP VS RS/CL (CDSREF = 00) RS/CL (CDSREF = 01) RS/CL (CDSREF = 10) RS/CL (CDSREF = 11) Figure 7 Reset Sample and Clamp Timing For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described above. The VRLC/VBIAS pin is sampled by Rs at the same time as Vs samples the video level in this mode. OFFSET ADJUST AND PROGRAMMABLE GAIN The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset DAC to compensate for offsets and then amplified by an 8-bit PGA. The gain and offset for each channel are independently programmable by writing to control bits DAC[7:0] and PGA[7:0]. In colour line-by-line mode the gain and offset coefficients for each colour can be multiplexed in order (Red → Green → Blue → Red…) by pulsing the ACYC/RLC pin, or controlled via the FME, ACYCNRLC and INTM[1:0] bits. Refer to the Line-by-Line Operation section for more details. ADC INPUT BLACK LEVEL ADJUST The output from the PGA must be offset to match the full-scale range of the ADC. For negative-going input signals, a black level (zero differential) output from the PGA should be offset to the top of the ADC range. For positive going input signal the black level should be offset to the bottom of the ADC range. This is achieved by writing to control bits PGAFS[1:0]. OVERALL SIGNAL FLOW SUMMARY Figure 8 represents the processing of the video signal through the WM8192. INPUT SAMPLING OFFSET DAC PGA BLOCK BLOCK BLOCK V1 + VIN - V2 ++ X V3 analog x (65535/VFS) D +0 if PGAFS[1:0]=11 1 +65535 if PGAFS[1:0]=10 +32768 if PGAFS[1:0]=0x digital CDS = 1 OP[7:0] PGA gain A = 208/(283-PGA[7:0]) CDS = 0 VVRLC Offset DAC RLCEXT=0 RLC DAC D2 D2 = D1 if INVOP = 0 D2 = 65535-D1 if INVOP = 1 VRESET RLCEXT=1 OUTPUT INVERT BLOCK ADC BLOCK See parametrics for DAC voltages. 260mV*(DAC[7:0]-127.5)/127.5 VIN is RINP or GINP or BINP VRESET is VIN sampled during reset clamp VRLC is voltage applied to VRLC pin CDS, RLCEXT,RLCV[3:0], DAC[7:0], PGA[7:0], PGAFS[1:0] and INVOP are set by programming internal control registers. CDS=1 for CDS, 0 for non-CDS Figure 8 Overall Signal Flow WOLFSON MICROELECTRONICS LTD PP Rev 1.0 June 2000 10 WM8192 Product Preview The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC, optionally set via the RLC DAC. The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the black level of the input signal towards 0V, producing V2. The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range, outputting voltage V3. The ADC BLOCK then converts the analogue signal, V3, to a 16-bit unsigned digital output, D1. The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D2. CALCULATING OUTPUT FOR ANY GIVEN INPUT The following equations describe the processing of the video and reset level signals through the WM8192. INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the input video. V1 = VIN - VRESET .................................................................. Eqn. 1 If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted instead. V1 = VIN - VVRLC .................................................................... Eqn. 2 If RLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS. If RLCEXT = 0, VVRLC is the output from the internal RLC DAC. VVRLC = (VRLCSTEP ∗ RLCV[3:0]) + VRLCBOT ................................. Eqn. 3 VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC. OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST The resultant signal V1 is added to the Offset DAC output. V2 = V1 + {260mV ∗ (DAC[7:0]-127.5) } / 127.5 .................... Eqn. 4 PGA NODE: GAIN ADJUST The signal is then multiplied by the PGA gain, V3 = V2 ∗ 208/(283- PGA[7:0]) .............................................. Eqn. 5 ADC BLOCK: ANALOGUE-DIGITAL CONVERSION The analogue signal is then converted to a 16-bit unsigned number, with input range configured by PGAFS[1:0]. D1[15:0] = INT{ (V3 /VFS) ∗ 65535} + 32767 PGAFS[1:0] = 00 or 01 ..... Eqn. 6 D1[15:0] = INT{ (V3 /VFS) ∗ 65535} PGAFS[1:0] = 11 .............. Eqn. 7 D1[15:0] = INT{ (V3 /VFS) ∗ 65535} + 65535 PGAFS[1:0] = 10 .............. Eqn. 8 where the ADC full-scale range, VFS = 3V OUTPUT INVERT BLOCK: POLARITY ADJUST The polarity of the digital output may be inverted by control bit INVOP. D2[15:0] = D1[15:0] (INVOP = 0) ...................... Eqn. 9 D2[15:0] = 61535 – D1[15:0] (INVOP = 1) ...................... Eqn. 10 WOLFSON MICROELECTRONICS LTD PP Rev 1.0 June 2000 11 WM8192 Product Preview OUTPUT FORMATS The digital data output from the ADC is available to the user in 8 or 4-bit wide multiplexed formats by setting control bit MUXOP. Latency of valid output data with respect to VSMP is programmable by writing to control bits DEL[1:0]. The latency for each mode is shown in the Operating Mode Timing Diagrams section. Figure 9 shows the output data formats for Modes 1 – 2 and 4 – 6. Figure 10 shows the output data formats for Mode 3. Table 1 summarises the output data obtained for each format. MCLK MCLK 8+8-BIT OUTPUT 4+4+4+4-BIT OUTPUT A A 8+8-BIT OUTPUT B B C 4+4+4+4-BIT OUTPUT D Figure 9 Output Data Formats (Modes 1 − 2, 4 − 6) A B A B A B C D Figure 10 Output Data Formats (Mode 3) OUTPUT FORMAT MUXOP OUTPUT PINS OUTPUT 8+8-bit multiplexed 0 OP[7:0] A = d15, d14, d13, d12, d11, d10, d9, d8 B = d7, d6, d5, d4, d3, d2, d1,d0 4+4+4+4-bit (nibble) 1 OP[7:4] A = d15, d14, d13, d12 B = d11, d10, d9, d8 C = d7, d6, d5, d4 D = d3, d2, d1, d0 Table 1 Details of Output Data Shown in Figure 9 and Figure 10. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 June 2000 12 WM8192 Product Preview CONTROL INTERFACE The internal control registers are programmable via the serial digital control interface. The register contents can be read back via the serial interface on pin OP[7]/SDO. SERIAL INTERFACE: REGISTER WRITE Figure 11 shows register writing in serial mode. Three pins, SCK, SDI and SEN are used. A six-bit address (a5, 0, a3, a2, a1, a0) is clocked in through SDI, MSB first, followed by an eight-bit data word (b7, b6, b5, b4, b3, b2, b1, b0), also MSB first. Each bit is latched on the rising edge of SCK. When the data has been shifted into the device, a pulse is applied to SEN to transfer the data to the appropriate internal register. Note all valid registers have address bit a4 equal to 0 in write mode. SCK SDI a5 0 a3 a2 a1 a0 b7 b6 b5 Address b4 b3 b2 b1 b0 Data Word SEN Figure 11 Serial Interface Register Write SERIAL INTERFACE: REGISTER READ-BACK Figure 12 shows register read-back in serial mode. Read-back is initiated by writing to the serial bus as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. Writing address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of corresponding register (a5, 0, a3, a2, a1, a0) to be output MSB first on pin SDO (on the falling edge of SCK). Note that pin SDO is shared with an output pin, OP[7], therefore OEB should always be held low when register read-back data is expected on this pin. The next word may be read in to SDI while the previous word is still being output on SDO. SCK SDI a5 1 a3 a2 a1 a0 Address x x x x x x x x Data Word SEN SDO/ OP[7] d7 d6 d5 d4 d3 d2 d1 d0 Output Data Word OEB Figure 12 Serial Interface Register Read-back TIMING REQUIREMENTS To use this device a master clock (MCLK) of up to 12MHz and a per-pixel synchronisation clock (VSMP) of up to 6MHz are required. These clocks drive a timing control block, which produces internal signals to control the sampling of the video signal. MCLK to VSMP ratios and maximum sample rates for the various modes are shown in Table 4. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 June 2000 13 WM8192 Product Preview PROGRAMMABLE VSMP DETECT CIRCUIT The VSMP input is used to determine the sampling point and frequency of the WM8192. Under normal operation a pulse of 1 MCLK period should be applied to VSMP at the desired sampling frequency (as shown in the Operating Mode Timing Diagrams) and the input sample will be taken on the first rising MCLK edge after VSMP has gone low. However, in certain applications such a signal may not be readily available. The programmable VSMP detect circuit in the WM8192 allows the sampling point to be derived from any signal of the correct frequency, such as a CCD shift register clock, when applied to the VSMP pin. When enabled, by setting the VSMPDET control bit, the circuit detects either a rising or falling edge (determined by POSNNEG control bit) on the VSMP input pin and generates an internal VSMP pulse. This pulse can optionally be delayed by a number of MCLK periods, specified by the VDEL[2:0] bits. Figure 13 shows the internal VSMP pulses that can be generated by this circuit for a typical clock input signal. The internal VSMP pulse is then applied to the timing control block in place of the normal VSMP pulse provided from the input pin. The sampling point then occurs on the first rising MCLK edge after this internal VSMP pulse, as shown in the Operating Mode Timing Diagrams. MCLK INPUT PINS VSMP POSNNEG = 1 (VDEL = 000) INTVSMP (VDEL = 001) INTVSMP (VDEL = 010) INTVSMP (VDEL = 011) INTVSMP (VDEL = 100) INTVSMP (VDEL = 101) INTVSMP (VDEL = 110) INTVSMP (VDEL = 111) INTVSMP POSNNEG = 0 (VDEL = 000) INTVSMP (VDEL = 001) INTVSMP (VDEL = 010) INTVSMP (VDEL = 011) INTVSMP (VDEL = 100) INTVSMP (VDEL = 101) INTVSMP (VDEL = 110) INTVSMP (VDEL = 111) INTVSMP Figure 13 Internal VSMP Pulses Generated by Programmable VSMP Detect Circuit REFERENCES The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins VRT and VRB, where they must be decoupled to ground. Pin VRX is driven by a similar buffer, and also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin VRLC/VBIAS POWER SUPPLY The WM8192 can run from a 5V single supply or from split 5V (core) and 3.3V (digital interface) supplies. POWER MANAGEMENT Power management for the device is performed via the Control Interface. The device can be powered on or off completely by the EN bit. Alternatively, when control bit SELPD is high, only blocks selected by further control bits (SELDIS[3:0]) are powered down. This allows the user to optimise power dissipation in certain modes, or to define an intermediate standby mode to allow a quicker recovery into a fully active state. In Line-by-line operation, the green and blue channel PGAs are automatically powered down. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 June 2000 14 WM8192 Product Preview All the internal registers maintain their previously programmed value in power down modes and the Control Interface inputs remain active. Table 2 summarises the power down control bit functions. EN SELDPD 0 0 Device completely powers down. 1 0 Device completely powers up. X 1 Blocks with respective SELDIS[3:0] bit high are disabled. Table 2 Power Down Control LINE-BY-LINE OPERATION Certain linear sensors (e.g. Contact Image Sensors) give colour output on a line-by-line basis. i.e. a full line of red pixels followed by a line of green pixels followed by a line of blue pixels. In order to accommodate this type of signal the WM8192 can be set into Monochrome mode, with the input channel switched by writing to control bits CHAN[1:0] between every line. Alternatively, the WM8192 can be placed into colour line-by-line mode by setting the LINEBYLINE control bit. When this bit is set the green and blue processing channels are powered down and the device is forced internally to only operate in MONO mode (because only one colour is sampled at a time) through the red channel. Figure 14 shows the signal path when operating in colour line-by-line mode. VRLC/VBIAS VSMP CL RS MCLK V S TIMING CONTROL R G OFFSET MUX 8 WM8192 OFFSET DAC B RINP RLC GINP INPUT MUX + R G RLC BINP CDS PGA 8 PGA MUX B 16BIT ADC + I/P SIGNAL POLARITY ADJUST DATA I/O PORT RLC RLC DAC CONFIGURABLE SERIAL CONTROL INTERFACE 4 OP[7:0] SEN SCK SDI RLC/ACYC Figure 14 Signal Path When in Line-by-Line Mode In this mode the input multiplexer and (optionally) the PGA/Offset register multiplexers can be autocycled by the application of pulses to the RLC/ACYC input pin by setting the ACYCNRLC register bit. The multiplexers change on the first MCLK rising edge after RLC/ACYC is taken high. Alternatively, all three multiplexers can be controlled via the serial interface by writing to register bits INTM[1:0] to select the desired colour. It is also possible for the input multiplexer to be controlled separately from the PGA and Offset multiplexers. Table 3 describes all the multiplexer selection modes that are possible. FME ACYCNRLC 0 0 Internal, no force mux NAME Input mux, offset and gain registers determined by internal register bits INTM1, INTM0. DESCRIPTION 0 1 Auto-cycling, no force mux Input mux, offset and gain registers auto-cycled, RINP → GINP → BINP → RINP… on RLC/ACYC pulse. 1 0 Internal, force mux Input mux selected from internal register bits FM1, FM0; Offset and gain registers selected from internal register bits INTM1, INTM0. 1 1 Auto-cycling, force mux Input mux selected from internal register bits FM1, FM0; Offset and gain registers auto-cycled, RINP → GINP → BINP → RINP… on RLC/ACYC pulse. Table 3 Colour Selection Description in Line-by-Line Mode WOLFSON MICROELECTRONICS LTD PP Rev 1.0 June 2000 15 WM8192 Product Preview OPERATING MODES Table 4 summarises the most commonly used modes, the clock waveforms required and the register contents required for CDS and non-CDS operation. MODE DESCRIPTION CDS AVAILABLE MAX SAMPLE RATE SENSOR INTERFACE DESCRIPTION TIMING REQUIREMENTS REGISTER CONTENTS WITH CDS REGISTER CONTENTS WITHOUT CDS 1 Colour Pixel-by-Pixel Yes 2MSPS The 3 input channels are sampled in parallel. The signal is then gain and offset adjusted before being multiplexed into a single data stream and converted by the ADC, giving an output data rate of 6MSPS max. MCLK max = 12MHz MCLK: VSMP ratio is 6:1 SetReg1: 03(hex) SetReg1: 01(hex) 2 Monochrome/ Colour Line-by-Line Yes 2MSPS As mode 1 except: Only one input channel at a time is continuously sampled. MCLK max = 12MHz MCLK: VSMP ratio is 6:1 SetReg1: 07(hex) SetReg1: 05(hex) 3 Fast Monochrome/ Colour Line-by-Line Yes 4MSPS Identical to mode 2 MCLK max = 12MHz MCLK: VSMP ratio is 3:1 Identical to mode 2 plus SetReg3: bits 5:4 must be set to 0(hex) Identical to mode 2 4 Maximum speed Monochrome/ Colour Line-by-Line No 6MSPS Identical to mode 2 MCLK max = 12MHz MCLK: VSMP ratio is 2:1 CDS not possible SetReg1: 45(hex) 5 Slow Colour Pixel-by-Pixel Yes 1.5MSPS Identical to mode 1 MCLK max = 12MHz MCLK: VSMP ratio is 2n:1, n ≥ 4 Identical to mode 1 Identical to mode 1 6 Slow Monochrome/ Colour Line-by-Line Yes 1.5MSPS Identical to mode 2 MCLK max = 12MHz MCLK: VSMP ratio is 2n:1, n ≥ 4 Identical to mode 2 Identical to mode 2 Table 4 WM8192 Operating Modes Notes: 1. In Monochrome mode, SetReg3 bits 7:6 determine which input is to be sampled. 2. For Colour Line-by-Line, set control bit LINEBYLINE. For input selection, refer to Table 4, Colour Selection Description in Line-by-Line Mode. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 June 2000 16 WM8192 Product Preview OPERATING MODE TIMING DIAGRAMS The following diagrams show 8-bit multiplexed output data and MCLK, VSMP and input video requirements for operation of the most commonly used modes as shown in Table 4. The diagrams are identical for both CDS and non-CDS operation. Outputs from RINP, GINP and BINP are shown as R, G and B respectively. X denotes invalid data. 16.5 MCLK PERIODS MCLK VSMP INPUT VIDEO OP[7:0] (DEL = 00) RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB OP[7:0] (DEL = 01) BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB OP[7:0] (DEL = 10) GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB OP[7:0] (DEL = 11) RA RB GA GB BA BB RA RB GA GB BA BB RA RB GB GA BA BB RA RB GA GB BA BB RA RB GA GB BA BB Figure 15 Mode 1 Operation 16.5 MCLK PERIODS MCLK VSMP INPUT VIDEO OP[7:0] (DEL = 00) RA RB X X X X RA RB X X X X RA RB X X X X RA RB X X X X RA RB OP[7:0] (DEL = 01) X X RA RB X X X X RA RB X X X X RA RB X X X X RA RB X X X X OP[7:0] (DEL = 10) X X X X RA RB X X X X RA RB X X X X RA RB X X X X RA RB X X OP[7:0] (DEL = 11) RA RB X X X X RA RB X X X X RA RB X X X X RA RB X X X X RA RB Figure 16 Mode 2 Operation WOLFSON MICROELECTRONICS LTD PP Rev 1.0 June 2000 17 WM8192 Product Preview 23.5 MCLK PERIODS MCLK VSMP INPUT VIDEO OP[7:0] (DEL = 00) RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB OP[7:0] (DEL = 01) RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB OP[7:0] (DEL = 10) RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB OP[7:0] (DEL = 11) RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB Figure 17 Mode 3 Operation 16.5 MCLK PERIODS MCLK VSMP INPUT VIDEO OP[7:0] (DEL = 00) RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB OP[7:0] (DEL = 01) RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB OP[7:0] (DEL = 10) RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB OP[7:0] (DEL = 11) RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB Figure 18 Mode 4 Operation WOLFSON MICROELECTRONICS LTD PP Rev 1.0 June 2000 18 WM8192 Product Preview 16.5 MCLK PERIODS MCLK VSMP INPUT VIDEO OP[7:0] (DEL = 00) X X RA RB GA GB BA BB X X RA RB GA GB BA BB X X RA RB GA GB BA BB X X RA RB GA GB OP[7:0] (DEL = 01) BA BB X X RA RB GA GB BA BB X X RA RB GA GB BA BB X X RA RB GA GB BA BB X X RA RB OP[7:0] (DEL = 10) GA GB BA BB X X RA RB GA GB BA BB X X RA RB GA GB BA BB X X RA RB GA GB BA BB X X OP[7:0] (DEL = 11) RA RB GA GB BA BB X X RA RB GA GB BA BB X X RA RB GA GB BA BB X X RA RB GA GB BA BB Figure 19 Mode 5 Operation (MCLK:VSMP Ratio = 8:1) 16.5 MCLK PERIODS MCLK VSMP INPUT VIDEO OP[7:0] (DEL = 00) X X RA RB X X X X X X RA RB X X X X X X RA RB X X X X X X OP[7:0] (DEL = 01) X X X X RA RB X X X X X X RA RB X X X X X X RA RB X X X X OP[7:0] (DEL = 10) X X X X X X RA RB X X X X X X RA RB X X X X X X RA RB X X OP[7:0] (DEL = 11) RA RB X X X X X X RA RB X X X X X X RA RB X X X X X X RA RB Figure 20 Mode 6 Operation (MCLK:VSMP Ratio = 8:1) WOLFSON MICROELECTRONICS LTD PP Rev 1.0 June 2000 19 WM8192 Product Preview DEVICE CONFIGURATION REGISTER MAP The following table describes the location of each control bit used to determine the operation of the WM8192. The register map is programmed by writing the required codes to the appropriate addresses via the serial interface. ADDRESS DESCRIPTION DEF <a5:a0> RW (hex) 000001 Setup Reg 1 000010 000011 BIT b7 b6 b5 b4 b3 b2 b1 b0 MODE4 PGAFS[1] PGAFS[0] SELPD MONO CDS EN 03 RW Setup Reg 2 20 RW DEL[1] DEL[0] RLCDACRNG 0 VRLCEXT INVOP MUXOP 0 Setup Reg 3 1F RW CHAN[1] CHAN[0] CDSREF [1] CDSREF [0] RLCV[3] RLCV[2] RLCV[1] RLCV[0] 000100 Software Reset 00 W 000101 Auto-cycle Reset 00 W 000110 Setup Reg 4 00 RW FM[1] FM[0] INTM[1] INTM[0] RLCINT FME ACYCNRLC LINEBYLINE 000111 Revision Number 41 R 001000 Setup Reg 5 00 RW 0 0 0 POSNNEG VDEL[2] VDEL[1] VDEL[0] VSMPDET 001001 Setup Reg 6 00 RW 0 0 0 0 SELDIS[3] SELDIS[2] SELDIS[1] SELDIS[0] 001010 Reserved 00 RW 0 0 0 0 0 0 0 0 001011 Reserved 00 RW 0 0 0 0 0 0 0 0 001100 Reserved 00 RW 0 0 0 0 0 0 0 0 100000 DAC Value (Red) 80 RW DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0] 100001 DAC Value (Green) 80 RW DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0] 100010 DAC Value (Blue) 80 RW DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0] 100011 DAC Value (RGB) 80 W DAC[7] DAC[6] DAC[5] DAC[4] DAC[3] DAC[2] DAC[1] DAC[0] 101000 PGA Gain (Red) 00 RW PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0] 101001 PGA Gain (Green) 00 RW PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0] 101010 PGA Gain (Blue) 00 RW PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0] 101011 PGA Gain (RGB) 00 W PGA[7] PGA[6] PGA[5] PGA[4] PGA[3] PGA[2] PGA[1] PGA[0] Table 5 Register Map REGISTER MAP DESCRIPTION The following table describes the function of each of the control bits shown in Table 5. REGISTER Setup Register 1 BIT NO BIT NAME(S) DEFAULT DESCRIPTION 0 EN 1 Global power down: 0 = complete power down, 1 = fully active. 1 CDS 1 Select correlated double sampling mode: 0 = single ended mode, 1 = CDS mode. 2 MONO 0 Mono/colour select: 0 = colour, 1 = monochrome operation. 3 SELPD 0 Selective power down: 0 = no individual control, 1 = individual blocks can be disabled (controlled by SELDIS[3:0]). 5:4 PGAFS[1:0] 00 Offsets PGA output to optimise the ADC range for different polarity sensor output signals. Zero differential PGA input signal gives: 00 = Zero output (use for bipolar video) 01 = Zero output 6 MODE4 WOLFSON MICROELECTRONICS LTD 0 10 = Full-scale positive output (use for negative going video) 11 = Full-scale negative output (use for positive going video) Required when operating in MODE4: 0 = other modes, 1 = MODE4. PP Rev 1.0 June 2000 20 WM8192 Product Preview REGISTER Setup Register 2 BIT NO BIT NAME(S) DEFAULT 1 MUXOP 0 DESCRIPTION Determines the output data format. 0 = 8-bit multiplexed (8+8 bits) 1 = 4-bit multiplexed mode (4+4+4+4-bits) 2 INVOP 0 Digitally inverts the polarity of output data. 0 = negative going video gives negative going output, 1 = negative-going video gives positive going output data. 3 VRLCEXT 0 When set powers down the RLCDAC, changing its output to Hi-Z, allowing VRLC/VBIAS to be externally driven. 5 RLCDACRNG 1 Sets the output range of the RLCDAC. 0 = RLCDAC ranges from 0 to AVDD (approximately), 1 = RLCDAC ranges from 0 to VRT (approximately). 7:6 DEL[1:0] 00 Sets the output latency in ADC clock periods. 1 ADC clock period = 2 MCLK periods except in Mode 3 where 1 ADC clock period = 3 MCLK periods. 00 = Minimum latency 01 = Delay by one ADC clock period Setup Register 3 3:0 RLCV[3:0] 1111 5:4 CDSREF[1:0] 01 Controls RLCDAC driving VRLC pin to define single ended signal reference voltage or Reset Level Clamp voltage. See Electrical Characteristics section for ranges. CDS mode reset timing adjust. 00 = Advance 1 MCLK period 01 = Normal 7:6 CHAN[1:0] 00 10 = Delay by two ADC clock periods 11 = Delay by three ADC clock periods 10 = Retard 1 MCLK period 11 = Retard 2 MCLK periods Monochrome mode channel select. 00 = Red channel select 01 = Green channel select 10 = Blue channel select 11 = Reserved Software Reset Any write to Software Reset causes all cells to be reset. Auto-cycle Reset Any write to Auto-cycle Reset causes the auto-cycle counter to reset to RINP. Setup Register 4 0 LINEBYLINE 0 Selects line by line operation 0 = normal operation, 1 = line by line operation. When line by line operation is selected MONO is forced to 1 and CHAN[1:0] to 00 internally, ensuring that the correct internal timing signals are produced. Green and Blue PGAs are also disabled to save power. 1 ACYCNRLC 0 When LINEBYLINE = 0 this bit has no effect. When LINEBYLINE = 1 this bit determines the function of the RLC/ACYC input pin and the input multiplexer and offset/gain register controls. 0 = RLC/ACYC pin enabled for Reset Level Clamp. Internal selection of input and gain/offset multiplexers, 1 = Auto-cycling enabled by pulsing the RLC/ACYC input pin. See Table 4, Colour Selection Description in Line-by-Line Mode for colour selection mode details. When auto-cycling is enabled, the RLC/ACYC pin cannot be used for reset level clamping. The RLCINT bit may be used instead. 2 FME 0 When LINEBYLINE = 0 this bit has no effect. When LINEBYLINE = 1 this bit controls the input force mux mode: 0 = No force mux, 1 = Force mux mode. Forces the input mux to be selected by FM[1:0] separately from gain and offset multiplexers. See Table 4 for details. 3 RLCINT 0 When LINEBYLINE = 1 and ACYCNRLC = 1 this bit is used to determine whether Reset Level Clamping is used. 0 = RLC disabled, 1 = RLC enabled. 5:4 INTM[1:0] 00 Colour selection bits used in internal modes. 00 = Red, 01 = Green, 10 = Blue and 11 = Reserved. See Table 4 for details. 7:6 FM[1:0] 00 Colour selection bits used in input force mux modes. 00 = Red, 01 = Green, 10 = Blue and 11 = Reserved. See Table 4 for details. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 June 2000 21 WM8192 REGISTER Product Preview BIT NO BIT NAME(S) DEFAULT 0 VSMPDET 0 3:1 VDEL[2:0] 000 4 POSNNEG 0 Setup Register 6 3:0 SELDIS[3:0] 0000 Offset DAC (Red) 7:0 DAC[7:0] 0 Red channel offset DAC value. Offset DAC (Green) 7:0 DAC[7:0] 0 Red channel offset DAC value Offset DAC (Blue) 7:0 DAC[7:0] 0 Red channel offset DAC value Offset DAC (RGB) 7:0 DAC[7:0] 0 A write to this register location causes the red, green and blue offset DAC registers to be overwritten by the new value PGA gain (Red) 7:0 PGA[7:0] 0 Determines the gain of the red channel PGA according to the equation: Red channel PGA gain = 208/(283-PGA[7:0]) PGA gain (Green) 7:0 PGA[7:0] 0 Determines the gain of the green channel PGA according to the equation: Green channel PGA gain = 208/(283-PGA[7:0]) PGA gain (Blue) 7:0 PGA[7:0] 0 Determines the gain of the blue channel PGA according to the equation: Blue channel PGA gain = 208/(283-PGA[7:0]) PGA gain (RGB) 7:0 PGA[7:0] 0 A write to this register location causes the red, green and blue PGA gain registers to be overwritten by the new value Setup Register 5 DESCRIPTION 0 = Normal operation, signal on VSMP input pin is applied directly to Timing Control block. 1 = Programmable VSMP detect circuit is enabled. An internal synchronisation pulse is generated from signal applied to VSMP input pin and is applied to Timing Control block. When VSMPDET = 0 these bits have no effect. When VSMPDET = 1 these bits set a programmable delay from the detected edge of the signal applied to the VSMP pin. The internally generated pulse is delayed by VDEL MCLK periods from the detected edge. See Figure 13, Internal VSMP Pulses Generated for details. When VSMPDET = 0 this bit has no effect. When VSMPDET = 1 this bit controls whether positive or negative edges are detected: 0 = Negative edge on VSMP pin is detected and used to generate internal timing pulse. 1 = Positive edge on VSMP pin is detected and used to generate internal timing pulse. See Figure 13 for further details. Selective power disable register - activated when SELPD = 1. Each bit disables respective cell when 1, enabled when 0. SELDIS[0] = Red CDS, PGA SELDIS[1] = Green CDS, PGA SELDIS[2] = Blue CDS, PGA SELDIS[3] = ADC Table 6 Register Control Bits WOLFSON MICROELECTRONICS LTD PP Rev 1.0 June 2000 22 WM8192 Product Preview RECOMMENDED EXTERNAL COMPONENTS DVDD 3 10 C1 DVDD1 8 DGND DVDD2 C2 AVDD 21 AGND1 AVDD 22 C3 2 AGND2 DGND AGND AGND 1 Video Inputs 28 27 26 VRT RINP VRX GINP VRB 24 C4 25 C5 23 BINP C6 C7 C8 VRLC/VBIAS C9 AGND WM8192 AGND OP[7]/SDO 7 Timing Signals 5 6 MCLK OP[6] VSMP OP[5] RLC/ACYC OP[4] OP[3] 12 11 9 Interface Controls 4 SCK OP[2] SDI OP[1] SEN OP[0] 20 DVDD 19 18 17 16 15 Output Data Bus 14 AVDD + C10 + C11 DGND + C12 AGND 13 OEB NOTES: 1. C1-9 should be fitted as close to WM8192 as possible. 2. AGND and DGND should be connected as close to WM8192 as possible. 3. DVDD should be connected as close to WM8192 as possible. Figure 21 External Components Diagram COMPONENT REFERENCE SUGGESTED VALUE DESCRIPTION C1 100nF De-coupling for DVDD1. C2 100nF De-coupling for DVDD2. C3 100nF De-coupling for AVDD. C4 10nF High frequency de-coupling between VRT and VRB. C5 1µF Low frequency de-coupling between VRT and VRB (non-polarised). C6 100nF De-coupling for VRB. C7 100nF De-coupling for VRX. C8 100nF De-coupling for VRT. C9 100nF De-coupling for VRLC. C10 10µF Reservoir capacitor for DVDD. C11 10µF Reservoir capacitor for DVDD. C12 10µF Reservoir capacitor for AVDD. Table 7 External Components Descriptions WOLFSON MICROELECTRONICS LTD PP Rev 1.0 June 2000 23 WM8192 Product Preview PACKAGE DIMENSIONS D: 28 PIN SOICW 7.5mm (0.3") Wide Body, 1.27mm Lead Pitch e DM016.B B 15 28 ZONE A E H L ZONE B h x 45o 14 1 D α C A1 -C- A Symbols A A1 B C D e E h H L α REF: SEATING PLANE 0.10 (0.004) Dimensions (mm) MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 17.70 18.10 1.27 BSC 7.40 7.60 0.25 0.75 10.00 10.65 0.40 1.27 o o 8 0 Dimensions (Inches) MIN MAX 0.0926 0.1043 0.0040 0.0118 0.0130 0.0200 0.0091 0.0125 0.6969 0.7125 0.0500 BSC 0.2914 0.2992 0.0100 0.0290 0.3940 0.4190 0.0160 0.0500 o o 0 8 JEDEC.95, MS-013 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES). B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN). D. MEETS JEDEC.95 MS-013, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. E. PIN ONE INDICATORS WILL BE LOCATED IN EITHER ZONE A OR ZONE B. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 June 2000 24