WOLFSON WM8144-10

WM8144-10
Production Data
October 1997 Rev. 3.0
Integrated 10-bit Data Acquisition system for
Imaging Applications
Description
Features
WM8144-10 integrates the analogue signal conditioning
required by CCD sensors with a 10-bit ADC and optional
pixel-by-pixel image compensation. WM8144-10 requires
minimal external circuitry and provides a cost effective
sensor-to-digital domain system solution.
•
•
•
•
•
•
Each analogue conditioning channel provides reset level
clamp, CDS, fine offset level shifting and gain
amplification. The three channels are multiplexed into the
ADC. Output from the ADC can either be direct or passed
through a digital post-processing function. The postprocessing provides compensation for variations in offset
and shading on a pixel-by-pixel basis.
Reset level clamp
Correlated Double Sampling (CDS)
Fine offset level shifting
Programmable Gain Amplification
10-Bit ADC with maximum 6 MSPS
Digital post-processing for pixel-by-pixel
image compensation
Simple clocking scheme
Control by serial or parallel interface
Time-multiplexed eight-bit data output mode
48 pin TQFP package
Pin compatible with WM8144-12
•
•
•
•
•
The flexible output architecture allows ten-bit data to be
accessed either on a ten-bit bus or via a time-multiplexed
eight-bit bus. The WM8144-10 can be configured for pixelby-pixel or line-by-line multiplexing operation. Reset level
clamp and/or CDS features can be optionally bypassed.
Device configuration is either by a simple serial or eightbit parallel interface.
Applications
•
•
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Document scanners
CCD sensor interfaces
Contact image sensor (CIS) interfaces
Block Diagram
VRLC
VRU VRT
VRB VRL
VSMP
VMID
MCLK
RLC
AVDD
AGND DVDD1 DVDD2 DGND
MUX
CC[2:0]
VMID
CL
RS
TIMING CONTROL
VS
OFFSET
S/H
RINP
DV
PGA
S/H
WM8144-10
5-BIT REG
CDS
8-BIT + SIGN
DAC
EXTERNAL
DATA STORE
INTERFACE
CDATA(7:0)
VMID
ORNG
OFFSET
S/H
GINP
M
U
X
PGA
S/H
5-BIT REG
CDS
8-BIT + SIGN
DAC
S/H
CDS
10/8
MUX
OEB
OP[9:0]
VMID
OFFSET
S/H
BINP
10 BIT
ADC
IMAGE
COMPENSATION
PROCESSING
PNS
PGA
5-BIT REG
8-BIT + SIGN
DAC
CONFIGURABLE
SERIAL/PARALLEL
CONTROL INTERFACE
VMID
SDI / DNA
SCK / RNW
SEN / STB
NRESET
Production Data data sheets contain final specifications current on publication
date. Supply of products conforms to
Wolfson Microelectronics standard terms
and conditions
Wolfson Microelectronics
Lutton Court, Bernard Terrace, Edinburgh EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
email: [email protected]
www: http://www.wolfson.co.uk
© 1997 Wolfson Microelectronics
WM8144-10
CDATA7
MCLK
VSMP
DVDD1
RLC
SCK/RNW
SDI/DNA
SEN/STB
OEB
33
32
31
30
28
27
26
25
29
CDATA6
34
35
CDATA4
CDATA5
Ordering Information
36
Package Outline
DEVICE
TEMP RANGE
0
0
WM8144-10CFT/V 0 C - 70 C
CDATA3
37
24
CDATA2
CDATA1
38
39
23
PNS
RINP
22
GINP
CDATA0
21
BINP
DGND
40
41
VMID
OP9
42
20
19
OP8
43
18
OP7
44
17
AGND
AVDD
OP6
OP5
45
46
16
VRL
15
VRU
OP4
47
14
OP3
48
13
VRB
VRT
5
6
7
8
9
10
NC
NC
DV
CC2
CC1
CC0
ORNG
NRESET
4
VRLC
11
12
2
OP1
OP0
DVDD2
3
1
OP2
WM8144-10
PACKAGE
48 Pin TQFP
NC - Make no external connection
Absolute Maximum Ratings
Analogue Supply Voltage. . . AGND - 0.3 V, AGND +7 V
Digital Supply Voltage. . . . DGND - 0.3 V, DGND +7 V
Digital Inputs . . . . . . . . DGND - 0.3 V, DVDD + 0.3 V
Digital Outputs. . . . . . . .DGND - 0.3 V, DVDD + 0.3 V
Reference inputs . . . . . . AGND - 0.3 V, AVDD + 0.3 V
RINP, GINP, BINP . . . . . .AGND - 0.3 V, AVDD + 0.3 V
Operating temperature range, TA . . . . . 0oC to +70oC
Storage Temperature . . . . . . . . . . -50oC to +150oC
Lead Temperature (soldering, 10 sec) . . . . . . +260oC
Note: Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by
continuously operating at or beyond these limits. Device functional operating range limits and guaranteed
performance specifications are given under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. The WM8144-10 is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and
storage of this device.
As per JEDEC specifications A112-A and A113-A this product requires specific storage conditions prior to
surface mount assembly. It has been classified as having a Moisture Sensitivity level of 2 and as such will be
supplied in vacuum sealed moisture barrier bags.
Recommended Operating Conditions
PARAMETER
TEST CONDITIONS
Supply Voltage
Operating Temperature Range
Input Common Mode Range
TA
VCMR
MIN
MAX UNIT
5.25
0
0.5
70
4.5
Wolfson Microelectronics
2
TYP
4.75
V
o
C
V
WM8144-10
Electrical Characteristics
VDD = 4.75V to 5.25V, GND = 0 V, ........T A = 0oC to +70oC, MLCK = 12MHz unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Supply Current - Active
110.0
150
mA
Supply Current - Standby
10.0
15
mA
Digital Inputs
High Level Input Voltage
VIH
Low Level Input Voltage
V IL
0.2*DVDD
V
High Level Input Current
IIH
1.0
µA
Low Level Input Current
I IL
1.0
µA
0.8*DVDD
Input Capacitance
V
10.0
pF
Digital Outputs
High Level Output Voltage
VOH
IOH = 1.0mA
Voltage output range
High Impedance Output Current
VOL
IOL = 1.0mA
V
DVDD-0.75
DGND+0.75
1.0
I OZ
V
µA
Input Multiplexer
Channel to Channel Gain Matching
0.5
%
ns
Input Video Set-up Time
tVSU
10
Input Video Hold Time
tVH
tRSU CDS Mode only
tRH CDS Mode only
25
ns
10
ns
25
ns
Reset Video Set-up Time
Reset Video Hold Time
Reference String
Reference Voltage - Top
VRT
VRU = 5.00 V, V RL = 0.00V
3.465
3.5
3.535
V
Reference Voltage - Bottom
V RB
VRU = 5.00 V, V RL = 0.00V
1.465
1.5
1.535
V
DAC Reference Voltage
VMID VRU = 5.00 V, V RL = 0.00V
2.475
2.5
2.525
R.L.C. Switch Impedence
Reset Level Clamp Options
200
V
Ohms
1.425
1.5
1.575
V
2.375
2.5
2.625
V
3.325
3.5
3.675
V
Impedance VRT to V RB
490
700
910 Ohms
Impedance VRU to VRL
1190
1700
2210 Ohms
VRLC VRU = 5.00 V, V RL = 0.00V
Voltage set by user
configuration - Table 7
8-bit DACs
Resolution
8
Zero Code Voltage
VDAC -10
Full Scale Voltage Error
0
Bits
VDAC +10
mV
10
mV
Differential Non Linearity
DNL
0.1
1 LSB
Integral Non Linearity
INL
0.4
1 LSB
Wolfson Microelectronics
3
WM8144-10
Electrical Characteristics (Contd.)
VDD = 4.75V to 5.25V, GND = 0 V, ........TA = 0oC to +70oC, MLCK = 12MHz unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
10-Bit ADC
Resolution
VDD = 5V
10
Bits
Maximum Sampling Rate
VDD = 5V
6
MSPS
Full Scale Transition Error Voltage at
VINP
DAC Code = 000H, VDD=5V,
measured relative to VRT
+/-50
+/-200
mV
Zero Scale Transition Error Voltage at
VINP
DAC Code = 000H, VDD=5V,
measured relative to VRB
+/-50
+/-200
mV
Differential Non Linearity
DNL
VDD = 5V
-1
Number of missing codes
+1.25 LSB
0 Code
PGA Gain
Red Channel Max. Gain, Note 1
Gr 12
4
Times
Green Channel Max. Gain, Note 2
Gg12 Mode=1
MCLK=12MHz; VDD=5V
7
Times
Blue Channel Max. Gain, Note 2
Gb12
7
Times
Red Channel Max. Gain, Note 2
Gr 8
MCLK=8MHz; VDD=5V
6
Times
Green Channel Max. Gain, Note 2
Blue Channel Max. Gain, Note 2
Gg8
Gb8
Mode=1
7
7
Times
Times
Note 1: Guaranteed monotonic up to PGA Gain code 0Fh
Note 2: Guaranteed monotonic up to PGA Gain code 1Fh
Wolfson Microelectronics
4
WM8144-10
Electrical Characteristics (Contd.)
VDD = 4.75V to 5.25V, GND = 0 V, ........TA = 0oC to +70oC, MLCK = 12MHz unless otherwise stated.
PARAMETER
Switching Characteristics
TEST CONDITIONS
MIN
TYP
MAX UNIT
MCLK Period
tPER
83.3
ns
MCLK High
tCKH
37.5
ns
MCLK Low
tCKL
37.5
ns
Data Set-up time
tDSU
ns
VSMP, RLC Data Hold Time
tDH
10
10
CDATA Data Hold Time
tDH
30
Output Propagation Delay
tPD
Output Enable TIme
Output Disable Time
Serial Interface
ns
ns
IOH = 1.0mA
75
ns
tPZE IOL = 1.0mA
tPEZ
75
ns
25
ns
SCK Period
tSPER
83.3
ns
SCK High
SCK Low
tSCKH
ns
ns
tSCKL
37.5
37.5
SDI Set up time
tSSU
10
ns
SDI Hold Time
tSH
10
ns
Set up time - SCK to SEN
tSCE
20
ns
Set up time - SEN to SCK
tSEC
20
ns
SEN Pulse W idth
tSEW
50
ns
Parallel Interface
RNW Low to OP[9:2] Tristate
tOPZ
Address Setup Time to STB Low
DNA Low Setup Time to STB Low
tASU
tADLS
0
10
ns
ns
ns
Strobe Low Time
20
ns
tSTB
50
Address Hold Time from STB High
tAH
10
ns
DNA Low Hold Time from STB High
tADLH
10
ns
Data Set-up Time to STB Low
DNA High Setup Time to STB Low
Data Hold Time from STB High
DNA High Hold Time from STB High
RNW High to OP[9:2] Output
tDSU
0
ns
tADHS
10
ns
tDH
10
ns
tADHH
tOPD
10
0
ns
ns
Wolfson Microelectronics
5
WM8144-10
Pin Descriptions
Pin No.
Name
Type
Description
23
RINP
Analogue IP
Red Channel input video
22
GINP
Analogue IP
Green Channel input video
21
BINP
Analogue IP
Blue Channel input video
33
CDATA[7]
Digital IO
Image compensation data read/write at twice ADC conversion rate
34
CDATA[6]
Digital IO
35
CDATA[5]
Digital IO
36
CDATA[4]
Digital IO
37
CDATA[3]
Digital IO
38
CDATA[2]
Digital IO
39
CDATA[1]
Digital IO
40
CDATA[0]
Digital IO
32
MCLK
Digital IP
Master clock. This clock is applied at either six, four or two times the input
pixel rate depending on the operational mode. MCLK is divided internally to
define the ADC samples rate and to provide the clock source for digital logic.
31
VSMP
Digital IP
Video sample synchronisation pulse. This signal is applied synchronously with
MLCK to specify the point in time that the input is sampled. The timing of
internal multiplexing between the R, G and B channels is derived from this
signal
29
RLC
Digital IP
19
VRLC
Analogue OP
Selects whether reset level clamp is applied on a pixel-by-pixel basis. If RLC
is required on each pixel then this pin can be tied high
Selectable analogue output voltage for RLC
13
VRT
Analogue IP
ADC reference voltages. The ADC reference range is applied between
14
VRB
Analogue IP
VRT (full scale) and VRB (zero level). VRU and VRL can be used to
15
VRU
Analogue IP
derive optimum reference voltages from an external 5V reference
16
VRL
Analogue IP
20
VMID
Analogue OP
42
OP[9]
Digital IO
Buffered mid-point of ADC reference string.
Tri-state digital 10-bit bi-directional bus. There are four modes:
43
OP[8]
Digital IO
Tri-state: when OEB = 1
44
OP[7]
Digital IO
Output ten-bit: ten bit data is output from bus
45
OP[6]
Digital IO
Output 8-bit multiplexed: data output on OP[9:2] at 2*ADC conversion rate
46
OP[5]
Digital IO
Input 8-bit: control data is input on bits OP[9:2]
47
OP[4]
Digital IO
48
OP[3]
Digital IO
1
OP[2]
Digital IO
2
3
OP[1]
OP[0]
Digital IO
Digital IO
Wolfson Microelectronics
6
WM8144-10
Pin Descriptions (contd.)
Pin No.
Name
Type
Description
8
CC[2]
Digital OP
Colour code outputs. These outputs indicate from which channel the
9
CC[1]
Digital OP
current output sample was taken (R = 00X, G = 01X, B = 10X).
10
11
CC[0]
ORNG
Digital OP
Digital OP
Two codes are provided per channel.
Out-of-range signal, active high. This signal indicates that the current
output pixel has exceeded the maximum or minimum achievable
somewhere within the pixel processing.
25
OEB
Digital IP
7
DV
Digital OP
Output tri-state control, all outputs (OP[9:0], DV, ORNG, CC[2:]) enabled
when OEB=0
Data valid output, active low.
12
NRESET
Digital IP
Reset input, active low. This signal forces a reset of all internal registers.
24
PNS
Digital IP
Control interface parallel (high) or serial (low, default)
27
SDI/DNA
Digital IP
Serial Interface: serial interface input data signal
28
SCK/RNW
Digital IP
Parallel interface: high = data, low = address
Serial Interface: serial interface clock signal
26
SEN/STB
Digital IP
Serial Interface: enable, active high
30
DVDD1
Digital supply
Parallel interface: strobe, active low
Positive Digital Supply (5V)
4
DVDD2
Digital supply
Positive Digital Supply (5V)
41
DGND
Digital supply
Digital ground (0V)
17
18
AVDD
AGND
Analogue supply Positive Analogue supply (5V)
Analogue supply Analogue Ground (0V)
5
NC
Unused
Pin must be left unconnected
6
NC
Unused
Pin must be left unconnected
Parallel interface: high = OP[9:2] is output, low = OP[9:2] is input bus
Wolfson Microelectronics
7
WM8144-10
Typical Performance
VDD = 5V, GND = 0 V, ........TA = 25oC.
WM8144 10 Bit INL Plot
0.8
4
0.6
3
0.4
2
0.2
1
0
-0.2
-0.4
-0.6
LSB's
5
LSB's
LSB's
LSB's
WM8144 10 Bit DNL Plot
1
0
-1
-2
-3
-0.8
-4
-1
-5
0
256
512
768
1024
0
256
512
ADC Code
ADC 10 Bit DNL
Gr een
Blue
Actual Gain
Actual Gain
PGA Gain
Red
2
1
0
0
1
2
3
4
5
6
7
8
7
6
DNL
DNL
3
4
5
PGA Gain Code
6
7
8
PGA DNL @ MCLK = 12.3MHz
5
4
3
2
1
0
-1
-2
-3
-4
-5
3
4
5
6
7
8
Red
Gr een
Blue
0
1
2
3
4
5
PGA Gain Code
6
7
8
MCLK = 8MHz. Input 2.5V +/ - 100mV . Other 2 are at 2.5V. Colour.
Vdd =
Gain
PGA DNL @ MCLK = 8MHz
Wolfson Microelectronics
8
2
PGA Gain Code vs. Actual Gain
@ MCLK = 8MHz
Gai n DNL
Blue
2
1
Gain
Gr een
1
Blue
0
Red
0
Gr een
MCLK = 8MHz. Input set to
2.5V +/100mV.
Other 2 are at 2.5V Colour.
PGA
Gain
Code
PGA Gain Code vs. Actual Gain
@ MCLK = 12.3MHz
Gai n DNL
MCLK = 12.3MHz. Input 2.5V + /- 100mV. Ot her 2 are at 2.5V. Colour.
Gain Vd
Red
5
4
3
2
1
0
8
PGA
Gain
CodeOther 2 are at 2.5VGain
MCLK = 12.3MHz. Input set
to 2.5V
+/- 100mV.
Colo
5
4
3
2
1
0
-1
-2
-3
-4
-5
1024
ADC 10 Bit INL
PGA Gain
8
7
6
5
4
3
768
ADC Code
ADC Code
ADC Code
COLOUR
CCD
SENSOR
BLUE
GREEN
RED
CLAMP
S/H
S/H
CDS
S/H
S/H
S/H
S/H
GAIN
AMPS
OFFSET DAC
VMID
VMID
VMID
INTEGRATED TIMING CONTROL
SIMPLE TWO PIN
TIMING INTERFACE
M
U
X
10 BIT
ADC
CONTROL
INTERFACE
IMAGE
COMPENSATION
LOGIC
WM8144
OPTIONAL
EXTERNAL
RAM
SIMPLE SERIAL OR
PARALLEL CONTROL
INTERFACE
TEN BIT IMAGE DATA
AT UPTO 6MSPS
WM8144-10
System Diagram
Wolfson Microelectronics
9
WM8144-10
Theory of Operation
S/H, Offset DAC’s and PGA
Each analogue input (RINP, GINP, BINP) of the WM814410 consists of a sample and hold, a programmable gain
amplifier, and a DC offset correction block. The operation
of the red input stage is summarised in Figure 1.
The output from the offset DAC stage is referenced to
the VMID voltage. This allows the input to the ADC to
maximise the dynamic range, and is shown diagrammatically in Figure 1 by the final VMID addition.
For the input stage the final analogue voltage applied to
the ADC can be expressed as:
RINP
DAC_ CODE VMID 

VADC = G( Vvs − Vrs) +  (1− 2 * Sign) *
*
+ VMID
255
2 

S/H
+
Gain=G
VS
+
Voffset
VMID
VADC
-
S/H
VMID
+
RS
Figure 1
The sample/hold block can operate in two modes of operation, CDS (Correlated Double Sampling) or Single Ended.
In CDS operation the video signal processed is the difference between the voltage applied at the RINP input when
RS occurs, and the voltage at the RINP input when VS
occurs. This is summarised in Figure 2.
Vrs
Vvs
RS
VS
Figure 2
When using CDS the actual DC value of the input signal is
not important, as long as the signal extremes are maintained within 0.5 volts of the chip power supplies. This is
because the signal processed is the difference between
the two sample voltages, with the common DC voltage
being rejected.
In single ended operation, the VS and RS control signals
occur simultaneously, and the voltage applied to the reset switch is fixed at VMID. This means that the voltage
processed is the difference between the voltage applied
to RINP when VS/RS occurs, and VMID. When using Single ended operation the DC content of the video signal is
not rejected.
The Programmable Gain Amplifier block multiplies the resulting input voltage by a value between 0.5 and 8.25
which can be programmed independently for each of the
three input channels via the serial (or parallel) interface.
PGA gain is dependent on the 5-bit binary code programmed in the PGA registers. A typical plot of PGA
gain versus code is shown on Page 8. The DC value of
the gained signal can then be trimmed by the 8 bit plus
sign DAC. The voltage output by this DAC is shown as
Voffset in Figure 1. The range of the DAC is (VMID/2).
Where: VADC is the voltage applied to the ADC
G is the programmed gain
Vvs is the voltage of the video sample
Vrs is the voltage of the reset sample
Sign is the Offset DAC sign bit
DAC_CODE is the offset DAC value
VMID is the WM8144-10 generated VMID voltage
The ADC has a lower reference of VRB (typically 1.5 V)
and an upper reference of VRT (typically 3.5 V). When
an ADC input voltage is applied to the ADC equal to VRB
the resulting code is 000(hex). When an ADC input voltage is applied to the ADC equal to VRT the resulting code
is 3FF(hex).
Reset Level Clamp
Both CDS and Single ended operation can be used with
Reset Level Clamping. A typical input configuration is
shown in Figure 3.
WM8144
RINP
+
Gain=G
VS
S/H
VRLC
Figure 3
Wolfson Microelectronics
10
S/H
Cin
VMID
RS
-
WM8144-10
Theory of Operation (contd.)
The position of the clamp relative to the video sample is
programmable by CDSREF1-0 (see Table 7). By default,
the reset sample occurs on the fourth MCLK rising edge
after VSMP. The relative timing between the reset sample ( and CL) and video sample can be altered as shown
in Figure 4.
Video Input
Clamp Pulse
Figure 5
A reset level clamp is activated if the RLC pin is high on
an MCLK rising edge (Figure 6). By default this initiates
an internal clamp pulse three MCLK pulses later (Figure
4: CL). The relationship between CL and RS is fixed.
Therefore altering the RS position also alters the CL position (Figure 4). Table 7 shows the three possible voltages
to which the reset level can be clamped.
Figure 6: RLC Timing
Figure 4: Reset Sample and Clamp Timing
When the clamp pulse is active the voltage on the
WM8144-10 side of Cin, i.e. RINP, will be forced to be
equal to the VRLC clamp voltage (see Figure 5). The
VRLC clamp voltage is programmable to three different
levels via the serial interface (1.5V, 2.5V or 3.5V). The
voltage to which the clamp voltage should be programmed
is dependent on the type of sampling selected and the
polarity of the input video signal. For CDS operation it is
important to match the clamp voltage to the amplitude
and polarity of the video signal. This will allow the best
use of the wide input common-mode range offered by the
WM8144-10. If the input video is positive going it is advisable to clamp to Vcl (Lower clamp voltage). If the video
is negative going it is advisable to clamp to Vcu (Upper
clamp voltage). Regardless of where the video is clamped
the offset DAC is programmed to move the ADC output
corresponding to the reset level to an appropriate value
to maximise the ADC dynamic range. For Single Ended
operation it is recommended that the clamp voltage is set
to Vcm (Middle clamp voltage).
RINP, GINP and BINP Input Impedence
The input impedence of the WM8144-10 analogue inputs
is dependent on the sampling frequency of the input signal and the configuration of the internal gain amplifiers.
The input impedence = 1/(Capacitance * frequency)
where the Capacitance value changes from 0.3pF for
minimum gain to 9.6pF for maximum gain. Table 1 illustrates the minimum and maximum input impedence at
different frequencies.
Sampling
Frequency
(MHz)
0.5
1
Impedence with
minimum gain
(MΩ )
6.6
3.3
Impedence with
maximum gain
(KΩ)
208
104
2
1.6
52
4
0.8
26
6
0.5
17
Table 1: Effects of Frequency on Input Impedence
Wolfson Microelectronics
11
WM8144-10
Theory of Operation (Contd)
Example of Gain and Offset Operation
Input Video polarity
negative
Input sampling
CDS
Input voltage amplitude (VVS - VRS)
1.6V
Programmable gain
x1
Clamping
Yes, VCL = 3.5V
After the input capacitor the input to the WM8144-10 can
be represented as:
Vrs
Vvs
RS
VS
Figure 7
For a black pixel:
For a white pixel:
For the white pixel, using the same offset DAC value, the
ADC input can be expressed as:
VADC = 1*(VCL - 1.6 - VCL) + (1 - 2*0) *
Assuming that the offset DAC is set to 00dec:
0
VMID 
VADC = 1* (Vcl - Vcl) + (1− 2 * 0) *
VMID *
+ VMID
255
2 

VADC = 0 + 0 + VMID
VADC = VMID
VMID
2
+ VMID
Therefore the output codes from the ADC are between
921(dec) and 102(dec), which implies that the ADC input
has been set up to maximise the dynamic range available. If a digital representation of the ADC output with a
black level near 000(dec) and a white level near 1023(dec)
is required then the INVOP control bit should now be set
To maximise the dynamic range of the ADC input it is
necessary to program the offset DAC code to move the
ADC code corresponding to the black level towards code
1024(dec).
Hence set the offset DAC to 164(dec) with the sign bit not
set.
*
VMID
2
+ VMID
82
VADC = 0 + 255 * VMID + VMID
337
VADC = 255 * VMID
When the VMID is 2.5v, the ADC input voltage becomes
3.3 volts which will result in an ADC code of 921(dec).
This is near the ideal full-scale of 1023(dec).
Wolfson Microelectronics
12
*
337
VADC = 255 * VMID - 1.6
to ONE.
255
255
82
VADC = -1.6 + 255 * VMID + VMID
An input voltage of VMID corresponds to a code of 512(dec)
from the ADC.
164
164
When the VMID is 2.5V, the ADC input voltage becomes
1.7 volts which will result in a code of 102(dec). This is
near the ideal full-scale of 000(dec).
VRS = VCL
VVS = VCL
VADC = 1*(VCL - VCL) + (1 - 2*0) *
VRS = VCL
VVS = VCL - 1.6
WM8144-10
Theory of Operation (contd.)
DEMUX
AND MUX
CDATA
DEFAULT
DATA
PARTITIONING
DEFAULT
6
4,5 or 6
10
PIXEL OFFSET
ADDER
12
12,11 or 10
MUX
ADCOP
DATA VALID
GENERATION
MUX
DV OUTPUT
DEFAULT
MUX
11
LIMIT
10
PIXEL GAIN
ADJUST
Figure 12
Figure 8
22
LIMIT
10
DATA
LATCH
10
OUT OF RANGE
GENERATION
ADC
Digital Signal Processing
By default, the output from the ADC passes through the
digital compensation block without being altered and is
output directly on the OP[9:0] pins. If required, the pixel
data from the ADC can be processed further by the digital compensation block (Figure 8). This section describes
the sub-blocks of the digital compensation block.
CDATA Demultiplexor
The input to this block is coefficient data presented to the
CDATA[7:0] pins at twice the pixel rate. i.e. two eight-bit
words are input for each pixel of video data.
Data Partitioning
The sixteen bits of data per pixel from the CDATA
Demultiplexor is partitioned into pixel offset, pixel gain
and pixel valid bits (Table 3) . Table 4 details the resulting
range and resolution options.
Pixel Offset Adder
This uses the offset coefficients that are either supplied
externally via the CDATA interface or from the internal
default registers. The object of this block is to correct for
the small offsets which can occur from the CCD on a
pixel-by-pixel basis. The output from the Pixel Offset
Adder is limited to be between 0 and 1023(dec).
Pixel Gain Adjust
This block corrects for the pixel-by-pixel shading curve
non-uniformity and photo response non-uniformity within
the CCD sensor. This block has a gain range of 0 to 2.
The output word from the Pixel Gain Adjust is limited to
between 0 and 1023(dec).
OP[9:0] INPUT TO
8/10 MUX BLOCK
ORNG INPUT TO
8/10 MUX BLOCK
Effect of digital compensation on ADC output
The combined effect of the digital compensation sections on the ADC output is summarised by the formula:
OP[9:0] = (ADCOP + POC) * PSCF
where:
All values are decimal
OP[9:0] is the 10 bit result output from the WM8144-10
ADCOP is a 10 bit unsigned number from the ADC
POC is a 2's compliment number divided byNUMBER OF
POC BITS ALLOCATED/2
PSCF is an unsigned number divided by NUMBER OF
PSC BITS ALLOCATED/2
For this example assume PSC is allocated 12 bits and
POC is allocated 4 bits (refer to table
3:DVMODE,PWP0,PWP1 = 0). Table 1 shows some examples of the effect of the digital backend on the ADC
output.
Range
Default
Ex 1
Ex 2
Ex 3
Ex 4
Ex 5
Ex 6
Ex 7
Ex 8
Ex 9
ADCOP
0:1023
512
512
512
1022
1022
512
512
512
511
POC
-8:7
0
0
-7
6
6
6
0
0
0
0
PSC
0:4095
2048 (x1)
2048
2048
2048
2048
512
2560
512
4095
4095
OP[9:0]
0:1023
ORNG
0:1
512
505
518
1023
257
640
128
1023
1021
0
0
0
1
1
0
0
1
0
Table 2: Examples of digital backend calculation
Wolfson Microelectronics
13
WM8144-10
Theory of Operation (contd.)
P
W
P
1
D
V
M
O
D
E
P B7
W
P
0
B6
CDATA WORD 1
B5 B4 B3 B2
B1
B0
B7
B6
CDATA WORD 2
B5 B4 B3 B2
B1
B0
0
0
0
G11 G10 G9
G8 G7
G6
G5
G4 G3
G2
G1 G0
O3
O2
O1 O0
0
0
1
G10 G9
G8
G7 G6
G5
G4
G3 G2
G1
G0 O4
O3
O2
O1 O0
0
1
1
0
0
0
G9 G8
G10 G9
G7
G8
G6 G5
G7 G6
G4
G5
G3
G4
G2 G1
G3 G2
G0
G1
O5 O4 O3
G0 DV O3
O2
O2
O1 O0
O1 O0
1
0
1
G9
G7
G6 G5
G4
G3
G2 G1
G0
DV O4
O2
O1 O0
offset range
No. of gain
bits
gain
range
-8 : 7
-16 - 15
-32 - 31
-8 - 7
-16 : 15
12
11
10
11
10
0:2
0:2
0:2
0:2
0:2
G8
O3
Table 3: Bit Allocation Assignment
DVMODE PWP1 PWP0 No. of
offset
bits
0
0
0
1
1
0
0
1
0
0
0
1
0
0
1
4
5
6
4
5
DV bits
gain
resolution
(LSB
steps)
0.25
0
0.5
0
1
0
0.5
1
1
1
Table 4: Bit Range and Resolution Options
Data Valid Generation
The DV pin can be controlled to determine whether a DV
pulse will be generated for a particular pixel. For example, if red pixels only are required the following DV pulse
can be generated.
OP[9:0]
B
R
G
B
R
Output data interface
By default, data is output from the device as a ten-bit
wide word on OP[9:0]. Optionally, data can be output in
an eight-bit word format. Figure 11 shows this function.
Data is presented on pins OP[9:2] at twice pixel rate.
G
DV
Figure 9
Data Latch
Under control of the LATCHOP bit the output data bus
can be prevented from clamping until the next Data Valid
pulse. Hence the above output would become:
OP[9:0]
DV
Figure 10
R
R
A = d9,d8,d7,d6,d5,d4,d3,d2
B = d1,d0,X,X,X,X,X,ORNG
Figure 11: Eight-bit Multiplexed Bus Output
Wolfson Microelectronics
14
WM8144-10
Operational Modes
Video Sampling Options
WM8144-10 can interface to CCD sensors using four
basic modes of operation ( summarised in Table 4). Mode
configurations are controlled by a combination of control
bits and timing applied to MCLK and VMSP pins. The default operational mode is mode 1: colour with CDS enabled.
Colour mode definition (mode 1)
Figure 12 summarises the timing relationships within the
Colour mode. MCLK is applied at twice the required ADC
conversion rate. Synchronisation of sampling and channel multiplexing to the incoming video signal is performed
by the VSMP pulse (active high). The three input channels (R,G,B) are sampled in parallel on the rising edge of
MCLK following a VSMP pulse. The sampled data is multiplexed into a single data stream at three times the VSMP
rate and passes through the internal pipeline and emerges
on the OP[9:0] bus 20.5 MCLK periods later.
If the digital post-processing stage is activated, compensation data will be clocked into the device at twice the
ADC conversion rate (e.g. two reads per red pixel ). The
first of the two bytes will be required on the CDATA bus
15.5 MCLK periods after the corresponding VSMP pulse.
CC[2:0] can be used to control the three lower address
lines of an external RAM. Both Correlated Double Sampling (CDS) and single sample modes of operation are
available.
MSPS. This is achieved by altering the MCLK:VSMP
ratio to 3:1. In this mode, the timing of RS and CL must
be fixed (refer to Table 5).
The sampled video data will pass through the internal
pipeline and emerge on the OP[9:0] bus 29.5 MCLK
periods later.
If the digital post-processing stage is activated compensation data will be clocked into the device at twice
the internal pixel rate (e.g. two reads per red pixel ).
The first of the two bytes will be required on the CDATA
bus 22.5 MCLK periods after the corresponding VSMP
pulse.
Details of Max. Speed Monochrome mode
(mode 4)
Figure 15 summarises the timing relationships. This
mode allows the maximum sample rate to be increased
to 6 MSPS. This is achieved by altering the MCLK:VSMP
ratio to 2:1. The latency through the device is identical
to modes 1 and 2. CDS is not available in this mode.
Monochrome mode definitions
One input channel is continuously sampled on the rising
edge of MCLK following a VSMP pulse. The user can
specify which input channel (R,G,B) to be sampled by
writing to WM8144-10 internal control registers. There
are three separate monochrome modes with different
maximum sample rates and CDS availability.
Details of Monochrome mode timing (mode 2)
Figure 13 summarises the timing relationships. The timing in this mode is identical to mode 1 except for the
CC[2:0] outputs. One input channel is sampled three
times ( due to the multiplexer being held in one position)
and passes through the device as three separate samples. Two of the samples can be ignored at the output.
The CC[2:1] output pins reflect the input channel selected
(R,G or B).
Details of Fast Monochrome mode timing
(mode 3)
Figure 14 summarises the timing relationships. This mode
allows the maximum sample rate to be increased to 4
Wolfson Microelectronics
15
16
Table 5: WM8144-10 Mode Summary
Wolfson Microelectronics
Fast
Monochrome
Max Speed
Monochrome
3
4
No
Yes
Yes
Yes
CDS
available
* Only indicates relevant register bits
Monochrome
Colour
Description
2
1
Mode
6 MSPS Identical to Mode 2
4 MSPS Identical to Mode 2
MCLK max. 12MHz.
MCLK:VSMP ratio is 2:1.
MCLK max. 12MHz.
MCLK:VSMP ratio is 3:1.
2 MSPS One input channel is Identical to Mode 1
continuously
sampled. The internal
multiplexer is held in
one position under
control of the user.
Max.
Sensor Interface
Timing Requirements
Sample
Description
Rate
2 MSPS The three input
MCLK max. 12MHz.
channels (R,G,B) are MCLK:VSMP ratio is 6:1.
sampled in parallel at
max. 2MSPS. The
sampled data is
multiplexed into a
single data stream
before the internal
ADC giving an
internal serial data
rate of max. 6MSPS.
Setup Reg 1: 1D(H)
Setup Reg 3: bits b[76] define which
channel to be
sampled
Setup Reg 1: 19(H)
Register Contents
without CDS*
Not Applicable
Setup Reg 1: 5D(H)
Setup Reg 3: bits b[76] define which
channel to be
sampled
Identical to Mode 2
Identical to Mode 2
plus Setup Reg 3: bits
b[5-4] must be set to
00(H)
Setup Reg 1: 1F(H)
Setup Reg 3: bits
b[7-6] define which
channel to be
sampled
Setup Reg 1: 1B(H)
Register Contents
with CDS*
WM8144-10
Operational Modes (Contd.)
OUTPUT
SIGNALS
INTERNAL
SIGNALS
INPUT
SIGNALS
MCLK
CC[2:1]
CC[2]
1
b0
1
r1,g1,b1
g1
2
0
20.5 MCLK periods
r1
2
1
b1
r2,g2,b2
15.5 MCLK periods
2
2
r2
0
g2
3
1
b2
r3,g3,b3
3
2
r3
0
g3
4
1
b3
4
2
r4
r1:1 r1:2 g1:1 g1:2 b1:1 b1:2
r4,g4,b4
0
r1
g4
5
1
g1
b4
r5,g5,b5
5
2
b1
Operational Modes (Contd.)
CC[1]
CC[0]
DV
ORNG
OP[9:0]
ADC sample
ADC input
VS
RS
CDATA[7:0]
Input video
VSMP
WM8144-10
Device timing for mode 1
Figure 12: Default Timing in CDS Colour Mode
Wolfson Microelectronics
17
18
OUTPUT
SIGNALS
INTERNAL
SIGNALS
INPUT
SIGNALS
Wolfson Microelectronics
Figure 13: Default Timing in CDS Monochrome Mode
CC[2:1]
CC[2]*
X
X
1
r1
X
2
X
0
X
0
20.5 MCLK periods
X
0
X
X
X
X
r2,g2,b2
15.5 MCLK periods
2
0
X
X
X
0
3
X
0
X
X
X
X
r3,g3,b3
3
0
X
X
X
0
4
X
r1:1 r1:2
0
X
X
X
X
r4,g4,b4
4
0
X
X
X
'X' indicates don't care
* This example shows function when Red channel selected. CC[1] and CC[2] indicate the selected channel (R,G or B)
0
X
X
r1,g1,b1
0
r1
5
X
0
X
X
X
X
r5,g5,b5
5
0
X
X
Operational Modes (Contd.)
CC[1]*
CC[0]
DV
ORNG
OP[9:0]*
ADC sample
ADC input
VS
RS
CDATA[7:0]
Input video
VSMP
MCLK
WM8144-10
Device timing for mode 2
OUTPUT
SIGNALS
INTERNAL
SIGNALS
INPUT
SIGNALS
CC[2:1]*
CC[2]*
CC[1]*
0
29.5 MCLK periods
n
n+1
22.5 MCLK periods
0
0
0
0
0
* This example shows function when Red channel selected. CC[1] and CC[2] indicate the selected channel (R,G or B)
0
n
0
n:1
n:2
0
0
n
0
Operational Modes (Contd.)
CC[0]
DV
ORNG
OP[9:0]
ADC sample
ADC input
VS
RS
CDATA[7:0]
Input video
VSMP
MCLK
WM8144-10
Device timing for mode 3
Figure 14: Default Timing in Fast CDS Monochrome Mode
Wolfson Microelectronics
19
20
OUTPUT
SIGNALS
INTERNAL
SIGNALS
INPUT
SIGNALS
Wolfson Microelectronics
CC[2:1]*
CC[2]*
CC[1]*
0
0
20.5 MCLK periods
n
15.5 MCLK periods
0
0
0
0
0
0
n:1 n:2
0
0
0
n
0
* This example shows function when Red channel selected. CC[1] and CC[2] indicate the selected channel (R,G or B)
0
1
n
0
Operational Modes (Contd.)
CC[0]
DV
ORNG
OP[9:0]
ADC sample
ADC input
VS
CDATA[7:0]
Input video
VSMP
MCLK
WM8144-10
Device timing for mode 4
Figure 15: Default Timing in Max. Speed non-CDS Monochrome Mode
WM8144-10
Configuration of the WM8144-10
The WM8144-10 can be configured through a serial
interface or a parallel interface. Selection of the
interface type is by the PNS pin which must be tied
high (parallel) or low (serial).
Figure 16: Serial Interface Timing
Serial Interface
The serial interface consists of three pins (refer to
figure 16 ). A six-bit address is clocked in MSB first
followed by an eight-bit data word, also MSB first.
Each bit is latched on the rising edge of SCK, which
can operate at upto 12MHz. Once the data has been
shifted into the device, a pulse is applied to SEN to
transfer the data to the appropriate internal register.
Figure 17: Parallel Interface Timing
Parallel Interface
The parallel interface uses bits [9:2] of the OP bus as
well as the STB, DNA and RNW pins (refer to figure
17). Pin RNW must be low during a write operation.
The DNA pin defines whether the data byte is address
(low) or data (high). The data bus OP[9:2] is latched in
during the low period of STB. This interface is
compatible with the Extended Parallel Port interface.
the address location of internal data registers. In each case,
a further three sub-addresses are defined for the red, green
and blue register. Selection between the red, green and
blue registers is performed by address bits a1 and a0, as
defined in the table. Setting both a1 and a0 equal to 1 forces
all three registers to be updated to the same data value.
Blank entries can be taken as 'don't care' values.
Internal Register Definition
Table 5 summarises the internal register content. The
first 4 addresses in the table are used to program setup
registers and to provide a software reset feature ( 00H
is reserved ). The remaining 7 entries in the table define
Address
<a5:a0>
000000
000001
000010
000011
000100
000101
1000xx
1001xx
1010xx
1011xx
1100xx
1101xx
1110xx
xx
Description
Reserved
Setup Register 1
Setup Register 2
Setup Register 3
Software Reset
Setup Register 4
DAC values
DAC signs
PGA Gains
Pixel Offsets
Pixel Gain MSB
Pixel Gain LSB
Data Valid
Def'lt
(Hex)
1B
00
11
00
00
00
00
00
00
80
00
01
Bit
b7
b6
DVMODE
VSMP6M
CHAN[1]
CHAN[0]
DAC[7]
DAC[6]
DAC[5]
GAIN[11]
GAIN[10]
OFF[5]
GAIN[9]
a1
0
0
1
1
a0
0
1
0
1
Address LSB decode
Red Register
Green Register
Blue Register
Red, Green and Blue
b5
b4
b3
b2
b1
b0
DEFPG
LATCHOP
PWP[1]
MONO
INVOP
PWP[0]
CDS
RLC[1]
ENADC
MUXOP
RLC[0]
DAC[4]
DAC[3]
DAC[2]
DACRNG
DAC[1]
PGA[4]
OFF[4]
GAIN[8]
PGA[3]
OFF[3]
GAIN[7]
GAIN[3]
PGA[2]
OFF[2]
GAIN[6]
GAIN[2]
PGA[1]
OFF[1]
GAIN[5]
GAIN[1]
DEFDV
DEFPO
CDATOUT BYPASS
CDSREF[1] CDSREF[0]
DAC[0]
DSIGN
PGA[0]
OFF[0]
GAIN[4]
GAIN[0]
DV
Table 6: Register Map Contents
Wolfson Microelectronics
21
WM8144-10
Configuration of the WM8144-10 (Contd.)
Register
Setup
Register 1
Setup
Register 2
Bit No
0
1
Bit(s)
ENADC
CDS
Default
1
1
2
3
4
5
6
MONO
DEFPG
DEFPO
DEFDV
VSMP6M
0
1
1
0
0
Description
ADC standby control: 0 = standby, 1 = active
Select Correlated double sampling mode: 0 = normal sampling, 1 =
CDS mode
Mono/Colour select: 0 = colour, 1 = monochrome operation
Select Default Pixel Gain: 0 = external pixel gain, 1 = internal
Select Default Pixel Offsets: 0 = external pixel offsets, 1 = internal
Select default internal Data Valid: 0 = external DV, 1 = internal
Required when VSMP at 6MSPS: 0 = other mode, 1 = VSMP at 6MSPS
7
DVMODE
0
External Data Valid control (refer to Bit Allocation Assignment table)
0
1
2
3
MUXOP
0
Eight bit output mode: 0 = ten-bit, 1 = 8-bit multiplexed
INVOP
LATCHOP
0
0
4
5
BYPASS
CDATOUT
0
0
Inverts ADC output: 0 = non-inverting, 1 = inverting
OP bus updated on DV pulse; OP bus updated each sample, 1 = update
only on DV pulse
Bypass digital post-processing; 0 = no bypass, 1 = bypass
Data on OP pins available on CDAT pins; 0 = no, 1 = yes
1-0
RLC1-0
01
3-2
PWP1-0
00
5-4
CDSREF1-0
01
7-6
CHAN1-0
00
1
DACRNG
0
6
7
Setup
Register 3
Setup
Register 4
Reset Level Clamp voltage
00 = 1.5V
01 = 2.5V
10 = 3.5V
11 = Reserved
Parallel Word Partitioning
See Bit Allocation Assignment (Table 3)
CDS Mode Reset Timing Adjust
00 = Advance 1 MCLK Period
01 = Normal
10 = Retard 1 MCLK Period
11 = Retard 2 MCLK Period
Monochrome mode channel select
00 = Red Channel
01 = Green Channel
10 = Blue Channel
11 = Reserved
Alters range of offset DAC output
0 = DAC output range equal to Vmid/2 (1.25V)
1 = DAC output range equal to 1.5 * Vmid/2 (1.875V)
Table 7: Control Bit Descriptions
Wolfson Microelectronics
22
WM8144-10
Detailed timing diagrams
Figure 18: Detailed Video Input Timing - Modes 1 and 2
Figure 19: Detailed Digital Timing - Modes 1 and 2
Wolfson Microelectronics
23
WM8144-10
Detailed timing Diagrams (Contd.)
Figure 20: Detailed Video Input Timing - Mode 3
Figure 21: Detailed Digital Timing - Mode 3
Figure 22: Detailed Video Input Timing - Mode 4
Figure 23: Detailed Digital Timing - Mode 4
Wolfson Microelectronics
24
WM8144-10
Detailed timing Diagrams (Contd.)
tSPER
tSCKH tSCKL
SCK
tSSU
tSH
SDI
tSCE
tSEW
tSEC
SEN
Figure 24: Detailed Timing Diagram for Serial Interface
OP[9:2]
tSTB
tSTB
STB
8144 Out
Z
tASU
tAH
tDSU
Address In
tADLS
tDH
Data In
tADLH
tADHS
Z
8144 Out
tADHH
DNA
RNW
tOPD
tOPZ
Figure 25: Detailed Timing Diagram for Parallel Interface
Wolfson Microelectronics
25
WM8144-10
External component recommendations
DVDD
+
2 2µF
C6
+
C13
C5
0 . 1µF
C7
1 0µF
+
C14
0 . 1µF
3 3µF
C8
DGND
0 . 1µF
OP9
OEB
SDI/DNA
SEN/STB
RLC
DVDD1
MCLK
VSMP
CDATA7
SCK/RNW
VRLC
WM8144-10
OP8
AGND
OP7
AVDD
VRU
OP4
VRB
OP3
VRT
1
2
3
4
5
6
7
8
9
1 0µF
0 . 1µF
22
21
C1
20
1 0µF
C2
19
18
0 . 1µF
17
16
15
14
13
C3
0 . 1µF
C9
1 0µF
C10
0 . 1µF
C11
+
C16
+
C15
10 11 12
23
+
DVDD
NRESET
VRL
OP5
ORNG
OP6
CC0
48
VMID
CC1
47
DGND
CC2
46
BINP
DV
45
CDATA0
NC
44
GINP
NC
DGND
43
RINP
CDATA1
DVDD2
42
AVDD
24
PNS
CDATA2
OP0
41
AGND
1 0µF
C12
0 . 1µF
DGND
AGND
Wolfson Microelectronics
26
+
40
OP1
39
CDATA3
OP2
38
CDATA6
37
CDATA5
CDATA4
36 35 34 33 32 31 30 29 28 27 26 25
AGND
WM8144-10
Package Dimensions
0.27
0.17
0.50
36
0.08 M
25
37
24
48
13
0.13NOM
1
12
5.50TYP
Gage Plane
7.002
9.002
0.25
0.05MIN
0o - 7o
1.45
1.35
0.75
0.45
Seating Plane
0.08
1.60MAX
48 Pin TQFP
Notes: A .
B.
C.
All linear dimensions are in millimeters
This drawing is subject to change without notice.
Falls within JEDEC MO-026
Wolfson Microelectronics
27