NSC DS8831J

DS7831/DS8832
Dual TRI-STATE ® Line Driver
General Description
Features
Through simple logic control, the DS7831/DS8832 can be
used as either a quad single-ended line driver or a dual differential line driver. They are specifically designed for party
line (bus-organized) systems. The DS8832 does not have
the VCC clamp diodes found on the DS7831.
The DS7831 is specified for operation over the −55˚C to
+125˚C military temperature range. The DS8832 is specified
for operation over the 0˚C to +70˚C temperature range.
n
n
n
n
n
Series 54/74 compatible
17 ns propagation delay
Very low output impedance — high drive capability
40 mA sink and source currents
Gating control to allow either single-ended or differential
operation
n High impedance output state which allows many outputs
to be connected to a common bus line
Connection and Logic Diagram
Dual-In-Line Package
DS005800-1
Top View
Order Number DS8832J or DS8832N
See NS Package Number J16A or N16A
For Complete Military 883 Specificatons,
See RETS Data Sheet.
Order Number DS7831J/883, DS7831W/883,
See NS Package Number J16A or W16A
TRI-STATE ® is a registered trademark of National Semiconductor Corp.
© 1999 National Semiconductor Corporation
DS005800
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DS7831DS8832 Dual TRI-STATE Line Driver
May 1999
Truth Table
(Shown for A Channels Only)
Differential/
“A” Output Disable
Single-Ended
Input A1
Output A1
Input A2
Output A2
Logical “1” or
Same as
Logical “1” or
Same as
Logical “0”
Input A1
Logical “0”
Input A2
Mode Control
0
0
0
0
1
X
X
1
0
0
X
1
Logical “1” or
Opposite of
Logical “1” or
Same as
1
X
Logical “0”
Input A1
Logical “0”
Input A2
X
Impedance
High
X
X
X
Impedance
State
X = Don’t Care
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2
High
State
Absolute Maximum Ratings (Note 2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
DS7831
DS8831/DS8832
Temperature (TA)
DS7831
DS8832
Supply Voltage
7V
Input Voltage
5.5V
Output Voltage
5.5V
Storage Temperature Range
−65˚C to +150˚C
Lead Temperature (Soldering, 4 sec.)
260˚C
Maximum Power Dissipation (Note 1) at 25˚C
Cavity Package
1433 mW
Molded Package
1362 mW
Min
Max
Units
4.5
4.75
5.5
5.25
V
V
−55
0
+125
+70
˚C
˚C
Note 1: Derate cavity package 9.6 mW/˚C above 25˚C; derate molded package 10.9 mW/˚C above 25˚C.
Electrical Characteristics (Notes 3, 4)
Symbol
Parameter
Conditions
VIH
Logical “1” Input Voltage
VIL
Logical “0” Input Voltage
VCC = Min
VCC = Min
VOH
Logical “1” Output Voltage
DS7831
Max
DS7831
VCC = Min
IIH
Logical “1” Input Current
VCC = Max
IIL
Logical “0” Input Current
IOD
Output Disable Current
ISC
Output Short Circuit Current
VCC = Max, VIN = 0.4V
VCC = Max, VO = 2.4V or 0.4V
VCC = Max, (Note 5)
ICC
Supply Current
VCLI
Input Diode Clamp Voltage
VCLO
Output Diode Clamp
Voltage
1.8
2.3
V
2.4
2.7
V
1.8
2.5
V
IO = −5.2 mA
IO = 40 mA
IO = 32 mA
2.4
2.9
0.29
0.29
DS7831, VIN = 5.5V
DS8832, VIN = 2.4V
−40
V
0.50
V
0.40
V
0.50
V
0.40
V
1
mA
40
µA
−1.0
−1.6
mA
40
µA
−100
−120
mA
90
mA
−40
VCC = Max in TRI-STATE
VCC = 5.0V, TA = 25˚C, IIN = −12 mA
VCC = 5.0V,
IOUT = −12 mA
DS7831
TA = 25˚C
DS8832
IOUT = 12 mA
V
IO = −40 mA
IO = −2 mA
IO = −40 mA
IO = 40 mA
IO = 32 mA
DS8832
Units
V
0.8
VCC = Min
Logical “0” Output Voltage
Typ
2.0
DS8832
VOL
Min
65
DS7831
−1.5
V
−1.5
V
VCC + 1.5
V
Switching Characteristics
TA = 25˚C, VCC = 5V, unless otherwise noted
Symbol
tpd0
Parameter
Conditions
Min
Typ
Max
Units
13
25
ns
13
25
ns
6
12
ns
14
22
ns
Propagation Delay to a Logical “0”
from Inputs A1, A2, B1, B2
Differential Single-ended Mode
Control to Outputs
tpd1
Propagation Delay to a Logical “1”
from Inputs A1, A2, B1, B2
Differential Single-ended Mode
Control to Outputs
t1H
Delay from Disable Inputs to High
Impedance State (from Logical “1”
(See Figure 4 and Figure 5 )
Level)
t0H
Delay from Disable Inputs to High
Impedance State (from Logical “0” Level)
3
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Switching Characteristics
(Continued)
TA = 25˚C, VCC = 5V, unless otherwise noted
Symbol
tH1
Parameter
Conditions
Min
Typ
Max
Units
14
22
ns
18
27
ns
Propagation Delay from Disable Inputs
to Logical “1” Level (from High
Impedance State)
tH0
Propagation Delay from Disable Inputs
to Logical “0” Level (from High
Impedance State)
Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they
are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 3: Unless otherwise specified min/max limits apply across the −55˚C to +125˚C temperature range for the DS7831 and across the 0˚C to +70˚C range for the
DS8832. All typical values are for TA = 25˚C and VCC = 5V.
Note 4: All currents into device pins shown as positive, out of device pins as negative, all voltage referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 5: Applies for TA = 125˚C only. Only one output should be shorted at a time.
Mode of Operation
state. This is accomplished by ensuring that a logical “1” is
applied to at least one of the Output Disable pins of each device which is to be in the “high impedance” state. A NOR gate
was purposely chosen for this function since it is possible
with only two DM5442/DM7442, BCD-to-decimal decoders,
to decode as many as 100 DS7831, DS8832’s (Figure 2).
The unique device whose Disable inputs receive two logical
“0” levels assumes the normal low impedance output state,
providing good capacitive drive capability and waveform integrity especially during the transition from the logical “0” to
logical ”1” state. The other outputs — in the high impedance
state — take only a small amount of leakage current from the
low impedance outputs. Since the logical “1” output current
from the selected device is 100 times that of a conventional
Series 54/74 device (40 mA vs. 400 µA), the output is easily
able to supply that leakage current for several hundred other
DS7831/DS8831’s, DS7832/DS8832’s and still have available drive for the bus line (Figure 3).
To operate as a quad single-ended line driver apply logical
“0”s to the output disable pins (to keep the outputs in the normal low impedance mode) and apply logical “0”s to both
Differential/Single-ended Mode Control inputs. All four channels will then operate independently and no signal inversion
will occur between inputs and outputs.
To operate as a dual differential line driver apply logical “0”s
to the Output Disable pins and apply at least one logical “1”
to the Differential/Single-ended Mode Control inputs.
The inputs to the A channels should be connected together
and the inputs to the B channels should be connected together.
In this mode the signals applied to the resulting inputs will
pass non-inverted on the A2 and B2 outputs and inverted on
the A1 and B1 outputs.
When operating in a bus-organized system with outputs tied
directly to outputs of other DS7831, DS8832’s (Figure 1), all
devices except one must be placed in the “high impedance”
DS005800-2
FIGURE 1.
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4
Mode of Operation
(Continued)
DS005800-3
FIGURE 2.
DS005800-4
FIGURE 3.
5
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Typical Performance Characteristics
Propagation Delay from Input
to Output (Channel 1)
Propagation Delay from Input
to Output (Channel 1)
DS005800-5
Delay from Disable to High
Impedance State
DS005800-10
Delay from Disable to Low
Impedance State
DS005800-12
Total Supply Current vs
Frequency
DS005800-11
Propagation Delay vs Load
Capacitance
DS005800-13
Logical “1” Output Voltage
vs Source Current
DS005800-14
Logical “0” Output Voltage
vs Sink Current
DS005800-16
DS005800-15
IOUT vs VOUT High
Impedance Output State
DS005800-17
Propagation Delay in
Differential Mode
DS005800-18
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Propagation Delay from Input
to Output (Channel 2)
DS005800-19
6
Typical Performance Characteristics
(Continued)
DS005800-6
Switching Time Waveforms
DS005800-7
Input characteristic:
Amplitude = 3.0V
Frequency = 1.0 MHz, 50% duty cycle
tr = tf ≤ ns (10% to 90%)
7
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Switching Time Waveforms
(Continued)
DS005800-8
FIGURE 4.
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8
AC Load Circuit
DS005800-9
Symbol
Switch S1
Switch S2
CL
tpd1
closed
closed
50 pF
tpd0
closed
closed
50 pF
t0H
closed
closed
*5 pF
t1H
closed
closed
*5 pF
tH0
closed
open
50 pF
tH1
open
closed
50 pF
*Jig capacitance
FIGURE 5.
9
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Physical Dimensions
inches (millimeters) unless otherwise noted
Ceramic Dual-In-Line Package (J)
Order Number DS7831J or DS8832J
NS Package Number J16A
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10
DS7831DS8832 Dual TRI-STATE Line Driver
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
Order Number DS8832N
NS Package Number N16A
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