AK8181G Preliminary 3.3V LVDS 1:4 Clock Fanout Buffer AK8181G Features Description The AK8181G is a member of AKM’s LVDS clock fanout buffer family designed for telecom, networking and computer applications, requiring a range of clocks with high performance and low skew. The AK8181G distributes 4 buffered clocks. Four differential 3.3V LVDS outputs Selectable two LVCMOS/LVTTL clock inputs Clock output frequency up to 650MHz Translates LVCMOS/LVTTL input signals to LVDS levels Output skew : 30ps (maximum) Part-to-part skew : 500ps (maximum) Propagation delay : 2.2ns (maximum) Additive phase jitter(RMS): 0.1ps (typical) Operating Temperature Range: -40 to +85℃ Package: 20-pin TSSOP (Pb free) Pin compatible with ICS8545I AK8181G are derived from AKM’s long-termexperienced clock device technology, and enable clock output to perform low skew. The AK8181G is available in a 20-pin TSSOP package. Block Diagram draft-E-01 Feb-2013 -1- AK8181G Pin Descriptions Package: 20-Pin TSSOP(Top View) Pin No. Pin Name 1 2 3 VSS CLK_EN CLK_SEL Pin Type Pullup down PWR --- IN IN Pull up Pull down Description Negative power supply Synchronizing clock output enable (LVCMOS/LVTTL) Pin is connected to VDD by internal resistor. (typ. 51kΩ High (Open): clock outputs follow clock input. Low: Q outputs are forced low, Qn outputs are forced high. CLK Select Input (LVCMOS/LVTTL) Pin is connected to VSS by internal resistor. (typ. 51kΩ High: selects CLK2 input Low (Open): selects CLK1 input 4 CLK1 IN Pull down 5 NC -- --- 6 CLK2 IN Pull down 7 NC -- --- 8 OE IN Pull up Single-ended clock input Pin is connected to VSS by internal resistor. (typ. 51kΩ No connect Single-ended clock input Pin is connected to VSS by internal resistor. (typ. 51kΩ No connect Output enable. Controls enabling and disabling of outputs Q0, Q0n through Q3, Q3n. Pin is connected to VDD by internal resistor. (typ. 51kΩ 9 VSS PWR --- Negative power supply 10 VDD PWR --- Positive power supply 11, 12 Q3n, Q3 OUT --- Differential clock output (LVDS) 13 VSS PWR --- Negative power supply 14, 15 Q2n, Q2 OUT --- Differential clock output (LVDS) 16, 17 Q1n, Q1 OUT --- Differential clock output (LVDS) 18 VDD PWR --- Positive power supply 19, 20 Q0n, Q0 OUT --- Differential clock output (LVDS) Ordering Information Part Number Marking Shipping Packaging Package Temperature Range AK8181G AK8181G Tape and Reel 20-pin TSSOP -40 to 85 °C Feb-2013 draft-E-01 -2- AK8181G Absolute Maximum Rating Over operating free-air temperature range unless otherwise noted Items Supply voltage Input voltage Symbol Ratings Unit VDD -0.3 to 4.6 V Vin VSS-0.5 to VDD+0.5 V IIN ±10 mA Tstg -55 to 150 C Input current (any pins except supplies) Storage temperature (1) Note (1) Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rating conditions for extended periods may affect device reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. (2) VSS=0V ESD Sensitive Device This device is manufactured on a CMOS process, therefore, generically susceptible to damage by excessive static voltage. Failure to observe proper handling and installation procedures can cause damage. AKM recommends that this device is handled with appropriate precautions. Recommended Operation Conditions Parameter Operating temperature Supply voltage (1) Symbol Conditions Ta VDD Min Typ -40 VDD5% 3.135 3.3 Max Unit 85 C 3.465 V (1) Power of 3.3V requires to be supplied from a single source. A decoupling capacitor of 0.1F for power supply line should be located close to each VDD pin. Pin Characteristics Parameter Symbol Conditions Min Typ Max Unit Input Capacitance CIN 4 pF Input Pullup Resistor RPU 51 kΩ Input Pulldown Resistor RPD 51 kΩ Power Supply Characteristics Parameter Symbol Conditions CLK1 = input 650MHz Power Supply Current IDD CLK2 = open CLK1 = open CLK2 = input 650MHz draft-E-01 Min Typ Max Unit 47 mA 47 mA Feb-2013 -3- AK8181G DC Characteristics (LVCMOS/LVTTL) All specifications at VDD=3.3V5%, Ta: -40 to +85℃, unless otherwise noted Parameter Input High Voltage Symbol Conditions MAX Unit 2.0 VDD+0.3 V -0.3 1.3 V -0.3 0.8 V Vin=VDD=3.465V 150 μA Vin=VDD=3.465V 5 μA VIH CLK1, CLK2 Input Low Voltage Input High Current CLK_SEL, OE, CLK_EN, CLK_SEL CLK_EN, OE VIL IH Vin=VSS, CLK_SEL Input Low Current IL CLK_EN, OE VDD=3.465V Vin=VSS, VDD=3.465V MIN TYP -5 μA -150 μA DC Characteristics (Differential) All specifications at VDD=3.3V5%, VSS=0V, Ta: -40 to +85℃, unless otherwise noted Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Symbol Conditions VOD MIN TYP MAX Unit 200 280 360 mV 40 mV ΔVOD VOS 1.125 ΔVOS 1.25 1.375 V 5 25 mV High Impedance Leakage Current IOZ +10 μA Differential Output Short Circuit Current IOSD -3.5 -5 mA Output Voltage High VOH 1.34 1.6 V Output Voltage Low VOL OE = Low -10 0.9 Feb-2013 1.06 V draft-E-01 -4- AK8181G AC Characteristics All specifications at VDD=3.3V5%, VSS=0V, Ta: -40 to +85℃, unless otherwise noted Parameter Symbol Output Frequency Propagation Delay Output Skew tPD (3) (4) Buffer Additive Jitter, RMS Output Rise/Fall Time Output Duty Cycle MIN TYP fOUT (1) (2) (3) Part-to-Part Skew Conditions (5) (5) 0.7 MAX Unit 650 MHz 2.2 ns tsk(O) 30 ps tskPP 500 ps tjit 156.25MHz (12kHz – 20MHz) tr , tf 20% to 80% @50MHz DCOUT 0.1 ps 100 500 ps 45 55 % All parameters measured at f ≤ 650MHz unless noted otherwise. The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter. (1) Measured from VDD/2 of the input to the differential output crossing point. (2) Defined as skew between outputs at the same supply voltage and with equal load conditions. (3) This parameter is defined in accordance with JEDEC Standard 65. (4) Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. (5) Design value. draft-E-01 Feb-2013 -5- AK8181G Figure 1 3.3V Output Load Test Circuit Figure 2 Differential Output Level Figure 3 Output Skew Figure 4 Output Rise/Fall Time Figure 5 Propagation Delay Figure 6 Output Duty/ Pulse Width/ Period Figure 7 Part-to-Part Skew Feb-2013 draft-E-01 -6- AK8181G Figure 8 Offset Voltage Setup Figure 9 Differential Output Voltage Setup Figure 10 High Impedance Leakage Figure 11 Differential Output Short Circuit Current Setup Setup draft-E-01 Feb-2013 -7- AK8181G Function Table The following table shows the inputs/outputs clock state configured through the control pins. Table 1: Control Input Function Table Inputs Outputs OE CLK_EN CLK_SEL Selected Source Q0:Q3 Q0n:Q3n 1 0 0 (Open) CLK1 Disabled: Low Disabled: High 1 0 1 CLK2 Disabled: Low Disabled: High 1 1 (Open) 0 (Open) CLK1 Enabled Enabled 1 1 (Open) 1 CLK2 Enabled Enabled 0 Don’t care Don’t care --- Hi-Z Hi-Z After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 12. In the active mode, the state of the outputs are a function of the CLK1 and CLK2 inputs as described in Table 2. Figure 12 CLK_EN Timing Diagram Table 2: Clock Input Function Table Inputs Outputs CLK1/2 Q0 : Q3 Q0n : Q3n 0 Low High 1 High Low Feb-2013 draft-E-01 -8- AK8181G Package Information Mechanical data : 20pin TSSOP 6.50±0.10 0.15±0.05 11 1 6.40±0.10 4.40±0.10 0.6±0.10 20 10 0.25±0.05 0.65 0°～8° S 0.10±0.05 0.10 S 1.10 MAX 0.90±0.05 Marking 20 11 b AK8181G XXXXXXX c a: b: c: #1 Pin Index Part number Date code ( 7 digits) a 10 1 RoHS Compliance All integrated circuits form Asahi Kasei Microdevices Corporation (AKM) assembled in “lead-free” packages* are fully compliant with RoHS. (*) RoHS compliant products from AKM are identified with “Pb free” letter indication on product label posted on the anti-shield bag and boxes. draft-E-01 Feb-2013 -9- AK8181G IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. Feb-2013 draft-E-01 - 10 -