AK8181E Preliminary 3.3V LVPECL 1:4 Clock Fanout Buffer AK8181E Features Description The AK8181E is a member of AKM’s LVPECL clock fanout buffer family designed for telecom, networking and computer applications, requiring a range of clocks with high performance and low skew. The AK8181E distributes 4 buffered clocks. Four differential 3.3V LVPECL outputs Selectable crystal or differential clock inputs Clock output frequency up to 650MHz Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on PCLKn input Output skew : 10ps (typical) Part-to-part skew : 150ps (maximum) Propagation delay : 0.9ns (typical) Additive phase jitter(RMS): PCLKp/[email protected] : 0.04ps (typical) XTAL@50MHz : 0.14ps (typical) Operating Temperature Range: -40 to +85℃ Package: 20-pin TSSOP (Pb free) Pin compatible with ICS8533I-31 AK8181E are derived from AKM’s long-termexperienced clock device technology, and enable clock output to perform low skew. The AK8181E is available in a 20-pin TSSOP package. Block Diagram draft-E-01 Feb-2013 -1- AK8181E Pin Descriptions Package: 20-Pin TSSOP(Top View) Pin No. Pin Name 1 VSS Pin Type Pullup Down PWR --- Description Negative power supply Synchronizing clock output enable (LVCMOS/LVTTL) 2 CLK_EN IN Pull up Pin is connected to VDD by internal resistor. (typ. 51kΩ) High(Open): clock outputs follow clock input. Low: Q outputs are forced low, Qn outputs are forced high. CLK Select Input (LVCMOS/LVTTL) 3 CLK_SEL IN Pull down Pin is connected to VSS by internal resistor. (typ. 51kΩ) High: selects XTAL inputs Low(Open): selects PCLKp/n inputs Non-inverting differential clock input 4 PCLKp IN Pull down 5 PCLKn IN Pull up 6 XTAL_IN IN --- Crystal oscillator interface 7 XTAL_OUT IN --- Crystal oscillator interface 8, NC -- --- No connect Pin is connected to VSS by internal resistor. (typ. 51kΩ) Inverting differential clock input Pin is connected to VDD by internal resistor. (typ. 51kΩ) 9 NC -- --- No connect 10 VDD PWR --- Positive power supply 11, 12 Q3n, Q3 OUT --- Differential clock output (LVPECL) 13 VDD PWR --- Power supply 14, 15 Q2n, Q2 OUT --- Differential clock output (LVPECL) 16, 17 Q1n, Q1 OUT --- Differential clock output (LVPECL) 18 VDD PWR --- Positive power supply 19, 20 Q0n, Q0 OUT --- Differential clock output (LVPECL) Ordering Information Part Number Marking Shipping Packaging Package Temperature Range AK8181E AK8181E Tape and Reel 20-pin TSSOP -40 to 85 °C Feb-2013 draft-E-01 -2- AK8181E Absolute Maximum Rating Over operating free-air temperature range unless otherwise noted Items Supply voltage Symbol Ratings Unit VDD -0.3 to 4.6 V Vin VSS-0.5 to VDD+0.5 V IIN ±10 mA Tstg -55 to 150 C Input voltage Input current (any pins except supplies) Storage temperature (1) Note (1) Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rating conditions for extended periods may affect device reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. (2) VSS=0V ESD Sensitive Device This device is manufactured on a CMOS process, therefore, generically susceptible to damage by excessive static voltage. Failure to observe proper handling and installation procedures can cause damage. AKM recommends that this device is handled with appropriate precautions. Recommended Operation Conditions Parameter Operating temperature Supply voltage (1) Symbol Conditions Ta VDD Min Typ -40 VDD5% 3.135 (1) Power of 3.3V requires to be supplied from a single source. be located close to each VDD pin. 3.3 Max Unit 85 C 3.465 V A decoupling capacitor of 0.1F for power supply line should Pin Characteristics Parameter Symbol Conditions Min Typ Max Unit Input Capacitance CIN 4 pF Input Pullup Resistor RPU 51 kΩ Input Pulldown Resistor RPD 51 kΩ Power Supply Characteristics Parameter Symbol Conditions PCLKp/n = input Power Supply Current IDD XTAL = open XTAL = input PCLKp/n = open draft-E-01 650MHz 50MHz Min Typ Max Unit 32 mA 35 mA Feb-2013 -3- AK8181E DC Characteristics (LVCMOS/LVTTL) All specifications at VDD= 3.3V5%, Ta: -40 to +85℃, unless otherwise noted Parameter Symbol Input High Voltage Conditions VIH Input Low Voltage Input High Current IH CLK_EN -0.3 Input Low Current IL CLK_EN MAX Unit VDD+0.3 V 0.8 V Vin=VDD=3.465V 150 μA Vin=VDD=3.465V 5 μA Vin=VSS, CLK_SEL TYP 2.0 VIL CLK_SEL MIN VDD=3.465V Vin=VSS, VDD=3.465V -5 μA -150 μA DC Characteristics (Differential) All specifications at VDD= 3.3V5%, Parameter Ta: -40 to +85℃, unless otherwise noted Symbol PCLKp Input High Current IH PCLKn Input Low Current IL PCLKn Unit Vin=VDD=3.465V 150 μA Vin=VDD=3.465V 5 μA VDD=3.465V Vin=VSS, VDD=3.465V Peak-to-Peak Input Voltage Common Mode Input Voltage MAX Vin=VSS, PCLKp (1) (2) Conditions (1) (2) MIN TYP -5 μA -150 μA VPP 0.15 1.3 V VCMR VSS+0.5 VDD-0.85 V MAX Unit For single ended applications, the maximum input voltage for PCLKp and PCLKn is VDD+0.3V. Common mode voltage is defined as VIH. DC Characteristics (LVPECL) All specifications at VDD= 3.3V5%, Parameter Output High Voltage Output Low Voltage Ta: -40 to +85℃, unless otherwise noted Symbol (3) (3) Peak-to-Peak Output Voltage Swing (3) Conditions MIN TYP VOH VDD-1.4 VDD-0.9 V VOL VDD-2.0 VDD-1.7 V VSWING 0.6 1.0 V Outputs terminated with 50Ω to VDD-2V. Feb-2013 draft-E-01 -4- AK8181E AC Characteristics All specifications at VDD= 3.3V5%, Parameter Symbol Output Frequency (1) (2) (3) Part-to-Part Skew Conditions MIN TYP MAX Unit 650 MHz fOUT Propagation Delay Output Skew Ta: -40 to +85℃, unless otherwise noted (3) (4) tPD 0.9 ns tsk(O) 10 ps tskPP 150 PCLKp/n 156.25MHz Buffer Additive Jitter, RMS (5) tjit (12kHz – 20MHz) XTAL 50MHz (12kHz – 20MHz) Output Rise/Fall Time (5) Output Duty Cycle tr , tf 20% to 80% DCOUT PCLKp/n ps 0.04 ps 0.14 ps 200 600 ps 50 % All parameters measured at f ≤ 650MHz unless noted otherwise. The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter. (1) Measured from the differential input crossing point to the differential output crossing point. (2) Defined as skew between outputs at the same supply voltage and with equal load conditions. (3) This parameter is defined in accordance with JEDEC Standard 65. (4) Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. (5) Design Value Crystal Characteristics All specifications at VDD= 3.3V5%, VSS=0V, Ta: -40 to +85°C, unless otherwise noted Parameter Conditions MIN MAX Unit 50 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW Mode of Oscillation TYP Fundamental Frequency 12 draft-E-01 Feb-2013 -5- AK8181E Figure 1 3.3V Output Load Test Circuit Figure 2 Differential Input Level Qxn 80% Clock Outputs Qx Qyn 80% VSWING 20% 20% tR tF Qy tsk(o) Figure 3 Output Skew Figure 4 Output Rise/Fall Time Figure 5 Propagation Delay Figure 6 Output Duty/ Pulse Width/ Period Feb-2013 draft-E-01 -6- AK8181E Function Table The following table shows the inputs/outputs clock state configured through the control pins. Table 1: Control Input Function Table Inputs Outputs CLK_EN CLK_SEL Selected Source Q0:Q3 Q0n:Q3n 0 0 (Open) PCLKp/n Disabled: Low Disabled: High 0 1 XTAL Disabled: Low Disabled: High 1 (Open) 0 (Open) PCLKp/n Enabled Enabled 1 (Open) 1 XTAL Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock or crystal oscillator edge as shown in Figure 7. In the active mode, the state of the outputs are a function of the PCLKp/n and XTAL inputs as described in Table 2. Figure 7 CLK_EN Timing Diagram Table 2 Clock Input Function Table Inputs Outputs Input to Output Polarity High Differential to Differential Non Inverting PCLKp PCLKn Q0:Q3 Q0n:Q3n 0 1 Low 1 0 0 1 High Low Differential to Differential Non Inverting Biased (1) Low High Single Ended to Differential Non Inverting Biased (1) High Low Single Ended to Differential Non Inverting Biased (1) 0 High Low Single Ended to Differential Inverting Biased (1) 1 Low High Single Ended to Differential Inverting (1) Please refer to the application Information section, “Wiring the Differential Input to Accept Single Ended Levels”. draft-E-01 Feb-2013 -7- AK8181E Application Information Wiring the Differential Input to Accept Single Ended Levels Figure.8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. Figure 8 Single Ended Signal Driving Differential Input Feb-2013 draft-E-01 -8- AK8181E Package Information Mechanical data : 20pin TSSOP 6.50±0.10 0.15±0.05 11 1 6.40±0.10 4.40±0.10 0.6±0.10 20 10 0.25±0.05 0.65 0°～8° S 0.10±0.05 0.10 S 1.10 MAX 0.90±0.05 Marking 20 11 b AK8181E XXXXXXX c a: b: c: #1 Pin Index Part number Date code ( 7 digits) a 10 1 RoHS Compliance All integrated circuits form Asahi Kasei Microdevices Corporation (AKM) assembled in “lead-free” packages* are fully compliant with RoHS. (*) RoHS compliant products from AKM are identified with “Pb free” letter indication on product label posted on the anti-shield bag and boxes. draft-E-01 Feb-2013 -9- AK8181E IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKM products are neither intended nor authorized for use as critical components Note1) in any safety, life support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. Feb-2013 draft-E-01 - 10 -