AKM AK8181H

AK8181H
2.5V, 3.3V LVPECL 1:10
Preliminary Clock Fanout Buffer
AK8181H
Features
Description
The AK8181H is a member of AKM’s LVPECL
clock fanout buffer family designed for telecom,
networking and computer applications, requiring a
range of clocks with high performance and low
skew. The AK8181H distributes 10 buffered clocks.
Ten differential 2.5V, 3.3V LVPECL outputs
Two Selectable differential inputs
PCLKxp/n pairs can accept the following
differential input levels; LVPECL, LVDS,
LVHSTL, SSTL, HCSL
Clock output frequency up to 700MHz
Translates any single-ended input signal to
3.3V LVPECL levels with resistor bias on
PCLKxn input
Output skew : 30ps typical
Part-to-part skew : 340ps maximum
Propagation delay : (T.B.D)ns maximum
Additive phase jitter(RMS) : 0.045ps (typical)
Operating Temperature Range: -40 to +85℃
Package: 32-pin LQFP (Pb free)
Pin compatible with ICS85310I-01
AK8181H are derived from AKM’s long-termexperienced clock device technology, and enable
clock output to perform low skew. The AK8181H is
available in a 32-pin LQFP package.
Block Diagram
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AK8181H
Pin Descriptions
Package: 32-Pin LQFP(Top View)
Pin No.
1, 9, 16,
25, 32
2
Pin Name
VDD
CLK_SEL
Pin
Type
Pullup
down
PWR
---
IN
Pull down
Description
Positive power supply
CLK Select Input (LVCMOS/LVTTL)
Pin is connected to VSS by internal resistor. (typ. 51kΩ
High: selects PCLK1p/n inputs
Low (Open): selects PCLK0p/n inputs
Non-inverting differential clock input
3
PCLK0p
IN
Pull down
Pin is connected to VSS by internal resistor. (typ. 51kΩ
*When using PCLK1 input (CLK_SEL=High), it should be
connected to VSS or opened.
Inverting differential clock input
4
PCLK0n
5
nc
IN
Pull up
---
Pin is connected to VDD by internal resistor. (typ. 51kΩ
*When using PCLK1 input (CLK_SEL=High), it should be
connected to VDD or opened.
No connect
Non-inverting differential LVPECL clock input
6
PCLK1p
IN
Pull down
Pin is connected to VSS by internal resistor. (typ. 51kΩ
*When using PCLK0 input (CLK_SEL=Low), it should be
connected to VSS or opened.
Inverting differential clock input
7
PCLK1n
IN
Pull up
8
VSS
PWR
---
Pin is connected to VDD by internal resistor. (typ. 51kΩ
*When using PCLK0 input (CLK_SEL=Low), it should be
connected to VDD or opened.
Negative power supply
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AK8181H
Pin No.
Pin Name
Pin
Type
Pullup
down
10, 11
Q9n, Q9
OUT
---
Differential clock output (LVPECL/ECL)
12, 13
Q8n, Q8
OUT
---
Differential clock output (LVPECL/ECL)
14, 15
Q7n, Q7
OUT
---
Differential clock output (LVPECL/ECL)
17, 18
Q6n Q6
OUT
---
Differential clock output (LVPECL/ECL)
19, 20
Q5n, Q5
OUT
---
Differential clock output (LVPECL/ECL)
21, 22
Q4n, Q4
OUT
---
Differential clock output (LVPECL/ECL)
23, 24
Q3n, Q3
OUT
---
Differential clock output (LVPECL/ECL)
26, 27
Q2n, Q2
OUT
---
Differential clock output (LVPECL/ECL)
28, 29
Q1n, Q1
OUT
---
Differential clock output (LVPECL/ECL)
30, 31
Q0n, Q0
OUT
---
Differential clock output (LVPECL/ECL)
Description
Ordering Information
Part Number
Marking
Shipping
Packaging
Package
Temperature
Range
AK8181H
AK8181H
Tape and Reel
32-pin LQFP
-40 to 85 °C
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AK8181H
Absolute Maximum Rating
Over operating free-air temperature range unless otherwise noted
Items
Supply voltage
Input voltage
(2)
(2)
Symbol
Ratings
Unit
VDD
-0.3 to 4.6
V
Vin
VSS-0.3 to VDD+0.3
V
IIN
±10
mA
Tstg
-55 to 150
C
Input current (any pins except supplies)
Storage temperature
(1)
Note
(1) Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any other conditions beyond those
indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rating
conditions for extended periods may affect device reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
(2) VSS=0V
ESD Sensitive Device
This device is manufactured on a CMOS process, therefore, generically susceptible to
damage by excessive static voltage. Failure to observe proper handling and
installation procedures can cause damage. AKM recommends that this device is handled with
appropriate precautions.
Recommended Operation Conditions
Parameter
Symbol
Operating temperature
Positive supply voltage
(1)
Conditions
Min
Ta
-40
VDD
2.375
Typ
3.3
Max
Unit
85
C
3.8
V
(1) Power of 3.3V requires to be supplied from a single source. A decoupling capacitor of 0.1F for power supply line should
be located close to each VDD pin.
Pin Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input Capacitance
CIN
4
pF
Input Pullup Resistor
RPU
51
kΩ
Input Pulldown Resistor
RPD
51
kΩ
Power Supply Characteristics
Parameter
Power Supply Current
Symbol
Conditions
IDD
Feb-2013
Min
Typ
Max
Unit
115
mA
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AK8181H
DC Characteristics (LVCMOS/LVTTL)
All specifications at VDD = 2.375V to 3.8V, VSS = 0V, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Input High Voltage
VIL
Input High Current
CLK_SEL
Input Low Current
TYP
MAX
Unit
2.0
VDD+0.3
V
VDD = 2.5V
1.7
VDD+0.3
V
VDD = 3.3V
-0.3
0.8
V
VDD = 2.5V
-0.3
0.7
V
150
μA
Vin = VDD = 3.8V
IIH
CLK_SEL
MIN
VDD = 3.3V
VIH
Input Low Voltage
Conditions
Vin = VSS,
IIL
μA
-5
VDD = 3.8V
DC Characteristics
All specifications at VDD = 2.375V to 3.8V, VSS = 0V, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
PCLKxp
Input High Current
PCLKxn
IIH
Conditions
MIN
MAX
Unit
Vin = VDD = 3.8V or 2.625V
150
μA
Vin = VDD = 3.8V or 2.625V
5
μA
Vin = VSS,
PCLKxp
Input Low Current
IIL
Peak-to-Peak Input Voltage
Common Mode Input Voltage
(1)
(2)
(1) (2)
-5
μA
-150
μA
VDD = 3.8V or 2.625V
Vin = VSS,
PCLKxn
VDD = 3.8V or 2.625V
TYP
VPP
0.15
1.3
V
VCMR
VSS+0.5
VDD-0.85
V
VIL should not be less than -0.3V.
Common mode voltage is defined as VIH.
DC Characteristics (LVPECL)
All specifications at VDD = 2.375V to 3.8V, VSS = 0V, Ta: -40 to +85℃, unless otherwise noted
Parameter
Output High Voltage
Output Low Voltage
Symbol
(1)
(1)
Peak-to-Peak Output Voltage Swing
(1)
Conditions
MIN
TYP
MAX
Unit
VOH
VDD-1.4
VDD-0.9
V
VOL
VDD-2.0
VDD-1.7
V
VSWING
0.6
1.0
V
Outputs terminated with 50Ω to VDD-2V.
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AK8181H
AC Characteristics
All specifications at VDD = 2.375V to 3.8V or, VSS = 0V, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Output Frequency
Propagation Delay
Output Skew
(1)
(2) (3)
Part-to-Part Skew
MIN
MAX
Unit
fOUT
700
MHz
tPD
T.B.D
ns
tsk(O)
(3) (4)
Buffer Additive Jitter, RMS
Output Rise/Fall Time
Output Duty Cycle
Conditions
(5)
TYP
30
tskPP
(5)
ps
340
tjit
155.52MHz (12kHz – 20MHz)
tr , tf
20% to 80%
DCOUT
0.045
150
47
50
ps
ps
500
ps
53
%
All parameters measured at f ≤ 700MHz unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
(1) Measured from the differential input crossing point to the differential output crossing point.
(2) Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output
differential cross points.
(3) This parameter is defined in accordance with JEDEC Standard 65.
(4) Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
(5) Design value.
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AK8181H
Figure 1 LVPECL Output Load
Figure 2 Differential Input Level
AC Test Circuit
Qxn
80%
Clock
Outputs
Qx
Qyn
80%
VSWING
20%
20%
tR
tF
Qy
tsk(o)
Figure 3 Output Skew
Figure 4 Output Rise/Fall Time
Figure 5 Part-to-Part Skew
Figure 6 Propagation Delay
Figure 7 Output Duty/ Pulse Width/ Period
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AK8181H
Function Table
The following table shows the inputs/outputs clock state configured through the control pins.
Table 1: Control Input Function Table
Inputs
Outputs
Input to Output
Polarity
High
Differential to Differential
Non Inverting
PCLK0/1p
PCLK0/1n
Q0:Q9
Q0n:Q9n
0
1
Low
1
0
0
1
High
Low
Differential to Differential
Non Inverting
Biased
(1)
Low
High
Single Ended to Differential
Non Inverting
Biased
(1)
High
Low
Single Ended to Differential
Non Inverting
Biased
(1)
0
High
Low
Single Ended to Differential
Inverting
Biased
(1)
1
Low
High
Single Ended to Differential
Inverting
(1) Please refer to the application Information section, “Wiring the Differential Input to Accept Single Ended
Levels”.
Table 2 Clock Input Function Table
Inputs
CLK_SEL
Selected Source
0
PCLK0p/n
1
PCLK1p/n
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AK8181H
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure.8 shows how the differential input can be wired to accept single ended levels. The reference
voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be
located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position
the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and
VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
Figure 8 Single Ended Signal Driving Differential Input
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AK8181H
Package Information
 Mechanical data : 32pin LQFP
Preliminary
9.00±0.20
7.00
17
25
16
32
9
7.00
0.80
8
1.35～1.45
1
0.37±0.05
0.20
M
0゜～7゜
1.60MAX
9.00±0.20
24
0.60±0.10
0.10 S
Feb-2013
0.05～0.15
0.09～0.20
S
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AK8181H
 Marking
a:
b:
c:
#1 Pin Index
Part number
Date code (7 digits)
Preliminary
(1) AKM is the brand name of AKM’ｓ IC’s.
AKM and the logo -
- are the brand of AKM’s IC’s and identify that AKM
continues to offer the best choice for high performance mixed-signal solution under
this brand.
 RoHS Compliance
All integrated circuits form Asahi Kasei Microdevices Corporation (AKM)
assembled in “lead-free” packages* are fully compliant with RoHS.
(*) RoHS compliant products from AKM are identified with “Pb free” letter indication on
product label posted on the anti-shield bag and boxes.
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AK8181H
IMPORTANT NOTICE
 These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
 Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
 Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
 AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it,
and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
 It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
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