[AK8451] AK8451 1 channel-input 16 bit 6MSPS ADC Device Outline ■AFE Block The AK8451 is a +3.3 V, Two Channel 16 Bit 6MSPS ADC which integrates on-chip Offset Adjust DAC, Gain Adjust PGA, CDS circuit and <4.5~5.7V> 3 channel LED Drivers. ■ LED Driver Block This product is the 3 channel LED driver who drives the LED of the anode common in the constant current. The current to pass for each channel can be adjusted by the external resistance and the register setting. Also, it has the control pins which turn on or off the current. Features ■AFE Block CCD I/F Number of Channels 1 channel Range 1.98 Vpp (typ.) Signal Input Range 0~3.3V @ DC Direct Coupled input mode at AVDD = 3.3 V Integrated On-chip CDS circuit Compatible with both Positive and Negative signal polarities ADC Maximum Conversion Rate 6 MSPS Resolution Black Level Correction DAC 16 Bit (Straight Binary Code) Correctable Range ± 240 mV (typ.) Resolution Gain Adjust 8 Bit Adjustable Range 0 dB ~ +13.9 dB (typ.) (1.0× ~ 4.9×) Resolution 6 Bit Total Performance ( Input ~ Video ADC ) Output Noise 5 LSBs rms (typ.) @ PGA Gain = 0 dB setting Data Output 2 bit wide or 4bit wide Power Supplies Analog part: +3.3V ±5 % / Digital Output part: +3.3V ±0.3V CPU I/F 3-Wire Serial Interface (Write Only) Clock, Data are commonly shared with A/D Data Output pins Power Dissipation 132mW (typ.) with DC Direct Coupled input mode at AVDD= 3.3V Operating Temperature Range 0 °C ~ +70 °C Package 28 Pin QFN Pin pitch: 0.4 mm, Mold size: 4 mm × 4 mm VREF Output for CCD: 1.1V±100mV。10mAmax. MS0937-E-01 2011/04 1 ASAHI KASEI ■ LED Driver Block Operation Voltage(LVDD) Absolute Maximum Voltage Operating Temperature Range LED driver current [AK8451] 4.5V~5.7V 6.5V 0 ~ 70°C RED：60mA(Adjustment external resister:20m~60mA) GREEN: (Programmable: RED-29% ; 4.17% step ) BLUE： (Programmable: RED-29% ; 4.17% step ) Usable Vf range of the LED is from 1.5V to <LVDD-0.5V>. The resistance for the current regulation is usable in 1/16W -type. The number of channels of applying an current to the LED is at the same time to one or two. When the external resistance value becomes the assumption outside, it has the protection circuit which doesn't make the electric current which flows through the □Rch Current Accuracy LED equal to or more than 150mA±30%. 53 ~ 67mA(at 60mA setting) □LED Current rise / fall time less than 10μs (10%←→90%) □LED Vf Range □Application <1.5V>(min.) ~ <LVDD-0.5V>(max.) A light source driver for CIS module of MFP MS0937-E-01 2011/04 2 ASAHI KASEI [AK8451] Block Diagram VCLP DC Connect Mode CDS Mode VCOM VRP VREFO Reference Voltage Clamp Switch CISIN0 VRN CDS S/H 16bit ADC 6M PGA RESETB 16 Output Control D0/SDCLK D1/SDATA D2 D3 6 8bit DAC LVDD 4.5~5.7V Control Registers 8 SDENB LED_R LED_G LED_B SW TG SW LEDR_EN LEDG_EN LEDB_EN SW Current B IREF Current G Current R LVDD LVSS TSMP MCLK AVDD AVSS DRVDD DRVSS Fig. 1 Block diagram MS0937-E-01 2011/04 3 ASAHI KASEI [AK8451] Pin Functions No. 1 2 Name IREF VREFO IO I O Hi-Z 3 4 CISIN0 VCLP I IO (note 2) 5 6 7 8 9 10 11 12 13 14 15 16 NC AVSS AVDD LED_R LVDD LVSS LED_G LED_B LEDR_EN LEDG_EN LEDB_EN D0/SDCLK PWR PWR O PWR PWR O O I I I IO (note 3) 17 D1/SDATA IO (note 3) 18 19 20 DRVSS DRVDD D2 PWR PWR O PD Hi-Z Hi-Z Hi-Z H or L Description LED current setting external resister pin Reference voltage output :1.1V External capacitor : 0.33μＦ Sensor Signal input Sensor Reference Level input at DC Direct Coupled mode Clamp Level output at CDS mode (external Cap.: 0.1μF) Unused(note 1) Analog ground Analog power supply LED output pin R LED power supply LED ground LED output pin G LED output pin B LED control input R LED control input G LED control input B SDENB=High ; A/D Data output : Lower Bit (D0) SDENB=Low ; Serial Interface Clock input SDENB=High ; A/D Data output : Lower Bit (D1) SDENB=Low ; Serial Interface Data input A/D Output buffer ground A/D Output buffer power supply A/D Data output : D2 Bit (note4) 21 D3 O 22 23 24 25 26 27 SDENB MCLK TSMP RESETB VCOM VRN I I I I O O H or L A/D Data output : Upper Bit (D3) (note4) Hi-Z L Serial Interface Enable Main Clock Sampling Timing Reset pin : Active Low, on chip pull-up resister : 100kΩ (typ.) Internal Reference Voltage : external capacitor 0.1μF ADC Negative Reference Voltage : external capacitor 0.1μF (note 5) 28 VRP O L ADC Positive Reference Voltage : external capacitor 0.1μF (note 5) I: input , O: output , PWR: power/ground pin (note 1)Please connect it with analog ground on the board. (note 2)It will be input on DC mode, be Hi-Z on CCD mode. (note 3)Please be input state. (note 4)It will be H or L since PD mode. (note 5)It is connect with AVSS via internal resistance. MS0937-E-01 2011/04 4 ASAHI KASEI [AK8451] Pin Allocation LEDB_EN 15 D0/SDCLK 16 D1/SDATA 17 DRVSS 18 DRVDD 19 D2 20 D3 21 SDENB 22 14 LEDG_EN MCLK 23 13 LEDR_EN TSMP 24 12 LED_B AK8451VN Top View RESETB 25 11 LED_G VCOM 26 10 LVSS VRN 27 9 LVDD VRP 28 8 LED_R 7 AVDD 6 AVSS 5 N.C. 4 VCLP 3 CISIN0 2 VREFO 1 IREF MS0937-E-01 2011/04 5 ASAHI KASEI [AK8451] Circuit Block Description Sensor Interface Part Circuit to sample & hold input signal which is fed on CISIN0 pin. Signal input range is 1.98V (typ.). There are two input modes, DC Direct Coupled Mode and CDS Mode. In DC Direct Coupled Mode, Positive polarity signal is handled. In CDS Mode, Negative polarity signal is handled. Signal Reference Voltage should be input on VCLP pin in DC Direct Coupled mode. In CDS mode, Voltage level to clamp signal is internally generated and it is output on VCLP pin. Black Level Correction Circuit Circuit to add an offset voltage to the sampled signal level. Voltage range of DAC which generates Offset is ±240 mV (typ.) and its resolution is 8 Bit. PGA Part Circuit to adjust signal amplitude, prior to AD conversion. Adjustable gain range is from 0dB to 13.9dB ( typ. ) (1.0× ~ 4.9×) and its resolution is 6 Bit. ADC Part AD conversion circuit to convert into Digital data an Analog signal after both Black level correction and Gain adjustment are made. Its resolution is 16 Bit with its maximum conversion rate of 6MSPS. Data output is in a straight Binary code. 0000h is output at Black level input ( 0Vpp input ) and FFFFh is output at White level input ( maximum input ). Output Control Part A 16 Bit-wide × 1ch ADC output data is re-arranged into 2 Bit × 8 cycle×1ch or 4Bit × 4cycle×1ch stream at this part. In Single Edge Mode operation, Data is output at the rising edge of MCLK. In Double Edge Mode operation, it is output at both rising and falling edges of MCLK. Output mode is 2bit or 4bit by single mode, only 2bit on double mode. Particulars is on P34 & P35. Reference Voltage Generator Circuit to generate internal reference voltages. Clamp Reference Voltage VCLP, internal common voltage VCOM and ADC reference voltages VRP and VRN are generated. Each reference voltage is output on respective device pins. For voltage stabilization, capacitors should be connected between respective pins and AVSS. LED Driver Part This product generates has 3 channel LED driver to drive RGB constant current. Use the ON/ OFF digital terminal to control the constant current. Serial Interface Part A 3-Wire Interface circuit to access setting-registers. SDCLK (clock) and SDATA (data) pins are shared with D0 and D1 pins of ADC Data Output. When SDENB pin is at low, D0 and D1pins function as SDCLK and SDATA input pins. In order to avoid both SDCLK and SDATA pins to become floating condition, proper pull-down resistors should be connected between D0 / SDCLK pin, D1 / SDATA pin and AVSS respectively. MS0937-E-01 2011/04 6 ASAHI KASEI [AK8451] Absolute Maximum Ratings Voltages are referenced to corresponding ground level. AVSS = DRVSS = 0V Item Symbol Min. Max. Unit Remarks Power supplies Analog power supply Output buffer power supply LEDD power supply AVDD −0.3 4.5 V DRVDD −0.3 4.5 V LVDD −0.3 6.5 V Digital Input Voltage VTD −0.3 AVDD+0.3 V Analog Input Voltage VTA −0.3 AVDD+0.3 V Storage temperature Tstg −65 150 °C Operation under a condition exceeding above limits may cause permanent damage to the device. Normal operation is not guaranteed under the above extreme conditions. Recommended Operating Conditions Voltages are referenced to corresponding ground level. AVSS = DRVSS = 0V Item Symbol Min. Typ. Max. Unit Power supplies Analog power supply Output buffer power supply LEDD power supply Operating temperature AVDD DRVDD LVDD Ta 3.135 3.0 4.5 0 3.3 3.3 5.5 3.465 3.6 5.7 70 Remarks V V °C Please power on AVDD and LVDD the same time or AVDD first. Electrical Characteristics DC characteristics (AVDD=3.135~3.465V, DRVDD=3.0~3.6V, Ta=0∼70°C, unless otherwise specified) Item Symbol Pin Min. Typ. Max. Unit Remarks H level input voltage VIH Note 1,2 0.7× V Note 4,5 AVDD L level input voltage VIL Note 1,2 0.3× V Note 4,5 AVDD H level output voltage VOH Note 3 0.7× V IOH= −2mA DRVDD L level output voltage VOL Note 3 0.3× V IOL=2mA DRVDD Input leakage current 1 IL1 Note 1,5 −10 10 μA Input leakage current 2 IL2 Note 2 −69.3 10 μA apply 0V ~ AVDD High-Z leakage current ILZ Note 4 −10 10 μA Pull-up resistor RPU Note 2 50 100 150 kΩ (Note 1) TSMP, MCLK, SDENB (Note 2) RESETB (Note 3) D0, D1 (at SDENB=High), D2, D3 (Note 4) SDATA, SDCLK (at SDENB = Low ) (Note 5) LEDR_EN, LEDG_EN, LEDB_EN MS0937-E-01 2011/04 7 ASAHI KASEI [AK8451] AFE block, Analog characteristics (AVDD=3.3V, DRVDD=3.3V, MCLK=40MHz,Single Edge Mode, Ta=25°C, Item VCOM voltage VRP voltage VRN voltage VREF voltage at current sink error at current source error Maximum signal input level Absolute gain Sampling rate Input reference level VCLP input resistence Input signal range Clamp level (VCLP voltage) Clamp resister Min. 1.4 1.9 0.9 1.0 Typ. Max. Reference voltage 1.5 1.6 2.0 2.1 1.0 1.1 1.1 1.2 +0.1 -0.1 –0.7 –1.50 1 0 10 0 1.98 Analog input 1.98 0 0.7 –0.60 0.30 6 1.1 1.5 60 AVDD 2.08 2.18 7 10 CDS advantage Unit V V V V V V Vp-p dB dB MSPS V kΩ V V kΩ -40 dB Black level correction DAC Resolution 8 bit Correctable range ±215 ±240 ±265 mV Internal offset voltage –50 50 mV PGA(Programmable Gain Amp.) circuit Resolution 6 bit Min. gain 0 dB Max. gain 13.3 13.9 14.5 dB Video ADC Resolution 16 bit DNL –16 +16 LSB INL -96 ±32 +96 LSB Noise Output noise 6 LSBrms 16 LSBrms Power Consumption Analog part 31.5. 47 mA power dissipations 35.5 52 mA 0.1 mA Digital output driver power 3 6 mA dissipation unless otherwise specified) Remarks Band Gap error @ I=10mA ( diff. @I=0mA) @ I=-10mA( diff. @I=0mA) At DC mode (Note 1) At CDS mode (Note 1) At DC mode At DC mode At DC mode （Note 2） At CDS mode At CDS mode (note 11) (Note 3) (Note 4) (Note 5) (Note 7) PGA min. PGA max. At DC mode (Note 7) At CDS mode (Note 7) At power down (Note 8) (Note 9) (Note 1) 0dB is defined at the gain where ADC output reaches its full-scale when 1.98Vpp signal is input with PGA setting at 00h. (Note 2) At 2 bit bus mode. (Note ３) CISIN0 input signal must be in this range which is referenced to AVSS. (Note 4) Monotonicity guaranteed. (Note 5) ±50 mV of the total correctable range is used for internal offset adjustment. MS0937-E-01 2011/04 8 ASAHI KASEI [AK8451] (Note 6) It defines that a boundary point of ADC output codes between 0000h and 0001h exists within ±50mV range of the offset adjustment DAC setting when 1.1V is fed on CISIN & VCLP pins in DC Direct Coupled mode, and when PGA gain is set to 0dB. (Note 7) Relative value to the gain at PGA setting is 00h. (Note 8) A full-scale minus 2 dB, 1 MHz sine-wave signal is input. (@ 4bit bus） (Note 9) A clock supply to MCLK is stopped. (Note 10) At the capacitive load is 20pF. (Note 11) Condition: Input signal frequency : 1MHz, Noise frequency : 0.1MHz, Signal : Noise = 10:1.No shipping inspection. LEDD block, Analog characteristics (AVDD=3.3V, LVDD=5.5, MCLK=40MHz, Single Edge Mode, Ta=25°C, Item LED drive current range The LED protection circuit activation current LED current (Including resistance accuracy) (RED) Min. 20 105 Typ. 150 Max. 60 195 Unit mA mA 53 60 67 mA unless otherwise specified) Remarks Å There is possibility to adjust the typical value after ES evaluation. It adjusts together with the Min./Max. value. IREF resister =4.7k±1% LED pin voltage =2.0V(Note 1) LED current Red Green Blue LED current accuracy (GREEN,BLUE) 100 105 105 95 95 LED current LED pin voltage dependence LVDD power consumption 94.8 90.7 86.5 82.3 78.2 74.0 69.8 -2.5 100 95.8 91.7 87.5 83.3 79.2 75.0 70.8 0.6 % % % 96.8 92.7 88.5 84.3 80.2 76.0 71.8 2.5 % % % % % % % % % 1.5 mA IREF resister =4.7k±1% LED pin voltage =2.0V LED pin voltage =0.5V 000 001 010 011 100 101 110 111 LED pin voltage =2.0V reference Except LED drive current (Note 1) IREF resister(kΩ) = 60 ÷ [RED LED current(mA)] × 4.7(kΩ) . And [RED LED current] can be set within the range of 20mA～60mA . (AVDD=3.135~3.465V, LVDD= 4.5~5.7 V, Ta=0∼70°C, unless otherwise specified) Item Min. Typ. Max. Unit Remarks LED pin voltage 0.5 V LED Vf 1.5 4.8 V When LVDD<5.3V case, Vf(max.)=LVDD-0.5V MS0937-E-01 2011/04 9 ASAHI KASEI [AK8451] ■ LEDD block, Switching characteristics (AVDD=3.135~3.465V, LVDD= 4.5~5.7 V, Ta=0∼70°C, unless otherwise specified) No. Item min. typ. max. Unit Condition 1 LED current rise time 10 μsec 2 LED current fall time 10 μsec 3 Reset valid setup time 0.1 μsec LEDB_EN(0.7AVDD) LEDB_EN(0.7AVDD):base position To LEDR_EN(0.3AVDD) LEDG_EN(0.3AVDD) 4 Count up setup time 0.1 μsec LEDB_EN(0.3AVDD) LEDB_EN(0.3AVDD):base position To LEDR_EN(0.7AVDD) LEDG_EN(0.7AVDD) 5 Reset invalid setup time 0.1 μsec LEDB_EN(0.3AVDD) LEDB_EN(0.3AVDD):base position To LEDR_EN(0.3AVDD) LEDG_EN(0.3AVDD) L E D R _E N L E D G _E N L E D B _E N 0.7AV D D 0.3AV D D 90% L E D R ,G ,B C urren t 10% 1 ２ - LED*_EN through mode 0.7AV D D L E D R _E N L E D G _E N 0.3AV D D 0.7AV D D 0.3AV D D 3 4 0.3AV D D 5 0.7AV D D L E D B _E N (R eset) 0.3AV D D 90% L E D R ,G ,B C urren t 10% 1 2 - Except the through mode MS0937-E-01 2011/04 10 ASAHI KASEI [AK8451] ■ AFE block, Switching characteristics No. 1 2 3 4 5 6 7 8 9 10 (AVDD=3.135~3.465V, DRVDD=3.0~3.6V, Ta=0∼70°C , unless otherwise specified) Item pin min. typ. max. unit Condition MCLK cycle time (T) MCLK 41.6 250 ns mode 1(note 2) 20.8 125 mode 2(note 2) 41.6 250 mode 3(note 2) MCLK H / L width MCLK 20.8 ns mode 1(note 2) 10.4 mode 2(note 2) 20.8 mode 3(note 2) TSMP setup time TSMP 5 ns Note 1 (referenced to MCLK↑) TSMP hold time TSMP 5 ns Note 1 (referenced to MCLK↑) Aperture delay CISIN 2 ns Data level (referenced to MCLK↑) Aperture delay CISIN 2 ns Reference level (referenced to MCLK↑) TSMP cycle TSMP 4T mode 1(note 2) (MCLK period-unit ) 8T mode 2(note 2) 4T mode 3(note 2) Data output delay D0, At load: 20pF (referenced to MCLK↑) D1,D2,D3 Drivability 2 25 ns : normal mode 2 20 ns : x2 mode Pipeline delay D0, 6 At 4bit bus (SMP period-unit ) D1,D2,D3 5 At 2bit bus Reset pulse width RESETB 50 ns Note 1) Number of MCLK rising edges during TSMP = H duration is allowed to be 1 to 3 times in Single Edge, 2bit bus Mode operation, and only a single edge is allowed in the other mode operation. Note 2) mode 1 ~ mode 3 explanation mode 1 : single edge/ 4bit bus mode mode 2 : single edge/ 2bit bus mode mode 3 : double edge/ 2bit bus mode MS0937-E-01 2011/04 11 ASAHI KASEI [AK8451] CISIN0 Sample Point 5 MCLK 0.7AVDD 0.7AVDD 0.5AVDD 0.3AVDD 1 (T) 2 2 7 0.7AVDD TSMP 0.3AVDD 4 3 4 3 SHD (Internal) Sampling timing (DC mode, AFE 1ch, Single edge, 4 bit bus mode ) CISIN0 Sample Point Sample Point 6 MCLK 5 0.7AVDD 0.7AVDD 0.5AVDD 0.3AVDD 1 (T) 2 2 7 0.7AVDD TSMP 0.3AVDD 4 3 4 3 SHD (Internal) SHR (Internal) Sampling timing (CDS mode, AFE 1ch, Single edge, 4 bit bus mode ) MS0937-E-01 2011/04 12 ASAHI KASEI [AK8451] CISIN0 Sample Point 5 MCLK 0.7AVDD 0.5AVDD 0.7AVDD 0.3AVDD 1 (T) 2 2 7 0.7AVDD TSMP 0.3AVDD 4 3 3 4 SHD (Internal) Sampling timing (DC mode, AFE 1ch, Single edge, 2 bit bus mode ) CISIN0 Sample Point Sample Point 6 MCLK 5 0.7AVDD 0.5AVDD 1 7 0.3AVDD 2 2 0.7AVDD TSMP 0.3AVDD 4 3 4 3 SHD (Internal) SHR (Internal) Sampling timing (CDS mode, AFE 1ch, Single edge, 2 bit bus mode ) MS0937-E-01 2011/04 13 ASAHI KASEI [AK8451] CISIN0 Sample Point 5 MCLK 0.7AVDD 0.7AVDD 0.5AVDD 0.3AVDD 1 (T) 2 2 7 0.7AVDD TSMP 0.3AVDD 4 3 3 4 SHD (Internal) Sampling timing (DC mode, AFE 1ch, Double edge, 2 bit bus mode ) CISIN0 Sample Point Sample Point 6 MCLK 5 0.7AVDD 0.7AVDD 0.5AVDD 0.3AVDD 1 (T) 2 2 7 0.7AVDD TSMP 0.3AVDD 4 3 4 3 SHD (Internal) SHR (Internal) Sampling timing (CDS mode, AFE 1ch, Double edge, 2 bit bus mode ) MS0937-E-01 2011/04 14 ASAHI KASEI [AK8451] M CLK 0 .7 AV D D 0 .3 AV D D D 0, D 1 0 .7 D R V D D 0 .3 D R V D D D 2, D 3 8 Data output timing ( Single edge mode ) M CLK 0 .7 A V D D 0 .3 A V D D D 0, D 1 D 2, D 3 0 .7 D R V D D 0 .3 D R V D D 8 8 Data output timing ( Double edge mode ) RESETB 0.3AVDD 0.3AVDD 10 Reset pulse width MS0937-E-01 2011/04 15 ASAHI KASEI [AK8451] n+2 n+1 n n+6 n+5 n+4 n+3 n+7 C IS IN 0 M CLK TSM P SH D (In ter n a l) D 0 ～ D 3 n -7 n -6 n -4 n -5 n -3 n -1 n -2 n Pipeline delay (AFE 1ch, Single edge, 4 bit bus mode ) n+2 n+1 n n+6 n+5 n+4 n+3 n+7 C IS IN 0 M CLK TSM P SHD (In ter n a l) n -5 D 0 ～ D 3 n -7 n -3 n -4 n -2 n -1 n N +1 Pipeline delay (AFE1ch, Single edge, 2 bit bus mode ) n+2 n+1 n n+6 n+5 n+4 n+3 n+7 C IS IN 0 M CLK TSM P SH D (In ter n a l) D 0 ～ D 3 n -7 n -5 n -4 n -3 n -2 n -1 n N +1 Pipeline delay (AFE1ch, Double edge, 2 bit bus mode ) MS0937-E-01 2011/04 16 ASAHI KASEI [AK8451] Serial interface: Switching characteristics No. 1 2 3 4 5 6 7 8 9 10 11 12 ( AVDD=3.135~3.465V, DRVDD=3.0~3.6V ,Ta= 0~70°C , unless otherwise specified) Item pin Min. Typ. Max. unit Condition Clock Period SDCLK 0.1 10 MHz Clock Pulse Width (H duration) SDCLK 40 ns Clock Pulse Width ( L duration ) SDCLK 40 ns SDENB setup time SDENB 80 ns (to SDCLK rising edge↑) SDENB hold time SDENB 80 ns (from SDCLK rising edge↑) Data High-Z delay D0, D1 0 40 ns (from SDENB falling edge↓) Data Enable delay D0, D1 0 40 ns (from SDENB rising edge↑) SDATA setup time SDATA 40 ns (to SDCLK rising edge↑) SDATA hold time SDATA 40 ns ( from SDCLK rising edge↑) SDENB SDCLK,SDENB Rise time SDCLK 6 ns SDENB SDCLK,SDENB Fall time SDCLK 6 ns SDENB SDENB High level pulse width SDENB 40 ns 12 SDENB 0.7AVDD 0.7AVDD 0.3AVDD 0.3AVDD 11 10 6 7 0.7DVDD D0 0.3DVDD 4 1 5 0.7AVDD SDCLK 0.3AVDD 6 10 3 2 11 7 0.7DVDD D1 SDATA 0.3DVDD 0.7AVDD 0.3AVDD 8 9 Serial interface timing Clock Input pin SDCLK and Data Input pin SDATA for Serial Interface are shared with A/D Data Output pins, D0 and D1 respectively. When SDENB becomes low, D0 and D1 are put into High-Z conditions and it is enabled to input SDCLK and SDATA. SDATA is captured at the rising edge of SDCLK. SDATA is 16 Bit long. Write “zeros“ first bit and from the 5th Bit to the 5th MS0937-E-01 2011/04 17 ASAHI KASEI [AK8451] Bit. 2nd~4th Bits are assigned for Register Address where the 2nd Bit is MSB and the 4th Bit is LSB. 9th~ 16th Bits are assigned for Data where the 9th Bit is MSB and the 16th Bit is LSB. 16 and more rising edges of SDCLK are required while SDENB is low, from the time to fall to the time to rise. When it is less than 16 rises, registers will not be written properly. If it is more than 16 rises while SDENB is low, from falling to rising, the last 16 edges become effective. There is a possibility that an erroneous data will be written into registers if noises occur on D0 Output / SDCLK input pin and D1 Output / SDATA input pin when these pins are at High-Z conditions. To avoid this, resistors should be connected between D0 / SDCLK pin, D1 / SDATA pin and AVSS respectively to pull-down these pins. SDENB High-Z D0 SDCLK High-Z D1 SDATA 0 A2 A1 A0 0 0 0 0 B7 B6 B5 B4 B3 B2 B1 B0 0 0 Register Write MS0937-E-01 2011/04 18 ASAHI KASEI [AK8451] - Power on reset 3.135V AVDD AVDD 100kΩ RESETB AVDD rise time max. 10ms 0.33μF RESETB AK8451 max. 100ms It becomes possible for the register writing after 100 ms. Power on reset At the power-on, Power-On-Reset must be executed by using RESETB pin. When a 0.33 uF external capacitor on RESETB pin is used, the rise time of AVDD must be shorter than 10 ms in order to assure proper Power-On-Reset operation. Maximum time from AVDD power-on to the release from Power-On-Reset is 100 ms. Registers should be written after waiting for longer than 100 ms after AVDD power-on. As electric charge is retained in the external capacitor even after AVDD is made to 0V, voltage on RESETB pin does not go to 0V immediately. If AVDD is powered-up again before RESETB pin returns to 0V, a proper Power-On-Reset operation is not made. In order to assure proper Power-On-Reset operation when to power-up AVDD again, it is required that AVDD time to be kept at 0V is longer than 300 ms. If the 300 ms AVDD time to be kept at 0V, is not obtainable, the device must be reset by applying a low pulse externally on RESETB pin. MS0937-E-01 2011/04 19 ASAHI KASEI [AK8451] -Register Map Sub Adrs Bits Default Register Function 0H 7 6 5 4 3:2 1 0 7:0 Value 0******* *0****** **0***** ***0**** ****00** ******0* *******0 10000000 Name RST Reserved 1 OUT_DR MD_CCD TMG_SHR MD_DBLEGG NPD DAC0 Register reset Reserved 1 Output buffer drivability Input mode, CDS mode / DC mode Reference level sampling timing Clock mode select Power down mode Offset DAC0 setting 5:0 7:6 5:3 2 1 0 7:0 **000000 00****** **000*** *****0** ******0* *******0 ******** PGA0 LEDSPEED SHDSET OUT_BS OEN TEST_O Reserved 2 PGA0 Gain setting TSMP frequency selection SHD timing setting Output bus select Output buffer enable Output order select Reserved 2 5:0 6 5:3 2:0 7:6 3:2 1:0 ******** *0****** **000*** *****000 00****** ****00** ******00 Reserved 3 HALF G_CURRENT B_CURRENT A_CONT TGMODE TGCSEL Reserved 3 LED current half mode G current setting B current setting Lower address access control TGMODE register TGCSEL register 1H 2H 3H 4H 5H 6H 7H MS0937-E-01 2011/04 20 ASAHI KASEI [AK8451] Operation mode setting register 1 RST：D7 (Address “0000”, Reset “0000 0000”） Register reset 0 Register reset (At reset) 1 release from Reset When this bit is set to “1“, all other registers are set to initial values, except for this bit. When this bit is “1“, write operation into all other registers except for this bit is ignored. Reserved 1：D6 0 Normal mode 1 Prohibited OUT_DR：D5 Output Buffer Drivability 0 Normal ( at reset ) 1 2× ( Double ) When Output Buffer Drivability is set to “2ד, maximum output current of the output buffers increases. This selection is used when the Data Output Delay which is referenced to Data Capture clock becomes too large, due to capacitive loading. MD_CCD：D4 Input mode 0 DC Direct-Coupled mode 1 CDS mode Signal Polarity which can be processed by the AK8451 is determined by the type of Input Modes. In DC Direct-Coupled Mode, it handles Positive polarity (signal is output toward higher voltage than reference level: VCLP ) and in CDS Mode, it handles Negative polarity (signal is output toward lower voltage than reference level). MS0937-E-01 2011/04 21 ASAHI KASEI [AK8451] TMG_SHR:D[3:2] Feed-Through Level Sampling Pulse (SHR) Position 00 2×MCLK(1×) delay from the Data Level Sampling position 01 3×MCLK(1.5×) delay from the Data Level Sampling position 10 4×MCLK(2×) delay from the Data Level Sampling position 11 5×MCLK(2.5×) delay from the Data Level Sampling position Note ) In the brackets (value), it is the value when the operation frequency= 4×MCLK. CISIN0 MCLK Data Level Sampling TSMP SHD (Internal) R0B3~B2= 00b Reference Level Sampling 01b SHR (Internal) 10b 11b AFE 1ch/ Single edge/ 4 bit bus mode input output timing MS0937-E-01 2011/04 22 ASAHI KASEI [AK8451] CISIN0 MCLK Data Level Sampling TSMP SHD (Internal) R0B3~B2= 00b Reference Level Sampling 01b SHR (Internal) 10b 11b AFE 1ch/ Single edge/ 2 bit bus mode input output timing CISIN0 MCLK Data Level Sampling TSMP SHD (Internal) R0B3~B2= 00b Reference Level Sampling 01b SHR (Internal) 10b 11b AFE 1ch/ Double edge/ 2 bit bus mode input output timing MS0937-E-01 2011/04 23 ASAHI KASEI [AK8451] MD_DBLEGG：D1 Clock mode select 0 Single edge mode 1 Double edge mode NPD：D0 Power Down Setting 0 Power Down 1 Normal In the power down, regardless of the condition of SDENB, the logic of the following pin is as follows. D0/SDCLK Input D1/SDATA Input D2 H or L; Fixed level (High or Low depends on the previous condition.) D3 H or L; Fixed level (High or Low depends on the previous condition.) The table of each setting Clock mode Single edge Double edge Output bus sel. Compatible / not 4 bit bus ○ ○ × ○ 2 bit bus 4 bit bus 2 bit bus MS0937-E-01 2011/04 24 ASAHI KASEI [AK8451] Offset DAC0 data setting (Address “0001”, reset “1000 0000”） register DAC output 00000000 -240.0mV 00000001 -238.1mV 00000010 ・ -236.2mV ・ ・ ・ 01111110 -3.8mV 01111111 -1.9 mV 10000000 0 mV 10000001 +1.9mV 10000010 ・ +3.8mV ・ ・ ・ 11111101 +234.4mV 11111110 +236.3mV 11111111 +238.1mV ; x is setting value Offset(x) = −240 + 480 / 256 × x[mV] @ reset x=128, Offset(128)=0mV Offset DAC setting FFh 80h 00h S/H CIS signal Black Max. Min. PGA Cal. After black cal. level S/H output level ADC Output code The change of the level by the offset setting (DC direct mode = pos. polarity ) CDS Black cal. PGA 00h 80h FFh Offset DAC setting CIS signal(CCD type) CDS output level After black cal. level ADC Min. Max. Output code The change of the level by the offset setting (CDS mode = neg. polarity ) MS0937-E-01 2011/04 25 ASAHI KASEI ( address “0010”, reset “xx00 0000”） Gain(x) = Gain [ times ] 000000 1.000 000001 1.015 000010 1.029 000011 1.042 : : : : 111100 4.168 111101 4.400 111110 4.659 111111 4.950 1.98 80 × [times] 2.0 16 + (63 − x) ; x is setting value x=0, Gain(0)=1.003 times gain[times] @ reset register 5 0.5 4 0.4 3 0.3 2 0.2 1 0.1 0 gain step [times] PGA0 gain setting [AK8451] gain[times] step[times] 0 0 16 32 48 setting value [DEC] 64 gain curve (theoretical figure) ** The definition with the above PGA gain is the value of PGA simple substance. In DC direct mode, ( the positive-polarity ) is gained < PGA gain's being duple > after offset adjustment in the voltage of the difference between the reference voltage which is inputted to the VCLP terminal and the signal level ( the part of SHD ). In CDS mode , ( the negative electrode ), the voltage of the difference between the reference level ( the part of SHR ) and the signal level ( the part of SHD ) is gained absolute gain duple(-0.6dB typ.) and it is < PGA gain's being duple > after offset adjustment. MS0937-E-01 2011/04 26 ASAHI KASEI Operation setting 2 LEDSPEED：D[7:6] [AK8451] ( address “0011”, reset “0000 0000”) TSMP frequency select for adjust LED timing ００ LED timing frequency diving ratio = 1 (1MHz <=TSMP frequency < 2MHz) ０１ LED timing frequency diving ratio = 1/2 (2MHz <=TSMP frequency < 4.4MHz) １０ LED timing frequency diving ratio = 1/4 (TSMP frequency >=4MHz) １１ Inhibition LED current LED*_EN Internal EN signal MCLK TSMP ** By ００ setting LED＊_EN OFF to ON timing（Single edge mode/２ bit output） LED current LED*_EN Internal EN signal MCLK TSMP ** By ００ setting LED＊_EN ON to OFF（Single edge mode/２ bit output） MS0937-E-01 2011/04 27 ASAHI KASEI [AK8451] LED current LED*_EN Internal EN signal MCLK TSMP ** By 01 setting LED＊_EN OFF to ON （Single edge mode/２ bit output） LED current LED*_EN Internal EN signal MCLK TSMP ** By ０１ setting LED＊_EN ON to OFF（Single edge mode/２ bit output） LED current LED*_EN Internal EN signal MCLK TSMP ** By １０ setting LED＊_EN OFF to ON（Single edge mode/２ bit output） MS0937-E-01 2011/04 28 ASAHI KASEI [AK8451] LED current LED*_EN Internal EN signal MCLK TSMP ** By １０ setting LED＊_EN ON to OFF（Single edge mode/２ bit output） SHDSET：D[5:3] SHD timing 000 It is delayed for 7(3.5) clocks than a data sampling position. 001 It is delayed for 6(3) clocks than a data sampling position. 010 It is delayed for 5(2.5) clocks than a data sampling position. 011 It is delayed for 4(2) clocks than a data sampling position. 1XX SHD ( input clock) = TSMP CISIN0 MCLK TSMP SHD 000b (Internal) 001b 010b 011b 1xxb AFE1ch / single edge mode / 4 bit bus mode IO timing MS0937-E-01 2011/04 29 ASAHI KASEI [AK8451] CISIN0 MCLK Data Level Sampling TSMP SHD (Internal) 000b 001b 010b 011b 1XXb AFE1ch / single edge / 2 bit bus mode IO timing CISIN0 MCLK TSMP SHD 000b (Internal) 001b 010b 011b 1xxb AFE1ch / double edge / 2 bit bus mode IO timing MS0937-E-01 2011/04 30 ASAHI KASEI [AK8451] OUT_BS：D2 Output bus size mode 0 2 bit bus mode 1 4 bit bus mode The table of each setting Clock mode Single edge Double edge Output bus sel. Compatible / not 4 bit bus ○ ○ × ○ 2 bit bus 4 bit bus 2 bit bus MS0937-E-01 2011/04 31 ASAHI KASEI [AK8451] CISIN0 MCLK TSMP D3 D7 D3 D15 D11 D7 D3 D15 D11 D7 D3 D15 D2 D6 D2 D14 D10 D6 D2 D14 D10 D6 D2 D14 D1 D5 D1 D13 D9 D5 D1 D13 D9 D5 D1 D13 D0 D4 D0 D12 D8 D4 D0 D12 D8 D4 D0 D12 AFE1ch / single edge / 4 bit bus mode IO timing CISIN0 MCLK TSMP D3 D2 D1 D5 D3 D1 D15 D13 D11 D9 D7 D5 D3 D1 D15 D13 D11 D9 D7 D5 D3 D1 D15 D13 D0 D4 D2 D0 D14 D12 D10 D8 D6 D4 D2 D0 D14 D12 D10 D8 D6 D4 D2 D0 D14 D12 AFE1ch / single edge / 2 bit bus mode IO timing MS0937-E-01 2011/04 32 ASAHI KASEI [AK8451] CISIN0 MCLK TSMP D3 D2 D1 D5 D3 D1 D15 D13 D11 D9 D7 D5 D3 D1 D15 D13 D11 D9 D7 D5 D3 D1 D15 D13 D0 D4 D2 D0 D14 D12 D10 D8 D6 D4 D2 D0 D14 D12 D10 D8 D6 D4 D2 D0 D14 D12 AFE1ch / double edge / 2 bit bus mode IO timing OEN：D1 Output buffer enable 0 enable 1 Hi-z MS0937-E-01 2011/04 33 ASAHI KASEI [AK8451] TEST_O：D0 Output order select 0 Pattern 0 1 Pattern 1 AFE1ch / single edge / 4 bit bus mode format M CLK TSM P P attern 0 D 1(D 3) D 0(D 2) D 1(D 3) D 0(D 2) D 15 D 11 D7 D3 D 14 D 10 D6 D2 D 13 D9 D5 D1 D 12 D8 D4 D0 P attern 1 Proh ibited AFE1ch / single edge / 2 bit bus mode CISIN0 MCLK Data Level Sampling TSMP SHD (Internal) 000b 001b 010b 011b 1XXb MS0937-E-01 2011/04 34 ASAHI KASEI [AK8451] AFE1ch / double edge / 2 bit bus mode format MCLK TSMP Pattern 0 D1 D0 D15 D13 D11 D9 D7 D5 D3 D1 D14 D12 D10 D8 D6 D4 D2 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Pattern 1 D1 D0 MS0937-E-01 2011/04 35 ASAHI KASEI LED setting 1 [AK8451] ( address “0110”, reset “X0000000” ) HALF:D6 LED current half mode 0 Normal mode 1 The LED output current value becomes 1/2. G_CURRENT： Green current setting D[5:3] [%] This value is a ratio with the red LED. 000 100 001 95.8 010 91.7 011 87.5 100 83.3 101 79.2 110 75 111 70.8 B_CURRENT： Blue current setting D[2:0] [%] This value is a ratio with the red LED. 000 100 001 95.8 010 91.7 011 87.5 100 83.3 101 79.2 110 75 111 70.8 MS0937-E-01 2011/04 36 ASAHI KASEI LED setting 2 [AK8451] ( address “0111”, reset “00XX 0000”） A_CONT：D[7:6] Lower address (00H ~ 06H) access control 00 Access enable ( Normal Operation ） 01 Access disable 10 Access disable 11 Access disable It becomes impossible in writing a thing except "00" in D:[7:6] to write notes in lower-address (00H-06H). Write "00" in D:[7:6] and use to be general. MS0937-E-01 2011/04 37 ASAHI KASEI TGMODE：D[3:2] [AK8451] Operation 00 LED*_EN through mode 01 <TG mode a> LEDR_EN：RÆoffÆGÆoffÆBÆoff : LED switch order LEDG_EN：GÆoffÆBÆoffÆRÆoff : LED switch order LEDB_EN：LED counter reset 10 <TG mode b> LEDR_EN：GÆoff ÆBÆoff ÆRÆoff LEDG_EN：BÆoffÆRÆoffÆGÆoff : LED switch order : LED switch order LEDB_EN：LED counter reset 11 <TG mode c> LEDR_EN：BÆoff ÆRÆoff ÆGÆoff LEDG_EN：RÆoffÆGÆoffÆBÆoff : LED switch order : LED switch order LEDB_EN：LED counter reset At LED*_EN through mode function LEDR EN LEDG EN L E D B _E N LEDR R on LEDG R on G on LEDB At TG mode function B on B on ( Following figure is example of TGMODE =01 setting ) LEDR EN LEDG EN LEDB_EN LEDR LEDG LEDB Ron Gon Ron Gon Bon Ron Gon Reset Ron Gon Bon MS0937-E-01 2011/04 38 ASAHI KASEI TGCSEL：D[1:0] [AK8451] Operation 00 When TGMODE≠”00” ; The LED repeats on/off of 3 color in turn. 01 When TGMODE≠”00” ; The LED repeats on/off, that the first only 2 color is alternate. 10 When TGMODE≠”00” ; Only the first color LED repeats on/off. 11 Prohibited TGMODE =01 setting example TGCSEL= 00 LEDR EN LEDG EN L E D B _E N LEDR LEDG R on G on LEDB R on R on G on B on G on G on B on B on TGCSEL = 01 LEDR EN LEDG EN L E D B _E N LEDR LEDG R on G on LEDB R on R on G on G on G on G on B on B on TGCSEL = 10 LEDR EN LEDG EN L E D B _E N LEDR LEDG R on G on R on G on R on R on G on G on R on G on LEDB MS0937-E-01 2011/04 39 ASAHI KASEI [AK8451] External circuit example DRVDD:3.3V 0.1μF min.10 kΩ min.10 kΩ 15 SDENB LEDB_EN 16 D1 D0 17 18 DRVSS 19 DRVDD 20 D2 D3 21 22 14 LEDG_EN 23 13 MCLK LEDR_EN 24 0.1μF 12 AK8451VN TSMP 0.33μF LED_B Top View 25 11 RESETB LED_G 26 10 VCOM 0.1μF 27 0.1μF 28 LVDD: 5.5V LVSS 9 VRN LVDD 8 LED_R AVDD:3.3V 7 AVDD 6 5 AVSS N.C. 4 VCLP 3 2 CISIN0 VREFO 1 IREF VRP 4.7kΩ 0.1μF 0.33μF 0.1μF Reference Voltage DC direct mode DRVDD:3.3V 0.1μF min.10 kΩ min.10 kΩ 15 SDENB LEDB_EN 16 D0 D1 17 DRVSS 18 DRVDD 19 20 D2 D3 21 22 14 LEDG_EN 23 13 MCLK LEDR_EN 24 0.1μF 0.1μF LED_B Top View 25 11 RESETB LED_G 26 10 VCOM LVSS 27 9 VRN 8 LED_R 7 0.1μF 0.1μF AVDD 4.7kΩ 6 5 AVSS N.C. 4 VCLP 3 2 1 IREF VRP CISIN0 28 LVDD VREFO 0.1μF 12 AK8451VN TSMP 0.33μF LVDD: 5.5V AVDD:3.3V 0.1μF 0.33μF CDS mode * The radiation PAD on the package solder side connect with analog ground (AVSS). MS0937-E-01 2011/04 40 ASAHI KASEI [AK8451] Package Package dimension unit [mm] 4.0±0.1 2.8 15 21 14 22 8 28 7 B 1 0.4±0.05 2.0 2.8 4.0±0.1 A C0.2 2.0 0.2±0.05 0.4 +0.022 0.778 - 0.023 0.2 S Marking 1. Marketing code :8451 2. Date code :XXX Week code :Y The company management code 8451 XXXY Marking MS0937-E-01 2011/04 41 ASAHI KASEI [AK8451] IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. MS0937-E-01 2011/04 42