AKM AP1601

［AP1601］
AP1601
LED light control IC, dimmer compatible
DESCRIPTION
The AP1601 is a control IC which is suitable for LED lighting applications to supply a current to LEDs from an AC
power source. The AP1601 can be configured as a DCM isolated flyback circuit or as a CCM non-isolated step
down chopper circuit (Buck converter). Also, LED lighting applications for a phase control dimmer (hereinafter
called TRIAC dimmer) can be constructed with fewer external components on the application board.
Many functions for LED lighting applications are integrated into the AP1610 such as: 30V pre-driver, TRIAC
dimmer control circuit, constant current circuit using the auxiliary winding of the transformer, noise reduction
circuit during DCM operation and various protection functions.
The AP1601A also has an independent analog dimming pin and a PWM dimming pin for non-TRIAC dimming
systems, providing a low cost LED application with a wide range of dimming configurations.
FEATURES






LED driver with reduced external component count.
 Constant current control using auxiliary winding of transformer. (no photo-coupler is
required)
Rectified AC voltage up to 275V can be applied for start-up / Start up by rectified AC voltage up
to 275V.
Current control functions
 DCM flyback: Control with switching frequency changed by peak current on primary side and
forward voltage of LEDs.
 CCM chopper (Buck): Control with off-time changed by peak current on primary side and
forward voltage of LEDs.
 Analog dimming by external DC input. (Current peak control)
 PWM dimming by external pulse input.
TRIAC dimmer compatible, Built in current supply circuit
Protection circuits
 LED open protection.
 Over current protection when transformer is shorted.
 Under voltage lockout. (UVLO)
 Thermal protection.
Package
 14pin SOP.
APPLICATION

MS 1454-E-01
Indoor LED lights up to 40W maximum
 LED down light.
 LED bracket.
 LED ceiling light.
1
2012/08
［AP1601］
BLOCK DIAGRAM
HV
2.8uA
VDD
REF
Depletion
MOSFET
5V
Regulator
BLEED
BLEEDER
OUT
SWVDD
RESET
1.2V
2uA
LD
S
+
Driver
SEL
UVLO
R
S
2.5V
OVP
Q
Driver
Q
100kΩ
R
CLK
TSD
OCP
LEB
ZCD
x5
CS
HOLD
2MΩ
VFC
OSC
PW M
GND
Figure 1. AP1601 Block diagram
Block
BLEEDER
5V Regulator
SWVDD
RESET
UVLO
OVP
Driver
TSD
OCP
CLK
ZCD
HOLD
LEB
MS 1454-E-01
Description
By monitoring the BLEED pin voltage and SWVDD condition, a bleed from HV
pin or VDD charge ON/OFF is controlled.
5V for internal circuits is generated from VDD pin.
By monitoring VDD pin voltage and if VDD voltage is deficient, a signal to
BLEEDER is output.
By monitoring 5V regulator startup condition, malfunction of internal circuits
using 5V is prevented.
By monitoring VDD pin voltage, Driver output is held to GND level and 5V
regulator is inactivated so that malfunction at low voltage is prevented.
Over voltage detection circuit on VDD pin.
Driver for external N type MOSFET.
Overheat detection circuit.
Over current detection circuit for external MOSFET.
Internal clock / Off-time generation circuit.
Bottom voltage detection circuit.
By sampling the auxiliary winding voltage, which is proportional to the Vf of the
LEDs, a internal voltage is generated, which compensates for the CLK frequency
on DCM or the off-time on CCM.
Leading edge blank circuit
2
2012/08
［AP1601］
PIN CONFIGURATION/DESCRIPTION
LD 1
14 OSC
PWM 2
13 VFC
GND 3
12 SEL
REF 4
11 CS
BLEED 5
10 GND
NC 6
9 OUT
HV 7
8 VDD
Figure 2. Pin Configuration of AP1601
No.
Description
Analog dimming signal input pin
1
LD
I
Built in pull-up circuit (pulled by 2uA(typ) current source)
PWM dimming signal input pin
2
PWM
I
Built in pull-down resistor (2MΩ(typ))
IC ground pin
3,10
GND
PWR
This pin is connected to the frame for heat transfer.
Internal regulator output pin
4
REF
O
For stability, please connect a capacitor of 0.1uF.
Threshold set pin of the current source for TRIAC dimmer.
While VBLEED pin voltage is less than (1.2V(typ)), a signal is sent to the
5
BLEED
I
internal control circuit.
Built in pull-up circuit. (pulled by 2.8uA(typ) current source)
NC pin
6
NC
Please do not connect to any pins. This pin is open.
Current source pin for TRIAC dimmer.
Provide a current to GND to prevent malfunction of TRIAC dimmer operation.
7
HV
I
During start up and when the external power supplied to VDD is deficient,
the power supplied to the VDD pin has priority over the BLEED control
signal.
IC power input pin.
8
VDD
PWR
For voltage stability, please connect a capacitor from 1uF to 10uF.
Gate drive pin for external MOSFET.
9
OUT
O
1nF capacitor can be charged in 50ns(typ).
Built in pull down resistor (100kΩ(typ)).
External MOSFET current detection pin.
11
CS
I
Peak current is set connecting resistor between the source pin and GND.
This pin also detects over current.
12
SEL
I
Fixed frequency mode / Fixed off-time mode switch pin.
Switching frequency/ Off-time compensation input pin.
13
VFC
I
This pin also detects bottom voltage (when SEL=REF)
Switching frequency / Off-time set pin
14
OSC
O
Resistor should be connected to GND (details are described later)
* (I/O) I: Input pin, O: Output pin, PWR: Power pin, -: N/A
MS 1454-E-01
Pin
I/O
3
2012/08
［AP1601］
ABSOLUTE MAXIMUM RATINGS
Ta=25C unless otherwise specified.
Parameter
HV (*1)
VDD (*1)
BLEED, OUT (*1,*2)
REF (*1)
CS, PWM, LD, OSC, VFC, SEL (*1,*3)
Junction Temperature
Storage Temperature
Power Dissipation (*4)
Symbol
VHV_max
VDD_max
VMV_max
VREF_max
VLV_max
Tj
Tstg
PD
Min.
-0.3
-0.3
-0.3
-0.3
-0.3
-40
-55
Max.
450
30
VDD_max+0.3
6.0
VREF_max+0.3
125
150
1.5
Unit
V
V
V
V
V
C
C
W
Note:
*1 All voltages refer to GND pin (GND) as zero (reference) voltage.
*2 If VDD_max exceeds 29.7V, the maximum value is limited to 30V.
*3 If VREF_max exceeds 5.7V, the maximum value is limited to 6V.
*4 25.4mm×25.4mm×1.6 mm FR4 board, 50% GND copper area, Ta=25C. PD must be decreased at the rate of
15mW/C for operation above 25C
The maximum ratings are the absolute limitation values with the possibility of damaging the IC.
When the operation exceeds these standards the specifications cannot be guaranteed.
RECOMMENDED OPERATING CONDITION
Parameter
Operating Voltage Range (*5,*6)
HV Voltage (*5)
BLEED, CS, PWM, LD, OSC, VFC, SEL(*5)
Operating Temperature Range (*7)
Symbol
VDD
VHV
Ta
Min.
10
GND
-40
Typ.
Max.
20
400
VREF
105
Unit
V
V
V
°C
*5 All voltages refer to GND pin (GND) as zero (reference) voltage.
*6 VDD is applied after UVLO is released. (UVLOH：17.6V(typ))
*7 In high power applications or low thermal conductivity of the application board or if both are true, the
maximum ambient temperature value needs to be lowered not to exceed maximum Tj value.
MS 1454-E-01
4
2012/08
［AP1601］
ELECTRICAL CHARACTERISTICS
Ta=25C, HV=open, VDD=15V, REF=0.1uF, PWM=VREF, SEL=GND, R15=200kΩ, VFC=VREF unless otherwise
specified.
VDD is applied after UVLO is released, which is after the HV voltage (18V typical) is applied.
1. Supply Current
Parameter
Supply Current
Specification
TYP
MAX
IDD1
2.0
3.0
mA
IDD2
1.4
2.1
mA
Specification
TYP
MAX
Symbol
MIN
Unit
Note
PWM=VREF CS=0.6V
OUT=No Load
(*8)
PWM=0V (*8)
2. Control circuits
Parameter
Symbol
MIN
Unit
Note
Operating mode
SEL voltage H
VSELH
SEL voltage L
Current control
CS pin control voltage
Leading edge blank
VSELL
4.5
V
V
525
450
mV
ns
2.65
V
0.5
V
V
V
VPEAK
TLEB
475
200
VLD
0.3
VLD2
VPWMH
VPWML
3.0
1.5
Switching frequency 1
FOP1
95
100
105
kHz
Switching frequency 2
FOP2
135
150
165
kHz
Switching frequency 3
FOP3
40
50
60
kHz
Off-time
TOSC
9
10
11
us
VTHZC
0.05
0.1
0.15
V
SEL=VREF (DCM)
VOUTH
VOUTL
Tr
Tf
VDD-0.3
VDD-0.18
VDD-0.05
0.05
0.12
50
50
0.2
100
100
V
V
ns
ns
IOUT= -10mA (*8)
IOUT= 10mA (*8)
OUT load:1000pF
OUT load:1000pF
1.0
1.2
1.4
V
BLEED pin
450
900
710
1350
Ω
Ω
IHV=20mA (*8)
IHV=10mA, Tj=125 (*8)
LD pin input voltage
PWM voltage H
PWM voltage L
VFC zero cross detection
voltage
Gate drive
OUT pin output voltage H
OUT pin output voltage L
Rising time
Falling time
TRIAC dimmer current source
Current source threshold
VBLEED
voltage
Resistor 1 (HV-GND)
Resistor 2 (HV-GND)
MS 1454-E-01
500
300
0.5
Fixed frequency mode,
Bottom voltage detection
(DCM)
Fixed off-time mode(CCM)
RONH1
RONH2
5
LD=VREF
PWM=VREF, CS=0.6V
LD pin input voltage range
while analog dimming
Analog dimming unused
Switching operation
Cease switching
R15=100kΩ, VVFC=1V,
SEL=VREF (DCM)
R15=100kΩ, VVFC=1.5V,
SEL=VREF (DCM)
R15=100kΩ, VVFC=0.5V,
SEL=VREF (DCM)
R15=100kΩ, VVFC=1V,
SEL=GND (CCM)
2012/08
［AP1601］
ELECTRICAL CHARACTERISTICS (the rest)
Ta=25C, HV=open, VDD=15V, REF=0.1uF, PWM=VREF, SEL=GND, R15=200kΩ, VFC=VREF unless otherwise
specified.
VDD is applied after UVLO is released, which is after the HV voltage (18V typical) is applied.
Parameter
Startup circuit
Operating startup voltage
Operating shutoff voltage
Startup current source
threshold voltage 1
Startup current source
threshold voltage 2
Startup current
Internal regulator
REF voltage
REF dropout voltage
Protection circuits
Thermal protection
Thermal protection
release temperature
MIN
Specification
TYP
MAX
UVLOH
UVLOL
15.5
5.6
17.6
6.4
19.8
7.2
V
V
VDD voltage rising
VDD voltage falling
VDDH
9.1
10.3
11.6
V
VDD voltage rising
VDDL
7.8
8.8
9.9
V
VDD voltage falling
IDDCH
-12
-8.5
-5.0
mA
VHV=100V, VDD=6.5V(*8)
VREF
VDROP
4.9
5.0
20
5.1
100
V
mV
REF current: 0mA(*8)
REF current: -7mA(*8)
TSD
130
150
170
C
Design Assurance Value
ΔTSD
29
65
101
C
Design Assurance Value
Symbol
Unit
CS over current detection
OCP
720
800
880
mV
VDD over voltage
OVP
23
26
29
V
detection
Note:
*8 Current definition: Flow to the pin is plus, flow out from the pin is minus.
MS 1454-E-01
6
Note
LATCH off
LATCH off
2012/08
［AP1601］
OPERATION
1) Operation outline
The AP1601 operates directly from a rectified AC voltage supply (100~240V). It has 2 selectable operating
modes, a DCM flyback type and a CCM chopper type (buck) constant current driver. Switching frequency, set by
an external resistor, can be automatically adjusted depending upon the LED Vf value. The LED current variation
related to the LED Vf variation will be minimized.
Furthermore, the LED current is controlled constant on chopper type (buck) even when the input voltage varies.
Dimming can be done using a peak current control method, a PWM pulse current control method, or switching
frequency adjustment independently or in combination.
(In the following description, the symbols and numbers on the external parts refer to Figure 22. A typical isolated
flyback application circuit for TRIAC dimming is shown later)
2) Operation
2-1) Operation mode
The AP1601 can select from 2 different operation modes. The mode is determined by the voltage of the SEL pin.
SEL pin
voltage
VREF
Operation mode
Fixed frequency mode
Fixed off-time mode
GND
External MOSFET control
OUT pin H→L
OUT pin L→H
The OUT pin is switched from H After rising of the internal CLK signal
to L by detecting peak voltage on determined by the OSC pin voltage: if
the CS pin
the VFC pin voltage becomes lower
than the bottom voltage detection
level (<VTHZC), the OUT pin is
switched from L to H.
The OUT pin is switched from H After passage of the off-time
to L by detecting peak voltage on determined by OSC pin voltage, the
the CS pin
OUT pin is switched from L to H.
The fixed frequency mode is suitable for the discontinuous current conduction mode in the flyback circuit shown
in Figure 3. On the other hand, the fixed off-time mode is suitable for the continuous current conduction mode in
the chopper circuit (buck) shown in Figure 4. Please refer to the application examples of Figure 22 and Figure 23
for the complete circuits.
Q1 On state current route
VPeak
Q1 Off state current route
CS
T1 D5
Lp Current
Vin
R4
C4
Lp
D3
R12
R11
Ls Current
Ls
ILp_Peak
C6 +
VF
Lp, Ls Current
R14
D2
D5 Current
LED Current
Lb
U1
VFC
VF
0
OUT
Ls Voltage
Q1
-Vin/N
VFC
CS
R13
CLK(Internal)
ZCDInternal)
OSC
REF
SEL
ton toff
R15
OUT
Figure 3 Operation of flyback circuit on fixed frequency mode
MS 1454-E-01
7
2012/08
［AP1601］
VP e a k
Q 1 O n s t a t e c u r r e n t r o u t eCS
IL p _ P e a k
Vin
Q 1 O f f s t a t e c u r r e nD5
t route
Lp C urrent
VF
R12
R11
LE D C urrent
T1
C8
D2
U1
VFC
Lp
Lb
VF
0
OUT
Q1
Lp Voltage
Vin - VF
VFC
CS
Of f
Time
R13
C L K ( Int e r na l)
OSC
SEL
Re s e t C L K ( Int e r na l)
ton
R15
toff
OUT
Figure 4 Operation of chopper circuit (buck) on fixed off-time mode
2-2) Current control
The external N channel MOSFET of the AP1601 moves into off-state by detecting the peak current and by using
the internal clock (CLK) determined by the VFC voltage (*1) and resistor R15 between the OSC and GND, the
MOSFET migrates into on-state (*2). By repeating this PWM switching behavior, the LED current is controlled.
The LED current, which is affected by LED forward voltage variation or fluctuation of an external cause, will be
compensated to keep it constant by the VFC pin monitoring the auxiliary winding voltage on the transformer and
automatically adjusting the internal clock (CLK) cycle.
Note:
*1 It indicates the sampling voltage (VVFC) of the VFC voltage after 700ns (design value) after the OUT pin is
turned to VOUTL level.
*2 In the fixed frequency mode, it migrates into an on-state waiting for the VFC voltage to become lower than
VTHZC (0.1V(typ)) after the rising CLK.
2-2-1) Fixed frequency mode
The AP1601 LED current on the flyback circuit is set by the self-inductance of the transformer’s (T1) primary
winding peak current and switching frequency (Fsw). The ratio between the primary winding and the secondary
winding (0.2 Nps 1) of the transformer is obtained from the switching frequency requirement.
Approximation of LED average current ILED_ave is;
1 L p  I Lp _ peak  Fsw
I LED _ ave    
2
VF  VFD 5
2
Here, η is the energy transmission efficiency of the transformer T1 from the primary winding to the secondary
winding (η=0.85～0.95), VF is the total of the LED forward voltage connected in series, VFD5 is the diode forward
voltage.
Peak current is set by resistor R13 connected between the Q1 source and GND, switching frequency is set by
resistor R15 described before and the VVFC voltage. However, there is an upper limit of the switching frequency
on DCM flyback operation.
Even if the Internal CLK signal is set higher, it is limited to the switching frequency upper limit.
Figure 5 is showing a wave form image on DCM flyback operation of OUT pin voltage, Q1 drain-source voltage
(VDS), transformer primary side current (ILP) and transformer secondary side current (ILs).
MS 1454-E-01
8
2012/08
［AP1601］
OU T
tON
tO
( A )t O
F F 1
F F 2
Ts
(B)
(C )
VDS
tON
ON
OFF
OUT
D5
ILp
V
L
ILp
ILs
ILs
in
tOFF1
OFF
ON
tOFF2
OFF
OFF
0
0
 t
p
0
I Lp _ Peak
N

VF  VFD5
t
LS
0
Figure 5. DCM flyback mode wave form
The AP1601 fixed frequency mode is using the T1 auxiliary winding, waiting until the Q1 drain voltage falls off
after the secondary current becomes zero, then moves to the next cycle. Approximations of “tON, tOFF1” time
requirement in Figure 5 are;
tON 
tOFF 1 
I LP _ Peak
N

Lp
Vin
 I LP _ Peak
LS
LP

 I LP _ Peak  N
VF  VFD 5 VF  VFD 5
Next, the tOFF2 period is the time for compensation to the LED VF variation. By detecting the bottom voltage using
the VTHZC threshold, tOFF2 (for example) is defined by (B) or (C) if each switching is observed. However, the
internal CLK operates at a constant cycle while VVF is maintained constant, and tOFF2 will be an ideal period if
averaged for a sufficiently long time (e.g., 10ms for 100kHz switching frequency).
The shortest amount of the tOFF2 time is between (A) and (B) shown in Figure 5. This is the reason why the drain
voltage doesn’t fall off immediately due to resonance caused by the primary side inductance (Lp) of the
transformer and a parasitic capacitor (Clump) between Q1 drain and GND.
Approximation of tOFF2’s minimum time is as follows.
tOFF 2 _ min    L p  Clump
If the compensation for LED VF variation is Corr%, the approximation of the set value is as follows.
tOFF 2  (tON  tOFF 1  tOFF 2 _ min )  Corr%
e.g. When Vin=100V, Lp=680uH, ILp=0.7A, VF=30V, VFD5=0.7V, N=0.4, Clump=100pF and ±Corr%=±30%,
tON=4.76us, tOFF1=6.2us, tOFF2_min=0.82us, and tOFF2 is calculated to be 3.53us.
From this, when the set frequency is approximately 69kHz and energy transmission efficiency of the transformer
η is 0.9, the LED average current will be approximately 337mA.
When the frequency needs to be higher without affecting to the other parameters, tOFF1 should be shorter by
changing the winding ratio (N) lower.
However, when the winding ratio (N) decreases, transformer transmission efficiency tends to be less, and the
AP1601 shortest tOFF1 time is designed at 2us, therefore, please do not be shorter than that in steady state.
In actual AC power source input, Vin is the absolute value of the sine wave, peak current is proportional to Vin
until a certain voltage level, please calculate using the time of the half cycle of the AC power frequency
(50Hz/60Hz).
MS 1454-E-01
9
2012/08
［AP1601］
The AP1601 switching frequency on fixed frequency mode is roughly determined by R15 connected between the
OSC and GND and the sampling voltage on the VFC pin in normal state as follows.
FSW 
VVFC [V ]
 107 kHz
R15 []
0.5V  VVFC  1.5V、20k  R15  400k
Figure 6 shows the relationship between the VFC pin voltage wave form and the voltage sampling point, as well
as between the VVFC voltage and the internal CLK frequency when using R15=100kΩ
in case of a 100 k  connedted
250
between
OSC
pin and GND
200
Sampling Point(V VFC)
TVFC ,delay
FCLK(kHz)
150
100
toff
Waveform of VFC terminal
50
0
1
2
3
4
5
VVFC(V)
Figure 6. VVFC sampling point and relationship between voltage and internal CLK frequency at
R15=100kΩ
Figure 7 shows an image of the compensation for the LED current changed by the VFC pin waveform that is
proportional to the variation of the LED VF. The left side waveforms are for high VF, the right side are for low VF.
expand toff
VFC
Average Current
ILS
Figure 7. Average current compensation on switching frequency changed by VVFC voltage change.
When the LED VF increases, a voltage that is proportional to the secondly winding and the auxiliary winding
is output as the auxiliary winding voltage immediately after the MOSFET turns off.
The switching frequency is changed due to the OSC pin voltage changes that are according to the sampling
voltage divided by a resistor divider from the auxiliary winding. This changes the power. Approximation of VVFC
is given by the following equation.
VVFC 
MS 1454-E-01
N

R12
  B  VD 5  VC 6   VD 2 
R11  R12  N S

10
2012/08
［AP1601］
NS、NB are respectively the number of the secondary winding and the auxiliary winding of transformer T1 .
The VVFC voltage is reflected in the OSC pin voltage and is in the range from 0.2V(typ) to 2V(typ); if it is less than
0.2V , the OSC voltage will be 0.2V, and if it is more than 2V(typ), the OSC pin voltage will be 2V(typ). (refer to
Figure 6.)
As the graph in Figure 6 shows, VVFC which is the center of VF variation should be 1V to compensate LED VF
variation. When the voltage is 1V, the ratio of R11 and R12 is approximately given by the following formula.
R11 N B

 VD5  VC 6   VD 2  1
R12 N S
R11’s selectable range is from 5kΩ to 100kΩ. The number of transformer auxiliary winding is determined by the
VDD voltage.
The VDD pin voltage, VDD in stable operation, is approximately given by the following formula,
VDD 
NB
 VD 5  VC 6   VD 4  I DD  R3
NS
When the LED VF variation is expected to be ±30%, the VDD voltage, which is the center of the variation, should
be set approximately to 15V to be operating within the VDD operating voltage range.
Bottom voltage detection (VTHZC)
Figure 8 shows the schematic of bottom voltage detection on the VFC pin.
As the figure is shown, the rising edge of the internal CKL is the regular interval (=Ts)
However, by the bottom voltage detection function, CLK is kept on high level until VFC becomes less than VTHZC
as shown in the dashed line box A in the figure.
If the VFC pin is already less than VTHZC at the internal CLK rising edge, the OUT pin should be VOUTH level.
However, there are the following exceptions in order to prevent malfunction.
① If internal CLK rises while the OUT pin is VOUTH level, the CLK will not be maintained.
② TBLANK period (700ns, design value) immediately after the OUT pin becomes VOUTL level, ZCD(Internal) shown in
Figure 8 is held as low level and VTHZC detection on the VFC pin is disabled.
A
Ts
Ts
Ts
CLK(Internal)
OUT
VDS
VFC
VTHZC
ZCD(Internal)
Figure 8. Bottom voltage detection (VTHZC)
By this bottom voltage detection function, the external MOSFET is able to turn on in low voltage and current
level, and a noise-reduction effect can be expected. Furthermore, switching-loss can be reduced and power
efficiency will be improved.
MS 1454-E-01
11
2012/08
［AP1601］
2-2-2) Fixed off-time mode
CCM chopper (buck) circuit using the AP1601 fixed off-time mode controls the peak current and the bottom
current of the coil constant (constant ripple control). By this control, the switching frequency is changed for
input voltage and LED VF variation.
Figure 4 shows the current path of a chopper (buck) circuit, current, or voltage waveform for each part. The
primary side of the transformer is controlled by the OUT pin which turns the MOSFET (Q1)on and off.
The current path when the OUT pin turns on (VOUTH) is Vin－LED－Lp－Q1－R13－GND.
The current path when the OUT pin turns off is Lp－D5－LED. The peak current of Lp when the OUT pin turns on
is controlled by turning the OUT pin off and detecting the CS pin voltage. The bottom current should be set by the
transformer primary winding self inductance, LED VF, off-time (tOFF).
If the diode D V can be ignored (VFD5<<VF), the transformer primary side current when the MOSFET turns off
will be decreasing with time

VF
 t OFF . tOFF is the time after Q1 turns off.
Lp
For example, the ILp bottom current is constant when VF, Lp and tOFF are constant.
When VF is varied, the transformer auxiliary winding is affected by the variation, off-time changes inversely
according to the VVFC voltage which is changed by the variation, the bottom current is kept constant.
Fixed off-time control allows the DC voltage input to be on the VFC pin because the bottom voltage detection on
the VFC pin is not performed (refer to Figure 4).
LED average current ILED_ave is,
1 V t
I LED _ ave  I Lp _ peak   F OFF
2
Lp
ILp_peak is peak current on the transformer primary side.
Relationship between off-time tOFF(us) and R15(kΩ) connected between the OSC pin and GND when VVFC is 1V is,
tOFF [  s] 
1
 R15 [k]
10
tOFF [  s] 
1 R15 [k]

10 VVFC [V ]
If VVFC is considered further,
VVFC is proportional to the VF, even when VF is varied; LED average current is held constant, offset by tOFF.
However, if the off-time is long and the bottom current becomes zero (from CCM to DCM), LED average current is
affected by on-time, so the LED current cannot be compensated by VVFC. Thus, the off-time setting is
approximately limited by the following formula.
tOFF 
Lp
VF
 I Lp _ peak
Constant ripple current control maintains the peak current and the bottom current constant, and the current
control can be done without being affecting by the input voltage fluctuation and LED VF variation, in spite of the
fact that the switching frequency is changed by input and output voltage changes.
Figure 9 shows examples of frequency change when the input voltage changes and the number of LEDs
connected in series (VF) changes. In order to be within desired switching frequency range, the transformer
primary side inductance (Lp), ripple width between the peak current and the bottom current needs to be
configured properly.
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(Example)
Number of LEDs vs Switching frequency
110
170
106
150
Frequency (kHz)
Frequency (kHz)
AC input voltage vs Switching frequency
102
98
94
(Example)
130
110
90
85 105 125 145 165 185 205 225 245 265
5
6
7
8
9
Input voltage (VAC)
Number of LEDs connected in series
(kHz)
Figure 9. Examples of frequency changes as in input voltage changes or number of LEDs change
Switching frequency Fsw is approximately given by the following formula,
Fsw 
Vin  VF
V
 F
L p  I Lp _ peak  I Lp _ bottom  Vin
ILp_bottom is the bottom current on the transformer primary side after the off-time tOFF period.
2-2-3) Analog dimming
LED analog dimming is available using the LD pin. Analog dimming is achieved by decreasing the peak current on
the transformer primary side. Analog diming is controlled by applying an external voltage to the LD pin. The
allowable voltage range on the LD pin is from 0 to VREF(5V (typ)). The peak detection voltage on the CS pin is
changed when the LD voltage is less than 2.65V(typ) as shown in Figure 10. Switching will not stop even if the LD
pin connects to GND.
Normalized ILp_Peak Current (%)
100
50
0
1
2
3
4
5
LD (V)
Figure 10. Relationship between LD pin voltage and transformer primary side current (ILp_peak)
2-2-4) PWM dimming
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PWM dimming is available using the PWM pin. PWM diming is controlled by applying an external pulse to the
PWM pin, which is referenced to GND. The allowable voltage range on the PWM pin is from 0 to VREF(5V (typ))
and up to 2kHz PWM pulse signal may be used. By holding the PWM pin voltage to less than VPWML (less than
0.5V), the OUT pin can be fixed to off level (VOUTL)
2-2-5) Leading edge blank and shortest on time of OUT pin
The AP1601 does not detect current by masking for a certain period after the Nch MOSFET turns on. This is
called leading edge blank (TLEB). It means, the voltage on the CS pin is ignored during this period. The period is
necessary to avoid instantaneously turning OUT off and on or ceasing the switching by the over current
protection function when the reverse recovery current of diode D5 or the discharge current from parasitic
capacitor is large while Q1 is on.
However, all current detection on the CS pin is started after TLEB , the shortest on time of Q is limited by the
leading edge blank. Worst case of TLEB at 25C is 450ns.
ton
toff
OUT
TLEB
TLEB
CS
Mask area
Figure 11. CS pin voltage leading edge blank
Thus, input voltage range, output voltage range, ripple width and the transformer primary side inductance
should be determined to guarantee that the on-time during the operation is always more than TLEB . On-time is
approximately given by the following formula and limited by TLEB.
Flyback circuit;
Chopper (buck) circuit;
t on 
t on 
L p  I Lp _ peak
Vin
 t d _ MOS
L p  ( I Lp _ peak  I Lp _ bottom)
Vin  Vout
 TLEB  t d _ MOS
 t d _ MOS
 TLEB  t d _ MOS
Td_MOS represents a delay time until MOSFET (Q1) turns off after the OUT pin is turned off.
If on-time is less than the delay time during the operation condition, the peak current will be higher than the set
value and the average current will also shift higher. Furthermore, if the CS pin voltage after TLEB becomes higher
than the over current protection threshold voltage, the switching will be ceased.
2-3) Gate drive
The OUT pin is the gate driver output, which can drive 1000pF capacitor at 50ns(typ) of raising and falling time
by using the VDD voltage.
2-4) TRIAC dimming
The AP1601 has a built-in circuit which is compatible with TRIAC dimmers.
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［AP1601］
Voltage of both ends of Bulb (RL)
that is controlled by the phase of
TRIAC dimmer.
T TR RI IAAC調
m m
C d光i 回
路e r
c i r c u i t
I n c白a 熱
n d電
e s球e n t
B u l b
負 荷RL
Load: RL
LATCH period
VR
C I n p u t
ACA 入力
C
TRIAC
BLEED period
HOLD period
RESET period
DIAC
図 7 T R I A調
C光 器 に よ る 電 圧 波 形
Figure 12. TRIAC dimmer
As shown in Figure 12, a TRIAC Dimmer for resistive loads like incandescent lamps performs dimming by
changing the input power which is controlled by cutting any angle of the phase for the input sine-wave. The time
constant determined by the Variable resistor (VR) turns the TRIAC (bidirectional thyristor) on in the dimmer
and supplies the power to the load. The TRIAC sustains its conduction once turned on until the current to sustain
the operation becomes lower than the threshold.
θ
The Input current of the switching circuit becomes discontinuous because the diode-bridge turns off when it is
below the input capacitor
B L E E区
D(C1)
間 voltage.
H O L区
D 間
AP1601 is a switching power supply, but to be compatible with a TRIAC Dimmer, it needs to emulate a resistive
load for the TRIAC Dimmer (between the BLEED period and RESET period in Figure 12).
AP1601 has a BLEED current function for efficiency reasons, which supplies a current from the DB1
(Diode-bridge) plus pin to the minus pin through a resistor in the IC only while the TRIAC Dimmer needs a
current to stay on. The function allows normal operation for TRIAC Dimmer applications.
Setting of BLEED current as a TRIAC dimmer supporting current is shown below.
VBLEED to determine when BLEED current flows is 1.2V(typ), On resistance of the HV pin to sink BLEED current
is 450Ω(typ), If maximum BLEED current is 20mA, the resistor to be connected between the BLEED pin and the
HV pin is approximately given by the following formula.
Resistors R5, R6 to determine when BLEED current flows are given as follows.
If, in case of Vrf_th to determine when BLEED current flows is 35V and R5=510kΩ, R6 is,
1.2V  R5
1.2  510
R6  
 18 [k]
Vrf _ th  1.2V
35  1.2
Resistor R2 connected on the HV pin to limit current is given as follows.
R2 
Vrf _ th  450  20mA
20mA
 1.3 [k]
2-5) Startup circuit
The AP1601 has a startup circuit which is supplied power from the high voltage HV pin. By using the auxiliary
winding (Lb) of the transformer, the external device count relevant to startup can be further reduced, this also,
allows power loss after startup to be reduced significantly. The internal startup circuit is also connected to the
VDD pin through a diode as shown below, and the VDD pin voltage increases in accordance with the applied
input voltage.
When the VDD pin voltage reaches the operating startup voltage (UVLOH=18V typical), the internal circuit is
activated and switching is started. The internal startup circuit is cut off from the HV pin in this state, and the
power to the internal circuit is supplied directly from the auxiliary winding of the flyback transformer to the VDD
pin, which is more efficient.
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Vline
DB1
BLEED
R2
EN
HV
T1
Current
Limit
R3
D4
VDD
Lb
C2
Figure 13. Startup circuit
VC6 volatage
Inactivate startup circuit
Pin voltage (V)
LED output pin voltage
Power supplied from the transformer
auxiliary winding phase
UVLO_H
VC1 voltage
VDD pin voltage
Constant current charging
Switching
Input voltage (V)
LED On
Time (ms)
Red: VDD pin voltage (left axis), GREEN: LED anode voltage (left axis), BLUE: Input voltage (Vrf: right axis)
Figure 14. Waveform at startup
Figure 14 shows the voltage waveform immediately after power on of an AC100V application.
Red: VDD pin voltage, Blue: primary side input capacitor (C1) voltage, Green: Output electrolytic capacitor
voltage. The left vertical axis represents the VDD pin voltage and the C6 pin voltage, the right vertical axis is the
C1 voltage.
In this example, the LED is lit approximately 50ms after power on. (Condition: Input voltage 100Vac, C1=0.47uF,
C2=10uF, C6=100uF, VOUT=33V)
2-5-1) Power-on state – initiation of IC operation phase
External capacitor, C2 starts charging through the internal startup circuit powered from the HV pin after power
on. This charging path will be cut off when the VDD pin achieves operating startup voltage (UVLOH). When VDD
is below the UVLOH voltage, the internal circuits, except some circuits needed for startup, cease operation.
2-5-2) Initiation of IC operation - Stable operation phase
When VDD pin voltage becomes UVLOH, REF will be supplied power from VDD first (charge C7)
If REF is rising, the internal reset signal rises, all of the IC circuits start and the switching operation starts.
However, usually, the voltage of electrolytic capacitor (C6) connected on the secondary side is lower than VDD
immediately after switching starts, therefore, power from the auxiliary winding to the VDD pin will not be
supplied, so, the switching operation is performed by consuming the power from charged capacitor (C2). When
the voltage of electrolytic capacitor (C6) connected on the secondary side rises enough, power from the
transformer auxiliary winding to the VDD pin becomes sufficient and VDD will be stable.
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To prevent the VDD pin voltage from becoming lower than UVLOL when the power from the auxiliary winding is
deficient, constant current charging from the HV pin to the VDD pin is properly performed to maintain the VDD
voltage to a certain voltage range by using SWVDD monitoring of the VDD pin voltage. The Startup circuit that
connects between the HV pin to the VDD pin is enabled at the SWVDD lower limit voltage (VDDL: 8.8V(typ)), and
disabled at the upper limit voltage (VDDH: 10.3V(typ)).
If there is no power from auxiliary winding and power continues to be intermittently supplied from the HV pin to
VDD, the IC generates heat due to the voltage drop from the input voltage to the VDD voltage (8.8V(typ)～
10.3V(typ)). Please adjust the HV pin voltage to less than 120VRMS by resistor R2 connected between the HV pin
and Vrf when the HV pin voltage exceeds 120VRMS.
Time chart in regard to startup circuit is shown in Figure 15.
UVLOH
VDD powered from the
auxiliary winding is stable.
VDDH
Power OFF
VDD
VDDL
UVLO(Internal)
SWVDD(Internal)
REF
RESET(Internal
)
OUT
Figure 15. Image of startup circuit operation (Time chart)
2-6) Internal regulator
The AP1601 has a built in 5V regulator to supply voltage from the VDD pin to the internal circuits, And if thermal
conditions are met, a maximum of a 7mA current can be supplied to external circuits from the REF pin.
For voltage stability, please connect a 0.1uF capacitor (class B) between the REF pin and GND.
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3) Protection function
Protection
function
Thermal
protection
Over current
Over voltage
UVLO
Operation
If the IC temperature exceeds the
detection condition, the OUT pin
turns to GND level.
If an over current flows to the
external MOSFET, the OUT pin
turns to GND level.
If LED is open or LED VF is high, the
OUT pin turns to GND level.
To prevent malfunction of the IC,
the OUT pin is fixed to GND level
and cease 5V regulator.
Shut-off state
Detection condition
Cease driver
Auto-release
IC junction temp.
150C
Cease driver
Latch off
Cease driver
Latch off
Cease all
Auto-release
CS pin voltage
after TLEB
0.8V(typ)
VDD pin voltage
26V(typ)
When VDD pin
voltage decreasing
6.4V(typ)
Release
condition
65C
Down from
detection temp.
*1
*1
17.6V(typ)
Note:
*1. In order to release the latch off state, please apply a voltage of less than UVLOL for at least 10ms to the VDD
pin.
#
When the REF pin is shorted to GND, the IC prevents heat generation by limiting internal regulator
maximum current to 40mA (design value).
If ambient temperature is high or the HV pin voltage is high or if both are true, the junction temperature
may exceed the absolute maximum rating. If the rating is exceeded, the specification can not be guaranteed.
3-1) Thermal protection
To prevent thermal runaway of the IC, the junction temperature is always monitored and the IC operation is
controlled. When the junction temperature exceeds TSD (design value is 150°C typical), switching stops.
When the junction temperature goes below the thermal release temperature (ΔTSD, 65°C(typ)), switching
restarts. Once the thermal protection is activated, the specification can not be guaranteed.
3-2) Over current protection
The CS pin voltage is monitored after turning the MOSFET on and after the leading edge blanking period
(TLEB:300ns (typ)). If the CS pin voltage is at the OCP voltage (0.8V typical), switching stops and is latched.
For example, when the CS pin voltage is 0.5V and the current is 500mA, the OCP level reaches 800mA. The
application circuit is protected when the primary winding, the secondary winding, or the auxiliary winding is
shorted. For releasing the over current protection, please apply a voltage of less than UVLOL for at least 10ms to
the VDD pin.
3-3) Over Voltage Protection
The VDD pin voltage is monitored, and if the voltage exceeds the OVP voltage (26V typical), switching stops and
is latched. It typically functions as an open protection for secondary side where LEDs are connected. For
releasing the over voltage protection, please apply a voltage of less than UVLOL for al least 10ms to the VDD pin.
3-4) UVLO
Under Voltage Lockout. The circuit provides an ON signal to the internal circuits when the VDD pin voltage is
higher than UVLOH (17.6V typical) and an OFF signal when the VDD pin is lower than UVLOL (6.4V typical). If the
VDD pin voltage is lower than the UVLOL voltage, the IC stops switching. If the HV pin voltage is high enough, the
VDD pin is provided a current through the internal startup circuit to reach UVLOH and restart the IC.
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CHARACTERISTICS
20
5.2
15
5.1
VREF [V]
UVLO [V]
1) Temperature dependency
10
5
5
4.9
UVLH
UVLL
0
4.8
-40
-20
0
20
40
Ta [℃]
60
80
100
-40
-20
20
40
Ta [℃]
60
80
100
80
100
Figure 17. VREF voltage
0.55
400
0.525
350
TLEB[ns]
VPEAK[V]
Figure 16. UVLO voltage
0
0.5
0.475
300
250
0.45
200
-40
-20
0
20
40
Ta [℃]
60
80
100
-40
Figure 18. Peak current detection voltage (LD=REF)
-20
0
20
40
Ta [℃]
60
Figure 19. Leading Edge Blank
120
1000
R15=100kΩ,VVFC=1V
800
RONH [Ω]
Fsw[kHz]
110
100
600
90
400
80
200
-40
-20
0
20
40
Ta [℃]
60
80
-40
100
Figure 20. Switching frequency (SEL=VREF)
MS 1454-E-01
-20
0
20
40
Ta [℃]
60
80
100
Figure 21. Equivalent R value HV-GND (IHV=20mA)
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［AP1601］
APPLICATION EXAMPLE
L
Vrf
DIMMER
+OUT
Vin
F1
D1
R1
D5
C6
Ls
T1
C1
R4
C4
Lp
R14 VF
DB1
D3
R15
N
R2
R5
R7
Lb
U1
R9
R10
-OUT
C9
R8
C7
LD
OSC
PWM
VFC
GND
SEL
REF
CS
BLEED
V1
D4
D2
REF
Q1
R3
R11
R13
GND
V1
R6
OUT
HV
R12
VDD
C2
Figure 22. Typical isolated flyback circuit compatible with TRIAC dimmer
L
Vrf
DIMMER
F1
+OUT
Vin
D1
R1
C1
D5
Lp
DB1
T1
R15
N
R2
R5
R7
Lb
U1
R9
LD
OSC
PWM
VFC
GND
SEL
REF
CS
C9
R8
R10
C7
BLEED
D4
V1
D2
Q1
R3
R11
R13
V1
GND
R6
OUT
HV
R12
VDD
C8
C2
Figure 23. Typical non-isolated chopper circuit compatible with TRIAC dimmer
* The above figures are for reference only.
* A varistor to absorb a surge voltage, a common mode choke coil to reduce noise, across the line capacitor and
such are not shown above.
* In order to prevent a large current from continuously flowing when the IC has failed due to incorrect wiring
during assembly or abnormal pulse noises and so forth, please place the appropriate fuse to meet the
appropriate standards in the appropriate place in the circuit.
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-OUT
［AP1601］
PACKAGE and MARKING
1) Dimension (14 pin SOP)
[Unit:mm]
Figure 24. Package outline
MS 1454-E-01
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［AP1601］
2) Marking
Figure 25. Marking Information
Upper
Product name：AP1601
Lower
Date code: 7 digits
2 digits (Last 2 digits of year) +2 digits (weekly code) + 3 digits (production code)
IMPORTANT NOTICE

Descriptions of external circuits, application circuits, software and other related information contained
in this document are provided only to illustrate the operation and application examples of the
semiconductor products. You are fully responsible for the incorporation of these external circuits,
application circuits, software and other related information in the design of your equipments. Asahi Kasei
Microdevices Corporation (AKM) assumes no responsibility for any losses incurred by you or third parties
arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.

Any export of these products, or devices or systems containing them, may require an export license or
other official approval under the law and regulations of the country of export pertaining to customs and
tariffs, currency exchange, or strategic materials.

AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life
support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use,
except for the use approved with the express written consent by Representative Director of AKM. As used
here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected
to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance
of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure
to function or perform may reasonably be expected to result in loss of life or in significant injury or
damage to person or property.

It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or
otherwise places the product with a third party, to notify such third party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and
hold AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.
MS 1454-E-01
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