SN74CBT34X245 32-BIT FET BUS SWITCH SCDS089C – MAY 1999 – REVISED MAY 2001 D D D D D D D DBB PACKAGE (TOP VIEW) Member of Texas Instruments’ Widebus + Family 5-Ω Switch Connection Between Two Ports TTL-Compatible Input Levels Flow-Through Architecture Optimizes PCB Layout Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) NC 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 GND NC 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 GND NC 3A1 3A2 3A3 3A4 3A5 3A6 3A7 3A8 GND NC 4A1 4A2 4A3 4A4 4A5 4A6 4A7 4A8 GND description The SN74CBT34X245 provides 32 bits of high-speed TTL-compatible bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The device is organized as four 8-bit bus switches, two 16-bit bus switches, or one 32-bit bus switch. When output enable (OE) is low, the switch is on, and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the two ports. This device is fully specified for partial-powerdown applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 50 32 49 33 48 34 47 35 46 36 45 37 44 38 43 39 42 40 41 VCC 1OE 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 VCC 2OE 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 VCC 3OE 3B1 3B2 3B3 3B4 3B5 3B6 3B7 3B8 VCC 4OE 4B1 4B2 4B3 4B4 4B5 4B6 4B7 4B8 NC – No internal connection Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments. Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74CBT34X245 32-BIT FET BUS SWITCH SCDS089C – MAY 1999 – REVISED MAY 2001 ORDERING INFORMATION TA ORDERABLE PART NUMBER PACKAGE† TOP-SIDE MARKING –40°C to 85°C TVSOP – DBB Tape and reel SN74CBT34X245DBBR CBT34X245 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each 8-bit bus switch) INPUT OE FUNCTION L A port = B port H Disconnect logic diagram (positive logic) 1A1 2 78 9 71 1A8 1B1 2A1 1B8 2A8 79 68 19 61 2B1 2B8 69 1OE 3A1 12 2OE 22 58 29 51 3A8 3B1 4A1 3B8 4A8 59 32 48 39 41 4B1 4B8 49 3OE 4OE absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74CBT34X245 32-BIT FET BUS SWITCH SCDS089C – MAY 1999 – REVISED MAY 2001 recommended operating conditions (see Note 3) MIN MAX VCC VIH Supply voltage 4 5.5 High-level control input voltage 2 VIL TA Low-level control input voltage Operating free-air temperature –40 UNIT V V 0.8 V 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to TI application report Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK II VCC = 4.5 V, VCC = 5.5 V, II = –18 mA VI = 5.5 V or GND Ioff ICC VCC = 0, VCC = 5.5 V, VI or VO = 0 to 5.5 V IO = 0, VCC = 5.5 V, VI = 3 V or 0 One input at 3.4 V, VO = 3 V or 0, VCC = 4 V, TYP at VCC = 4 V OE = VCC ∆ICC‡ Ci Control inputs Control inputs Cio(OFF) ron§ VCC = 4.5 V MIN TYP† VI = VCC or GND Other inputs at VCC or GND MAX UNIT –1.2 V ±5 µA 10 µA 6 µA 3.5 mA 3.5 pF 5.5 pF VI = 2.4 V, II = 15 mA 11 17 VI = 0 II = 64 mA II = 30 mA 5 7 5 7 Ω VI = 2.4 V, II = 15 mA 8 13 † All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. ‡ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. § Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tpd¶ A or B B or A ten OE A or B PARAMETER VCC = 4 V VCC = 5 V ± 0.5 V MIN MAX MIN 2.2 6.5 1.9 UNIT MAX 0.25 ns 6 ns tdis A or B 1.9 6.2 2.2 6.7 ns OE ¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74CBT34X245 32-BIT FET BUS SWITCH SCDS089C – MAY 1999 – REVISED MAY 2001 PARAMETER MEASUREMENT INFORMATION 7V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V Output Control LOAD CIRCUIT 1.5 V 1.5 V 0V tPLZ tPZL 3V Input 1.5 V 1.5 V 0V tPLH 1.5 V 3.5 V 1.5 V 1.5 V VOL Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL + 0.3 V VOL tPHZ tPZH tPHL VOH Output Output Waveform 1 S1 at 7 V (see Note B) 1.5 V VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 25-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing SN74CBT34X245DBBR ACTIVE TSSOP DBB Pins Package Eco Plan (2) Qty 80 2000 Pb-Free (RoHS) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-1-250C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTSS005D – JANUARY 1995 – REVISED MARCH 2002 DBB (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 80 PINS SHOWN 0,23 0,13 0,40 80 0,07 M 41 6,20 6,00 8,30 7,90 0,20 0,09 1 Gage Plane 40 A 0,25 0°–ā8° 0,75 0,45 Seating Plane 1,20 MAX 0,15 0,05 PINS** 0,08 80 100 A MAX 17,10 20,90 A MIN 16,90 20,70 DIM 4040212 / E 03/02 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC : 80 Pin – MO-153 Variation FF 100 Pin – MO-194 Variation BB POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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