TI SN74CBTLV1G125DBV

SCDS057G − MARCH 1998 − REVISED OCTOBER 2003
D 5-Ω Switch Connection Between Two Ports
D Rail-to-Rail Switching on Data I/O Ports
D Ioff Supports Partial-Power-Down Mode
DBV OR DCK PACKAGE
(TOP VIEW)
OE
A
GND
Operation
description/ordering information
1
5
VCC
4
B
2
3
The SN74CBTLV1G125 features a single
high-speed line switch. The switch is disabled
when the output-enable (OE) input is high.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
−40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING‡
SOT (SOT-23) − DBV
Tape and reel
SN74CBTLV1G125DBVR
V25_
SOT (SC-70) − DCK
Tape and reel
SN74CBTLV1G125DCKR
VM_
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
‡ The actual top-side marking has one additional character that designates the assembly/test site.
FUNCTION TABLE
INPUT
OE
FUNCTION
L
A port = B port
H
Disconnect
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
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POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCDS057G − MARCH 1998 − REVISED OCTOBER 2003
logic diagram (positive logic)
2
4
A
OE
SW
B
1
simplified schematic, each FET switch
A
B
(OE)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
VCC
Supply voltage
VIH
High-level control input voltage
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VIL
Low-level control input voltage
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
MIN
MAX
2.3
3.6
UNIT
V
1.7
V
2
0.7
0.8
V
TA
Operating free-air temperature
−40
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
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SCDS057G − MARCH 1998 − REVISED OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VIK
II
VCC = 3 V,
VCC = 3.6 V,
II = −18 mA
VI = VCC or GND
Ioff
ICC
VCC = 0,
VCC = 3.6 V,
VI or VO = 0 to 3.6 V
IO = 0,
VI = VCC or GND
One input at 3 V,
Other inputs at VCC or GND
∆ICC‡
Control inputs
Ci
Control inputs
Cio(OFF)
VCC = 3.6 V,
VI = 3 V or 0
TYP†
MAX
UNIT
−1.2
V
±1
µA
10
µA
10
µA
300
µA
2.5
VO = 3 V or 0,
OE = VCC
VI = 0
VCC = 2.3 V,
TYP at VCC = 2.5 V
VI = 1.7 V,
ron§
VI = 0
VCC = 3 V
pF
7
pF
II = 64 mA
II = 24 mA
7
10
7
10
II = 15 mA
II = 64 mA
15
25
5
7
II = 24 mA
II = 15 mA
5
7
Ω
VI = 2.4 V,
10
15
† All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
‡ This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND.
§ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
tpd¶
A or B
B or A
ten
tdis
OE
A or B
1
4
OE
A or B
1
5
PARAMETER
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
0.15
UNIT
MAX
0.25
ns
1
4
ns
1
4.1
ns
¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and a load capacitance of 50 pF, when
driven by an ideal voltage source (zero output impedance).
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3
SCDS057G − MARCH 1998 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
2 × VCC
RL
From Output
Under Test
S1
Open
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
RL
LOAD CIRCUIT
VCC
CL
RL
V∆
2.5 V ±0.2 V
3.3 V ±0.3 V
30 pF
50 pF
500 Ω
500 Ω
0.15 V
0.3 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
VCC/2
th
VCC
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
VCC/2
0V
tPHL
tPLH
VOH
VCC/2
Output
VCC/2
VOL
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
tPHL
VCC/2
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
VOL + V∆
VOL
tPHZ
tPZH
VCC/2
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
4
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Oct-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74CBTLV1G125CRE4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74CBTLV1G125CRG4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74CBTLV1G125DBVRE4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74CBTLV1G125DBVR
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74CBTLV1G125DCKR
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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