HFBR-1115TZ Transmitter
HFBR-2115TZ Receiver
Fiber Optic Transmitter and Receiver Data Links for 125 MBd
Data Sheet
Description
Features
The HFBR-1115TZ/-2115TZ series of data links are highperformance, cost-efficient, transmitter and receiver
modules for serial optical data communication applications specified at 100 Mbps for FDDI PMD or 100 Base-FX
Fast Ethernet applications.
• Full compliance with the optical performance requirements of the FDDI PMD standard
These modules are designed for 50 or 62.5 μm core multimode optical fiber and operate at a nominal wavelength
of 1300 nm. They incorporate our high performance,
reliable, long-wavelength, optical devices and proven
circuit technology to give long life and consistent performance.
Transmitter
The transmitter utilizes a 1300 nm surface-emitting
InGaAsP LED, packaged in an optical subassembly. The LED
is dc-coupled to a custom IC which converts differentialinput, PECL logic signals, ECL-referenced (shifted) to a +5 V
power supply, into an analog LED drive current.
Receiver
The receiver utilizes an InGaAs PIN photodiode coupled
to a custom silicon transimpedance preamplifier IC. The
PIN-preamplifier combination is ac-coupled to a custom
quantizer IC which provides the final pulse shaping for
the logic output and the Signal Detect function. Both the
Data and Signal Detect Outputs are differential. Also, both
Data and Signal Detect Outputs are PECL compatible, ECLreferenced (shifted) to a +5 V power supply.
Package
The overall package concept for the Data Links consists of
the following basic elements: two optical subassemblies,
two electrical subassemblies, and the outer housings as
illustrated in Figure 1.
* ST is a registered trademark of AT&T Lightguide Cable Connectors.
• Full compliance with the optical performance requirements of the ATM 100 Mbps physical layer
• Full compliance with the optical performance requirements of the 100 Mbps fast ethernet physical layer
• Other versions available for:
– ATM
– Fibre Channel
• Compact 16-pin DIP package with plastic ST* connector
• Wave solder and aqueous wash process compatible
package
• Manufactured in an ISO 9001 certified facility
Applications
• FDDI concentrators, bridges, routers, and network
interface cards
• 100 Mbps ATM interfaces
• Fast ethernet interfaces
• General purpose, point-to-point data communications
• Replaces DLT/R1040-ST1 model transmitters and
receivers
The package outline drawing and pinout are shown
in Figures 2 and 3. The details of this package outline
and pinout are compatible with other data-link
modules from other vendors.
RECEIVER
PIN PHOTODIODE
DIFFERENTIAL
DATA IN
DIFFERENTIAL
QUANTIZER
IC
SIGNAL
DETECT OUT
PREAMP IC
ELECTRICAL
SUBASSEMBLIES
OPTICAL
SUBASSEMBLIES
SIMPLEX ST®
RECEPTACLE
TRANSMITTER
DIFFERENTIAL
DATA IN
VBB
DRIVER IC
LED
TOP VIEW
Figure 1. Transmitter and receiver block diagram.
THREADS
3/8 – 32 UNEF-2A
HFBR-111X/211XT
DATE CODE (YYWW)
SINGAPORE
12.19
MAX.
8.31
41 MAX.
5.05
5.0
0.9
7.01
9.8 MAX.
2.45
19.72
NOTES:
1. MATERIAL ALLOY 194 1/2H – 0.38 THK
FINISH MATTE TIN PLATE 7.6 µm MIN.
2. MATERIAL PHOSPHOR BRONZE WITH
120 MICROINCHES TIN LEAD (90/10)
OVER 50 MICROINCHES NICKEL.
12
17.78
(7 x 2.54)
8 x 7.62
3. UNITS = mm
HOUSING PINS 0.38 x 0.5 mm
NOTE 1
PCB PINS
DIA. 0.46 mm
NOTE 2
Figure 2. Package outline drawing.
2
3
NC
9NC
OPTICAL PORT
8
NC
GND
10NO PIN
7
NO PIN
9NC
VCC
11GND 6
GND
11V
6
CC
VCC
12GND 5
GND
12V
5
CC
13V
4
CC
8
10GND 7
GND
13GND 4
GND
DATA
14GND 3
SD
14DATA3
DATA
15V
2
SD
15DATA2
16NC
1
NC
BB
TRANSMITTER
NO PIN
16NC
1
OPB – OPTICAL POWER BUDGET – dB
OPTICAL PORT
14
12
62.5/125 µm
10
8
6
50/125 µm
4
2
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
FIBER OPTIC CABLE LENGTH – km
RECEIVER
Figure 3. Pinout drawing.
Figure 4. Optical power budget at BOL vs. fiber optic cable length.
The optical subassemblies consist of a transmitter subassembly in which the LED resides and a receiver subassembly housing the PIN-preamplifier combination.
Transmitter and Receiver Optical Power Budget versus
Link Length
The electrical subassemblies consist of a multi-layer
printed circuit board on which the IC chips and various
sufrace-mounted, passive circuit elements are attached.
Each transmitter and receiver package includes an internal
shield for the electrical subassembly to ensure low EMI
emissions and high immunity to external EMI fields.
The outer housing, including the ST* port, is molded
of filled, nonconductive plastic to provide mechanical
strength and electrical isolation. For other port styles,
please contact your Avago Technologies Sales Representative.
Each data-link module is attached to a printed circuit
board via the 16-pin DIP interface. Pins 8 and 9 provide
mechanical strength for these plastic-port devices and
will provide port-ground for forthcoming metal-port
modules.
Application Information
The Applications Engineering group of the Fiber Optics
Product Division is available to assist you with the technical
understanding and design tradeoffs associated with these
transmitter and receiver modules. You can contact them
through your Avago Technologies sales representative.
The following information is provided to answer some of
the most common questions about the use of these parts.
3
The Optical Power Budget (OPB) is the available optical
power for a fiber-optic link to accommodate fiber cable
losses plus losses due to in-line connectors, splices,
optical switches, and to provide margin for link aging and
unplanned losses due to cable plant reconfiguration or
repair.
Figure 4 illustrates the predicted OPB associated with
the transmitter and receiver specified in this data sheet
at the Beginning of Life (BOL). This curve represents the
attenuation and chromatic plus modal dispersion losses
associated with 62.5/125 μm and 50/125 μm fiber cables
only. The area under the curve represents the remaining
OPB at any link length, which is available for overcoming
non-fiber cable related losses.
Avago LED technology has produced 1300 nm LED devices
with lower aging characteristics than normally associated
with these technologies in the industry. The industry convention is 1.5 dB aging for 1300 nm LEDs; however, Avago
1300 nm LEDs will experience less than 1 dB of aging
over normal commercial equipment mission-life periods.
Contact your Avago Technologies sales representative for
additional details.
Figure 4 was generated with an Avago fiber-optic link
model containing the current industry conventions
for fiber cable specifications and the FDDI PMD optical
parameters.
These parameters are reflected in the guaranteed performance of the transmitter and receiver specifications
in this data sheet. This same model has been used extensively in the ANSI and IEEE committees, including the ANSI
X3T9.5 committee, to establish the optical performance
requirements for various fiber-optic interface standards.
The cable parameters used come from the ISO/IEC
JTC1/ SC 25/WG3 Generic Cabling for Customer Premises
per DIS 11801 document and the EIA/TIA-568-A Commercial Building Telecommunications Cabling Standard per
SP-2840.
Transmitter and Receiver Signaling Rate Range and BER
Performance
For purposes of definition, the symbol rate (Baud), also
called signaling rate, is the reciprocal of the symbol time.
Data rate (bits/sec) is the symbol rate divided by the
encoding factor used to encode the data (symbols/bit).
When used in FDDI, ATM 100 Mbps, and Fast Ethernet
applications, the performance of Avago Technologies’
1300 nm HFBR-1115TZ/-2115TZ data link modules is guaranteed over the signaling rate of 10 MBd to 125 MBd to
the full conditions listed in the individual product specification tables.
The data link modules can be used for other applications at signaling rates outside of the 10 MBd to 125 MBd
range with some penalty in the link optical power budget
primarily caused by a reduction of receiver sensitivity.
Figure 5 gives an indication of the typical performance of
these 1300 nm products at different rates.
The 1300 nm transmitter will tolerate the worst-case input
electrical jitter allowed in the table without violating the
worst-case output jitter requirements of Section 8.1 Active
Output Interface of the FDDI PMD standard.
The 1300 nm receiver will tolerate the worst-case input
optical jitter allowed in Section 8.2 Active Input Interface
of the FDDI PMD standard without violating the worstcase output electrical jitter allowed in the Table E1 of the
Annex E.
The jitter specifications stated in the following transmitter
and receiver specification table are derived from the
values in Table E1 of Annex E. They represent the worstcase jitter contribution that the transmitter and receiver
are allowed to make to the overall system jitter without
violating the Annex E allocation example. In practice, the
typical jitter contribution of the Avago Technologies’ data
link modules is well below the maximum amounts.
Recommended Handling Precautions
It is advised that normal static precautions be taken in
the handling and assembly of these data link modules to
prevent damage which may be induced by electrostatic
discharge (ESD). The HFBR-1115TZ/-2115TZ series meets
MIL-STD-883C Method 3015.4 Class 2.
Care should be taken to avoid shorting the receiver Data
or Signal Detect Outputs directly to ground without
proper currentlimiting impedance.
3.0
1 x 10-2
2.5
2.0
1.5
1.0
0.5
0
1 x 10-3
CENTER OF
SYMBOL
1 x 10-4
1 x 10-5
1 x 10-6
1 x 10-7
1 x 10-8
2.5 x 10-10
1 x 10-11
1 x 10-12
0
25
50
75 100 125 150 175 200
SIGNAL RATE (MBd)
CONDITIONS:
1. PRBS 27-1
2. DATA SAMPLED AT CENTER OF DATA SYMBOL.
3. BER = 10-6
4. TA = 25° C
5. VCC = 5 Vdc
6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
Figure 5. Transmitter/Receiver relative optical power budget at constant BER
vs. signaling rate.
4
The Avago 1300 nm data link modules are designed to
operate per the system jitter allocations stated in Table E1
of Annex E of the FDDI PMD standard.
BIT ERROR RATIO
TRANSMITTER/RECEIVER RELATIVE OPTICAL
POWER BUDGET AT CONSTANT BER (dB)
These data link modules can also be used for applications
which require different bit-error-ratio (BER) performance.
Figure 6 illustrates the typical trade-off between link BER
and the receiver input optical power level.
Data Link Jitter Performance
-6
-4
-2
0
2
4
RELATIVE INPUT OPTICAL POWER – dB
CONDITIONS:
1. 125 MBd
2. PRBS 27-1
3. TA = 25° C
4. VCC = 5 Vdc
5. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
Figure 6. Bit-error-ratio vs. relative receiver input optical power.
Solder and Wash Process Compatibility
Board Layout–Interface Circuit and Layout Guidelines
The transmitter and receiver are delivered with protective process caps covering the individual ST* ports. These
process caps protect the optical subassemblies during
wave solder and aqueous wash processing and act as dust
covers during shipping.
It is important to take care in the layout of your circuit
board to achieve optimum performance from these data
link modules. Figure 7 provides a good example of a
power supply filter circuit that works well with these parts.
Also, suggested signal terminations for the Data, Data-bar,
Signal Detect and Signal Detect-bar lines are shown. Use
of a multilayer, ground-plane printed circuit board will
provide good high-frequency circuit performance with
a low inductance ground return path. See additional
recommendations noted in the interface schematic
shown in Figure 7.
These data link modules are compatible with either
industry standard wave- or hand-solder processes.
Shipping Container
The data link modules are packaged in a shipping
container designed to protect it from mechanical and ESD
damage during shipment or storage.
Rx
Tx
*
A
L2
1
+5 Vdc
C2
0.1
GND
9 NC
NC 8
10 GND
NO 7
PIN
11 VCC
*
*
9 NC
NC 8
GND 7
GND 6
10 NO
PIN
11 GND
12 VCC
GND 5
12 GND
VCC 5
VCC 4
*
L1
1
VCC 6
C1
0.1
C7
10
(OPTIONAL)
C3
0.1
C4
10
A
13 GND
GND 4
13 GND
DATA
14 D
GND 3
14 SD
D 3
DATA
DATA
15 D
VBB 2
15 SD
D 2
DATA
NO
16 PIN
NC 1
R3
82
R2
82
R4
130
R1
130
16 NC
NC 1
R7
82
C6
0.1
R9
82
C5
0.1
R5
82
R8
130
R6
130
R11
82
SD
SD
TERMINATE D, D
AT Tx INPUTS
TOP VIEWS
R10
130
R12
130
TERMINATE D, D, SD, SD AT
INPUTS OF FOLLOW-ON DEVICES
Notes:
1. Resistance is in ohms. Capacitance is in microfarads. Inductance is in microhenries.
2. Terminate transmitter input data and data-bar at the transmitter input pins. Terminate the receiver output data, data-bar, and signal detect-bar at
the follow-on device input pins. For lower power dissipation in the signal detect termination circuitry with small compromise to the signal quality,
each signal detect output can be loaded with 510 ohms to ground instead of the two resistor, split-load pecl termination shown in this schematic.
3. Make differential signal paths short and of same length with equal termination impedance.
4. Signal traces should be 50 ohms microstrip or stripline transmission lines. Use multilayer, ground-plane printed circuit board for best highfrequency
performance.
5. Use high-frequency, monolithic ceramic bypass capacitors and low series DC resistance inductors. Recommend use of surface-mount coil
inductors and capacitors. In low noise power supply systems, ferrite bead inductors can be substituted for coil inductors. Locate power supply
filter components close to their respective power supply pins. C7 is an optional bypass capacitor for improved, low-frequency noise power supply
filter performance.
6. Device ground pins should be directly and individually connected to ground.
7. Caution: do not directly connect the fiber-optic module PECL outputs (data, data-bar, signal detect, signal detect-bar, VBB) to ground without
proper current limiting impedance.
8. (*) Optional metal ST optical port transmitter and receiver modules will have pins 8 and 9 electrically connected to the metal port only and not
connected to the internal signal ground.
Figure 7. Recommended interface circuitry and power supply filter circuits.
5
Board Layout – Hole Pattern
The Avago transmitter and receiver hole pattern is compatible with other data link modules from other vendors.
The drawing shown in Figure 8 can be used as a guide in
the mechanical layout of your circuit board.
Regulatory Compliance
These data link modules are intended to enable commercial system designers to develop equipment that
complies with the various international regulations
governing certification of Information Technology Equipment. Additional information is available from your Avago
sales representative.
(16X) ø 0.8 ± 0.1
.032 ± .004
All HFBR-1115TZ LED transmitters are classified as
IEC-825-1 Accessible Emission Limit (AEL) Class 1 based
upon the current proposed draft scheduled to go into
effect on January 1, 1997. AEL Class 1 LED devices are considered eye safe. See Application Note 1094, LED Device
Classifications with Respect to AEL Values as Defined in the
IEC 825-1 Standard and the European EN60825-1 Directive.
The material used for the housing in the HFBR-1115TZ/2115TZ series is Ultem 2100 (GE). Ultem 2100 is recognized for a UL flammability rating of 94V-0 (UL File Number
E121562) and the CSA (Canadian Standards Association)
equivalent (File Number LS88480).
–A–
Ø 0.000 M A
17.78
.700
(7X) 2.54
.100
7.62
.300
Figure 8. Recommended board layout hole pattern.
6
TOP VIEW
UNITS = mm/INCH
180
160
3.0
1.5
3.5
2.0
140 2.5
120
tr/f – TRANSMITTER
OUTPUT OPTICAL
RISE/FALL TIMES – ns
3.0
3.5
100
1280
1300 1320
1.025
1.00
0.975
0.90
0.075
40 ± 0.7
0.50
± 0.725
± 0.725
0% TIME
INTERVAL
0.10
0.025
0.0
-0.025
-0.05
5.6
10.0
1.525
0.525
4.850
80 ± 500 ppm
0.075
1.975
4.40
TIME – ns
THE HFBR-1115TZ OUTPUT OPTICAL PULSE SHAPE FITS WITHIN THE BOUNDARIES
OF THE PULSE ENVELOPE FOR RISE AND FALL TIME MEASUREMENTS.
Figure 10. Output optical pulse envelope.
5
-31.0 dBm
4
2.5 x 10-10 BER
2
1.0 x 10-12 BER
0
-3
-2
-1
0
1
PA (PO + 1.5 dB
< PA < -31.0 dBm)
INPUT OPTICAL POWER
(> 1.5 dB STEP INCREASE)
PO = MAX (PS OR -45.0 dBm)
(PS = INPUT POWER FOR BER < 102)
INPUT OPTICAL POWER
(> 4.0 dB STEP DECREASE)
-45.0 dBm
1
-4
MIN (PO + 4.0 dB OR -31.0 dBm)
OPTICAL POWER
3
2
3
4
EYE SAMPLING TIME POSITION (ns)
CONDITIONS:
1.TA = 25° C
2. VCC = 5 Vdc
3. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
4. INPUT OPTICAL POWER IS NORMALIZED TO
CENTER OF DATA SYMBOL.
5. NOTE 21 AND 22 APPLY.
Figure 11. HFBR-2115TZ receiver relative input optical power vs.
eye sampling time position.
SIGNAL
DETECT
OUTPUT
RELATIVE INPUT OPTICAL POWER – dB
5.6
1.525
0.525
100% TIME
INTERVAL
HFBR-1115TZ FDDI TRANSMITTER TEST RESULTS
OF λC, ∆λ AND tr/f ARE CORRELATED AND
COMPLY WITH THE ALLOWED SPECTRAL WIDTH
AS A FUNCTION OF CENTER WAVELENGTH FOR
VARIOUS RISE AND FALL TIMES.
Figure 9. HFBR-1115TZ transmitter output optical spectral width (FWHM) vs.
transmitter output optical center wavelength and rise/fall times.
4.850
10.0
1340 1360 1380
λC – TRANSMITTER OUTPUT OPTICAL
CENTER WAVELENGTH –nm
7
4.40
1.975
1.25
RELATIVE AMPLITUDE
∆λ – TRANSMITTER OUTPUT OPTICAL
SPECTRAL WIDTH (FWHM) –nm
200
SIGNAL – DETECT (ON)
AS – MAX
ANS – MAX
SIGNAL – DETECT (OFF)
TIME
AS – MAX — MAXIMUM ACQUISITION TIME (SIGNAL).
AS – MAX IS THE MAXIMUM SIGNAL – DETECT ASSERTION TIME FOR THE STATION.
AS – MAX SHALL NOT EXCEED 100.0 µs. THE DEFAULT VALUE OF AS – MAX IS 100.0 µs.
ANS – MAX — MAXIMUM ACQUISITION TIME (NO SIGNAL).
ANS – MAX IS THE MAXIMUM SIGNAL – DETECT DEASSERTION TIME FOR THE STATION.
ANS – MAX SHALL NOT EXCEED 350 µs. THE DEFAULT VALUE OF AS – MAX IS 350 µs.
Figure 12. Signal detect thresholds and timing.
HFBR-1115TZ Transmitter Pin-Out Table
Pin
Symbol
Functional Description
Reference
1
NC
No internal connect, used for mechanical strength only
2
VBB
VBB Bias output
3
GND
Ground
Note 3
4
GND
Ground
Note 3
5
GND
Ground
Note 3
6
GND
Ground
Note 3
7
OMIT
No pin
8
NC
No internal connect, used for mechanical strength only
Note 5
9
NC
No internal connect, used for mechanical strength only
Note 5
10
GND
Ground
Note 3
11
VCC
Common supply voltage
Note 1
12
VCC
Common supply voltage
Note 1
13
GND
Ground
Note 3
14
DATA
Data input
Note 4
15
DATA
Inverted Data input
Note 4
16
NC
No internal connect, used for mechanical strength only
HFBR-2115TZ Receiver Pin-Out Table
Pin
Symbol
Functional Description
Reference
1
NC
No internal connect, used for mechanical strength only
2
DATA
Inverted Data input
Note 4
3
DATA
Data input
Note 4
4
VCC
Common supply voltage
Note 1
5
VCC
Common supply voltage
Note 1
6
VCC
Common supply voltage
Note 1
7
GND
Ground
Note 3
8
NC
No internal connect, used for mechanical strength only
Note 5
9
NC
No internal connect, used for mechanical strength only
Note 5
10
OMIT
No pin
11
GND
Ground
Note 3
12
GND
Ground
Note 3
13
GND
Ground
Note 3
14
SD
Signal Detect
Note 2, 4
15
SD
Inverted Signal Detect
Note 2, 4
16
OMIT
No pin
Notes:
1. Voltages on VCC must be from the same power supply (they are connected together internally).
2. Signal Detect is a logic signal that indicates the presence or absence of an input optical signal. A logic-high, VOH, on Signal Detect indicates
presence of an input optical signal. A logic-low, VOL, on Signal Detect indicates an absence of input optical signal.
3. All GNDs are connected together internally and to the internal shield.
4. DATA, DATA, SD, SD are open-emitter output circuits.
5. On metal-port modules, these pins are redefined as “Port Connection.”
8
Specifications – Absolute Maximum Ratings
Parameter
Symbol
Min.
Storage Temperature
TS
-40
Lead Soldering Temperature
TSOLD
Lead Soldering Time
tSOLD
Supply Voltage
VCC
Data Input Voltage
VI
Differential Input Voltage
Output Current
Typ.
Max.
Unit
100
°C
260
°C
10
sec.
-0.5
7.0
V
-0.5
VCC
V
VD
1.4
V
IO
50
mA
Max.
Unit
Reference
Note 1
Recommended Operating Conditions
Parameter
Symbol
Min.
Typ.
Ambient Operating Temperature
TA
0
70
°C
Supply Voltage
VCC
4.5
5.5
V
Data Input Voltage – Low
VIL - VCC
-1.810
-1.475
V
Data Input Voltage – High
VIH - VCC
-1.165
-0.880
V
Data and Signal Detect Output Load
RL
Signaling Rate
fS
10
Parameter
Symbol
Min.
Typ.
Supply Current
ICC
145
Power Dissipation
PDISS
Threshold Voltage
VBB - VCC
Data Input Current – Low
IIL
Data Input Current – High
IIH
Reference
50
W
Note 2
125
mBd
Note 3
Figure 5
Max.
Unit
Reference
185
mA
Note 4
0.76
1.1
W
Note 7
-1.42
-1.3
-1.24
V
Note 5
-350
0
HFBR-1115TZ Transmitter Electrical Characteristics
(TA = 0° C to +70° C, VCC = 4.5 V to 5.5 V)
mA
14
350
mA
Typ.
Max.
Unit
Reference
HFBR-1115TZ Receiver Electrical Characteristics
(TA = 0° C to +70° C, VCC = 4.5 V to 5.5 V)
Parameter
Symbol
Supply Current
ICC
82
145
mA
Note 6
Power Dissipation
PDISS
0.3
0.5
W
Note 7
Data Output Voltage – Low
VOL - VCC
-1.840
-1.620
V
Note 8
Data Output Voltage – High
VOH - VCC
-1.045
-0.880
V
Note 8
Data Output Rise Time
tr
0.35
2.2
ns
Note 9
Data Output Fall Time
tf
0.35
2.2
ns
Note 9
Signal Detect Output Voltage –
Low (De-asserted)
VOL - VCC
-1.620
V
Note 8
Signal Detect Output Voltage –
High (Asserted)
VOH - VCC
-0.880
V
Note 8
Signal Detect Output Rise Time
tr
0.35
2.2
ns
Note 9
Signal Detect Output Fall Time
tf
0.35
2.2
ns
Note 9
9
Min.
-1.840
-1.045
HFBR-1115TZ Transmitter Optical Characteristics
(TA = 0° C to +70° C, VCC = 4.5 V to 5.5 V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Reference
Output Optical Power
62.5/125 µm, NA = 0.275 fiber
PO, BOL
PO, EOL
-19
-20
-16.8
-14
-14
dBm avg.
Note 13
Output Optical Power
50/125 µm, NA = 0.20 fiber
PO, BOL
PO, EOL
dBm avg.
Note 13
0.03
-35
%
dB
Note 14
Optical Extinction Ratio
0.001
-50
Output Optical Power at Logic "O" State
PO("O")
Center Wavelength
lC
-45
dBm avg.
Note 15
1308
1380
nm
Note 16
Figure 9
Spectral Width – FWHM
∆l
137
170
nm
Note 16
Figure 9
Optical Rise Time
tr
0.6
1.0
3.0
ns
Note 16, 17
Figure 9, 10
Optical Fall Time
tf
0.6
2.1
3.0
ns
Note 16, 17
Figure 9, 10
Duty Cycle Distortion Contributed by
the Transmitter
DCD
0.02
0.6
ns p-p
Note 18
Figure 10
Data Dependent Jitter Contributed by
the Transmitter
DDJ
0.02
0.6
ns p-p
Note 19
Random Jitter Contributed by
the Transmitter
RJ
0
0.69
ns p-p
Note 20
1270
HFBR-2115TZ Receiver Optical and Electrical Characteristics
(TA = 0° C to +70° C, VCC = 4.5 V to 5.5 V)
Parameter
Symbol
Typ.
Max.
Unit
Reference
Input Optical Power
Minimum at Window Edge
PIN Min. (W)
Min.
-33.5
-31
dBm avg.
Note 21
Figure 11
Input Optical Power
Minimum at Eye Center
PIN Min. (C)
-34.5
-31.8
dBm avg.
Note 22
Figure 8
Input Optical Power Maximum
PIN Max.
-14
dBm avg.
Note 21
Operating Wavelength
l
1270
Duty Cycle Distortion Contributed by
the Receiver
DCD
Data Dependent Jitter Contributed by
the Receiver
-11.8
1380
nm
0.02
0.4
ns p-p
Note 10
DDJ
0.35
1.0
ns p-p
Note 11
Random Jitter Contributed by
the Receiver
RJ
1.0
2.14
ns p-p
Note 12
Signal Detect – Asserted
PA
PD +1.5 dB
-33
dBm avg.
Note 23, 24
Figure 9
Signal Detect – De-asserted
PD
-45
dBm avg.
Note 25, 26
Figure 12
Signal Detect – Hysteresis
PA – PD
1.5
2.4
dB
Figure 9
Signal Detect – Asserted Time (off to on)
AS_Max
0
55
100
ms
Note 23, 24
Figure 12
Signal Detect – De-asserted Time (on to off )
ANS_Max
0
110
350
ms
Note 25, 26
Figure 12
10
Notes:
1. This is the maximum voltage that can be applied across the
Differential Transmitter Data Inputs to prevent damage to the input
ESD protection circuit.
2. The outputs are terminated with 50 Ω connected to VCC - 2 V.
3. The specified signaling rate of 10 MBd to 125 MBd guarantees
operation of the transmitter and receiver link to the full conditions
listed in the FDDI Physical Layer Medium Dependent standard.
Specifically, the link bit-error-ratio will be equal to or better than
2.5 x 10-10 for any valid FDDI pattern. The transmitter section
of the link is capable of DC to 125 MBd. The receiver is internally
AC-coupled which limits the lower signaling rate to 10 MBd. For
purposes of definition, the symbol rate (Baud), also called signaling
rate, fs, is the reciprocal of the symbol time. Data rate (bits/sec) is
the symbol rate divided by the encoding factor used to encode the
data (symbols/bit).
4. The power supply current needed to operate the transmitter is
provided to differential ECL circuitry. This circuitry maintains a nearly
constant current flow from the power supply. Constant current
operation helps to prevent unwanted electrical noise from being
generated and conducted or emitted to neighboring circuitry.
5. This value is measured with an output load RL = 10 kΩ.
6. This value is measured with the outputs terminated into 50 Ω
connected to VCC - 2 V and an Input Optical Power level of -14 dBm
average.
7. The power dissipation value is the power dissipated in the
transmitter and receiver itself. Power dissipation is calculated as the
sum of the products of supply voltage and currents, minus the sum
of the products of the output voltages and currents.
8. This value is measured with respect to VCC with the output
terminated into 50 Ω connected to VCC - 2 V.
9. The output rise and fall times are measured between 20% and 80%
levels with the output connected to VCC - 2 V through 50 Ω.
10. Duty Cycle Distortion contributed by the receiver is measured at
the 50% threshold using an IDLE Line State, 125 MBd (62.5 MHz
square-wave), input signal. The input optical power level is -20 dBm
average. See Application Information–Data Link Jitter Section for
further information.
11. Data Dependent Jitter contributed by the receiver is specified with
the FDDI DDJ test pattern described in the FDDI PMD Annex A.5.
The input optical power level is -20 dBm average. See Application
Information – Data Link Jitter Section for further information.
12. Random Jitter contributed by the receiver is specified with an
IDLE Line State, 125 MBd (62.5 MHz square-wave), input signal.
The input optical power level is at the maximum of “PIN Min. (W).”
See Application Information – Data Link Jitter Section for further
information.
13.These optical power values are measured with the following
conditions:
• The Beginning of Life (BOL) to the Endof Life (EOL) optical power
degradation is typically 1.5 dB per the industry convention for
long wavelength LEDs. The actual degradation observed in
Avago Technologie’s 1300 nm LED products is < 1dB, as specified
in this data sheet.
• Over the specified operating voltage and temperature ranges.
• With HALT Line State, (12.5 MHz square-wave), input signal.
• At the end of one meter of noted optical fiber with cladding
modes removed. The average power value can be converted to
a peak power value by adding 3 dB. Higher output optical power
transmitters are available on special request.
14. The Extinction Ratio is a measure of the modulation depth of the
optical signal. The data “0” output optical power is compared to the
data “1” peak output optical power and expressed as a percentage.
With the transmitter driven by a HALT Line State (12.5 MHz
squarewave) signal, the average optical power is measured. The data
“1” peak power is then calculated by adding 3 dB to the measured
average optical power. The data “0” output optical power is found
by measuring the optical power when the transmitter is driven by a
logic “0” input. The extinction ratio is the ratio of the optical power at
the “0” level compared to the optical power at the “1” level expressed
as a percentage or in decibels.
11
15. The transmitter provides compliance with the need for Transmit_
Disable commands from the FDDI SMT layer by providing an Output
Optical Power level of < -45 dBm average in response to a logic “0”
input. This specification applies to either 62.5/125 μm or 50/125 μm
fiber cables.
16. This parameter complies with the FDDI PMD requirements for the
tradeoffs between center wavelength, spectral width, and rise/fall
times shown in Figure 9.
17. This parameter complies with the optical pulse envelope from the
FDDI PMD shown in Figure 10. The optical rise and fall times are
measured from 10% to 90% when the transmitter is driven by the
FDDI HALT Line State (12.5 MHz square-wave) input signal.
18. Duty Cycle Distortion contributed by the transmitter is measured
at a 50% threshold using an IDLE Line State, 125 MBd (62.5 MHz
square-wave), input signal. See Application Information – Data Link
Jitter Performance Section of this data sheet for further details.
19. Data Dependent Jitter contributed by the transmitter is specified
with the FDDI test pattern described in FDDI PMD Annex A.5. See
Application Information – Data Link Jitter Performance Section of
this data sheet for further details.
20. Random Jitter contributed by the transmitter is specified with an
IDLE Line State, 125 MBd (62.5 MHz square-wave), input signal. See
Application Information – Data Link Jitter Performance Section of
this data sheet for further details.
21. This specification is intended to indicate the performance of the
receiver when Input Optical Power signal characteristics are present
per the following definitions. The Input Optical Power dynamic
range from the minimum level (with a window timewidth) to the
maximum level is the range over which the receiver is guaranteed to
provide output data with a Bit-Error-Ratio (BER) better than or equal
to 2.5 x 10-10.
• At the Beginning of Life (BOL).
• Over the specified operating voltage and temperature ranges.
• Input symbol pattern is the FDDI test pattern defined in FDDI
PMD Annex A.5 with 4B/5B NRZI encoded data that contains a
duty-cycle base-line wander effect of 50 kHz. This sequence
causes a near worst-case condition for intersymbol interference.
• Receiver data window time-width is 2.13 ns or greater and
centered at midsymbol. This worst-case window timewidth is
the minimum allowed eyeopening presented to the FDDI PHY
PM_Data indication input (PHY input) per the example in FDDI
PMD Annex E. This minimum window time-width of 2.13 ns is
based upon the worst-case FDDI PMD Active Input Interface
optical conditions for peak-to-peak DCD (1.0 ns), DDJ (1.2 ns) and
RJ (0.76 ns) presented to the receiver.
To test a receiver with the worst-case FDDI PMD Active Input jitter
condition requires exacting control over DCD, DDJ, and RJ jitter
components that is difficult to implement with production test
equipment. The receiver can be equivalently tested to the worstcase FDDI PMD input jitter conditions and meet the minimum
output data window time-width of 2.13 ns. This is accomplished by
using a nearly ideal input optical signal (no DCD, insignificant DDJ
and RJ) and measuring for a wider window time-width of 4.6 ns.
This is possible due to the cumulative effect of jitter components
through their superposition (DCD and DDJ are directly additive
and RJ components are rms additive). Specifically, when a nearly
ideal input optical test signal is used and the maximum receiver
peak-topeak jitter contributions of DCD (0.4 ns), DDJ (1.0 ns), and
RJ (2.14 ns) exist, the minimum window time-width becomes
8.0 ns – 0.4 ns – 1.0 ns – 2.14 ns = 4.46 ns, or conservatively 4.6 ns.
This wider window time-width of 4.6 ns guarantees the FDDI PMD
Annex E minimum window time-width of 2.13 ns under worst-case
input jitter conditions to the Avago Technologies’ receiver.
22. All conditions of Note 21 apply except that the measurement is
made at the center of the symbol with no window time-width.
23. This value is measured during the transition from low to high levels
of input optical power.
24. The Signal Detect output shall be asserted, logic-high (VOH), within
100 μs after a step increase of the Input Optical Power. The step
will be from a low Input Optical Power, ≤ -45 dBm, into the range
between greater than PA, and -14 dBm. The BER of the receiver
output will be 10-2 or better during the time, LS_Max (15 μs) after
Signal Detect has been asserted. See Figure 12 for more information.
25. This value is measured during the transition from high to low levels
of input optical power. The maximum value will occur when the
input optical power is either -45 dBm average or when the input
optical power yields a BER of 10-2 or better, whichever power is
higher.
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26. Signal Detect output shall be deasserted, logic-low (VOL), within
350 μs after a step decrease in the Input Optical power from a level
which is the lower of -31 dBm or PD + 4 dB (PD is the power level at
which Signal Detect was de-asserted), to a power level of -45 dBm
or less. This step decrease will have occurred in less than 8 ns. The
receiver output will have a BER of 10-2 or better for a period of 12
μs or until signal detect is de-asserted. The input data stream is the
Quiet Line State. Also, Signal Detect will be de-asserted within a
maximum of 350 μs after the BER of the receiver output degrades
above 10-2 for an input optical data stream that decays with a
negative ramp function instead of a step function. See Figure 12 for
more information.
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Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved.
AV01-0151EN - July 11, 2013