AZP94 PECL/ECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs www.azmicrotek.com FEATURES DESCRIPTION • Selectable Divide Ratio • Selectable Enable Polarity and Threshold (CMOS or PECL) • Tristate Compatible Outputs • Input Buffer Powers Down when Disabled • High Bandwidth o 1.5+ GHz (÷1) o 3.0+ GHz (÷2) • -145 dBc/Hz (÷1) Typical Noise Floor • -151 dBc/Hz (÷2) Typical Noise Floor The AZP94 is a ÷1 or ÷2 clock generation part specifically designed to accommodate Colpitts or Pierce based oscillators. The tristate compatible outputs allow for on-the-fly switching of multiple oscillators on a common bus. Other features are incorporated to reduce board components. A voltage reference and input biasing allows for easy oscillator interface. The AZP94 provides a ÷ 2 mode of operation for more frequency options and is selectable with a single connection. A selectable enable is also provided which doubles as a reset when the AZP94 is in ÷2 mode. With a single connection, the enable can be selected to operate as active high or active low. BLOCK DIAGRAM APPLICATIONS • Colpitts or Pierce based oscillators • Multiple oscillators on a common bus PACKAGE AVAILABILITY • Part Number (PN) AZP94NAG 1 MLP8 o Green/RoHS Compliant/Pb-Free Package Marking MLP8 J4G <Date Code>2 1 Tape & Reel - Add 'R1' at end of PN for 7in (1k parts), 'R2' (2.5k) for 13in 2 See www.azmicrotek.com for date code format www.azmicrotek.com +1-480-962-5881 Request a Sample 1630 S Stapley Dr, Suite 127 Mesa, AZ 85204 USA May 2012, Rev 2.0 Arizona Microtek, Inc. AZP94 PECL/ECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs PIN DESCRIPTION AND CONFIGURATION Table 1 - Pin Description Pin 1 2 3 4 5 6 7 8 9 Name EN-SEL D VBB EN DIV-SEL Q ¯ Q VCC Type Input Input Input Input Input Output Output Power Function Enable Polarity Select Data Input Reference Voltage Output Enable Divide Select Inverted PECL Output PECL Output Positive Supply VEE Power Negative Supply EN-SEL 1 8 VCC D 2 7 Q Q VEE VBB 3 6 EN 4 5 DIV-SEL Figure 1 - Pin Configuration www.azmicrotek.com +1-480-962-5881 Request a Sample 2 May 2012, Rev 2.0 Arizona Microtek, Inc. AZP94 PECL/ECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs ENGINEERING NOTES FUNCTIONALITY The AZP94 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function. The divide ratio is selected with the DIV-SEL pin/pad. When DIV-SEL is open (NC), the AZP94 functions as a standard receiver. If DIV-SEL is connected to VEE, it functions as a ÷2 divider. Enable (EN) functionality is selected with the EN-SEL pin/pad which has three valid states: open (NC), VEE, or connected to VEE via a 20kΩ ± 20% resistor. Leaving EN-SEL open or connecting it to VEE allows the EN pin/pad to function as an active high CMOS/TTL enable. When EN-SEL is open, an internal 75kΩ pull-up resistor is selected which enables the outputs whenever EN is left open. When EN-SEL is connected to VEE, an internal 75kΩ pull-down resistor is selected which disables the outputs whenever EN is left open. Connecting the EN-SEL to VEE with a 20kΩ resistor will allow the EN pin/pad to function as an active low PECL/ECL enable with an internal 75kΩ pull-down resistor. In this mode, outputs are enabled when EN is left open (NC). The default logic condition can be overridden by connecting the EN to VCC with an external resistor of ≤20kΩ. If the enable signal is CMOS (rail-to-rail) and the logic sense is active low (EN-SEL connected to VEE with a 20kΩ resistor), the EN pin/pad voltage swing must be reduced using two external resistors. Contact the factory for details. When the AZP94 is disabled, the Q and Q ¯ outputs are forced LOW and the input buffer is powered down to minimize feed through. This feature allows tristate compatible parallel output connections. Multiple AZP94 chip outputs can be wired together. Since both outputs are forced LOW in the disable mode, an enabled AZP94 can drive the output lines without interference from the unselected units. In addition, the AZP94 can be used in parallel connection with PECL/ECL parts whose outputs are high impedance when disabled. The EN pin/pad also functions as a reset when the ÷2 mode is selected. In the ÷2 mode, the counter resets when the outputs are disabled. The AZP94 provides a VBB with an 1880Ω internal bias resistor from D to VBB. This feature allows AC coupling with minimal external components. The VBB pin supports 1.5mA sink/source current and should be bypassed to ground or VCC with a 0.01 µF capacitor. TRISTATE COMPATIBLE OPERATION The outputs of the AZP94 are emitter followers as shown in the left side of Figure 2. When a part is disabled, both outputs are set in the LOW state. This allows a HIGH output from an enabled part to override a disabled output and pull the combined line HIGH as seen in the right hand side of Figure 2. When the enabled part output is LOW, the combined line remains LOW. If all connected AZP94 parts are disabled, both output lines will be in the LOW state. As another feature, while disabled, the input buffer is powered down to minimize feed through. www.azmicrotek.com +1-480-962-5881 Request a Sample 3 May 2012, Rev 2.0 Arizona Microtek, Inc. AZP94 VCC PECL/ECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs L L H H L L H H L L H L L L Q Q DISABLED Internal Drive ENABLED Q,Q AZP94 Transistor Output Stage VT DISABLED Figure 2 - Typical Tristate Operation Table 2 - Divide Truth Table ÷Ratio ÷1 ÷2 DIV-SEL NC VEE1 1 DIV-SEL connection must be ≤1Ω. Table 3 - Enable Truth Table EN-SEL NC VEE 20kΩ to VEE EN CMOS Low or VEE CMOS High, VCC or NC CMOS Low, VEE or NC CMOS High or VCC PECL Low, VEE or NC PECL High or VCC Q Low Data Low Data Low Data Q ¯ Low Data Low Data Low Data Figure 3 illustrates the timing sequences for the AZP94 in the ÷1 mode which is determined by leaving the DIV-SEL open (NC). It also illustrates the enable in the active High mode being controlled by a CMOS signal. This mode is determined by leaving the EN-SEL open (NC). www.azmicrotek.com +1-480-962-5881 Request a Sample 4 May 2012, Rev 2.0 Arizona Microtek, Inc. AZP94 PECL/ECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs D EN (CMOS) Q Q Figure 3 - Timing Diagram Figure 4 illustrates the timing sequences for the AZP94 in the ÷2 mode which is determined by connecting the DIV-SEL to VEE. It also illustrates the enable in the active Low mode being controlled by a PECL signal. This mode is determined by connecting the EN-SEL to VEE via 20kΩ resistor. D EN (PECL) Q Q Figure 4 - Timing Diagram 1000 900 VOUTpp(mV) 800 ÷2 700 600 ÷1 500 400 300 200 0 1000 2000 3000 4000 5000 6000 Input Frequency (MHz) Figure 5 - Typical Large Signal Output Swing Measured with 750mv D input, Q/Q ¯ each terminated to VCC-2V via 50 Ω resistors www.azmicrotek.com +1-480-962-5881 Request a Sample 5 May 2012, Rev 2.0 Arizona Microtek, Inc. AZP94 PECL/ECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs PERFORMANCE DATA Table 4 - Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which device life may be impaired. Symbol Characteristic Condition Rating Unit VCC PECL Power Supply VEE = 0V 0 to + 6.0 V VI_PECL PECL Input Voltage VEE = 0V 0 to + 6.0 V VEE ECL Power Supply VCC = 0V -6.0 to 0 V VI_ECL ECL Input Supply V VCC = 0V -6.0 to 0 Continuous 50 Surge 100 IHGOUT Output Current mA TA Operating Temperature Range - -40 to +85 °C TSTG Storage Temperature Range - -65 to +150 °C ESDHBM Human Body Model Electro Static Discharge - 2500 V ESDMM Machine Model Electro Static Discharge - 200 V ESDCDM Charged Device Model Electro Static Discharge - 2000 V Table 5 - 100K ECL DC Characteristics 100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND) -40°C Symbol Characteristic VOH Output HIGH Voltage1 VOL 1 0°C 25°C 85°C Unit Min Max Min Max Min Max Min Max -1085 -880 -1025 -880 -1025 -880 -1025 -880 mV -1900 -1555 -1900 -1620 -1900 -1620 -1900 -1620 mV -1165 -740 -1165 -740 -1165 -740 -1165 -740 mV Input HIGH Voltage EN (CMOS)3 VEE+ 2000 VCC VEE+ 2000 VCC VEE+ 2000 VCC VEE+ 2000 VCC mV Input LOW Voltage D,EN (ECL)2 -1900 -1475 -1900 -1475 -1900 -1475 -1900 -1475 mV Input LOW Voltage EN (CMOS)3 VEE VEE+ 800 VEE VEE+ 800 VEE VEE+ 800 VEE VEE+ 800 mV VBB Reference Voltage -1390 -1250 -1390 -1250 -1390 -1250 -1390 -1250 mV IIH Input HIGH Current EN 150 µA Output LOW Voltage Input HIGH Voltage D,EN (ECL) VIH VIL Input LOW Current EN (ECL) IIL 150 2 Input LOW Current EN (CMOS) 1 IEE Power Supply Current 1 2 3 2 3 150 150 0.5 0.5 0.5 0.5 -150 -150 -150 -150 34 34 34 µA 37 mA Specified with each output terminated through 50Ω resistors to VCC - 2V. EN-SEL connected to VEE through a 20kΩ resistor EN-SEL connected to VEE or left open (NC) www.azmicrotek.com +1-480-962-5881 Request a Sample 6 May 2012, Rev 2.0 Arizona Microtek, Inc. AZP94 PECL/ECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs Table 6 - 100K LVPECL DC Characteristics 100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V) -40°C Symbol Characteristic VOH Output HIGH Voltage1,2 VOL 1,2 Output LOW Voltage VIH VIL 85°C Max Min Max Min Max Min Max 2215 2420 2275 2420 2275 2420 2275 2420 mV 1745 1400 1680 1400 1680 1400 1680 mV Input HIGH Voltage D,EN (ECL) 2135 2560 2135 2560 2135 2560 2135 2560 mV Input HIGH Voltage EN (CMOS) 4 2000 VCC 2000 VCC 2000 VCC 2000 VCC mV Input LOW Voltage D,EN (ECL) 3 1400 1825 1400 1825 1400 1825 1400 1825 mV Input LOW Voltage EN (CMOS) 4 GND 800 GND 800 GND 800 GND 800 mV 1910 2050 1910 2050 1910 2050 1910 2050 mV 150 µA 1 IIH Input HIGH Current EN 150 Input LOW Current EN (ECL) 3 Input LOW Current EN (CMOS) 4 150 150 0.5 0.5 0.5 0.5 -150 -150 -150 -150 2 Power Supply Current 34 34 For supply voltages other than 3.3V, use the ECL table values and ADD supply voltage value 2 Specified with each output terminated through 50Ω resistors to VCC - 2V. EN-SEL connected to VEE through a 20kΩ resistor EN-SEL connected to VEE or left open (NC) 4 µA 34 1 3 Unit Min 1400 Reference Voltage IEE 25°C 3 VBB IIL 0°C 37 mA Table 7 - 100K PECL DC Characteristics 100K PECL DC Characteristics (VEE = GND, VCC = +5.0V) -40°C Symbol Characteristic VOH Output HIGH Voltage1,2 VOL 1,2 Output LOW Voltage VIH Max Min Max Min Max Min Max 3915 4120 3975 4120 3975 4120 3975 4120 mV 3100 3380 3100 3380 3100 3380 mV Input HIGH Voltage D,EN (ECL) 3835 4260 3835 4260 3835 4260 3835 4260 mV Input HIGH Voltage EN (CMOS) 4 2000 VCC 2000 VCC 2000 VCC 2000 VCC mV 3 3100 3525 3100 3525 3100 3525 3100 3525 mV Input LOW Voltage EN (CMOS)4 GND 800 GND 800 GND 800 GND 800 mV 3610 3750 3610 3750 3610 3750 3610 3750 mV 150 µA 1 IIH Input HIGH Current EN Input LOW Current EN (ECL) 150 3 Input LOW Current EN (CMOS) 2 Power Supply Current 4 150 150 0.5 0.5 0.5 0.5 -150 -150 -150 -150 34 34 34 1 For supply voltages other than 3.3V, use the ECL table values and ADD supply voltage value 2 Specified with each output terminated through 50Ω resistors to VCC - 2V. EN-SEL connected to VEE through a 20kΩ resistor EN-SEL connected to VEE or left open (NC) 3 4 Unit Min 3445 Reference Voltage IEE 85°C 3100 VBB IIL 25°C 3 Input LOW Voltage D,EN (ECL) VIL 0°C www.azmicrotek.com +1-480-962-5881 Request a Sample µA 37 mA 7 May 2012, Rev 2.0 Arizona Microtek, Inc. AZP94 PECL/ECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs Table 8 - AC Characteristics AC Characteristics (VEE = -3.0V to -5.5V; VCC=GND or VEE=GND; VCC = +3.0V to +5.5V) Symbol -40°C Characteristic Min Typ 0°C Max Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit Propagation Delay D to Q/Q ¯1 EN to QHG/QbHG1,2 Duty Cycle Skew3 tPLH/tPHL tSKEW Vpp (AC) 4 Input Swing 5 450 450 450 450 ps 3000 3000 3000 3000 ps 20 ps 20 5 20 5 20 5 150 1000 150 1000 150 1000 150 1000 mV 100 240 100 240 100 240 100 240 ps 1 Output Rise/Fall (20% - 80%) tr/tf 1 2 Specified with each output terminated through 50Ω resistors to VCC - 2V. Specified from 50% EN input edge to VOH min to VOL max of the Q/Q ¯ outputs 3 Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device. 4 VPP is the peak-to-peak differential input swing for which AC parameters are guaranteed. www.azmicrotek.com +1-480-962-5881 Request a Sample 8 May 2012, Rev 2.0 Arizona Microtek, Inc. AZP94 PECL/ECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs PACKAGE DIAGRAM MLP8 Green/RoHS compliant/Pb-Free MSL=1 Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part. www.azmicrotek.com +1-480-962-5881 Request a Sample 9 May 2012, Rev 2.0