AZM AZP94_09

ARIZONA MICROTEK, INC.
AZP94
ECL/PECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs
FEATURES
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PACKAGE AVAILABILITY
Green and RoHS Compliant / Lead (Pb)
PACKAGE
PART NO.
MARKING
NOTES
Free Package Available
MLP 8 (2x2) Green
J4G
3.0V to 5.5V Operation
/ RoHS Compliant
AZP94NAG
1,2
<Date Code>
Selectable Divide Ratio
/ Lead (Pb) Free
Selectable Enable Polarity and
1
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Threshold (CMOS/TTL or PECL)
Tape & Reel.
2
Date code format: “Y” for year followed by “WW” for week.
Tristate Compatible Outputs
Input Buffer Powers Down when
Disabled
Selectable Input Biasing
High Bandwidth for ≥1GHz
Available in a MLP 8 (2x2) Package
S Parameter and IBIS Model Files
Available on Arizona Microtek Website
DESCRIPTION
The AZP94 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function. The divide ratio is
selected with the DIV-SEL pin/pad. When DIV-SEL is open (NC), the AZP94 functions as a standard receiver. If
DIV-SEL is connected to VEE, it functions as a ÷2 divider.
Enable (EN) functionality is selected with the EN-SEL pin/pad which has three valid states: open (NC), VEE, or
connected to VEE via a 20kΩ ± 20% resistor. Leaving EN-SEL open or connecting it to VEE allows the EN pin/pad to
function as an active high CMOS/TTL enable. When EN-SEL is open, an internal 75kΩ pull-up resistor is selected
which enables the outputs whenever EN is left open. When EN-SEL is connected to VEE, an internal 75kΩ pulldown resistor is selected which disables the outputs whenever EN is left open.
Connecting the EN-SEL to VEE with a 20kΩ resistor will allow the EN pin/pad to function as an active low
PECL/ECL enable with an internal 75kΩ pull-down resistor. In this mode, outputs are enabled when EN is left open
(NC). The default logic condition can be overridden by connecting the EN to VCC with an external resistor of
≤20kΩ. If the enable signal is CMOS (rail-to-rail) and the logic sense is active low (EN-SEL connected to VEE with
a 20kΩ resistor), the EN pin/pad voltage swing must be reduced using two external resistors. Contact the factory for
details.
When the AZP94 is disabled, the Q and Q
¯ outputs are forced LOW and the input buffer is powered down to
minimize feed through. This feature allows tristate compatible parallel output connections. Multiple AZP94 chip
outputs can be wired together. Since both outputs are forced LOW in the disable mode, an enabled AZP94 can drive
the output lines without interference from the unselected units. In addition, the AZP94 can be used in parallel
connection with PECL/ECL parts whose outputs are high impedance when disabled.
The EN pin/pad also functions as a reset when the ÷2 mode is selected. In the ÷2 mode, the counter resets when
the outputs are disabled.
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (623) 505-2414
www.azmicrotek.com
AZP94
MLP 8, 2x2 mm Package (AZP94NA)
The AZP94NA provides a VBB with an 1880Ω internal bias resistor from D to VBB. This feature allows AC
coupling with minimal external components. The VBB pin supports 1.5mA sink/source current and should be
bypassed to ground or VCC with a 0.01 μF capacitor.
TYPICAL TRISTATE COMPATIBLE OPERATION
Tristate Compatible Operation
The outputs of the AZP94 are emitter followers as shown in the left side of the drawing. When a part is
disabled, both outputs are set in the LOW state. This allows a HIGH output from an enabled part to override a
disabled output and pull the combined line HIGH as seen in the right hand side of the drawing. When the enabled
part output is LOW, the combined line remains LOW.
If all connected AZP94 parts are disabled, both output lines will be in the LOW state.
NOTE: The specifications in the ECL/PECL tables are valid when thermal equilibrium has been established.
June 2009 Rev - 6
www.azmicrotek.com
2
AZP94
SIGNAL DESCRIPTION
PIN/PAD
D
Q/Q
¯
VBB/D
¯
BIAS
EN
EN-SEL
DIV-SEL
VEE
VCC
FUNCTION
Data Input
Data Outputs
Reference Voltage Output
Input Bias Return
Enable/Reset Input
Enable Logic Select
Divide Ratio Select
Negative Supply
Positive Supply
ENABLE TRUTH TABLE
EN-SEL
EN
NC
CMOS Low or VEE1
NC
CMOS High, VCC or NC
VEE
CMOS Low, VEE or NC1
VEE
CMOS High or VCC
PECL Low, VEE or NC1
20kΩ to VEE
PECL High or VCC
20kΩ to VEE
1
Counter Reset for ÷2 Ratio
DIVIDE TRUTH TABLE
Q
Low
Data
Low
Data
Data
Low
Q
¯
Low
Data
Low
Data
Data
Low
TIMING DIAGRAM
June 2009 Rev - 6
www.azmicrotek.com
3
DIV-SEL
DIVIDE
RATIO
NC
÷1
VEE1
÷2
1
DIV-SEL connection must
be ≤1Ω.
AZP94
AZP94NA
MLP 8, 2x2 mm
TOP VIEW
June 2009 Rev - 6
www.azmicrotek.com
4
AZP94
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
VCC
VI
VEE
VI
IHGOUT
TA
TSTG
Characteristic
PECL Power Supply
(VEE = 0V)
PECL Input Voltage
(VEE = 0V)
ECL Power Supply
(VCC = 0V)
ECL Input Voltage
(VCC = 0V)
Output Current
— Continuous
— Surge
Operating Temperature Range
Storage Temperature Range
Rating
0 to +6.0
0 to +6.0
-6.0 to 0
-6.0 to 0
50
100
-40 to +85
-65 to +150
Unit
Vdc
Vdc
Vdc
Vdc
mA
°C
°C
100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND)
Symbol
VOH
VOL
VIH
VIL
VBB
IIH
IIL
IEE
1.
2.
3.
-40°C
Characteristic
1
Min
-1085
-1900
0°C
Max
-880
-1555
Min
-1025
-1900
Output HIGH Voltage
Output LOW Voltage1
Input HIGH Voltage
-1165
-740
D/D
¯ , EN (ECL)2
-1165
VCC
EN (CMOS)3 VEE+2000
VEE+2000
Input LOW Voltage
-1900
-1475
-1900
D/D
¯ , EN (ECL)2
VEE
VEE + 800
VEE
EN (CMOS)3
Reference Voltage
-1390
-1250
-1390
Input HIGH Current EN
150
Input LOW Current
0.5
0.5
EN (ECL)2
-150
-150
EN (CMOS)3
Power Supply Current1
34
Specified with outputs terminated through 50Ω resistors to VCC - 2V.
EN-SEL connected to VEE through a 20kΩ resistor
EN-SEL connected VEE or left open (NC)
25°C
85°C
Unit
Max
-880
-1620
Min
-1025
-1900
Max
-880
-1620
Min
-1025
-1900
Max
-880
-1620
-740
VCC
-1165
VEE+2000
-740
VCC
-1165
VEE+2000
-740
VCC
mV
-1475
VEE + 800
-1250
150
-1900
VEE
-1390
-1475
VEE + 800
-1250
150
-1900
VEE
-1390
-1475
VEE + 800
-1250
150
mV
0.5
-150
mV
μA
μA
0.5
-150
34
mV
mV
34
37
mA
100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V)
Symbol
VOH
VOL
VIH
VIL
VBB
IIH
IIL
IEE
1.
2.
3.
4.
-40°C
Characteristic
1,2
Min
2215
1400
0°C
Max
2420
1745
Min
2275
1400
25°C
Max
2420
1680
Output HIGH Voltage
Output LOW Voltage1,2
Input HIGH Voltage1
2135
2560
2135
2560
D/D
¯ , EN (PECL)3
EN (CMOS)4
2000
VCC
2000
VCC
Input LOW Voltage1
1400
1825
1400
1825
D/D
¯ , EN (PECL)3
EN (CMOS)4
GND
800
GND
800
Reference Voltage1
1910
2050
1910
2050
Input HIGH Current EN
150
150
Input LOW Current
0.5
0.5
EN (PECL)3
-150
-150
EN (CMOS)4
Power Supply Current2
34
34
For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value.
Specified with outputs terminated through 50Ω resistors to VCC - 2V.
EN-SEL connected to VEE through a 20kΩ resistor
EN-SEL connected VEE or left open (NC)
June 2009 Rev - 6
www.azmicrotek.com
5
85°C
Unit
Min
2275
1400
Max
2420
1680
Min
2275
1400
Max
2420
1680
2135
2000
2560
VCC
2135
2000
2560
VCC
mV
1400
GND
1910
1825
800
2050
150
1400
GND
1910
1825
800
2050
150
mV
0.5
-150
mV
μA
μA
0.5
-150
34
mV
mV
37
mA
AZP94
100K PECL DC Characteristics (VEE = GND, VCC = +5.0V)
Symbol
VOH
VOL
VIH
VIL
VBB
IIH
IIL
IEE
1.
2.
3.
4.
-40°C
Characteristic
0°C
Min
3915
3100
1,2
Max
4120
3445
Min
3975
3100
25°C
Max
4120
3380
Output HIGH Voltage
Output LOW Voltage1,2
Input HIGH Voltage1
3835
4260
3835
4260
D/D
¯ , EN (PECL)3
EN (CMOS)4
2000
VCC
2000
VCC
Input LOW Voltage1
3100
3525
3100
3525
D/D
¯ , EN (PECL)3
EN (CMOS)4
GND
800
GND
800
1
Reference Voltage
3610
3750
3610
3750
Input HIGH Current EN
150
150
Input LOW Current
0.5
0.5
EN (PECL)3
-150
-150
EN (CMOS)4
Power Supply Current2
34
34
For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value.
Specified with outputs terminated through 50Ω resistors to VCC - 2V.
EN-SEL connected to VEE through a 20kΩ resistor
EN-SEL connected VEE or left open (NC)
85°C
Unit
Min
3975
3100
Max
4120
3380
Min
3975
3100
Max
4120
3380
3835
2000
4260
VCC
3835
2000
4260
VCC
mV
3100
GND
3610
3525
800
3750
150
3100
GND
3610
3525
800
3750
150
mV
0.5
-150
mV
mV
mV
μA
μA
0.5
-150
34
37
mA
AC Characteristics (VEE = -3.0V to -5.5V; VCC = GND or VEE = GND; VCC = +3.0V to +5.5V)
Symbol
Characteristic
Min
-40°C
Typ
Max
Min
0°C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Propagation Delay
450
450
450
(SE)
D to Q/Q
¯ Outputs1
3000
3000
3000
EN to Q/Q
¯ Outputs1,2
tSKEW
Duty Cycle Skew3
(SE)
5
20
5
20
5
20
5
VPP (AC) Differential Input Swing4
150
1000
150
1000
150
1000
150
Output Rise/Fall1
tr / t f
100
240
100
240
100
240
100
(20% - 80%)
1.
Specified with outputs terminated through 50Ω resistors to VCC - 2V.
¯ outputs
2.
Specified from 50% EN input edge to VOH min or VOL max of the Q/Q
3.
Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.
4.
The peak-to-peak differential input swing is the range for which AC parameters are guaranteed. The device has a voltage gain of ≈ 100.
tPLH / tPHL
AC PP INPUT
D
D
V PP (AC)
June 2009 Rev - 6
www.azmicrotek.com
6
Max
Unit
450
3000
20
1000
ps
ps
mV
240
ps
AZP94
Typical Large Signal Outputs, Q/Q
¯
1000
900
800
700
VOUTpp(mV)
600
500
400
300
200
100
0
0
500
1000
1500
2000
2500
3000
3500
4000
FREQUENCY (MHz)
Measured with 750mv D input, Q/Q
¯ each terminated to VCC-2V via 50 Ω resistors.
June 2009 Rev - 6
www.azmicrotek.com
7
AZP94
PACKAGE DIAGRAM
MLP 8 2x2mm
Pin 1 Dot
By Marking
2.000±0.050
MLP 8
(2x2mm)
2.000±0.050
TOP VIEW
Pin 1 Identification
R0.100 TYP
0.350±0.050
0.250±0.050
0.500 bsc
8
1
7
6
2 1.200±0.050
exp. pad
3
5
4
0.600±0.050
exp. pad
BOTTOM VIEW
0.750±0.050
0.000-0.050
1
2
SIDE VIEW
Note: All dimensions are in mm
June 2009 Rev - 6
www.azmicrotek.com
8
3 4
0.203±0.025
1.750
Ref.
AZP94
TAPE & REEL PACKAGING
MLP 8 2x2mm
Direction of Travel
Package
MLP 8 (2x2mm)
June 2009 Rev - 6
Suffix
R1
R2
Reel Diameter
7”
13”
Quantity
1000
2500
www.azmicrotek.com
9
Carrier Tape Width
8mm
8mm
Carrier Tape Pitch
4mm
4mm
AZP94
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc.
makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona
Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license
rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly
or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.
June 2009 Rev - 6
www.azmicrotek.com
10