OPA454 SBOS391 – DECEMBER 2007 High-Voltage (100V), High-Current (50mA) OPERATIONAL AMPLIFIERS, G = 1 Stable FEATURES DESCRIPTION 1 • WIDE POWER-SUPPLY RANGE: ±5V (10V) to ±50V (100V) • HIGH OUTPUT LOAD DRIVE: IO > ±50mA • WIDE OUTPUT VOLTAGE SWING: 1V to Rails • INDEPENDENT OUTPUT DISABLE OR SHUTDOWN • WIDE TEMPERATURE RANGE: –40°C to +85°C • PACKAGES: SO and HSOP PowerPAD™ 23 APPLICATIONS • • • • • • • • TEST EQUIPMENT AVALANCHE PHOTODIODE: High-V Current Sense PIEZOELECTRIC CELLS TRANSDUCER DRIVERS SERVO DRIVERS AUDIO AMPLIFIERS HIGH-VOLTAGE COMPLIANCE CURRENT SOURCES GENERAL HIGH-VOLTAGE REGULATORS/POWER The OPA454 is a low-cost operational amplifier with high voltage (100V) and relatively high current drive (25mA). It is unity-gain stable and has a gain-bandwidth product of 2.5MHz. The OPA454 is internally protected against over-temperature conditions and current overloads. It is fully specified to perform over a wide power-supply range of ±5V to ±50V or on a single supply of 10V to 100V. The status flag is an open-drain output that allows it to be easily referenced to standard low-voltage logic circuitry. This high-voltage op amp provides excellent accuracy, wide output swing, and is free from phase inversion problems that are often found in similar amplifiers. The output can be independently disabled using the Enable/Disable Pin that has its own common return pin to allow easy interface to low-voltage logic circuitry. This disable is accomplished without disturbing the input signal path, not only saving power but also protecting the load. Featured in a small exposed metal pad package, the OPA454 is easy to heatsink over the extended industrial temperature range, –40°C to +85°C. Status Flag Table 1. OPA454 RELATED PRODUCTS V+ PRODUCT Enable/Disable (E/D) OPA445 -IN OPA454 VO +IN Enable/Disable Common (E/D Com) V- (1) (1) DESCRIPTION 80V, 15mA OPA452 80V, 50mA OPA547 60V, 750mA OPA548 60V, 3A OPA549 60V, 9A OPA551 60V, 200mA OPA567 5V, 2A OPA569 5V, 2.4A The OPA445 is pin-compatible with the OPA445, except in applications using the offset trim, and NC pins other than open. 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated OPA454 www.ti.com SBOS391 – DECEMBER 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) (1) (2) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING OPA454 SO-8 DDA OPA454 OPA454 HSOP-20 (2) DWD OPA454 For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Available Q2, 2008. ABSOLUTE MAXIMUM RATINGS (1) Supply Voltage OPA454 UNIT 120 V (V–) – 0.3 to (V+) + 0.3 V ±10 mA VS = (V+) – (V–) Signal Input Terminals, Voltage (2) Signal Input Terminals, Current (2) E/D to E/D Com Voltage +5.5 Output Short-Circuit (3) ISC Operating Temperature TJ –55 to +125 °C –55 to +125 °C +150 °C Human Body Model (HBM) 4000 V Charged Device Model (CDM) 500 V Machine Model (MM) 150 V Storage Temperature Junction Temperature ESD Rating: (1) (2) (3) V Continuous TJ Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3V beyond the supply rails should be current limited to 10mA or less. Short-circuit to ground. PIN ASSIGNMENTS DDA PACKAGE SO-8 PowerPAD (TOP VIEW) E/D Com (Enable/Disable Common) DWD PACKAGE(1) HSOP-20 PowerPAD (TOP VIEW) 1 8 E/D (Enable/Disable) 7 V+ V- 1 20 V- (3) 2 19 NC (3) 3 18 NC 17 Status Flag 16 VOUT 15 V+ 7 14 NC 8 13 NC E/D Com (Enable/Disable Common) 9 12 E/D (Enable/Disable) V- 10 11 V- (1) -IN (1) 2 2 +IN 3 V- 4 PowerPAD Heat Sink (Located on bottom side) NC 6 OUT 5 Status Flag PowerPAD is internally connected to V–. Soldering the PowerPAD to the PCB is always required, even with applications that have low power dissipation. NC V- 4 +IN 5 (3) 6 (3) (3) (2) NC -IN NC (3) PowerPAD Heat Sink (Located on top side) (1) Available Q2, 2008. (2) PowerPAD is internally connected to V–. (3) NC = No internal connection Submit Documentation Feedback (3) (3) Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 OPA454 www.ti.com SBOS391 – DECEMBER 2007 ELECTRICAL CHARACTERISTICS: VS = ±50V Boldface limits apply over the specified temperature range, TA = –40°C to +85°C. At TP (1) = +25°C, RL = 4.8kΩ to mid-supply, VCM = VOUT = mid-supply, unless otherwise noted. OPA454 PARAMETER CONDITIONS MIN TYP MAX UNIT ±0.2 ±4 mV ±1.6 ±10 µV/°C 25 100 µV/V ±1.4 ±100 pA OFFSET VOLTAGE Input Offset Voltage vs Temperature VOS (2) vs Power Supply IO = 0 dVOS/dT PSRR VS = ±4V to ±60V, VCM = 0V INPUT BIAS CURRENT Input Bias Current IB vs Temperature See Typical Characteristics Input Offset Current IOS ±0.2 ±100 pA en 300 nV/√Hz 35 nV/√Hz NOISE Input Voltage Noise Density, f = 10Hz Input Voltage Noise Density, f = 10kHz f = 0.01Hz to 10Hz Current Noise Density, f = 1kHz in 15 µVPP 40 fA/√Hz INPUT VOLTAGE RANGE Common-Mode Voltage Range Common-Mode Rejection VCM CMRR Linear Operation (V–) + 2.5 See Note VS = ±50V, –25V ≤ VCM ≤ +25V 100 146 (3) (V+) – 2.5 V dB VS = ±50V, –45V ≤ VCM ≤ +45V 100 147 dB Over Temperature VS = ±50V, –25V ≤ VCM ≤ +25V 80 88 dB Over Temperature VS = ±50V, –45V ≤ VCM ≤ +45V 72 82 dB Differential 1013 || 10 Ω || pF Common-Mode 1013 || 9 Ω || pF 130 dB 112 dB 115 dB 106 dB 102 dB 84 dB INPUT IMPEDANCE OPEN-LOOP GAIN Open-Loop Voltage Gain (4) AOL (V–) + 1V < VO < (V+) – 1V, RL = 49kΩ, IO = ±1mA 100 (V–) + 1V < VO < (V+) – 1V, RL = 49kΩ, IO = ±1mA (V–) + 1V < VO < (V+) – 2V, RL = 4.8kΩ, IO = ±10mA 100 (V–) + 1V < VO < (V+) – 2V, RL = 4.8kΩ, IO = ±10mA (V–) + 2V < VO < (V+) – 3V, RL = 1880Ω, IO = ±25mA (V–) + 2V < VO < (V+) – 3V, RL = 1880Ω, IO = ±25mA (1) (2) (3) (4) 80 TP is the temperature of the leadframe die pad (exposed thermal pad) of the PowerPAD package. See typical characteristic curve, Offset Voltage Drift Production Distribution (Figure 14). Typical range is (V–) + 1.5V to (V+) – 1.5V. Measured using low-frequency (<10Hz) ±49V square wave. See typical characteristic curve, Current Limit vs Temperature (Figure 24). Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 3 OPA454 www.ti.com SBOS391 – DECEMBER 2007 ELECTRICAL CHARACTERISTICS: VS = ±50V (continued) Boldface limits apply over the specified temperature range, TA = –40°C to +85°C. At TP = +25°C, RL = 4.8kΩ to mid-supply, VCM = VOUT = mid-supply, unless otherwise noted. OPA454 PARAMETER CONDITIONS MIN TYP MAX UNIT FREQUENCY RESPONSE (5) Gain-Bandwidth Product GBW Slew Rate SR Small-Signal 2.5 MHz G = ±1, VO = 80V Step, RL = 3.27kΩ 13 V/µs 35 kHz Full-Power Bandwidth (6) Settling Time: ±0.1% (7) G = ±1, VO = 20V Step 3 µs Settling Time: ±0.01% (7) G = ±5 or ±10, VO = 80V Step 10 µs Total Harmonic Distortion + Noise (8) VS = +40.6V/–39.6V, G = ±1, f = 1kHz, VO = 77.2VPP 0.0008 % THD+N OUTPUT Voltage Output Swing From Rail (9) VO Continuous Current Output, dc RL = 49kΩ, AOL ≥ 100dB, IO = 1mA (V–) + 1 (V+) – 1 V RL = 4.8kΩ, AOL ≥ 100dB, IO = 10mA (V–) + 1 (V+) – 2 V RL = 1880Ω, AOL ≥ 80dB, IO = 26mA (V–) + 2 (V+) – 3 V Depends on Circuit Conditions Maximum Peak Current Output, Current Limit (10) See Figure 6 IO +120/–150 mA +140/–170 mA 200 pF See Figure 5 Ω Output Capacitance 18 pF Feedthrough Capacitance (11) 150 fF Enable → Disable 6 µs Disable → Enable 4 µs Over-Current Delay (13) 15 µs Over-Current Recovery Delay (13) 10 µs Alarm (status flag high) +150 °C Return to Normal Operation (status flag low) +130 Over Temperature Capacitive Load Drive (5) CLOAD Open-Loop Output Impedance RO Output Disabled STATUS FLAG PIN (Referenced to E/D Com) (12) Status Flag Delay Junction Temperature Output Voltage (5) TJ Normal Operation RL = 100Ω During Thermal Overdrive, Alarm (5) (6) (7) (8) (9) (10) (11) (12) (13) 4 °C E/D Com + 2 (V+) – 2.5 V V See Typical Characteristic curves. See typical characteristic curve, Maximum Output Voltage vs Frequency (Figure 12). See the Applications Information section, Settling Time. Supplies reduced to allow closer swing to rails due to test equipment limitations. See typical characteristic curve Total Harmonic Distortion + Noise vs Temperature (Figure 30 and Figure 31) for additional power levels. See typical characteristic curve, Output Voltage Swing vs Output Current (Figure 11). Measured using low-frequency (<10Hz) ±49V square wave. See typical characteristic curve, Current Limit vs Temperature (Figure 24). Measured using Figure 1. 100kΩ pull-up resistor to (V+). E/D common to (V–). Status flag indicates an over temperature or over-current condition. See Typical Characteristic curves for current limit behavior. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 OPA454 www.ti.com SBOS391 – DECEMBER 2007 ELECTRICAL CHARACTERISTICS: VS = ±50V (continued) Boldface limits apply over the specified temperature range, TA = –40°C to +85°C. At TP = +25°C, RL = 4.8kΩ to mid-supply, VCM = VOUT = mid-supply, unless otherwise noted. OPA454 PARAMETER CONDITIONS MIN Pin Open or Forced High TYP MAX UNIT E/D Com + 2.5 E/D Com + 5 V E/D Com E/D Com + 0.65 V E/D (ENABLE/DISABLE) PIN E/D Pin, Referenced to E/D Com Pin (14) (15) High (output enabled) VSD Low (output disabled) VSD Pin Forced Low Output Disable Time 4 µs Output Enable Time 3 µs E/D COM PIN Voltage Range (V–) (V+) – 5 V POWER SUPPLY Specified Range VS ±50 Operating Voltage Range ±5 Quiescent Current IQ Quiescent Current in Shutdown Mode V ±50 V IO = 0 3.2 4 mA IO = 0, VE/D = 0.65V 150 210 µA TEMPERATURE RANGE Specified Range TA –40 +85 °C Operating Range TA –55 +125 °C Thermal Resistance, Junction-to-Case (16) θJC SO-8 PowerPAD (17) HSOP-20 °C/W 10 °C/W 24/52 °C/W 65 °C/W θJA Thermal Resistance, Junction-to-Ambient SO-8 PowerPAD (17) HSOP-20 (18) (14) (15) (16) (17) (18) 10 See typical characteristic curve, IENABLE vs VENABLE (Figure 46). High enables the outputs. TP is the temperature of the leadframe die pad (exposed thermal pad) of the PowerPAD package. Lower value is for land area of 1-inch × 1-inch, 2-oz copper. Upper value is for exposed-pad sized area of 1-oz copper. Value given is for DW-20 package, similar to the DWD package, but without an exposed pad. Actual θJA may approach θJC by selection of external heatsink and airflow. +50V E/D VOUT RL 50kW 100VPP 10kHz E/D Com -50V Figure 1. Feedthrough Capacitance Circuit Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 5 OPA454 www.ti.com SBOS391 – DECEMBER 2007 TYPICAL CHARACTERISTICS At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted. OPEN-LOOP GAIN AND PHASE vs FREQUENCY PHASE MARGIN vs TEMPERATURE 70 65 140 120 100 Phase 80 60 40 20 0 0.1 1 10 55 50 CL = 100pF 100 1k 10k 100k 1M 40 -75 10M -50 -25 0 25 50 75 100 Frequency (Hz) Exposed Thermal Pad Temperature (°C) Figure 2. Figure 3. UNITY-GAIN BANDWIDTH vs TEMPERATURE OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY 125 Open-Loop Output Impedance (W) 1M 3.6 3.4 3.2 VCM = 0V 3.0 2.8 VCM = 45V 2.6 VCM = -45V 2.4 2.2 CL = 30pF. 100pF, and 200pF 2.0 -75 -50 -25 0 25 100k 10k 1k 100 10 1 50 75 100 125 1 10 100 1k 10k Exposed Thermal Pad Temperature (°C) Frequency (Hz) Figure 4. Figure 5. OPEN-LOOP GAIN vs PEAK-LOAD CURRENT 100k 1M 10M OPEN-LOOP GAIN vs TEMPERATURE 140 140 130 130 VS = ±50V 120 120 110 110 AOL (dB) AOL (dB) CL = 200pF 45 3.8 Bandwidth (MHz) 60 Gain RLOAD = 4.87kW CLOAD = 50pF VCM = 0V -20 VS = ±15V 100 90 100 RLOAD = 48kW VOUT = ±49V (dc) IOUT = ±1mA 90 80 VS = ±4V 80 70 70 60 60 0 6 VCM = -45V VCM = 0V VCM = +45V CL = 30pF 160 Phase Margin (°) Open-Loop Gain, Phase (dB, °) 180 5 10 15 20 25 50 -75 RL = 4.8kW VOUT = +48V, -49V (dc) IOUT = +9.9mA to -10mA RL = 1.88kW VOUT = +47V, -48V (dc) IOUT = ±25mA -50 -25 0 RL = 900W VOUT = +45V, -47V (dc) IOUT = 50mA to -52mA 25 50 75 Peak IL (mA) Exposed Thermal Pad Temperature (°C) Figure 6. Figure 7. Submit Documentation Feedback 100 125 Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 OPA454 www.ti.com SBOS391 – DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted. POWER-SUPPLY AND COMMON-MODE REJECTION RATIO vs TEMPERATURE COMMON-MODE REJECTION RATIO vs FREQUENCY 140 120 120 100 PSRR and CMRR (dB) PSRR CMRR (dB) 100 80 VCM = -45V 60 40 VCM = +45V 80 60 0.01 0.1 1 10 100 100kHz, CMRR 40 1.3MHz, CMRR 20 20 0 0.001 1kHz, CMRR 10kHz, CMRR 1k VCM = +45V VCM = -45V 0 -75 10k -50 -25 0 25 50 75 100 125 Frequency (Hz) Exposed Thermal Pad Temperature (°C) Figure 8. Figure 9. POWER-SUPPLY REJECTION RATIO vs FREQUENCY OUTPUT VOLTAGE SWING vs OUTPUT CURRENT (Measured When Status Flag Transitions From Low to High) 140 50 120 49 100 48 VOUT (V) PSRR (dB) -55°C 80 60 47 +85°C +125°C +25°C -47 40 -48 20 -49 0 -50 -55°C 1 10 100 1k 10k 100k 1M 0 20 30 40 IOUT (mA) Figure 10. Figure 11. MAXIMUM OUTPUT VOLTAGE vs FREQUENCY DDA PACKAGE OFFSET VOLTAGE PRODUCTION DISTRIBUTION 120 Population 80 50 Average = 111mV Standard Deviation = 142mV VOUT = ±49V RL = 4.8kW IOUT = ±10mA 100 Output Voltage (VPP) 10 Frequency (Hz) 60 40 20 0 0 50 100 150 200 250 300 -4000 -3000 -2000 -1000 Frequency (kHz) 0 1000 2000 3000 4000 Offset Voltage (mV) Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 7 OPA454 www.ti.com SBOS391 – DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted. DDA PACKAGE OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION DDA PACKAGE, SOLDER-ATTACHED, VOS TC SHIFT Average = 0.34mV/°C Standard Deviation = 0.44mV/°C 10 2.0 9 1.6 8 1.2 7 0.8 6 0.4 5 0 4 Offset Voltage Drift (mV/°C) -0.4 3 -0.8 2 -1.2 1 -1.6 0 -2.0 Population Population Average = 1.57mV/°C Standard Deviation = 0.84mV/°C Output Voltage Shift (mV/°C) Figure 14. Figure 15. DDA PACKAGE, SOLDER-ATTACHED, VOS SHIFT OFFSET VOLTAGE WARMUP (60 Devices) 200 Average = 48mV/°C Standard Deviation = 28mV/°C Population Offset Voltage (mV) 150 100 VS = ±50V PowerPAD Attached 9in ´ 12in 0.062 Layer Metal PCB FR10 50 0 -50 -100 -200 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 -150 100s/div Offset Voltage Shift (mV) Figure 16. Figure 17. QUIESCENT CURRENT PRODUCTION DISTRIBUTION QUIESCENT CURRENT vs SUPPLY VOLTAGE 3.25 3.20 IQ (mA) Population 3.15 3.10 3.05 3.00 3.9 3.8 3.6 3.7 3.5 3.4 3.3 3.2 2.90 3.1 3.0 2.9 2.8 2.6 2.7 2.5 2.95 0 Figure 18. 8 10 20 30 40 50 60 70 80 90 100 110 120 Total Supply Voltage (V) Quiescent Current (mA) Figure 19. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 OPA454 www.ti.com SBOS391 – DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted. QUIESCENT CURRENT vs TEMPERATURE SHUTDOWN CURRENT vs TEMPERATURE 4.0 200 5 Typical Units Shown 3.8 Shutdown Current (mA) 3.6 IQ (mA) 3.4 3.2 3.0 2.8 2.6 2.4 180 160 140 120 2.2 2.0 -75 -50 -25 0 25 50 75 100 100 -75 125 -50 -25 0 25 50 75 100 Exposed Thermal Pad Temperature (°C) Exposed Thermal Pad Temperature (°C) Figure 20. Figure 21. INPUT BIAS CURRENT vs TEMPERATURE 125 INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE 20 100 15 10 10 IB (pA) IB (pA) 5 0 -5 1 Common-Mode Voltage Range -10 -15 0.1 -75 -50 -25 0 25 50 75 100 -20 -50 -40 -30 125 -20 -10 0 10 20 30 40 Exposed Thermal Pad Temperature (°C) VCM (V) Figure 22. Figure 23. CURRENT LIMIT vs TEMPERATURE STATUS FLAG VOLTAGE vs TEMPERATURE (E/D Com Connected to V–) (1) 200 50 8 7 RP = 20kW, IP = 5mA 180 6 VFLAG to V- ILIMIT (mA) Sourcing 160 140 5 4 RP = 50kW, IP = 2mA 3 RP = 100kW, IP = 100mA 2 120 1 Sinking 100 -75 -50 -25 0 25 50 75 100 125 RP = 200kW, IP = 50mA 0 -75 Exposed Thermal Pad Temperature (°C) Figure 24. (1) -50 -25 0 25 50 75 100 125 Exposed Thermal Pad Temperature (°C) Figure 25. See Figure 57 in the Applications Information section. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 9 OPA454 www.ti.com SBOS391 – DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted. MAXIMUM POWER DISSIPATION vs TEMPERATURE WITH MINIMUM ATTACH AREA SLEW RATE vs TEMPERATURE 2.0 16 SO-8 PowerPAD: TJ(max) = +125°C 15 14 Slew Rate (V/ms) Dissipation (W) 1.5 1.0 0.5 TJ (+125°C max) = TA + [(|VS| - |VO|) IO ´ qJA] qJA = +52°C/W, SO-8 PowerPAD (1in ´ 0.5in [25.4mm x 12.7mm] Heat-Spreader, 1oz Copper) TJ = +25°C + (1.93W ´ 52°C/W) = +125°C 0 -50 -25 0 25 50 13 12 11 G = +1 VS = ±45V VIN = 80V Step RLOAD = 4.8kW 10 9 75 100 8 -75 125 -50 -25 0 25 50 75 100 125 Exposed Thermal Pad Temperature (°C) Exposed Thermal Pad Temperature (°C) Figure 26. Figure 27. INPUT VOLTAGE NOISE SPECTRAL DENSITY 0.01Hz TO 10Hz INPUT VOLTAGE NOISE 100 5mV/div Voltage Noise (nV/ÖHz) 1000 10 1 10 100 1k 10k 20s/div 100k Frequency (Hz) THD + N (%) 0.035 Figure 29. TOTAL HARMONIC DISTORTION + NOISE vs TEMPERATURE TOTAL HARMONIC DISTORTION + NOISE vs TEMPERATURE 0.0030 G = +10 RI = 4.75kW VPP = 38.6V 0.0025 0.030 0.025 VS = -55, +55 0.020 THD + N (%) 0.040 Figure 28. G = +1 RI = 4.75kW VPP = 38.6V VS = +41.6, -40.6 0.0020 0.0015 VS = +40.6, -39.6 0.0010 VS = -49, +50 0.015 0.0005 0.010 0 10 100 1k 10k 100k 10 Frequency (Hz) 1k 10k 100k Frequency (Hz) Figure 30. 10 100 Figure 31. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 OPA454 www.ti.com SBOS391 – DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted. LARGE-SIGNAL STEP RESPONSE LARGE-SIGNAL STEP RESPONSE VIN VIN G = +1 TC = +105°C CLOAD = 50pF VCM = +30V RF = 10kW 500mV/div 500mV/div G = +1 TC = +60°C CLOAD = 50pF VCM = +30V RF = 10kW VOUT VOUT Time (1ms/div) Time (1ms/div) Figure 32. Figure 33. LARGE-SIGNAL STEP RESPONSE SMALL-SIGNAL STEP RESPONSE TC = +125°C TC = -55°C 50mV VIN (200mV/div) VOUT (400mV/div) TC = +25°C G = +2 TC = +100°C CLOAD = 100pF VCM = +40V RF = 10kW VIN VOUT G = +1 CLOAD = 100pF VCM = 0V RF = 0W Time (2.5ms/div) 2.0 1.5 Time (500ns/div) Figure 34. Figure 35. STEP RESPONSE GAIN PEAKING vs CLOAD (G = +1, VCM = 0V) (2) 180 G = +1 140 0.5 Peaking (%) VOUT (V) 1.0 0 -0.5 TC = -55°C TC = +25°C 120 TC = +85°C 100 TC = +125°C 80 60 -1.0 -1.5 RF = 0 W RF = 10kW 160 G = +2 RF = 10kW CLOAD = 100pF, 125°C VCM = +40V -2.0 40 20 0 0 1ms/div 100 200 300 400 500 CLOAD (pF) Figure 36. (2) Figure 37. See Application section Unity-Gain Noninverting Configuration. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 11 OPA454 www.ti.com SBOS391 – DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted. GAIN PEAKING vs CLOAD (G = +2, RF = 10kΩ, VCM = 0V) 30 CF = 0pF CF = 2.5pF CF = 5pF 25 GAIN OF +1 vs FREQUENCY (3) 10 TC = -55°C TC = +25°C CL = 200pF 6 20 TC = +85°C 15 TC = +125°C 10 CL = 100pF 4 Gain (dB) Peaking (%) TA = +25°C 8 2 0 5 -2 0 RF = 10kW, CF = 50pF RF = 0W -4 -5 100 200 300 400 500 10k CLOAD (pF) 10 100k 1M 10M Frequency (Hz) Figure 38. Figure 39. GAIN OF +2 vs FREQUENCY (4) SETTLING TIME, POSITIVE STEP (20V Step, Gain = 1, RF = 10kΩ) (5) (6) 0.08 20 TA = +25°C CL = 500pF 8 0.06 15 0.04 10 0.02 5 VIN (V) 4 CL = 50pF 2 0 V2 (Noninverting) 0 0 -0.02 -5 -10 CF = 0pF CF = 2.5pF CF = 5pF -2 -4 VIN -0.06 -15 -0.08 -20 -6 10k 100k 1M 10M -0.04 Voltage at V1 and V2 (V) V1 (Inverting) 6 Gain (dB) CL = 50pF -6 0 Time (1ms/div) Frequency (Hz) Figure 40. (3) (4) (5) (6) 12 Figure 41. See Application section Unity-Gain Noninverting Configuration. See Application section Unity-Gain Noninverting Configuration. See the Settling Time section. The grid for voltage at V1 and V2 is scaled 20mV or 0.1% per division. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 OPA454 www.ti.com SBOS391 – DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted. SETTLING TIME, NEGATIVE STEP (20V Step, Gain = 1, RF = 10kΩ) (7) (8) 0.06 10 0.04 5 0.02 0 V2 (Noninverting) 0 -0.02 -5 -10 -0.04 V1 (Inverting) Voltage at V1 and V2 (V) VIN OUT 4mV/div 15 VIN (V) ENABLE RESPONSE TIME 0.08 20 Status Flag Enable -0.06 -15 -0.08 -20 Time (1ms/div) Time (1ms/div) Figure 42. Figure 43. DISABLE RESPONSE TIME ENABLE RESPONSE OUT 4mV/div 4mV/div OUT Status Flag Status Flag Enable Enable Time (1ms/div) Time (1ms/div) Figure 44. Figure 45. IENABLE vs VENABLE ENABLE/DISABLE THRESHOLD vs TEMPERATURE 10 1.00 0.95 Threshold (V) IENABLE (mA) 0 -40°C -10 +25°C +85°C 0.90 0.85 0.80 -20 0.75 -30 0 (7) (8) 1 2 3 4 5 0.70 -75 -50 -25 0 25 50 VENABLE (V) Temperature (°C) Figure 46. Figure 47. 75 100 125 See the Settling Time section. The grid for voltage at V1 and V2 is scaled 20mV or 0.1% per division. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 13 OPA454 www.ti.com SBOS391 – DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted. ILIMIT SHOWING FLAG DELAY (TP = +125°C) (9) ILIMIT SHOWING FLAG DELAY (TP = +25°C) (10) 60 200 60 150 VFLAG 150 50 40 100 40 50 20 100 50 IOUT 30 0 20 -50 -50 10 -100 -100 0 0 IOUT (mA) 30 VFLAG (V) 50 IOUT (mA) VFLAG (V) VFLAG IOUT 10 0 -150 RP = 100kW RP = 100kW -10 -150 -10 -200 10ms/div 10ms/div Figure 48. Figure 49. ILIMIT SHOWING FLAG DELAY (TP = –55°C) (11) APPLY LOAD (25mA Sink Response) 1.6 50 +125°C +85°C +25°C -55°C 1.4 100 1.2 50 OPA454 1.0 VOUT (V) IOUT IOUT (mA) VFLAG (V) 40 30 0 20 -50 10 -100 0 -150 0 -200 -0.2 +50V 0.988VPP 0.01Hz - 150 VFLAG 2Hz 2ms Pulse + 60 -50V Mercury Wetted Relay 0.8 0.6 0.4 0.2 RP = 100kW -10 10ms/div 10ms/div Figure 50. Figure 51. REMOVE LOAD (25mA Sink Response) APPLY LOAD (25mA Source Response) 0.2 0 -0.2 -0.4 -0.4 VOUT (V) 0 -0.2 -0.6 -0.8 - OPA454 -50V -1.6 +50V 0.988VPP 0.01Hz OPA454 + -1.4 -1.0 - -1.2 +125°C +85°C +25°C -55°C -0.8 +50V 0.988VPP 0.01Hz -1.0 -0.6 2Hz 2ms Pulse -1.2 Mercury Wetted Relay -1.4 2Hz 2ms Pulse + VOUT (V) 0.2 -50V Mercury Wetted Relay +125°C +85°C +25°C -55°C -1.6 10ms/div 10ms/div Figure 52. Figure 53. (9) The OPA454 was connected to sufficient heatsinking to prevent thermal shutdown. (10) The OPA454 was connected to sufficient heatsinking to prevent thermal shutdown. (11) The OPA454 was connected to sufficient heatsinking to prevent thermal shutdown. 14 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 OPA454 www.ti.com SBOS391 – DECEMBER 2007 TYPICAL CHARACTERISTICS (continued) At TP = +25°C, VS = ±50V, and RL = 4.8kΩ connected to GND, unless otherwise noted. REMOVE LOAD (25mA Source Response) 1.6 1.4 1.2 RL = 1.8kW VOUT 0.6 OPA454 2Hz 2ms Pulse -50V Flag 20V/div - 0.8 V+ +50V 0.988VPP 0.01Hz + VOUT (V) 1.0 POWER ON +125°C +85°C +25°C -55°C Mercury Wetted Relay 0 0.4 Delay in V- is due to test equipment. Power supplies may be applied in any sequence. 0.2 0 -0.2 V- 20ms/div 10ms/div Figure 54. Figure 55. POWER OFF V+ RL = 1.8kW 20V/div VOUT Flag 0 V20ms/div Figure 56. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 15 OPA454 www.ti.com SBOS391 – DECEMBER 2007 APPLICATIONS INFORMATION POWER SUPPLIES Figure 57 shows the OPA454 connected as a basic noninverting amplifier. The OPA454 can be used in virtually any ±5V to ±50V op amp configuration. It is especially useful for supply voltages greater than 36V. The OPA454 may be operated from power supplies up to ±50V or a total of 100V with excellent performance. Most behavior remains unchanged throughout the full operating voltage range. Parameters that vary significantly with operating voltage are shown in the Typical Characteristics. Power-supply terminals should be bypassed with 0.1µF (or greater) capacitors, located near the power-supply pins. Be sure that the capacitors are appropriately rated for the power-supply voltage used. Some applications do not require equal positive and negative output voltage swing. Power-supply voltages do not need to be equal. The OPA454 can operate with as little as 10V between the supplies and with up to 100V between the supplies. For example, the positive supply could be set to 90V with the negative supply at –10V, or vice-versa (as long as the total is less than or equal to 100V). V+ IP 0.1mF V+ (1) RP R1 V+ -IN VIN OPA454 +IN R2 G = 1+ R2 R1 Status Flag VOUT INPUT PROTECTION The OPA454 has increased protection against damage caused by excessive voltage between op amp input pins or input pin voltages that exceed the power supplies; external series resistance is not needed for protection. Internal series JFETs limit input overload current to a non-destructive 4mA, even with an input differential voltage as large as 120V. Additionally, the OPA454 has dielectric isolation between devices and the substrate. Therefore, the amplifier is free from the limitations of junction isolation common to many IC fabrication processes. VOUT E/D RL E/D Com V0.1mF V- (1) V- Pull-up resistor with at least 10µA (choose RP = 1MΩ with V+ = 50V for IP = 50µA). LOWERING OFFSET VOLTAGE AND DRIFT Figure 57. Basic Noninverting Amplifier Configuration Low Offset, 5mV, Drift, 0.05mV/°C, Self-Zeroing Op Amp Gain 1st = 4.9V/V R1, 1st 10kW The OPA454 can be used with an OPA735 zero-drift series op amp to create a high-voltage op amp circuit that has very low input offset temperature drift. This circuit is shown in Figure 58. High-Voltage Op Amp Gain 2nd = 9.45V/V R1, 2nd 10kW R2, 1st 39.1kW R2, 2nd 84.5kW V+ 2nd Stage, +50V V+ 1st Stage, +5V VOUT 2nd Stage VOUT 1st Stage OPA454 A2, 2nd Stage OPA735 A1, 1st Stage VG = ±1V V1st Stage, -5V VOUT 1st Stage ±4.9V, Max RLOAD 10kW V2nd Stage, -50V VOUT 2nd Stage ±46V (92VPP), Max VINPUT = ±1VPP Figure 58. Two-Stage, High-Voltage Op Amp Circuit With Very Low Input Offset Temperature Drift 16 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 OPA454 www.ti.com SBOS391 – DECEMBER 2007 INCREASING OUTPUT CURRENT R1 The OPA454 drives an output current of a few milliamps to greater than 50mA while maintaining good op amp performance. See Figure 7 for open-loop gain versus temperature at various output current levels. In applications where the 25mA output current is not sufficient to drive the required load, the output current can be increased by connecting two or more OPA454s in parallel, as Figure 59 shows. Amplifier A1 is the master amplifier and may be configured in virtually any op amp circuit. Amplifier A2, the slave, is configured as a unity-gain buffer. Alternatively, external output transistors can be used to boost output current. The circuit in Figure 60 is capable of supplying output currents up to 1A, with the transistors shown. R2 (1) MASTER A1 RS 10W OPA454 VIN (1) RS 10W A2 OPA454 SLAVE RL (1) RS resistors minimize the circulating current that always flows between the two devices because of VOS errors. Figure 59. Parallel Amplifiers Increase Output Current Capability UNITY-GAIN NONINVERTING CONFIGURATION When in the noninverting unity-gain configuration, the OPA454 has more gain peaking with increasing positive common-mode voltage and increasing temperature. It has less gain peaking with more negative common-mode voltage. As with all op amps, gain peaking increases with increasing capacitive load. A resistor and small capacitor placed in the feedback path can reduce gain peaking and increase stability. R1 R2 +50V NPN TIP29C, MJL21194, MJE15003, MJL3281 CF V+ -IN (1) R3 (2) VOUT VIN +IN R4 0.2W 20W (3) VO OPA454 V- R5 0.2W RL = VOUT - ILRL IL PNP TIP30C, MJL21193, MJE15004, MJL1302A -50V (1) Provides current limit for OPA454 and allows the amplifier to drive the load when the output is between +0.7V and –0.7V. (2) Op amp VOUT swings from +47V to –48V. (3) VO swings from +44.1V to –45.1V at IL = 1A. Figure 60. External Output Transistors Boost Output Current Greater Than 1A Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 17 OPA454 www.ti.com SBOS391 – DECEMBER 2007 INPUT RANGE -46.0 50.5 V+ TA = +25°C -46.5 -47.0 Voltage (V) The OPA454 is specified to give linear operation with input swing to within 2.5V of either supply. Generally, a gain of +1 is the most demanding configuration. Figure 61 and Figure 62 show output behavior as the input swings to within 0V of the rail, using the circuit shown in Figure 64. Figure 63 shows the behavior with an input signal that swings beyond the specified input range to within 1V of the rail, also using the circuit in Figure 64. Notice that the beginning of the phase reversal effect may be reduced by inserting series resistance (RS) in the connection to the positive input. Note that VOUT does not swing all the way to the opposite rail. -47.5 VOUT RS = 50kW -48.0 -48.5 -49.0 VOUT RS = 0W VIN f = 1kHz -49.5 -50.0 V-50.5 0 20 40 60 80 100 Time (ms) Figure 63. Output Voltage With Input Voltage Down To (V–) + 1V TA = +25°C 50.0 VIN f = 1kHz Voltage (V) 49.5 VOUT RS = 50kW 49.0 RF 10kW 48.5 V+ = +50V 48.0 RS VOUT R S = 0W 47.5 RL 4.8kW 47.0 0 20 40 60 VOUT OPA454 80 V- = -50V VIN 100 Time (ms) Figure 61. Output Voltage With Input Voltage Up To V+ OUTPUT RANGE -46.0 TA = +25°C The OPA454 is specified to swing to within 1V of either supply rail with a 49kΩ load while maintaining excellent linearity. Swing to the rail decreases with increasing output current. The OPA454 can swing to within 2V of the negative rail and 3V of the positive rail with a 1.88kΩ load. The typical characteristic curve, Output Voltage Swing vs Output Current (Figure 11), shows this behavior in detail. -46.5 VOUT RS = 0W -47.0 Voltage (V) Figure 64. Input Range Test Circuit -47.5 VOUT RS = 50kW -48.0 -48.5 -49.0 VIN f = 1kHz -49.5 -50.0 V-50.5 0 20 40 60 80 100 Time (ms) Figure 62. Output Voltage With Input Voltage Down To V– 18 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 OPA454 www.ti.com SBOS391 – DECEMBER 2007 OPEN-LOOP GAIN LINEARITY SETTLING TIME Figure 65 shows the nonlinear relationship of AOL and output voltage. As Figure 65 shows, open-loop gain is lower with positive output voltage levels compared to negative voltage levels. Specifications in the Electrical Characteristics table are based upon the average gain measured at both output extremes. The circuit in Figure 66 is used to measure the settling time response. The left half of the circuit is a standard, false-summing junction test circuit used for settling time and open-loop gain measurement. R1 and R2 provide the gain and allow for measurement without connecting a scope probe directly to the summing junction, which can disturb proper op amp function by causing oscillation. |(VIN+) - (VIN-)| AOL is a Function of VOUT and ILOAD TP = +25°C The right half of the circuit looks at the combination of both inverting and noninverting responses. R5 and R6 remove the large step response. The remaining voltage at V2 shows the small-signal settling time that is centered on zero. This test circuit can be used for incoming inspection, real-time measurement, or in designing compensation circuits in system applications. RL = 1880W, 1mV/div RL = 900W, 2mV/div 74dB 106dB RL = 4.87kW, 200mV/div -50 -40 -30 -20 -10 89dB 0 10 20 30 40 Table 2. Settling Time Measurement Circuit Configuration Using Different Gain Settings for Figure 66 50 Output Voltage (V) GAIN Figure 65. Differential Input Voltage (+IN to –IN) versus Output Voltage COMPONENT 1 5 10 R1 (Ω) 10k 2k 1k R3 (Ω) 10k 2k 1k R7 (Ω) 10k 4k 9k R8 (Ω) ∞ 1k 1k VIN (VPP) 20 16 8 Inverting Response Measured Here, V1 R1 R2 10kW R3 R4 10kW -IN +IN Combination of Both Inverting and Noninverting Responses, V2 VOUT R5 10kW R6 10kW OPA454 A1 R7 VOUT A2 R8 -IN OPA454 +IN VIN Figure 66. Settling Time Test Measurement Circuit Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 19 OPA454 www.ti.com SBOS391 – DECEMBER 2007 If left disconnected, E/D Com is pulled near V– (negative supply) by an internal 10µA current source. When left floating, ENABLE is held approximately 2V above E/D Com by an internal 1µA source. Even though active operation of the OPA454 results when the ENABLE and E/D Com pins are not connected, a moderately fast, negative-going signal capacitively coupled to the ENABLE pin can overpower the 1µA pull-up current and cause device shutdown. This behavior can appear as an oscillation and is encountered first near extreme cold temperatures. If the enable function is not used, a conservative approach is to connect ENABLE through a 30pF capacitor to a low impedance source. Another alternative is the connection of an external current source from V+ (positive supply) sufficient to hold the enable level above the shutdown threshold. Figure 67 shows a circuit that connects ENABLE and E/D Com. Choosing RP to be 1MΩ with a +50V positive power supply voltage results in IP = 50µA. V+ (Positive Op Amp Supply) IP RP DVDD (Digital Supply) avoided to maximize reliability. It is always best to provide proper heat-sinking (either by a physical plate or by airflow) to remain considerably below the thermal shutdown threshold. For longest operational life of the device, keep the junction temperature below +125°C. THERMAL PROTECTION Figure 68 shows the thermal shutdown behavior of a socketed OPA454 that internally dissipates 1W. Unsoldered and in a socket, θJA of the DDA package is typically +128°C/W. With the socket at +25°C, the output stage temperature rises to the shutdown temperature of +150°C, which triggers automatic thermal shutdown of the device. The device remains in thermal shutdown (output is in a high-impedance state) until it cools to +130°C where it again is powered. This thermal protection hysteresis feature typically prevents the amplifier from leaving the safe operating area, even with a direct short from the output to ground or either supply. The rail-to-rail supply voltage at which catastrophic breakdown occurs is typically 135V at +25°C. However, the absolute maximum specification is 120V, and the OPA454 should not be allowed to exceed 120V under any condition. Failure as a result of breakdown, caused by spiking currents into inductive loads (particularly with elevated supply voltage), is not prevented by the thermal protection architecture. 140 40 V+ 5V Logic E/D -IN 20 100 0 VOUT OPA454 VOUT (V) E/D Com +IN 120 VOUT V- -20 80 -40 60 -60 40 -80 V(Negative Op Amp Supply) 20 VFLAG 0 -100 -120 0 200 400 Figure 67. ENABLE and E/D Com 20 -20 1000 800 600 (ms) 10kW CURRENT LIMIT Figure 24 and Figure 48 to Figure 50 show the current limit behavior of the OPA454. Current limiting is accomplished by internally limiting the drive to the output transistors. The output can supply the limited current continuously, unless the die temperature rises to +150°C, which initiates thermal shutdown. With adequate heat-sinking, and use of the lowest possible supply voltage, the OPA454 can remain in current limit continuously without entering thermal shutdown. Although qualification studies have shown minimal parametric shifts induced by 400 hours of thermal shutdown cycling, this mode of operation should be VFLAG (V) ENABLE AND E/D Com 100kW +50V +2.5V 10Hz Square Wave Submit Documentation Feedback RP 1MW -IN V+ Flag VFLAG VOUT +IN OPA454 VOUT E/D Com V- 625W -50V Figure 68. Thermal Shutdown Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 OPA454 www.ti.com SBOS391 – DECEMBER 2007 POWER DISSIPATION HEATSINKING Power dissipation depends on power supply, signal, and load conditions. For dc signals, power dissipation is equal to the product of the output current times the voltage across the conducting output transistor, PD = IL (VS – VO). Power dissipation can be minimized by using the lowest possible power-supply voltage necessary to assure the required output voltage swing. Power dissipated in the OPA454 causes the junction temperature to rise. For reliable operation, junction temperature should be limited to +125°C, maximum. Maintaining a lower junction temperature always results in higher reliability. Some applications require a heatsink to assure that the maximum operating junction temperature is not exceeded. Junction temperature can be determined according to Equation 1: TJ = TA + PD qJA (1) The OPA454 can supply output currents of 25mA and larger. Supplying this amount of current presents no problem for some op amps operating from ±15V supplies. However, with high supply voltages, internal power dissipation of the op amp can be quite high. Operation from a single power supply (or unbalanced power supplies) can produce even greater power dissipation because a large voltage is impressed across the conducting output transistor. Applications with high power dissipation may require a heatsink, or heat spreader. R1 100kW R2 10kW V1 +50V V+ -IN +IN OPA454 V- R3 100kW -50V VOUT R5 100W R4 9.9kW V2 Package thermal resistance, θJA, is affected by mounting techniques and environments. Poor air circulation and use of sockets can significantly increase thermal resistance to the ambient environment. Many op amps placed closely together also increase the surrounding temperature. Best thermal performance is achieved by soldering the op amp onto a circuit board with wide printed circuit traces to allow greater conduction through the op amp leads. Increasing circuit board copper area to approximately 0.5in2 decreases thermal resistance; however, minimal improvement occurs beyond 0.5in2, as shown in Figure 70. For additional information on determining heatsink requirements, consult Application Bulletin SBOA021 (available for download at www.ti.com). 60 Thermal Resistance, qJA (°C/W) For resistive loads, the maximum power dissipation occurs at a dc output voltage of one-half the power-supply voltage. Dissipation with ac signals is lower because the root-mean square (RMS) value determines heating. Application Bulletin SBOA022 explains how to calculate or measure dissipation with unusual loads or signals. For constant current source circuits, maximum power dissipation occurs at the minimum output voltage, as Figure 69 shows. 50 40 30 20 10 0 0 IL IL = [(V2 - V1)/R5] (R2/R1) = (V2 - V1)/1kW 0.5 1.0 1.5 2.0 2.5 3.0 2 RL Copper Area (inches ), 2 oz Figure 70. Thermal Resistance versus Circuit Board Copper Area Compliance Voltage Range = +47V, -48V NOTE: R1 = R3 and R2 = R4 + R5. Figure 69. Precision Voltage-to-Current Converter with Differential Inputs Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 21 OPA454 www.ti.com SBOS391 – DECEMBER 2007 PowerPAD THERMALLY-ENHANCED PACKAGES BOTTOM-SIDE PowerPAD PACKAGE The OPA454 comes in SO-8 and HSOP-20 PowerPAD versions that provide an extremely low thermal resistance (θJC) path between the die and the exterior of the package. These packages feature an exposed thermal pad. This thermal pad has direct thermal contact with the die; thus, excellent thermal performance is achieved by providing a good thermal path away from the thermal pad. TOP-SIDE PowerPAD PACKAGE The OPA454 DWD, HSOP-20, PowerPAD package has the exposed pad on the top side of the package, as Figure 71b shows. The top-side thermal pad can be used with commercially available heat-sinks and moving air to dissipate heat. The use of an external top-side heat-sink increases the effective surface area of the package face, which increases convection and radiation off the top surface of the package. Top-side heatsinking also avoids unnecessary heating of the printed circuit board (PCB), and permits installation of other PCB components onto the side opposite of the OPA454. The OPA454 SO-8 PowerPAD is a standard-size SO-8 package constructed using a downset leadframe upon which the die is mounted, as Figure 71a shows. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package. The thermal pad on the bottom of the IC can then be soldered directly to the PCB, using the PCB as a heatsink. In addition, plated-through holes (vias) provide a low thermal resistance heat flow path to the back side of the PCB. This architecture enhances the OPA454 power dissipation capability significantly, eliminates the use of bulky heatsinks and slugs traditionally used in thermal packages, and allows the OPA454 to be easily mounted using standard PCB assembly techniques. NOTE: Because the SO-8 PowerPAD is pin-compatible with standard SO-8 packages, the OPA454 is a drop-in replacement for operational amplifiers in existing sockets. Soldering the bottom-side PowerPAD to the PCB is always required, even with applications that have low power dissipation. Soldering the device to the PCB provides the necessary thermal and mechanical connection between the leadframe die pad and the PCB. Leadframe (Copper Alloy) IC (Silicon) Die Attach (Epoxy) External Heatspreader Die Pad Die Attach Chip Thermal Paste Power Transistor Mold Compound (Plastic) Leadframe Die Pad Exposed at Base of the Package (Copper Alloy) a) SO-8 PowerPAD cross-section view. Board b) HSOP-20 PowerPAD cross-section view. Figure 71. Cross-Section Views of a PowerPAD Package 22 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 OPA454 www.ti.com SBOS391 – DECEMBER 2007 BOTTOM-SIDE PowerPAD LAYOUT GUIDELINES The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat-dissipating device. Soldering the PowerPAD to the PCB is always required, even with applications that have low power dissipation. Follow these steps to attach the device to the PCB: 1. The PowerPAD must be connected to the most negative supply voltage on the device, V–. 2. Prepare the PCB with a top-side etch pattern. There should be etching for the leads as well as etch for the thermal pad. 3. Use of thermal vias improves heat dissipation, but are not required. The thermal pad can connect to the PCB using an area equal to the pad size with no vias, but externally connected to V–. 4. Place recommended holes in the area of the thermal pad. Recommended thermal land size and thermal via patterns for the SO-8 DDA package are shown in the thermal land pattern mechanical drawing appended at the end of this document. These holes should be 13 mils in diameter. Keep them small, so that solder wicking through the holes is not a problem during reflow. The minimum recommended number of holes for the SO-8 PowerPAD package is five. 5. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. These vias help dissipate the heat generated by the OPA454 IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered; thus, wicking is not a problem. 6. Connect all holes to the internal power plane of the correct voltage potential (V–). 7. When connecting these holes to the plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations, making the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the OPA454 PowerPAD package should make the connections to the internal plane with a complete connection around the entire circumference of the plated-through hole. 8. The top-side solder mask should leave the terminals of the package and the thermal pad area exposed. The bottom-side solder mask should cover the holes of the thermal pad area. This masking prevents solder from being pulled away from the thermal pad area during the reflow process. 9. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 10. With these preparatory steps in place, the PowerPAD IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This preparation results in a properly installed part. For detailed information on the PowerPAD package, including thermal modeling considerations and repair procedures, see technical brief SLMA002 PowerPAD Thermally-Enhanced Package, available for download at www.ti.com. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 23 OPA454 www.ti.com SBOS391 – DECEMBER 2007 TYPICAL APPLICATIONS Figure 72 and Figure 73 illustrate the OPA454 in a programmable voltage source and a bridge circuit, respectively. +95V 0.1mF 45.3kW 0-2mA DAC8811 or DAC7811 V+ -IN +IN Protects DAC During Slewing OPA454 VOUT = 0V to +91V V- RL 0.1mF -5V Figure 72. Programmable Voltage Source R1 1kW R3 10kW R2 9kW R4 10kW +50V +50V -IN VIN ±4V MASTER +IN V+ OPA454 V- VOUT A1 Up To 195V (1) Piezo Crystal V+ VOUT A2 -50V OPA454 -IN +IN SLAVE V-50V (1) For transducers with large capacitance, stabilization may become an issue. Be certain that the Master amplifier is stable before stabilizing the Slave amplifier. Figure 73. Bridge Circuit Doubles Voltage for Exciting Piezo Crystals 24 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 OPA454 www.ti.com SBOS391 – DECEMBER 2007 Figure 74 uses three OPA454s to create a high-voltage instrumentation amplifier. VCM ± VSIG must be between (V–) + 2.5V and (V+) – 2.5V. The maximum supply voltage equals ±50V or 100V total. V+ V1 OPA454 A1 Figure 75 uses three OPA454s to measure current in a high-side shunt application. VSUPPLY must be greater than VCM. VCM must be between (V–) + 2.5V and (V+) – 2.5V. Adhering to these restrictions keeps V1 and V2 within the voltage range required for linear operation of the OPA454. For example, if V+ = 50V and V– = 50V, then V1 = +47.5V (maximum) and V2 = –47.5V (minimum). The maximum supply voltage equals ±50V, or 100V total. R4 VR2 R5 V+ VSIG OPA454 (1) A3 R1 VOUT R2 VR6 V+ See Figure 76 and Figure 79 for example circuits that use the OPA454 in an output voltage boost configurations in three and six op amp output stages, respectively. R7 OPA454 A2 V2 VCM VOUT = (1 + 2R2/R1) (V2 - V1) V- (1) The linear input range is limited by the output swing on the input amplifiers, A1 and A2. Figure 74. High-Voltage Instrumentation Amplifier RSHUNT V+ VSUPPLY Plus or Minus V1 Load OPA454 A1 (1) R4 VR2 R5 V+ OPA454 R1 VOUT (2) A3 R2 VR6 V+ R7 OPA454 A2 V2 (1) VOUT = (1 + 2R2/R1) (V2 - V1) V- (1) To increase the linear input voltage range, configure A1 and A2 as unity-gain followers. (2) The linear input range is limited by the output swing on the input amplifiers, A1 and A2. Figure 75. High-Voltage Instrumentation Amplifier for Measuring High-Side Shunt Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 25 OPA454 www.ti.com SBOS391 – DECEMBER 2007 +100V +100V 10kW 10kW +100V +100V 100kW V01 V04 OPA454 V- 190kW OPA454 A4 A1 10kW 100kW V+ V+ 10kW V- 200kW 100kW V+ VLOAD = +97V, -98V (195VPP) VOUT OPA454 100kW A3 VIN V+ OPA454 A6 RLOAD 3.75kW V- VLOAD = +97V, -98V (195VPP) VOUT RLOAD 3.75kW V- VIN 10kW 10kW 100kW 100kW V05 V+ OPA454 A5 V02 V+ OPA454 A2 V- V100kW 100kW -100V -100V -100V -100V a) Noninverting, G = +20V/V b) Inverting, G = -20V/V Figure 76. Output Voltage Boost With +97V, –98V (195VPP) Across Load Connected to Ground (3 Op Amp Output Stage, see Figure 77 and Figure 78) 100 6 100 80 V01 50 40 25 VOUT (V) Voltage (V) VLOAD 0 -25 VOUT 60 4 VIN 2 20 0 0 VIN (V) 75 -20 V02 -2 -40 -50 -60 -4 -75 -80 -100 -100 Figure 77. 195VPP On 3.75kΩ Load to Ground 20kHz, Uses 3 OPA454s, 100V Supplies 26 -6 Time (10ms/div) Time (20ms/div) Figure 78. 3.75kΩ Load to Ground G = +20, 3 OPA454s, 100V Supplies (Note SR of 18V/µs, which is slightly higher than the specified 13V/µs due to tracking of the power-supply voltage) Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 OPA454 www.ti.com SBOS391 – DECEMBER 2007 +100V +100V 10kW 10kW +120V +120V 100kW 100kW V+ V+ OPA454 OPA454 A1 10kW A4 V- 190kW V100kW (+97V, -98V) 10kW 100kW RLOAD 7.5kW V+ 200kW V+ (-98V, +97V) OPA454 OPA454 A3 A6 VLOAD (±195V, 390VPP) V- V- 10kW 10kW VIN 100kW 100kW V+ V+ OPA454 OPA454 A2 A5 V- V100kW 100kW -100V -100V -100V -100V Figure 79. Output Voltage Boost With ±195V (390VPP) Across Bridge-Tied Load (6 Op Amps, see Figure 80 and Figure 81) 200 VLOAD 200 6 150 150 50 0 VIN VOUT 2 50 0 0 -50 -50 -100 -100 -150 -150 4 VIN (V) 100 VOUT (V) VOUT (V) 100 -2 -4 -200 -200 -6 Time (10ms/div) Time (20ms/div) Figure 80. 390VPP Across 7.5kΩ Load 20kHz, Uses 6 OPA454s, 100V Supplies Figure 81. 7.5kΩ Load G = +20, 6 OPA454s, 100V Supplies (Note SR of 34V/µs, which is significantly higher than the specified 13V/µs due to tracking of the power-supply voltage) Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 27 OPA454 www.ti.com SBOS391 – DECEMBER 2007 R1 25kW A red light emitting diode (LED) was used to generate Figure 84. R2 25kW V1 VOUT = V2 - V1 OPA454 R3 25kW Gain of the avalanche photodiode (APD) is adjusted by changing the voltage across the APD. Gain starts to increase when reverse voltage is increased beyond 130V for this API diode. Figure 85 shows this structure. R4 25kW 14 6V V2 12 VOUT Figure 82. High-Voltage Difference Amplifier HIGH-COMPLIANCE VOLTAGE CURRENT SOURCES 8 6 VLED 0V This section describes four different applications utilizing high compliance voltage current sources with differential inputs. Figure 69 and Figure 83 illustrate the different applications. VLED (V) VOUT (1V/div) 10 4 2 0 -2 -2V 5ms/div Figure 84. Avalanche Photodiode Circuit 25kW 25kW V1 OPA454 A1 25kW V2 25kW R OPA454 A2 Load IO IO = (V2 - V1)/R Figure 83. Differential Input Voltage-to-Current Converter for Low IOUT 28 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 OPA454 www.ti.com R7 10kW SBOS391 – DECEMBER 2007 R1 90kW +100V +100V R2 1kW V+ V+ OPA454 OPA454 A1 R4 100kW A2 +100V V- V- VOUT = 100 ´ RSENSE ´ ID V+ OPA454 + V1 Gain Adjust Voltage 2.5V to 9.5V RSENSE 100W V- +100V R3 1kW V+ OPA454 A4 VOUT +100V R8 198kW R9 4.9kW A3 V- R5 100kW LM4041D Adjusted for 2.0V 100W APD LED R10 3.1kW VLED -200V Example Circuit For Reverse Biasing APD (130V to 280V, max) Advanced Photonix, Inc. SD 036-70-62-531 Digi-Key SD 036-70-62-531 Figure 85. APD Gain Adjustment Using the OPA454, High-Voltage Op Amp Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): OPA454 29 PACKAGE OPTION ADDENDUM www.ti.com 31-Dec-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty OPA454AIDDA ACTIVE SO Power PAD DDA 8 OPA454AIDDAR ACTIVE SO Power PAD DDA 8 OPA454AIDWD PREVIEW HSOP DWD 20 75 TBD Call TI Call TI OPA454AIDWDR PREVIEW HSOP DWD 20 2000 TBD Call TI Call TI 75 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Jan-2008 TAPE AND REEL BOX INFORMATION Device OPA454AIDDAR Package Pins DDA 8 Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) SITE 41 330 12 6.4 5.2 2.1 8 Pack Materials-Page 1 W Pin1 (mm) Quadrant 12 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Jan-2008 Device Package Pins Site Length (mm) Width (mm) Height (mm) OPA454AIDDAR DDA 8 SITE 41 346.0 346.0 29.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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