54AC109 • 54ACT109 Dual JK Positive Edge-Triggered Flip-Flop Simultaneous LOW on CD and SD makes both Q and Q General Description The ’AC/’ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to ’AC/’ACT74 data sheet) by connecting the J and K inputs together. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock HIGH Features n n n n ICC reduced by 50% Outputs source/sink 24 mA ’ACT109 has TTL-compatible inputs Standard Military Drawing (SMD) — ’AC109: 5962-89551 — ’ACT109: 5962-88534 Logic Symbol IEEE/IEC DS100267-1 DS100267-7 Pin Names Description J1, J2, K1, K2 Data Inputs CP1, CP2 Clock Pulse Inputs CD1, CD2 Direct Clear Inputs SD1, SD2 Direct Set Inputs Q1, Q2, Q1, Q2 Outputs DS100267-2 FACT ® is a registered trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100267 www.national.com 54AC109 • 54ACT109 Dual JK Positive Edge-Triggered Flip-Flop August 1998 Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100267-3 DS100267-4 Truth Table (each half) Inputs Outputs SD CD CP J K Q L H X X X H Q L H L X X X L H L L X X X H H H H N L L L H H H N H L H H N L H Q0 H H N H H H L H H L X X Q0 Q0 Toggle Q0 H = HIGH Voltage Level L = LOW Voltage Level N = LOW-to-HIGH Transition X = Immaterial Q0(Q0) = Previous Q0 (Q0) before LOW-to-HIGH Transition of Clock Logic Diagram (one half shown) DS100267-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP Supply Voltage (VCC) ’AC ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA −65˚C to +150˚C 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. 175˚C DC Characteristics for ’AC Family Devices Symbol VIH VIL VOH VOL IIN Parameter VCC 54AC TA = −55˚C to +125˚C (V) Guaranteed Limits Minimum High Level 3.0 2.1 Input Voltage 4.5 3.15 5.5 3.85 Maximum Low Level 3.0 0.9 Input Voltage 4.5 1.35 5.5 1.65 Minimum High Level 3.0 2.9 Output Voltage 4.5 4.4 5.5 5.4 3.0 2.4 4.5 3.7 5.5 4.7 Maximum Low Level 3.0 0.1 Output Voltage 4.5 0.1 5.5 0.1 Maximum Input 3.0 0.5 4.5 0.5 5.5 0.5 5.5 Units Conditions VOUT = 0.1V V or VCC − 0.1V V or VCC − 0.1V VOUT = 0.1V IOUT = −50 µA V (Note 2) VIN = VIL or VIH IOH = −12 mA V IOH = −24 mA IOH = −24 mA IOUT = 50 µA V (Note 2) VIN = VIL or VIH IOL = 12 mA V IOL = 24 mA ± 1.0 µA IOL = 24 mA VI = VCC, GND 5.5 50 mA 5.5 −50 mA Leakage Current IOLD IOHD (Note 3) Minimum Dynamic Output Current 3 VOLD = 1.65V Max VOHD = 3.85V Min www.national.com DC Characteristics for ’AC Family Devices Symbol ICC Parameter Maximum Quiescent (Continued) VCC 54AC TA = −55˚C to +125˚C (V) Guaranteed Limits 5.5 40.0 Units µA Supply Current Conditions VIN = VCC or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C. DC Characteristics for ’ACT Family Devices Symbol VIH VIL VOH VOL IIN Parameter VCC 54ACT TA = −55˚C to +125˚C (V) Guaranteed Limits Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low Level 4.5 0.8 Input Voltage 5.5 0.8 Minimum High Level 4.5 4.4 Output Voltage 5.5 5.4 4.5 3.70 5.5 4.70 Maximum Low Level 4.5 0.1 Output Voltage 5.5 0.1 Maximum Input Units Conditions V VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA V (Note 5) VIN = VIL or VIH IOH = −24 mA V IOH = −24 mA IOUT = 50 µA V (Note 5) VIN = VIL or VIH IOL = 24 mA 4.5 0.50 5.5 0.50 5.5 ± 1.0 µA IOL = 24 mA VI = VCC, GND 5.5 1.6 mA VI = VCC − 2.1V Leakage Current ICCT Maximum ICC/Input (Note 6) IOLD Minimum Dynamic 5.5 50 mA IOHD Output Current 5.5 −50 mA VOLD = 1.65V Max VOHD = 3.85V Min ICC Maximum Quiescent 5.5 40.0 µA VIN = VCC Supply Current or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C. www.national.com 4 AC Electrical Characteristics 54AC TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 8) Min fmax tPLH tPHL tPLH tPHL Maximum Clock 3.3 65 Frequency 5.0 95 Fig. Units No. Max MHz Propagation Delay 3.3 1.0 17.5 CPn to Qn or Qn 5.0 1.0 12.0 Propagation Delay 3.3 1.0 13.5 CPn to Qn or Qn 5.0 1.0 10.0 Propagation Delay 3.3 1.0 13.0 CDn or SDn to Qn or Qn 5.0 1.0 9.5 Propagation Delay 3.3 1.0 14.0 CDn or SDn to Qn or Qn 5.0 1.0 10.5 ns ns ns ns Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements VCC Symbol Parameter (V) (Note 9) 54AC TA = −55˚C to +125˚C CL = 50 pF Fig. Units No. Guaranteed Minimum ts th tw trec Setup Time, HIGH or LOW 3.3 8.0 Jn or Kn to CPn 5.0 5.5 Hold Time, HIGH or LOW 3.3 0 Jn or Kn to CPn 5.0 0.5 Pulse Width 3.3 8.0 CDn or SDn or CPn 5.0 5.5 Recovery Time 3.3 0.5 CDn or SDn to CPn 5.0 0.5 ns ns ns ns Note 9: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V 5 www.national.com AC Electrical Characteristics 54ACT TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 10) Min fmax Maximum Clock Units Max 5.0 85 MHz 5.0 1.0 14.0 ns 5.0 1.0 12.0 ns 5.0 1.0 11.5 ns 5.0 1.0 12.5 ns Frequency tPLH Propagation Delay CPn to Qn or Qn tPHL Propagation Delay CPn to Qn or Qn tPLH Propagation Delay CDn or SDn to Qn or Qn tPHL Propagation Delay CDn or SDn to Qn or Qn Note 10: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements VCC Symbol Parameter (V) (Note 11) 54ACT TA = −55˚C to +125˚C CL = 50 pF Units Guaranteed Minimum Setup Time, HIGH or LOW ts 5.0 2.5 ns 5.0 2.0 ns 5.0 5.0 ns 5.0 0.5 ns Jn or Kn to CPn th Hold Time, HIGH or LOW Jn or Kn to CPn tw Pulse Width CPn or CDn or SDn trec Recovery Time CDn or SDn to CPn Note 11: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol CIN CPD Typ Units Input Capacitance Parameter 4.5 pF Power Dissipation 35.0 pF Capacitance www.national.com 6 Conditions VCC = OPEN VCC = 5.0V Physical Dimensions inches (millimeters) unless otherwise noted 20 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 16 Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 7 www.national.com 54AC109 • 54ACT109 Dual JK Positive Edge-Triggered Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16 Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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