54AC174 • 54ACT174 Hex D Flip-Flop with Master Reset General Description The ’AC/’ACT174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flops. n Outputs source/sink 24 mA n ’ACT174 has TTL-compatible inputs n Standard Microcircuit Drawing (SMD) — ’AC174: 5962-87626 — ’ACT174: 5962-87757 Features n ICC reduced by 50% Logic Symbols Pin Names Description D0–D5 Data Inputs CP Clock Pulse Input MR Master Reset Input Q0–Q5 Outputs DS100277-1 IEEE/IEC DS100277-2 FACT™ is a trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100277 www.national.com 54AC174 • 54ACT174 Hex D Flip-Flop with Master Reset July 1998 Connection Diagrams Pin Assignment for LCC Pin Assignment for DIP and Flatpak DS100277-4 DS100277-3 Functional Description The ’AC/’ACT174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input’s state is transferred to the corresponding flip-flop’s output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. The ’AC/’ACT174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Truth Table Inputs Output MR CP D L X X L H N H H H N L L H L X Q Q H = HIGH Voltage Level L = LOW Voltage Level N = LOW-to-HIGH Transition X = Immaterial Logic Diagram DS100277-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP Supply Voltage (VCC) ’AC ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA −65˚C to +150˚C 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT™ circuits outside databook specifications. 175˚C DC Characteristics for ’AC Family Devices Symbol Parameter VCC 54AC TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH Minimum High Level 3.0 2.1 Input Voltage 4.5 3.15 5.5 3.85 Maximum Low Level 3.0 0.9 Input Voltage 4.5 1.35 5.5 1.65 Minimum High Level 3.0 2.9 Output Voltage 4.5 4.4 5.5 5.4 VOUT = 0.1V V or VCC − 0.1V V or VCC − 0.1V VOUT = 0.1V IOUT = −50 µA V (Note 2) VIN = VIL or VIH VOL 3.0 2.4 4.5 3.7 5.5 4.7 Maximum Low Level 3.0 0.1 Output Voltage 4.5 0.1 5.5 0.1 IOH = −12 mA V IOH = −24 mA IOH = −24 mA IOUT = 50 µA V (Note 2) VIN = VIL or VIH IIN Maximum Input 3.0 0.50 4.5 0.50 5.5 0.50 5.5 ± 1.0 IOL = 12 mA V IOL = 24 mA µA IOL = 24 mA VI = VCC, GND Leakage Current IOLD IOHD Minimum Dynamic Output Current (Note 3) 5.5 50 mA 5.5 −50 mA 3 VOLD = 1.65V Max VOHD = 3.85V Min www.national.com DC Characteristics for ’AC Family Devices Symbol Parameter (Continued) VCC 54AC TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits ICC Maximum Quiescent 5.5 80.0 VIN = VCC µA Supply Current or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C. DC Characteristics for ’ACT Family Devices Symbol Parameter VCC 54ACT TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low Level 4.5 0.8 Input Voltage 5.5 0.8 Minimum High Level 4.5 4.4 Output Voltage 5.5 5.4 V VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA (Note 5) VIN = VIL or VIH VOL 4.5 3.70 5.5 4.70 Maximum Low Level 4.5 0.1 Output Voltage 5.5 0.1 V IOH = −24 mA V IOH = −24 mA IOUT = 50 µA (Note 5) VIN = VIL or VIH IIN Maximum Input 4.5 0.50 5.5 0.50 V IOL = 24 mA ± 1.0 µA IOL = 24 mA VI = VCC, GND 5.5 5.5 1.6 mA VI = VCC − 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC Leakage Current ICCT Maximum ICC/Input IOLD Minimum Dynamic Output Current (Note 6) 5.5 50 mA IOHD 5.5 −50 mA ICC Maximum Quiescent 5.5 80.0 µA Supply Current or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C. www.national.com 4 AC Electrical Characteristics VCC Symbol Parameter 54AC TA = −55˚C to +125˚C CL = 50 pF (V) (Note 8) Min fmax tPLH tPHL tPHL Maximum Clock 3.3 65 Frequency 5.0 90 Units Fig. No. Max MHz Propagation Delay 3.3 1.0 14.0 CP to Qn 5.0 1.5 10.5 Propagation Delay 3.3 1.0 13.0 CP to Qn 5.0 1.5 10.0 Propagation Delay 3.3 1.0 13.5 MR to Qn 5.0 1.5 11.0 ns ns ns Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements 54AC TA = −55˚C VCC Symbol Parameter (V) Fig. to +125˚C CL = 50 pF (Note 9) Units No. Guaranteed Minimum ts th tw tw trec Setup Time, HIGH or LOW 3.3 7.5 Dn to CP 5.0 5.5 Hold Time, HIGH or LOW 3.3 3.0 Dn to CP 5.0 3.0 MR Pulse Width, LOW 3.3 7.0 5.0 5.0 3.3 7.0 5.0 5.0 CP Pulse Width Recovery Time 3.3 3.0 MR to CP 5.0 2.0 ns ns ns ns ns Note 9: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Electrical Characteristics Symbol Parameter 54ACT TA = −55˚C to +125˚C CL = 50 pF VCC (V) (Note 10) Min fmax Maximum Clock Units Fig. No. Max 5.0 95 MHz 5.0 1.5 12.5 ns 5.0 1.5 13.0 ns 5.0 1.5 12.0 ns Frequency tPLH Propagation Delay CP to Qn tPHL Propagation Delay CP to Qn tPHL Propagation Delay MR to Qn Note 10: Voltage Range 5.0 is 5.0V ± 0.5V 5 www.national.com AC Operating Requirements 54ACT TA = −55˚C VCC Symbol Parameter (V) (Note 11) to +125˚C CL = 50 pF Fig. Units Guaranteed Minimum ts Setup Time, HIGH or LOW 5.0 3.0 ns 5.0 2.0 ns Dn to CP th Hold Time, HIGH or LOW Dn to CP tw MR Pulse Width, LOW 5.0 5.0 ns tw CP Pulse Width, HIGH OR LOW 5.0 5.0 ns trec Recovery Time 5.0 1.0 ns MR to CP Note 11: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol CIN CPD Parameter Typ Units Input Capacitance 4.5 pF Power Dissipation 85.0 pF Capacitance www.national.com 6 Conditions VCC = OPEN VCC = 5.0V No. Physical Dimensions inches (millimeters) unless otherwise noted 20-Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 16-Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 7 www.national.com 54AC174 • 54ACT174 Hex D Flip-Flop with Master Reset Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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