SN74CBTLV1G125-Q1 www.ti.com................................................................................................................................................................................................ SCDS289 – AUGUST 2009 LOW-VOLTAGE SINGLE FET BUS SWITCH Check for Samples: SN74CBTLV1G125-Q1 FEATURES 1 • • • • DBV PACKAGE (TOP VIEW) Qualified for Automotive Applications 5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation OE 1 A 2 GND 3 5 VCC 4 B See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION The SN74CBTLV1G125 features a single high-speed line switch. The switch is disabled when the output-enable (OE) input is high. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION (1) TA –40°C to 125°C (1) (2) PACKAGE SOT-23 – DBV (2) ORDERABLE PART NUMBER Reel of 3000 74CBTLV1G125DBVRQ1 TOP-SIDE MARKING VCTO For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Table 1. FUNCTION TABLE INPUT OE FUNCTION L A port = B port H Disconnect LOGIC DIAGRAM (POSITIVE LOGIC) 2 A OE 4 SW B 1 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated SN74CBTLV1G125-Q1 SCDS289 – AUGUST 2009................................................................................................................................................................................................ www.ti.com SIMPLIFIED SCHEMATIC, EACH FET SWITCH A B (OE) ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VCC VI MIN MAX Supply voltage range –0.5 4.6 (2) –0.5 Input voltage range Continuous channel current IIK Input clamp current θJA Package thermal impedance Tstg Storage temperature range (1) (2) (3) VI/O < 0 (3) DBV package –65 UNIT V 4.6 V 128 mA –50 mA 206 °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage VIH High-level control input voltage VIL Low-level control input voltage TA Operating free-air temperature (1) 2 MIN MAX 2.3 3.6 VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 V V VCC = 2.3 V to 2.7 V 0.7 VCC = 2.7 V to 3.6 V 0.8 –40 UNIT 125 V °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN74CBTLV1G125-Q1 SN74CBTLV1G125-Q1 www.ti.com................................................................................................................................................................................................ SCDS289 – AUGUST 2009 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT –1.2 V μA VIK VCC = 3 V, II = –18 mA II VCC = 3.6 V, VI = VCC or GND ±1 VCC = 0, VI or VO = 0 to 3.6 V, OE = 3.6 V 15 Ioff VCC = 0, VI or VO = 0 to 3.6 V, OE = 0 V ICC VCC = 3.6 V, VI = VCC or GND ΔICC (2) Ci Control inputs VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND Control inputs VI = 3 V or 0 Cio(OFF) VO = 3 V or 0, OE = VCC VI = 0 VI = 1.7 V, (3) VI = 0 VCC = 3 V VI = 2.4 V, (1) (2) (3) 10 μA μA pF 7 II = 32 mA μA 300 2.5 VCC = 2.3 V, TYP at VCC = 2.5 V ron 100 pF 7 10 II = 24 mA 7 10 II = 15 mA 15 25 II = 32 mA 5 7 II = 24 mA 5 7 II = 15 mA 10 15 Ω All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Measured by the voltage drop between A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 3.3 V ± 0.3 V TO (OUTPUT) A or B B or A ten OE A or B 0.5 8 tdis OE A or B 0.5 8 tpd (1) VCC = 2.5 V ± 0.2 V FROM (INPUT) PARAMETER (1) MIN MAX MIN 0.15 UNIT MAX 0.25 ns 0.5 7.5 ns 0.5 7.5 ns The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN74CBTLV1G125-Q1 3 SN74CBTLV1G125-Q1 SCDS289 – AUGUST 2009................................................................................................................................................................................................ www.ti.com PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND RL VCC 2.5 V ±0.2 V 3.3 V ±0.3 V LOAD CIRCUIT CL RL V∆ 30 pF 50 pF 500 Ω 500 Ω 0.15 V 0.3 V VCC Timing Input VCC/2 0V tw tsu VCC VCC/2 Input VCC/2 th VCC VCC/2 Data Input VCC/2 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC VCC/2 Input VCC/2 0V tPHL tPLH VOH VCC/2 Output VCC/2 VOL tPHL VCC/2 VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 0V tPZL Output Waveform 1 S1 at 2 × VCC (see Note B) tPLH VOH Output VCC Output Control tPLZ VCC VCC/2 tPZH VOL + V∆ tPHZ VCC/2 VOH − V∆ CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING A. F. VOL Figure 1. Load Circuit and Voltage Waveforms 4 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN74CBTLV1G125-Q1 PACKAGE OPTION ADDENDUM www.ti.com 2-Oct-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing 74CBTLV1G125DBVRQ1 ACTIVE SOT-23 DBV Pins Package Eco Plan (2) Qty 5 3000 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. 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OTHER QUALIFIED VERSIONS OF SN74CBTLV1G125-Q1 : • Catalog: SN74CBTLV1G125 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing 74CBTLV1G125DBVRQ1 SOT-23 DBV 5 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 179.0 8.4 Pack Materials-Page 1 3.2 B0 (mm) K0 (mm) P1 (mm) 3.2 1.4 4.0 W Pin1 (mm) Quadrant 8.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74CBTLV1G125DBVRQ1 SOT-23 DBV 5 3000 203.0 203.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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