TI TPS5102_08

TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
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DBT PACKAGE
(TOP VIEW)
Dual, Step-Down for Notebook System
Power
4.5 V to 25 V Input Voltage Range
Adjustable Output Voltage
95% Efficiency Achievable
PWM/Skip Mode Control Maintains High
Efficiency Under Light Load Conditions
Fixed-Frequency Operation
Resistorless Current Protection
Fixed High-Side Driver Voltage
Low Quiescent Current (0.6 mA, <1 µA for
Standby)
Small 30-Pin TSSOP
EVM Available (TPS5102EVM-135)
INV1
FB1
SOFTSTART1
PWM_SKIP
CT
RT
GND
REF
STBY1
STBY2
VCC
COMP
SOFTSTART2
FB2
INV2
description
1
30
2
29
3
28
4
27
5
26
6
25
7
24
8
23
9
22
10
21
11
20
12
19
13
18
14
17
15
16
LH1
OUT1_u
LL1
OUT1_d
OUTGND1
TRIP1
VCC_CNTP
TRIP2
VREF5
REG5V_IN
OUTGND2
OUT2_d
LL2
OUT2_u
LH2
The TPS5102 is a dual, high efficiency controller designed for notebook system power requirements. Under light
load conditions, high efficiency is maintained as the controller switches from the PWM mode to the lower
frequency Skip mode.
These two operating modes, along with the synchronous-rectifier drivers, dead-time, and very low quiescent
current, allow power to be conserved and the battery life extended, under all load conditions.
The resistor-less current protection and fixed high-side driver voltage simplify the system design and reduce
the external parts count. The wide input voltage range and adjustable output voltages allow flexibility for using
the TPS5102 in notebook power supply applications.
5V
+
C1
R3
Q1
R7
GND
C3
L1
R5
U1
TPS5102DBT
C7
D1
R8
Vo1
Q2
+
C10
C12
C4
C8
R2
R9
R10
C2
C5
C13
C11
+
Q3
C6
Vo2
R4
D2
C9
R1
R11
L2
Q4
R6
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
functional block diagram
VCC
To Channel 2
STNBY2
VREF5
STNBY1
VREF5
REF
REG5V_IN
1.185 V
REF
UVLO
+
_
_
+
To
Channel 2
4.5 V
RT
OSC
3.8 V
CT
To Channel 2
COMP
LH
To
Channel 2
To
Channel 2
+
_
1.1 V
OUT_U
LL
1 Shot
PWM/SKIP
OUT_D
SOFTSTART
SOFTSTART
OUTGND
_
+
Sync.
Signal
Skip Comp
To
Channel 2
VCC_CNTP
_
INV
_
+
+
+
+
_
PWM Comp
Error Amp
FB
1.185 V
2
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TRIP
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
AVAILABLE OPTIONS
PACKAGE
TA
EVM
TSSOP(DBT)
–40°C to 85°C
TPS5102IDBT
TPS5102EVM-135
TPS5102IDBTR
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
COMP
12
I/O
Voltage monitor comparator input
CT
5
I/O
External capacitor connection for switching frequency adjustment
FB1
2
O
CH1 error amp output
FB2
14
O
CH2 error amp output
GND
7
INV1
1
I
CH1 inverting input
INV2
15
I
CH2 inverting input
LH1
30
I/O
CH1 boost capacitor connection
LH2
16
I/O
CH2 boost capacitor connection
LL1
28
I/O
CH1 boost circuit connection
LL2
18
I/O
CH2 boost circuit connection
OUT1_d
27
I/O
CH1 low-side gate-drive output
OUT2_d
19
O
CH2 low-side gate-drive output
OUT1_u
29
O
CH1 high-side drive output
OUT2_u
17
O
CH2 high-side drive output
OUTGND1
26
Output GND 1
OUTGND2
20
Output GND 2
PWM_SKIP
4
I
PWM/SKIP mode select
L:PWM mode
H:SKIP mode
REF
8
O
1.185-V reference voltage output
REG5V_IN
21
I
External 5-V input
RT
SOFTSTART1
6
I/O
External resistor connection for switching frequency adjustment
3
I/O
External capacitor connection for CH1soft start timing.
SOFTSTART2
13
I/O
External capacitor connection for CH2 soft start timing.
STBY1
9
I
CH1 stand-by control
STBY2
10
I
CH2 stand-by control
TRIP2
23
I
External resistor connection for CH2 over current protection.
TRIP1
25
I
External resistor connection for CH1 over current protection.
VCC
Vref5
11
22
O
5-V internal regulator output
VCC_CNTP
24
I
Supply voltage sense input
Control GND
Supply voltage input
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TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
detailed description
Vref (1.185 V)
The reference voltage is used to set the output voltage and the overvoltage protection (COMP).
Vref5 (5 V)
The internal linear voltage regulator is used for the high-side driver bootstrap voltage. Since the input voltage
range is from 4.5 V to 25 V, this feature offers a fixed voltage for the bootstrap voltage greatly simplifying the
drive design. It is also used for powering the low side driver. The tolerance is 6%.
5-V Switch
If the internal 5 V switch senses a 5-V input from REG5V_IN pin, the internal 5-V linear regulator will be
disconnected from the MOSFET drivers. The external 5 V will be used for both the low-side driver and the high
side bootstrap, thus increasing the efficiency.
PWM/SKIP
This pin is used to change between PWM and Skip mode. If the pin is lower than 0.5-V, the IC is in regular PWM
mode; if a minimum 2-V is applied to this pin, the IC works in Skip mode. In light load condition (<0.2 A), the
skip mode gives a short pulse to the low-side FET instead of a full pulse. By this control, switching frequency
is lowered, reducing switching loss; also the output capacitor energy discharging through the output inductor
and the low-side FET is prevented. Therefore, the IC can achieve high efficiency at light load conditions
(< 0.2 A).
err-amp
Each channel has its own error amplifier to regulate the output voltage of the synchronous-buck converter. It
is used in the PWM mode for the high output current condition (>0.2A). Voltage mode control is applied.
skip comparator
In Skip mode, each channel has its own hysteretic comparator to regulate the output voltage of the
synchronous-buck converter. The hysteresis is set internally and typically at 8.5 mV. The delay from the
comparator input to the driver output is typically 1.2 µs.
low-side driver
The low-side driver is designed to drive low-Rds(on) n-channel MOSFETs. The maximum drive voltage is 5 V
from Vref5. The current rating of the driver is typically 1 A, source and sink.
high-side driver
The high side driver is designed to drive low-Rds(on) n-channel MOSFETs. The current rating of the driver is
1 A, source and sink. When configured as a floating driver, the bias voltage to the driver is developed from Vref5,
limiting the maximum drive voltage between OUT_u and LL to 5 V. The maximum voltage that can be applied
between LHx and OUTGND is 30 V.
deadtime control
Deadtime prevents shoot–through current from flowing through the main power FETs during switching
transitions by actively controlling the turn-on time of the MOSFETs drivers. The typical deadtime from
low-side-driver-off to high-side-driver-on is 70 ns, and 85 ns from high-side-driver-off to low-side-driver-on.
4
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TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
detailed description (continued)
current protection
Current protection is achieved by sensing the high-side power MOSFET drain-to-source voltage drop during
on-time at VCC_CNTP and LL. An external resistor between Vin and TRIP pin in serial with the internal current
source adjusts the current limit. When the voltage drop during the on-time is high enough, the current
comparator triggers the current protection and the circuit is reset. The reset repeats until the over-current
condition is removed.
COMP
COMP is an internal comparator used for any voltage protection such as the output under-voltage protection
for notebook power applications. If the core voltage is lower than the setpoint, the comparator turns off both
channels to prevent the notebook from damage.
SOFT1, SOFT2
Separate softstart terminals make it possible to set the start-up time of each output for any possibility.
STBY1, STBY2
Both channels can be switched into standby mode separately by grounding the STBY pin. The standby current
is as low as 1 µA.
ULVO
When the input voltage goes up to about 4 V, the IC is turned on, ready to function. When the input voltage is
lower than the turn-on value, the IC is turned off. The typical hysteresis is 40 mV.
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TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, Vcc (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 27 V
Input voltage, INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V
SOFTSTART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V
COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6 V
REG5_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6 V
STBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 15 V
Driver current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A
TRIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 27 V
CT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V
RT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V
LL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 27 V
LH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 32 V
OUT_u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 32 V
OUT_d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V
PWM/SKIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V
VCC_Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 27V
Power dissipation (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874 mW
Operating temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
Operating temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 125°C
Storage temperature (TSTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the network ground terminal.
2. This rating is specified at duty ≤ 10% on output rise and fall each pulse. Each pulse width (rise and fall) for the peak current should
not exceed 2 µs.
3. See Dissipation Rating Table for free-air temperature range above 25°C.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
DBT
874 mW
6.993 mW/°C
454 mW
recommended operating conditions
PARAMETERS
MIN
Supply voltage, Vcc
INV1/2 CT RT,
PWM/SKIP,
-0.1
V
-0.1
V
25
CT
100
pF
RT
fosc
82
kΩ
PWM
200
Operation temperature range, TA
6
5.5
12
VCC_SENSE
UNIT
6
STBY1, STBY2
TRIP1/2
MAX
25
SOFTSTART
5 V_IN
voltage VI
Input voltage,
Oscillator frequency
NOM
4.5
-40
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• DALLAS, TEXAS 75265
KHz
85
°C
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range, VCC = 7 V
(unless otherwise noted)
reference voltage
PARAMETER
TEST CONDITIONS
Vref
Reference voltage
TA = 25°C,
Ivref = 50 µA
Ivref = 50 µA
Regin
Line regulation
Vcc = 4.5, 25V,
I = 50 µA
Regl
Load regulation
I = 0.1 µA to 1 mA
MIN
TYP
MAX
1.167
1.185
1.203
1.155
1.215
UNIT
V
0.2
12
mV
0.5
10
mV
TYP
MAX
0.6
1.5
mA
1
1000
nA
TYP
MAX
UNIT
500
kHz
quiescent current
PARAMETER
TEST CONDITIONS
Icc
Operating current without switching
Both STBY > 2.5 V,
No switching,
Vin = 4.5 – 25 V
Iccs
Stand-by current
Both STBY < 0.5 V, Vin = 4.5 – 25 V
MIN
UNIT
oscillator
PARAMETER
fosc
Frequency
RT
fdv
Timing resistor
fdt
TEST CONDITIONS
MIN
PWM operation
56
Vcc = 4.5 V to 25 V
fosc change
VoscH
H
H level output voltage
H-level
VoscL
L
L level output voltage
L-level
kΩ
0.1%
TA = -40°C to 85°C
DC, includes internal comparator error
2%
1
Fosc = 200 kHz, Includes internal comparator error
Includes internal comparator error
1.1
1.2
1.17
0.4
Fosc = 200 kHz, Includes internal comparator error
0.5
0.6
0.43
V
V
error amp
PARAMETER
TEST CONDITIONS
Vio
Input offset voltage
Av
Open-loop voltage gain
GB
Unity-gain bandwidth
Isnk
Output sink current
Vo = 0.4 V
Isrc
Output source current
Vo = 1 V
MIN
TA = 25°C
TYP
MAX
UNIT
±2
±10
mV
50
30
dB
0.8
MHz
45
µA
300
µA
skip comparator
PARAMETER
Vhys†
Hysteresis window
Vhoff
Offset voltage
Ihbias
Bias current
TEST CONDITIONS
TLHT
Propagation delay‡ from INV to OUTxU
TLH
† Vhys is assured by design.
‡ The total delay in the table includes the driver delay.
MIN
TYP
MAX
6
9.5
13
UNIT
mV
2
mV
10
pA
TTL input signal
0.7
µs
10 mV overdrive on hysteresis band signal
1.2
µs
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TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range, VCC = 7 V
(unless otherwise noted) (continued)
driver deadtime
PARAMETER
TDRVLH
TDRVHL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Low side to high side
70
nS
High side to low side
85
nS
standby
PARAMETER
VIH
VIL
H-level input voltage
Tturnon
Tturnoff
Propagation delay
L-level input voltage
Propagation delay
TEST CONDITIONS
MIN
TYP
MAX
2.5
STBY1 STBY2
STBY1,
0.5
1.5
STBY to driver output
UNIT
V
µs
1.8
5V regulator
PARAMETER
TEST CONDITIONS
MIN
TYP
4.7
MAX
UNIT
VO
Regin
Output voltage
I = 10 mA
5.3
V
Line regulation
Vcc = 5.5 V, 25 V,
I = 10 mA
20
mV
Regl
Load regulation
I = 1 V, 10 mA,
Vcc = 5.5 V
40
mV
Ios
Short-circuit output current
Vref = 0 V
80
mA
5-V internal switch
PARAMETER
VTLH
VTHL
Threshold voltage
Vhys
Hysteresis
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4.2
4.8
V
4.1
4.7
V
30
150
mV
MAX
UNIT
UVLO
PARAMETER
VTLH
VTHL
Threshold voltage
Vhys
Hysteresis
TEST CONDITIONS
MIN
TYP
3.7
4.2
V
3.6
4.1
V
10
40
150
mV
UNIT
current limit
PARAMETER
Internal current source
MIN
TYP
MAX
PWM mode
TEST CONDITIONS
10
15
20
Skip mode
3
5
7
Input offset voltage
2.5
µA
mV
driver output
PARAMETER
OUT_u sink current
OUT_d sink current
OUT_u source current
OUT_d source current
8
TEST CONDITIONS
Vo = 3 V
Vo = 3 V
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• DALLAS, TEXAS 75265
MIN
TYP
0.5
1.2
0.5
1.2
–1
–1.7
–1
–1.5
MAX
UNIT
A
A
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range, VCC = 7 V
(unless otherwise noted) (continued)
softstart
PARAMETER
ICTRL
TEST CONDITIONS
Soft-start current
MIN
1.8
Maximum discharge current
VTLH
VTHL
TYP
MAX
2.5
3
0.92
Threshold voltage (skip mode)
UNIT
µA
mA
3.4
3.9
4.7
1.8
2.6
3.4
MIN
TYP
MAX
0.9
1.1
1.3
V
output voltage protection (COMP)
PARAMETER
TEST CONDITIONS
Threshold voltage
Progagation delay†, 50% duty cycle,
No capacitor on COMP or OUT_u pin,
Frequency = 200 kHz
UNIT
V
Turnon
900
ns
Turnoff (with channel on)
400
ns
† The delay time in the table includes the driver delay.
PWM/SKIP
PARAMETER
Threshold
Delay
TEST CONDITIONS
MIN
TYP
High to low
0.5
Low to high
2
High to low
550
Low to high
400
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MAX
• DALLAS, TEXAS 75265
UNIT
V
ns
9
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT (BOTH CHANNELS ON)
vs
INPUT VOLTAGE
QUIESCENT CURRENT (BOTH CHANNELS STANDBY)
vs
INPUT VOLTAGE
800
160
TJ = 125°C
140
IOff – Quiescent Current – nA
IQ – Quiescent Current –µ A
700
600
500
TJ = 25°C
TJ = -40°C
400
300
200
100
120
100
TJ = 125°C
80
60
40
TJ = -40°C
TJ = 25°C
20
0
0
10
20
VCC - Supply Voltage - V
0
30
20
7
10
15
VCC - Supply Voltage - V
4.5
Figure 1
Figure 2
DRIVE CURRENT (SOURCE)
vs
DRIVE VOLTAGE
DRIVE CURRENT (SINK)
vs
DRIVE VOLTAGE
3.5
3
5
TJ = -40°C
4
TJ = 25°C
TJ = 125°C
3
2
1
0
0.1
0.5
1
I(src) - Driver Source Current - A
V(snk) – Driver Output Voltage – V
V(src) – Driver Output Voltage – V
6
2.5
TJ = 125°C
2
TJ = 25°C
1.5
1
TJ = -40°C
0.5
0
0.1
Figure 3
10
1
0.5
I(snk) - Driver Sink Current - A
Figure 4
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• DALLAS, TEXAS 75265
25
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
TYPICAL CHARACTERISTICS
CURRENT PROTECTION SOURCE CURRENT
(SKIP MODE)
vs
INPUT VOLTAGE
CURRENT PROTECTION SOURCE CURRENT
(PWM MODE)
vs
INPUT VOLTAGE
14
5.2
13.8
5
I (trip) – Source Current – µ A
I (protec)– Source Current – µ A
TJ = 125°C
TJ = 125°C
5.1
4.9
4.8
4.7
4.6
TJ = 25°C
4.5
13.6
TJ = 25°C
13.4
13.2
TJ = -40°C
13
TJ = -40°C
4.4
12.8
4.3
12.6
4.2
0
20
10
VCC - Supply Voltage - V
4.5
30
7
10
15
20
VCC - Supply Voltage - V
Figure 6
Figure 5
PWM/SKIP THRESHOLD VOLTAGE
vs
INPUT VOLTAGE
1
Vref5 VOLTAGE
vs
CURRENT
5.1
TJ = -40°C
0.9
TJ = 25°C
0.7
TJ = 125°C
V ref5 – Voltage – V
V T – Threshold Voltage – V
TJ = 125°C
5
0.8
25
0.6
0.5
0.4
0.3
0.2
4.9
TJ = 25°C
4.8
TJ = -40°C
4.7
4.6
0.1
0
0
10
20
VI - Supply Voltage - V
30
4.5
0
Figure 7
–10
–20
–30
Ir - Current - mA
–40
–50
Figure 8
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TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
TYPICAL CHARACTERISTICS
SOFT START CHARGE CURRENT
vs
JUNCTION TEMPERATURE
MAXIMUM OUTPUT VOLTAGE
vs
SWITCHING FREQUENCY
–3
2.5
–2.5
Soft Start Charge Current
Maximum Output Voltage
2
1.5
1
0.5
–2
–1.5
–1
–0.5
0
0
1
100
10
–40
1000
Switching Frequency – kHz
Figure 9
–20
0
25
50
70
95
TJ - Junction Temperature - °C
Figure 10
SWITCHING FREQUENCY
vs
TIMING RESISTOR
1000
Switching Frequency
Ct = 47 pF
100
Ct = 100 pF
Ct = 150 pF
Ct = 220 pF
Ct = 330 pF
10
10
100
Timing Resistor - kΩ
Figure 11
12
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1000
125
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
TYPICAL CHARACTERISTICS
timing diagram
1.17 V Typ.
Err. Amplifier Output
0.43 V Typ.
High
Oscillator Output
Delay
OUTx_u
(100 nS Typ.)
Delay
Low
Duty
High
OUTx_d
Low
(100 nS Typ.)
Detected Over Current
Over-Current
Protection
High
Low
Current Limit
Inductor Current
IL = 0
TRIPx Voltage
LLx Voltage
GND
-Vf
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TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
APPLICATION INFORMATION
The design shown in this application report is a reference design for notebook applications. An evaluation
module (EVM), TPS5102EVM-135 (SLVP135), is available for customer testing and evaluation. The intent is
to allow a customer to fully evaluate the given design using the plug-in EVM supply shown here. For subsequent
customer board revisions, the EVM design can be copied onto the users’ PCB to shorten design cycle.
The following key design procedures will aid in the design of the notebook power supply using the TPS5102:
TP27
C6
R3
R5
SLVP135 EVM
Q1
TP26
R17
R4
L1
TP1
TP24
TP2
TP23
D1 C4
J5
TP21
R18
TP8
TP20
R19
TP9
TP19
TP6
TP7
C11
R10
R11
C19
J6
J15
J16
R21
TP10
C1
J7
J8
GND
J9
J10
GND
J11
TP11
R12
C12
TP12
C13
TP13
J12
TP18
C5
C15
D2
C21
TP14
Q4
TP17
TP15
TP16 D4
R13
C14
C20
Vo1
Vo1
Vo1GND
Vo1GND
Vin
Vin
Input GND
Input GND
Vo2GND
Vo2GND
Vo2
Vo2
RS2
C3
TP25
R14
J14
RS1
R2
L2
R20
R15
+
J13
C23
+
JP2
J4
C18
TP5
R9
J3
C22
TP22
TP4
C10
J2
+
C9
J1
Q2
C17
TP3
R8
R1
D3
+
C7
JP1
C2
+
C8
R6
Q3
TP28
R16 C16
Vin
Iin
Vo1
Io1
Vo2
6 V to 15 V
6 A
3.3 V
4 A
5 V
4 A
3.3 V
2.5 A
5V
2.5 A
16 V to 25 V
Io2
output voltage setpoint calculation
The output voltage is set by the reference voltage and the voltage divider. In the TPS5102, the reference voltage
is 1.185-V, and the divider is composed of two resistors in the EVM design that are R4 and R5, or R14 and R15.
The equation for the setpoint is:
R2
1
Vr
+ RVo–Vr
Where R1 is the top resistor (kΩ) ( R4 or R15); R2 is the bottom resistor (kΩ) ( R5 or R14); Vo is the required
output voltage (V); Vr is the reference voltage (1.185 V in TPS5102).
Example: R1 = 1 kΩ; Vr = 1.185 V; Vo = 3.3 V, then R2 = 560 Ω.
Some of the most popular output voltage setpoints are calculated in the table below:
VO
14
1.3 V
1.5 V
1.8 V
2.5 V
3.3 V
5V
R1 (top) (kΩ)
1V
1V
1V
1V
1V
1V
R2 (bottom) (kΩ)
10 V
3.7 V
1.9 V
0.9 V
0.56 V
0.31 V
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TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
APPLICATION INFORMATION
output voltage setpoint calculation (continued)
If a higher precision resistor is used, the voltage setup can be more accurate.
In some applications, the output voltage is required to be lower than the reference voltage. With a few extra
components, the lower voltage can be easily achieved. The drawing below shows the method.
VCC
VO
R(top)
Rz1
INV
Rz2
TPS5102
R(bottom)
Zener
In the schematic, the Rz1, the Rz2, and the zener are the extra components. Rz1 is used to give the zener
enough current to build up the zener voltage. The zener voltage is added to INV through Rz2. Therefore, the
voltage on the INV is still equal to the IC internal voltage (1.185 V) even if the output voltage is regulated at a
lower setpoint. The equation for setting up the output voltage is shown below:
( Vz – Vr )
Rz 2 = ( Vr –Vo)
Vr
Rtop + Rbtm
When Rz2 is the adjusting resistor for low output voltage; Vz is the zener voltage; Vr is the internal reference
voltage; Rtop is the resistor of the voltage sensing network; Rbtm is the bottom resistor of the sensing
network;VO is the required output voltage setpoint.
Example: Assuming the required output voltage setpoint is VO = 0.8 V, VZ = 5 V; Rtop = 1 kΩ; Rbottom = 1 kΩ,
Then the Rz2 = 2.43 kΩ.
output inductor ripple current
The output inductor current ripple can affect not only the efficiency, but also the output voltage ripple. The
equation is exhibited below:
Iripple
+ Vin * Vout * Iout
Lout
(Rdson
)R )
L
D
Ts
Where Iripple is the peak-to-peak ripple current (A) through the inductor; Vin is the input voltage (V); Vout is the
output voltage (V); Iout is the output current; Rdson is the on-time resistance of MOSFET (Ω); D is the duty cycle;
and Ts is the switching cycle (S). From the equation, it can be seen that the current ripple can be adjusted by
changing the output inductor value.
Example: Vin = 5 V; Vout = 1.8 V; Iout = 5 A; Rdson = 10 mΩ; RL = 5 mΩ; D = 0.36; Ts = 10 µS; Lout = 6 µH
Then, the ripple Iripple = 2 A.
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TPS5102
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SLVS239 - SEPTEMBER 1999
APPLICATION INFORMATION
output capacitor RMS current
Assuming the inductor ripple current totally goes through the output capacitor to ground, the RMS current in the
output capacitor can be calculated as:
Iorms
+ ǸD12I
Where Io(rms) is the maximum RMS current in the output capacitor (A); ∆I is the peak-to-peak inductor ripple
current (A).
Example: ∆I = 2 A, so Io(rms) = 0.58 A
input capacitor RMS current
Assuming the input ripple current totally goes into the input capacitor to the power ground, the RMS current in
the input capacitor can be calculated as:
Iirms
+
Ǹ
Io 2
D
(1–D)
) 121 D
Iripple 2
Where Ii(rms) is the input RMS current in the input capacitor (A); Io is the output current (A); Iripple is the
peak-to-peak output inductor ripple current; D is the duty cycle. From the equation, it can be seen that the
highest input RMS current usually occurs at the lowest input voltage, so it is the worst case design for input
capacitor ripple current.
Example: Io = 5 A; D = 0.36; Iripple = 2 A,
Then, Ii(rms) = 2.42 A
soft-start
The soft-start timing can be adjusted by selecting the soft-start capacitor value. The equation is
C soft
+2
T soft
Where Csoft is the soft-start capacitance (µF) (C9 or C13 in EVM design); Tsoft is the start-up time (S).
Example: Tsoft = 5 mS, so Csoft = 0.01 µF.
16
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TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
APPLICATION INFORMATION
current protection
The current limit in TPS5102 on each channel is set using an internal current source and an external resistor
(R18 or R19). The sensed high side MOSFET drain-to-source voltage drop is compared to the set point, if the
voltage drop exceeds the limit, the internal oscillator is activated, and it continuously reset the current limit until
the over-current condition is removed. The equation below should be used for calculating the external resistor
value for current protection setpoint:
Rcl
+ Rds(on)
In skip mode,
Rcl
+ Rds(on)
)
ń
)
ń
(Itrip Iind(p-p) 2)
0.000015
(Itrip Iind(p-p) 2)
0.000005
Where Rcl is the external current limit resistor (R10 or R11); Rds(on) is the high side MOSFET (Q1 or Q3)
on-time resistance. Itrip is the required current limit; Iind(p-p) is the peak-to-peak output inductor current.
Example for voltage mode: Rds(on) = 10 mΩ, Itrip = 5 A, Iind = 2 A, so Rcl = 4 kΩ.
loop-gain compensation
Voltage mode control is used in this controller for the output voltage regulation. To achieve fast, stabilized
control, two parts are discussed in this section: the power stage small signal modeling and the compensation
circuit design.
For the buck converter, the small signal modeling circuit is shown below:
a
ZL
∧
d
Vap
D
+
ia
VO
C
∧
Ic d
VI
L
ic
D
1
+
RL
c
R
ZRC
RC
p
From this equivalent circuit, several control transfer functions can be derived: input-to-output, output
impedance, and control-to-output. Typically the control-to-output transfer function is used for the feedback
control design.
Assuming Rc and RL are much smaller than R, the simplified small signal control-to-output transfer function is:
Vod
∧
Vo
∧
d
+ +
1
ƪ
)s C
) sCRc)
ǒRc ) RLǓ ) RL ) s LC
(1
ƫ
2
Where C is the output capacitance; Rc is the equivalent serial resistance (ESR) in the output capacitor; L is the
output inductor; RL is the equivalent serial resistance (DCR) in the output inductor; R is the load resistance.
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TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
APPLICATION INFORMATION
loop-gain compensation (continued)
To achieve fast transient response and the better output voltage regulation, a compensation circuit is added to
improve the feedback control. The whole system is shown:
Power
Stage
PWM
Vref
Compensation
The typical compensation circuit used as an option in the EVM design is a part of the output feedback circuit.
The circuitry is displayed below:
R1
R2
R4
C3
C1
_
R3
C2
To PWM
+
Vref
This circuit is composed of one integrator, two poles, and two zeros:
Assuming R1 << R2 and C2 << C3, the equation is:
Comp
+ sC(13R)2(1sC)3RsC4) 2R4)(1(1))sCsC2R12)R1)
Therefore,
+ 2pC11R1
1
Pole2 +
2pC2R4
Pole1
+ 2pC12R2
1
Zero2 +
2pC3R4
Zero1
Integrator
A simplified version used in the EVM design is exhibited below:
18
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+ 2pC13R2
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
APPLICATION INFORMATION
loop-gain compensation (continued)
VO
R2
R4
_
R3
Vref
C3
C2
To PWM
+
Assuming C2 << C3, the equation is:
Comp
) sC3R4)
+ sC3(1R2(1
) sC2R4)
There is one pole, one zero and one integrator:
Zero
+ 2pC13R4
Integrator
+ 2pfC13R2
Pole
+ 2pC12R4
The loop-gain concept is used to design a stable and fast feedback control. The loop-gain equation is derived
by the control-to-output transfer function times the compensation:
Loop–gain
+ Vod
Comp
The amplitude and the phase of this equation can be drawn with software such as MathCad. In turn, the stability
can be easily designed by adjusting the compensation parameters. The sample bode plot is shown below to
explain the phase margin, gain margin, and the crossover frequency.
The gain is drawn as 20 log (loop-gain), and the phase is in degrees. To explain them clearer, 180 degrees is
added to the phase, so that the gain and phase share the same zero.
The crossover frequency is the point at which the gain curve touches zero. The higher this frequency, the faster
the transient response, since the transient recovery time is 1/(crossover frequency). The phase is the phase
margin. The phase margin should be at least 60 degrees to cover all changes such as temperature. The gain
margin is the gap between the gain curve and the zero when the phase curve touches zero. This margin should
be at least 20 dB to guarantee stability over all conditions.
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TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
APPLICATION INFORMATION
180
166
152
138
124
110
96
82
68
20 Log (Loop-Gain) 54
180 + Phase 40
26
12
–2
–16
–30
–44
–58
–72
–86
–100
10
Phase
Phase
Margin
Gain
Gain
Margin
Crossover
100
103
104
105
106
f – Frequency – Hz
synchronization
Some applications require switching clock synchronization. There are two methods that can be used for
synchronization: the triangle wave synchronization and the square wave synchronization.
The triangle wave synchronization is displayed below:
TPS5102
740 mV
Ct
740 mV
Rt
It can be seen that both Rt and Ct are removed from the circuit. Therefore, two components are saved. This
method is good for the synchronization between two controllers. If the controller needs to be synchronized with
a digital circuit such as DSP, the square-type clock signal is usually used. The configuration exhibited below is
for this type of application:
20
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TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
APPLICATION INFORMATION
synchronization (continued)
TPS5102
Ct
Rt
An external resistor is added into the circuit, but Rt is still removed. Ct is kept to be a part of RC circuit generating
triangle waveform for the controller. Assuming the peak value of the square is known, the resistor and the
capacitor can be adjusted to achieve the correct peak-to-peak value and the offset value.
layout guidelines
Good power supply results will only occur when care is given to proper design and layout. Layout will affect noise
pickup and generation and can cause a good design to perform with less than expected results. With a range
of currents from milliamps to tens or even hundreds of amps, good power supply layout is much more difficult
than most general PCB designs. The general design should proceed from the switching node to the output,
then back to the driver section and, finally, parallel the low-level components. Below are several specific points
to consider before the layout of a TPS5102 design begins.
D
D
D
D
D
D
D
D
D
D
D
All sensitive analog components should be referenced to ANAGND. These include components connected
to Vref5, Vref, INV, LH, and COMP.
Analog ground and drive ground should be isolated as much as possible. Ideally, analog ground will connect
to the ground side of the bulk storage capacitors on VO, and drive ground will connect to the main ground
plane close to the source of the low-side FET.
Connections from the drivers to the gate of the power FETs should be as short and wide as possible to
reduce stray inductance. This becomes more critical if external gate resistors are not being used.
The bypass capacitor for VCC should be placed close to the TPS5102.
When configuring the high-side driver as a floating driver, the connection from LL to the power FETs should
be as short and as wide as possible.
When configuring the high-side driver as a floating driver, the bootstrap capacitor (connected from LH to
LL) should be placed close to the TPS5102.
When configuring the high-side driver as a ground-referenced driver, LL should be connected to DRVGND.
The bulk storage capacitors across VIn should be placed close to the power FETS. High-frequency bypass
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and to the source of the low-side FET.
High-frequency bypass capacitors should be placed across the bulk storage capacitors on VO.
LH and LL should be connected very close to the drain and source, respectively, of the high-side FET. LH
and LL should be routed very close to each other to minimize differential-mode noise coupling to these
traces.
The output voltage sensing trace should be isolated by either ground trace or Vcc trace.
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TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
APPLICATION INFORMATION
PWM AND SKIP MODE EFFICIENCY
COMPARISON
PWM AND SKIP MODE EFFICIENCY
COMPARISON
95
Output = 3.3 V
100
PWM Mode
Output = 5 V
95
90
90
Skip Mode
Efficiency – %
Efficiency – %
85
80
75
85
PWM Mode
Skip Mode
80
75
70
70
65
65
60
0
0.2
0.8
0.4
0.6
IO - Output Current - A
1
60
1.2
0
0.2
Figure 12
1.2
EFFICIENCY
vs
OUTPUT CURRENT
100
100
Output = 5 V
Output = 3.3 V
95
95
90
90
Efficiency – %
Efficiency – %
1
Figure 13
EFFICIENCY
vs
OUTPUT CURRENT
85
PWM Mode
80
75
70
Skip Mode
85
PWM Mode
80
Skip Mode
75
70
65
65
60
60
0
1
2
3
IO - Output Current - A
4
5
0
Figure 14
22
0.8
0.4
0.6
IO - Output Current - A
1
2
3
IO - Output Current - A
Figure 15
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4
5
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
APPLICATION INFORMATION
EFFICIENCY
vs
OUTPUT CURRENT
OUTPUT LOAD REGULATION
100
3.4
Output Load = 3.3 V
Dual Output Efficiency
3.38
95
3.36
VO – Output Voltage – V
Efficiency – %
90
85
80
75
3.34
3.32
3.3
3.28
3.26
70
3.24
65
3.22
60
3.2
0
20
40
80
60
100
0
1
Output Current – %
Figure 16
3.4
Output Load = 5 V
Output Line = 3.3 V
5.08
3.38
5.06
3.36
VO – Output Voltage – V
VO – Output Voltage – V
5
OUTPUT LINE REGULATION
5.1
5.04
5.02
5
4.98
4.96
3.34
3.32
3.3
3.28
3.26
4.94
3.24
4.92
3.22
4.9
1
4
Figure 17
OUTPUT LOAD REGULATION
0
2
3
IO - Output Current - A
2
3
IO - Output Current - A
4
5
3.2
0
Figure 18
20
10
VI - Input Voltage - V
30
Figure 19
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TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
APPLICATION INFORMATION
OUTPUT LINE REGULATION
DIODE VERSION EFFICIENCY
5.1
95
Output Line = 5 V
Output Diode Version = 3.3 V
5.09
90
85
5.07
Efficiency – %
VO – Output Voltage – V
5.08
5.06
5.05
5.04
5.03
80
75
70
5.02
65
5.01
5
5
10
15
20
VI - Input Voltage - V
25
30
60
0
1
Figure 20
4
Figure 21
3.3–V OUTPUT VOLTAGE RIPPLE
5–V OUTPUT VOLTAGE RIPPLE
Figure 22
24
2
3
IO - Output Current - A
Figure 23
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5
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
APPLICATION INFORMATION
Table 1. Bill of Materials
REF.
PN
DESCRIPTION
MANUFACTURER
SIZE
C1
C1†opt
RV-35V221MH10-R
Capacitor, electrolytic, 220 µF, 35 V
ELNA
10x10mm
10TPB220M
Capacitor, POSCAP, 220 µF, 10 V
Sanyo
7.3x4.3mm
C2
GMK325F106ZH
Capacitor, ceramic, 10 µF, 35 V
Taiyo Yuden
1210
C3
GMK325F106ZH
Capacitor, ceramic, 10 µF, 35 V
Taiyo Yuden
1210
C4
4TPB470M
Capacitor, POSCAP, 470 µF, 4 V
Sanyo
7.3x4.3mm
C5
C5†opt
10TPB220M
Capacitor, POSCAP, 220 µF, 10 V
Sanyo
7.3x4.3mm
6TPB330M
Capacitor, POSCAP, 330 µF, 6.3 V
Sanyo
7.3x4.3mm
C6†
Standard
Open, capacitor, ceramic, 0.22 µF, 16 V
805
C7
Standard
Capacitor, ceramic, 0,01 µF, 16 V
805
C8
Standard
Capacitor, ceramic, 220 pF, 16 V
805
C9
Standard
Capacitor, ceramic, 0.01 µF, 16 V
805
C10
Standard
Capacitor, ceramic, 100 pF, 16 V
C11
Standard
Capacitor, ceramic, 1 µF, 16 V
muRata
805
C12
GMK316F225ZG
Capacitor, ceramic, 2.2 µF, 35 V
Taiyo Yuden
1206
C13
Standard
Capacitor, ceramic, 0.01 µF, 16 V
805
C14
Standard
Capacitor, ceramic, 220 pF, 16 V
805
C15
C16†
Standard
Capacitor, ceramic, 0.1 µF, 16 V
805
Standard
Open, capacitor, ceramic, 0.1 µF, 16 V
C17
GMK316F225ZG
Capacitor, ceramic, 2.2 µF, 35 V
C18
Standard
Open
C19
Standard
Open
C20
GMK325F106ZH
Capacitor, ceramic, 10 µF, 35 V
Taiyo Yuden
1210
C21
C22†
GMK316F225ZG
Capacitor, ceramic, 2.2 µF, 35 V
Taiyo Yuden
1206
805
805
Taiyo Yuden
1206
805
805
7.3x4.3mm
C23†
7.3x4.3mm
D1
MBRS340T3
Diode, Schottky, 40 V, 3 A
Motorola
SMC
D2
MBRS340T3
Diode, Schottky, 40 V, 3 A
Motorola
SMC
D3
SD103-AWDICT-ND
Diode, Schottky, 40 V, 200 mA
Digikey
3.5x1.5mm
D4
SD103-AWDICT-ND
Diode, Schottky, 40 V, 200 mA
Digikey
3.5x1.5mm
L1
DO3316P-682
Inductor, 6.8 µH, 4.4 A
Coilcraft
0.5x0.37in
L2
DO3316P-682
Inductor, 6.8 µH, 4.4 A
Coilcraft
0.5x0.37in
J1-J16
CA26DA-D36W-OFC
Edge connector, surface mount, 0.040” board, 0.090”
standoff
NAS Interplex
0.040in
JP1
S1132-2-ND
Header, straight, 2-pin, 0.1 ctrs, 0.3” pins
Sullins
DigiKey # 1132-2-ND
JP1 shunt
S1132-14-ND
Shunt, jumper, 0.1”
Sullins
DigiKey #
929950-00-ND
JP2
S1132-14-ND
Header, straight, 2-pin, 0.1 ctrs, 0.3” pins
Sullins
DigiKey # 1132-2-ND
R1
Standard
Resistor, 5.1 Ω, 5%
805
R2
R3†
Standard
Resistor, 5.1 Ω, 5%
805
Standard
Open
805
R4
Standard
Resistor, 1.21 kΩ, 1%
805
R5
Standard
Resistor, 680 Ω, 1%
805
R6
Standard
Resistor, 5.1 kΩ, 5%
805
Resistor, 1 kΩ, 5%
805
R8
Standard
† Option table
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
APPLICATION INFORMATION
Table 1. Bill of Materials (continued)
REF.
PN
DESCRIPTION
MANUFACTURER
SIZE
R9
Standard
Resistor, 82 kΩ, 5%
805
R10
Standard
Resistor, 1 kΩ, 5%
805
R11
Standard
Resistor, 0 Ω, 5%
805
R12
Standard
Resistor, 1 kΩ, 5%
805
R13
Standard
Reistor, 1 kΩ, 5%
805
R14
Standard
Resistor, 310 kΩ, 1%
805
R15
R16†
Standard
Resistor, 1 kΩ, 1%
805
Standard
Open resistor, 5.1 Ω, 5%
805
R17
Standard
Resister, 15 Ω, 5%
805
R18
Standard
Resistor, 7.5 kΩ, 5%
805
R19
Standard
Resistor, 7.5 kΩ, 5%
805
R20
Standard
Resistor, 15 Ω, 5%
805
R21
Standard
Open
Q1
Si4410DY
Transistor, MOSFET, n-ch, 30 V, 10 A, 13 mΩ,
Siliconix
SO-8
Q2
Si4410DY
Transistor, MOSFET, n-ch, 30 V, 10 A, 13 mΩ,
Siliconix
SO-8
Q3
Si4410DY
Transistor, MOSFET, n-ch, 30 V, 10 A, 13 mΩ,
Siliconix
SO-8
Q4
Si4410DY
Transistor, MOSFET, n-ch, 30 V, 10 A, 13 mΩ,
Siliconix
SO-8
TPS5102
IC, Dual Controller
TI
TSSOP
U1
† Option table
805
This EVM is designed to cover as many applications as possible. For some more specific applications, the circuit
can be simpler. The table below gives some recommendations.
Table 2. EVM Application Recommendations
5V INPUT VOLTAGE
Change C1 to low profile capacitor
Sanyo 10TPB220M (220 µF, 10 V)
Or 6TPB330M (330 µF, 6.3 V)
Remove R12
<3–A OUTPUT CURRENT
Change Q1/Q2 and Q3/Q4 to dual pack MOSFET, IRF7311 to reduce the cost.
DIODE VERSION
Remove Q2 and Q4 to reduce the cost.
Table 3. Vendor and Source Information
MATERIAL
MOSFETS ((Q1–Q4))
INPUT CAPACITORS (C1)
MAIN DIODES (D1 – D2)
INDUCTORS (L1 – L2)
CERAMIC CAPACITORS
(C2, C3) (C12, C17, C21)
SOURCE
In EVM Design
Second Source
In EVM Design
PART NUMBER
Si4410DY (SILICONIX)
IRF7811 (International Rectifier)
RV–35V221MH10–R (ELNA)
Second Source
35CV330AX/GX (Sanyo)
UUR1V221MNR1GS (Nichicon)
MBRS340T3 (Motorola)
U3FWJ44N (Toshiba)
DO3316P–682 (Coilcraft)
CTDO3316P–682 (Inductor Warehouse)
In EVM Design
Second Source
In EVM Design
Second Source
IN EVM Design
GMK325F106ZH
GMK316F225ZG
(Taiyo Yuden)
Taiyo Yuden, Representative
26
POST OFFICE BOX 655303
DISTRIBUTORS
Local Distributor
Bell Microproducts
972–783–4191
870–633–5030
Future Electronics (Local Office)
Local Distributors
Local Distributors
972–248-3575
800–533–8295
SMEC
512–331–1877
e–mail: [email protected]
• DALLAS, TEXAS 75265
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
APPLICATION INFORMATION
Top Layer
Bottom Layer (Top View)
Top Assembly
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
APPLICATION INFORMATION
+
Load
0–4A
Load
0–4A
–
Power Supply
5–V, 5–A Supply
– +
NOTE: All wire pairs should be twisted.
28
Test Setup
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
APPLICATION INFORMATION
High current applications are described in table . The values are recommendations based on actual test circuits.
Many variations are possible based on the requirements of the user. Performance of teh circuit is dependent
upon the layout rather than the on specific components, if the device parameters are not exceeded. The power
stage, having the highest current levels and greatest dv/dt rates, should be given the most attention, as both
the supply and load can be severly affected by the power levels and edge rates.
Table 4. High Current Applications
REFERENCE
DESIGNATIONS
FUNCTION
8-A OUTPUT
2x ELNA
RV-35V221MH10-R
220 µF, 35 V
2x Taiyo Yuden
GMK325F106ZH
10 µF, 35 V
12-A OUTPUT
C1
Input Bulk Capacitor
C2 (C3)
Input Bypass Capacitor
L1 (L2)
Output Filter Indicator
Coiltronics UP3B-2R2
2.2 µH, 9.2 A
C4 (C22)
Output Filter Capacitor
2x Sanyo 4TPB470M
470 µF, 4 V
3x Sanyo 4TPB470M
470 µF, 4 V
4x ELNA
RV-35V221MH10-R
220 µF, 35 V
4x Taiyo Yuden
GMK325F106ZH
10 µF, 35 V
MicorMetals T68-8/90
Core w/7T, #16
1.0 µH, 25 A
4x Sanyo 4TPB470M
470 µF, 4 V
C5 (C23)
Output Filter Capacitor
2x Sanyo 6TPB330M
330 µF, 6.3 V
3x Sanyo 6TPB330M
330 µF, 6.3 V
4x Sanyo 6TPB330M
330 µF, 6.3 V
Q1 (Q3)
Power Switch
2x Siliconix Si4410DY
30 V, 10 A, 13 mΩ
3x Siliconix Si4410DY
30 V, 10 A, 13 mΩ
4x Siliconix Si4410DY
30 V, 10 A, 13 mΩ
Q2 (Q4)
Power Switch
2x Siliconix Si4410DY
30 V, 10 A, 13 mΩ
3x Siliconix Si4410DY
30 V, 10 A, 13 mΩ
4x Siliconix Si4410DY
30 V, 10 A, 13 mΩ
R17 (R20)
R18 (R19)
Switching Frequency
Gate Drive Resistor
Current Limit Resistor
7Ω
10 kΩ
200 kHz
5Ω
15 kΩ
150 kHz
4Ω
20 kΩ
100 kHz
POST OFFICE BOX 655303
3x ELNA
RV-35V221MH10-R
220 µF, 35 V
3x Taiyo Yuden
GMK325F106ZH
10 µF, 35 V
Coiltronics UP4B-1R5
1.5 µH, 13.4 A
16-A OUTPUT
• DALLAS, TEXAS 75265
29
TPS5102
DUAL, HIGH-EFFICIENCY CONTROLLER FOR NOTEBOOK PC POWER
SLVS239 - SEPTEMBER 1999
DBT (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
30 PINS SHOWN
0,50
0,27
0,17
30
16
0,08 M
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
15
0°- 8°
0,75
0,50
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
28
30
38
44
50
A MAX
7,90
7,90
9,80
11,10
12,60
A MIN
7,70
7,70
9,60
10,90
12,40
DIM
4073252/D 09/97
NOTES: A.
B.
C.
D.
30
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
12-Feb-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS5102IDBT
ACTIVE
TSSOP
DBT
30
60
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS5102IDBTG4
ACTIVE
TSSOP
DBT
30
60
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS5102IDBTR
ACTIVE
TSSOP
DBT
30
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS5102IDBTRG4
ACTIVE
TSSOP
DBT
30
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Sep-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS5102IDBTR
Package Package Pins
Type Drawing
TSSOP
DBT
30
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
6.95
8.3
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Sep-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS5102IDBTR
TSSOP
DBT
30
2000
346.0
346.0
33.0
Pack Materials-Page 2
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