SC2441
Very Low Input Voltage 2-Phase Synchronous
Step-down Controllers with Step-up Converter
POWER MANAGEMENT
Description
Features
2-Phase Synchronous step-down controllers
2-Phase Synchronous Continuous Conduction Mode
For High Efficiency Step-down Converters
Out of Phase Operation For Low Input Current Ripples
Operates Up To 1MHz Per Channel
Configurable Dual Outputs Or 2-Phase Single Output
Operation with Peak Current Mode Control
Excellent Current Sharing Between Phases
Wide Input Voltage Range: 1.8V to 15V
Duty Cycle Up to 90%
0.5V Feedback Voltages For Low-Voltage Outputs
Precision 50mV Current-Limit Threshold
Patented Combi-sense Technique for High SNR of Current-Sensing
Individual Soft-Start, Overload Shutdown and Enable
Step-up Regulator
Wide Input Voltage Range: 1.8V to 15V
Operates At Twice The Individual Channel Frequency
Of The Buck Controllers
0.23V VCESAT Switch at 1A
Fixed Frequency with Current-Mode Control
Common Features
External Synchronization
Industrial Temperature Range
The SC2441 is a high-frequency triple output switching
regulator controller. It consists of a dual out-of-phase
synchronous step-down PWM controller with high-current
output gate drives and a 1.7A integrated step-up switching regulator.
The dual-phase step-down controller of the SC2441 can
be configured to provide two individually controlled and
regulated outputs or a single output with shared current
in each phase. The buck controller can operate from an
input voltage of at least 4.72V or they can run off a supply
generated locally with the integrated boost regulator. This
makes the SC2441 ideally suited for applications where a
low-voltage input (3.3V, 2.5V, or 1.8V) is to be stepped
down for lower voltage logic yet the input is too low to
drive power MOSFET’s efficiently. The boost regulator can
be used to provide a third auxiliary output while generating the bias for the buck controllers.
Both the step-down controllers and the step-up regulator
employ fixed frequency peak current-mode control for fast
transient response. The master oscillator frequency can
be programmed by the user.
Individual soft-start and overload shutdown timer are employed in each step-down controller for hiccup overload
protection. In single-output configuration, the channel 1
timer controls the soft-start and overload shutdown functions of both controllers.
Applications
Low Voltage Distributed DC-DC Converters
Telecommunication Power Supplies
Servers and base stations
Typical Application Circuit
VIN
VINGND
+
R12
C38
D1
D2
R14
VIN
C36
C18
R28
7
8
+ C1
VIN
C2
28
18
VO1
Q1
L1
C8
VO1GND
R3
C25
C20
+
R5
C19
D7
COMP3
PH3
PVIN
BST2
BST1
GDH2
GDH1
20
GDL2
GDL1
PGND
2
RCS+1
16
15
RCS-1
14
C27
R18
1
C3
27
25
23
R4
13
VPN2
VPN1
CS2+
CS1+
CS2-
CS1-
FB2
FB1
COMP2
COMP1
22
3
17
SY NC
Rosc
SS1/EN1
VCC
C17
VO2
C23
D10
Q7
C24
R6
24
+
C15
VO2GND
C21
R11
R13
26
RCS+2
4
5
RCS-2
11
C28
12
C31
GND
6
C4
L2
R8
C30
R17
+
Q2
SC2441
R7
Q6
R10
R9
19
IN
VIN
D3
L3
FB3
R19
R16
9
10
21
R20
SS2/EN2
C32
Figure 1
Revision: January 10, 2005
C33
U1
1
US patent 6,441,597
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SC2441
POWER MANAGEMENT
Absolute Maximum Rating
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
Parameter
Symbol
Maximum Ratings
Units
Input Voltages
VIN , VPVIN
-0.3 to 20
V
VCC
-0.3 to 20
V
VBST1, VBST2
-0.3 to 20
V
Supply Voltage For Step-Dow n Controller
High-Side Driver Supply Voltages
VFB1, VFB2
-0.3 to 20
V
VCOMP1, VCOMP2
-0.3 to 4.5
V
VCS1(+), VCS1(-), VCS2(+), VCS2(-)
-0.3 to 20
V
VS/S
-0.3 to 20
V
FB1, FB2 Voltage
COMP1, COMP2 Voltages
CS1(+), CS1(-), CS2(+) and CS2(-)
Voltages
SY NC/SHDN Voltage
ROSC Voltage
SS1/EN1 AND SS2/EN2 Voltages
Peak Gate Drive Current
Peak VPN1 and VPN2 Output Currents
FB3 Voltage
VROSC
-0.3 to 5
V
VSS1, VSS2
-0.3 to 6
V
IGDH1, IGDH2, IGDL1, IGDL2
3
A
IVPN1, IVPN2
100
mA
VFB3
4
V
VCOMP3
-0.3 to 2
V
VPH3
-0.3 to 35
V
Ambient Temperature
TA
-40 to 85
°C
Thermal Resistance Junction to Case
θJC
13
°C/W
Thermal Resistance Junction to Ambient
θJA
84
°C/W
Storage Temperature Range
TSTG
-60 to 150
°C
Lead Temperature (Soldering) 10 sec
TLEAD
260
°C
COMP3 Voltage
PH3 Voltage
Electrical Characteristics
Unless specified: VIN = 2V, VCC = VBST1 = VBST1 =8V, SYNC/SHDN =2V, ROSC = 51.1kΩ, -40°C < TA = TJ < 85°C
Parameter
Symbol
Conditions
VCC Start Threshold
VCCTH
VCC Increasing
VCC UVLO Threshold
VCCTL
VCC Decreasing
ICC
VCC = 8V, VS/S = 2V
VCC < VCCTL, VS/S = 2V
VCC = 8V, VS/S = 0V
VFB1, VFB2
VIN = 3V
VCCTL < VCC < 10V
-40°C < TA < 85°C
Min
Typ
Max
Units
4.65
4.72
V
Undervoltage Lockout
VCC Operating Current
4.34
4.45
V
14
0.15
10
21
0.25
13
mA
0.496
0.507
V
-400
nA
Channel 1 and 2 Error Amplifiers
Feedback Voltage
0.487
Feedback Pin Input Bias Current
IFB1, IFB2
-160
Amplifier Transconductance
GM1, GM2
400
µΩ −1
ao1, ao2
75
dB
5
MHz
Open Loop Voltage Gain
Amplifier Unity Gain Bandwidth
(Note 1)
Amplifier Output Sink Current
VFB1, 2 = 1V, VCOMP1,2 = 2.5V
20
32
40
µA
Amplifier Output Source Current
VFB1, 2 = 0V, VCOMP1,2 = 2.5V
10
17
30
µA
VCS1(+) = VCS1(-) = 0
VCS2(+) = VCS2(-) = 0
-40°C < TA < 85°C
1.3
1.7
2.2
V
COMP Threshold for PWM Operation
FB2 Voltage For 2-Phase Single Output
Operation
2005 Semtech Corp.
1.55
2
V
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SC2441
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: VIN = 2V, VCC = VBST1 = VBST1 =8V, SYNC/SHDN =2V, ROSC = 51.1kΩ, -40°C < TA = TJ < 85°C
Parameter
Symbol
Conditions
Min
Typ
Max
Units
fOSC1, fOSC2
ROSC = 51.1kΩ
470
510
550
KHz
Maximum Duty Cycle
DMAX1,
DMAX2
ROSC = 51.1kΩ
88
90
Minimum Duty Cycle
DMIN1, DMIN2
ROSC = 51.1kΩ
Oscillator
Step-dow n Channel Sw itching Frequency
ROSC = 51.1kΩ (Note 1)
SY NC/SHDN Synchronizing Frequency
SY NC/SHDN Input High Voltage
VS/SH
SY NC/SHDN Input Low Voltage
VS/SL
SY NC/SHDN Input Current
1.2
%
0
%
2
MHz
1.5
VS/S = 0.2V
VS/S = 2V
IS/S
Shutdow n Delay
V
50
(Note 1)
0.5
V
1
100
µA
µs
85
Current-Sense Amplifiers and Current-Limit Comparators
Current Limit Threshold
VILIM1,
VILIM2
VCC = 8V
VCS1(-) = VCS2(-) = 0V
40
48
56
mV
Current Limit Threshold
VILIM1,
VILIM2
VCC = 8V
VCS1(-) = VCS2(-) = 5V
40
46.5
56
mV
Positive Current-Sense Input Bias Current
ICS1(+),
ICS2(+)
VCS1(+) = VCS1(-) = 0
VCS2(-) = VCS2(-) = 0
-0.37
-1
µA
Negative Current-Sense Input Bias Current
ICS1(-), ICS2(-)
VCS1(+) = VCS1(-) = 0
VCS2(+) = VCS2(-) = 0
-0.32
-1
µA
TA = 25°C, (Note 1)
180
ns
High-Side Gate Drive Peak Source Current
(Note 1)
2
A
High-Side Gate Drive Peak Sink Current
(Note 1)
2
A
Low -Side Gate Drive Peak Source Current
(Note 1)
2
A
Minimum PWM On-time
Gate Drivers
Low -Side Gate Drive Peak Sink Current
(Note 1)
2
A
Gate Drive Rise Time
CL = 3300pF
30
ns
Gate Drive Fall Time
CL = 3300pF
30
ns
Low -side Gate Drive to High-side Gate
Drive Non-overlapping Delay
CL = 0
74
ns
High-side Gate Drive to Low -side Gate
Drive Non-overlapping Delay
CL = 0
62
ns
Soft-Start, Overload Shutoff and Enable
Soft-Start Charging Current
ISS1, ISS2
VSS1 = VSS2 = 1.5V
2.3
µA
Soft-Start Voltage to Enable Overload
Shutoff
VSSEN1,
VSSEN2
VSS1 and VSS2 Increasing
3.25
V
Overload Shutoff FB Threshold
VFBOL1,
VFBOL2
VSS1, 2 = 3.8V
FB1 and FB2 Decreasing
Soft-Start Discharge Current
ISS1(DIS),
ISS2(DIS)
VFB1 = VFB2 = 0.3V
VSS1 = VSS2 = 3.8V
Soft-Start Voltage to Recover From
Overload Shutoff
VSSRCV1,
VSSRCV2
VSS1 and VSS2 Decreasing
2005 Semtech Corp.
3
0.348
0.36
0.372
µA
1.4
0.29
0.47
V
0.63
V
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SC2441
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: VIN = 2V, VCC = VBST1 = VBST1 =8V, SYNC/SHDN =2V, ROSC = 51.1kΩ, -40°C < TA = TJ < 85°C
Parameter
Symbol
Conditions
Min
Typ
Gate Drive Disable SS/EN Voltage
Gate Drive Enable SS/EN Voltage
Max
Units
0.5
V
1.2
V
PVIN 0.05
V
Virtual Phase Nodes
Output High Voltage
VVPN1,2H
IVPN1=0, IVPN2=0
Output Low Voltage
VVPN1,2L
IVPN1=0, IVPN2=0
Output High Voltage
VVPN1,2H
IVPN1= IVPN2= -12mA
Output Low Voltage
VVPN1,2L
IVPN1= IVPN2= 12mA
VIN Start Threshold
VINTH
VIN Increasing
VIN UVLO Threshold
VINTL
VIN Decreasing
Feedback Pin Bias Current
IFB3
Feedback Voltage
V FB 3
Feedback Amplifier Transconductance
GM3
180
µΩ-1
Feedback Amplifier Open-Loop Gain
a o3
50
dB
Boost Converter Switching Frequency
fOSC3
Maximum Switch Duty Cycle
DMAX3
Boost Converter Switch Saturation Voltage
VCESAT
ISW = 1A, TA = 25°C
Boost Switch Leakage Current
ILEAKAGE
V S W = 12V
20
PVIN 0.22
mV
V
200
mV
1.8
V
Boost Converter
Boost Switch Current Limit
1.55V < VIN < 16.5V
-40°C < TA < 85°C
ROSC = 51.1kΩ
1.74
1.45
1.225
250
nA
1.250
1.275
V
1.1
2
MHz
%
86
0.23
1.7
V
40
0.94
82
ILIMIT
1.59
0.35
V
5
µA
A
Note 1: Guaranteed by design not tested in production.
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SC2441
POWER MANAGEMENT
Pin Configurations
Ordering Information
D evice
(TOP VIEW)
SC 2441ITSTRT(1)(2)
S C 2441E V B
IN
VPN2
SS1/EN1
CS1+
CS1SYNC/SHDN
FB3
COMP3
GND
ROSC
FB1
COMP1
COMP2
FB2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P ackag e
Temp. R ange( TA)
TSSOP-28
-40 - 85°C
Evaluati on Board
PVIN
PH3
VPN1
BST1
PGND
GDH1
GDL1
VCC
GDL2
Notes:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices for the TSSOP-28 package.
(2) Lead free product.
GDH2
BST2
SS2/EN2
CS2+
CS2-
(28-Pin TSSOP)
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SC2441
POWER MANAGEMENT
Pin Descriptions
Pin
Pin N ame
Pin Function
1
IN
2
VPN2
3
SS1/EN1
4
C S 1+
The Non-i nverti ng Input of the C urrent-sense Ampli fi er/C omparator for the Step-down
C ontroller 1.
5
C S 1-
The Inverti ng Input of the C urrent-sense Ampli fi er/C omparator for the Step-down C ontroller 1.
Normally ti ed to the output of the converter.
Power Supply Voltage for the Analog Secti on of the Boost C onverter.
The Vi rtual Phase (Unloaded) Node of the Second Step-down C onverter. Used for "C ombi "
current sense only. Thi s pi n i s left open when sensi ng current wi th a sense resi stor at the
converter output.
An external capaci tor ti ed to thi s pi n sets (i ) the soft-start ti me (i i ) output overload latch off ti me
for step-down converter 1. Pulli ng thi s pi n below 0.5V shuts off the gate dri vers for the fi rst
controller.
Synchroni zati on and Shutdown Input. For normal operati on, ti e thi s pi n to a voltage above
1.5V. To shut-off both step-down controllers and the boost regulator, force thi s pi n to a voltage
less than 0.5V. The master osci llator can be synchroni zed by dri vi ng thi s pi n wi th an external
clock (external fCLK > frequency set wi th ROSC ). The boost converter runs at the external clock
frequency whereas the step-down controllers operate at half the clock frequency.
6
SYNC /SHD N
7
FB 3
The Inverti ng Input of the Error Ampli fi er for the Boost C onverter. FB3 i s ti ed to an external
resi sti ve di vi der for output3 voltage setti ng.
8
C OMP3
The Error Ampli fi er Output of the Boost C onverter. Thi s pi n i s used for loop compensati on.
Pulli ng thi s pi n below 0.4V di sables the step-up converter.
9
GND
10
ROSC
11
FB 1
12
C OMP1
13
C OMP2
14
FB 2
The Inverti ng Input of the Error Ampli fi er for the Step-down C ontroller 2. Ti e to an external
resi sti ve di vi der between output2 and the ground for output voltage sensi ng. Ti e to IN or VC C
for two-phase si ngle output appli cati ons
15
C S 2-
The Inverti ng Input of the C urrent-sense Ampli fi er/C omparator for the Step-down C ontroller 2.
Normally ti ed to the output of the converter.
16
C S 2+
The Non-i nverti ng Input of the C urrent-sense Ampli fi er/C omparator for the Step-down
C ontroller 2
17
SS2/EN2
An external capaci tor ti ed to thi s pi n sets (i ) the soft-start ti me (i i ) output overload latch off ti me
for step-down converter 2. Pulli ng thi s pi n below 0.5V shuts off the gate dri vers for the second
controller. Leave open for two-phase si ngle output appli cati ons.
18
BST2
Bootstrapped Supply for the Hi gh-si de Gate D ri ve 2. C onnect to a bootstrap capaci tor and an
external di ode as descri bed i n appli cati on i nformati on.
19
GD H2
Gate D ri ve Output for the Hi gh-si de N-channel MOSFET of Output 2. Gate dri ve voltage
swi ngs from ground to VBST2.
20
GD L2
Gate D ri ve Output for the Low-si de N-channel MOSFET of Output 2. Gate dri ve voltage
swi ngs from ground to VC C .
2005 Semtech Corp.
Analog Si gnal Ground.
An external resi stor connected from thi s pi n to GND sets the osci llator frequency.
The Inverti ng Input of the Error Ampli fi er for the Step-down C ontroller 1. Ti e to an external
resi sti ve di vi der between OUTPUT1 and the ground for output voltage sensi ng.
The Error Ampli fi er Output for Step-down C ontroller 1. Thi s pi n i s used for loop compensati on.
The Error Ampli fi er Output for Step-down C ontroller 2. Thi s pi n i s used for loop compensati on.
6
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SC2441
POWER MANAGEMENT
Pin Descriptions
21
VCC
Supply Voltage for Both Step-dow n Controllers and the Low -side Gate Drivers. The boost
converter output is tied to VCC if VIN in not high enough to fully enhance the pow er MOSFET's
and the boost converter provides an auxiliary supply voltage for the step-dow n controllers. Tie
VCC to VIN if the boost converter is not needed.
22
GDL1
Gate Drive Output for the Low -side N-channel MOSFET of Output 1. Gate drive voltage
sw ings from ground to VCC.
23
GDH1
Gate Drive Output for the High-side N-channel MOSFET of Output 1. Gate drive voltage
sw ings from ground to VBST1.
24
PGND
Ground Supply of the High-side and the Low -side Gate Drivers of Both Step-dow n Controllers.
It is also the emitter of the boost sw itch.
25
BST1
Bootstrapped Supply for the High-side Gate Drive 1. Connect to a bootstrap capacitor and an
external diode as described in application information.
26
VPN1
The Virtual Phase (Unloaded) Node of the First Step-dow n Converter. Used for "Combi"
current sense only. This pin is left open w hen sensing current w ith a sense resistor at the
converter output.
27
PH3
Boost Sw itch Collector. Connect to a boost inductor and a rectifying diode.
28
PVIN
Pow er Supply Voltage for the Boost Sw itch and the Virtual Phase Node Drivers.
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SC2441
POWER MANAGEMENT
Block Diagram
1.25V
IN
VIN UVLO
1.60/1.74V
REFERENCE
1
PVIN
CLK
SYNC/SHDN
28
CLK2
6
OSCILLATOR
ROSC
0.5V
FREQUENCY
CLK1
DIVIDER
10
0.36V
VCC
21
UVLO
4.45/4.65V
SLOPE COMP
COMP1
BST1
SHDN
12
25
SHDN
FB1
GDH1
SLOPE2
-
11
EA1
+
0.5V
23
-
R
+
S
PWM1
Q
SLOPE1
CS1+
4
CS15
+
+
ISEN1
Σ
-
GDL1
22
Soft-Start
And
Overload
Hiccup
Control 1
ILIM1
I
1.25V
-
OL
PGND
DSBL
24
SS1/EN1
3
-
B
+
ANALOG SWITCH
SEL
COMP2
26
FAULT
+
+
50mV
VPN1
Non-Overlapping
Conduction
Control
A
Y
CLK2
BST2
SEL
18
13
GDH2
FB2
-
14
19
EA2
+
0.5V
-
R
+
S
PWM2
PVIN
Q
Non-Overlapping
Conduction
VCC
Control
SLOPE2
CS2+
16
CS215
+
+
ISEN2
-
+
ILIM2
I
GND
50mV
9
-
Σ
FAULT
+
VPN2
2
GDL2
20
Soft-Start
And
Overload
Hiccup
Control 2
OL
DSBL
SS2/EN2
17
Step-down Controllers Functional Diagram
Figure 2
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SC2441
POWER MANAGEMENT
Block Diagram
PH3
COMP3
8
27
CLK
FB3
7
+
1.25V
EA3
-
R
+
S
PWM3
Q
+
ILIM3
-
14mV
SLOPE
COMP
+
Σ
7mΩ
+
+
ISEN3
-
24
Step-up Converter Functional Diagram
PGND
Figure 3
+
FB
0.36V
SS/EN
-
S
Q
2µΑ
OL
R
0.47V/3.25V
DSBL
FAULT
0.6V/0.9V
3µΑ
Details of the Soft-start and
Overload Hiccup Control Circuit
Figure 4
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SC2441
POWER MANAGEMENT
Typical Performance Characteristics
FB1 AND FB2 VOLTAGES vs TEMPERATURE
0.5
V CC = 5V
1.9
0.496
0.494
0.492
VOLTAGES (V)
1.28
VOLTAGE (V)
VOLTAGE (V)
2
1.3
V IN = 2V
0.498
1.26
1.24
1.2
-50
-25
0
25
50
75
100
VIN START
1.7
VIN UVLO
1.5
-50
-25
TEMPERATURE (ºC)
0
25
50
75
100
-50
-25
TEMPERATURE (ºC)
5
25
50
75
100
STEP-UP CONVERTER SWITCHING
FREQUENCY vs TEMPERATURE
1050
520
1040
ROSC = 51.1KΩ
515
0
TEMPERATURE (ºC)
STEP-DOWN CHANNEL SWITCHING
FREQUENCY vs TEMPERATURE
VCC START AND UVLO THRESHOLD
VOLTAGES vs TEMPERATURE
ROSC = 51.1KΩ
1030
FREQUENCY (KHz)
VCC START
4.6
VCC UVLO
4.4
4.2
510
FREQUENCY (KHz)
4.8
505
500
495
490
4
-25
0
25
50
75
1000
990
980
950
-50
100
1010
960
480
-50
1020
970
485
-25
0
25
50
75
-50
100
-25
TEMPERATURE (ºC)
TEMPERATURE (ºC)
STEP-UP SWITCH MAXIMUM DUTY- CYCLE
vs TEMPERATURE
MAXIMUM DUTY- CYCLE OF STEP-DOWN
CHANNEL vs TEMPERATURE
0
25
50
TEMPERATURE (ºC)
CS(-) = 0
88
89
48
VOLTAGES (mV)
DUTY CYCLE (%)
91
100
50
ROSC = 51.1KΩ
ROSC = 51.1KΩ
93
75
STEP-DOWN CONTROLLER CURRENT-LIMIT
THRESHOLD vs TEMPERATURE
90
95
DUTY CYCLE (%)
1.8
1.6
1.22
0.49
VOLTAGES (V)
VIN START AND UVLO THRESHOLD
VOLTAGES vs TEMPERATURE
FB3 VOLTAGE vs TEMPERATURE
86
84
CS(-) = 5V
46
44
87
82
42
85
80
40
VCC = 8V
-50
-25
0
25
50
TEMPERATURE (ºC)
2005 Semtech Corp.
75
100
-50
-25
0
25
50
TEMPERATURE (ºC)
10
75
100
-50
-25
0
25
50
75
100
TEMPERATURE (ºC)
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SC2441
POWER MANAGEMENT
Operation
Overview
The SC2441 is a constant frequency triple-output
switching regulator especially designed for operating from
input voltages as low as 1.8V. It consists of two currentmode step-down switch-mode PWM controllers driving
all N-channel MOSFET’s and a 1.7A step-up current-mode
controller with integrated 1.7A power switch. A low
voltage input (3.3V, 2.5V or 1.8V) can be stepped up to
5V-10V locally using the boost regulator to provide
sufficient gate drives for the step-down converters. The
boost converter can also be used to generate a third
output.
The two step-down channels of the SC2441 operate at
180 degrees out of phase from each other. Since input
currents are interleaved in a two-phase converter, input
ripple current is lower and smaller input capacitor can be
used for filtering.
The step-down controllers of the SC2441 operate in
synchronous continuous-conduction mode. They can be
configured either as two independent step-down
controllers producing two separate outputs or as a dualphase single-output controller by tying the FB2 pin to VCC.
In single output operation, the channel-one error amplifier
controls both channels and the channel-two error
amplifier is disabled. Soft-start and overload hiccup of
both channels is also synchronized to channel one.
Frequency Setting and Synchronization
The step-up regulator in the SC2441 runs at twice the
frequency of step-down controllers. Each step-down
controller runs at one-half of the oscillator frequency and
is 180 degrees out of phase from the other step-down
controller. The switching frequency of the step-up
regulator is the oscillator frequency and can be set with
an external resistor from the ROSC pin to the ground. The
boost regulator and the step-down controllers are capable
of operating up to 2 MHz and 1 MHz respectively. It is
necessary to consider the operating duty-ratio range
before deciding the switching frequency. See Applications
Information section for more details.
When synchronized externally, the applied clock frequency
(hence switching frequency of the step-up converter)
should be twice the individual phase frequency of the
step-down controllers. The synchronizing clock frequency
2005 Semtech Corp.
should also be between 1-1.33 times the set free-running
frequency.
If not synchronized, the SYNC/SHDN pin should be tied
to the input. Pulling the SYNC/SHDN pin below 0.5V shuts
off the SC2441 after 85µs time delay.
Control Loop
The step-down controllers and the boost regulator in the
SC2441 use peak current-mode control for fast transient
response, ease of compensation and current sharing in
single output operation. The low-side MOSFET of each
step-down channel is turned off at the falling-edge of
the phase clock. After a brief non-overlapping conduction
interval of 74ns, the high-side MOSFET is turned on. The
phase inductor current ramps up. When the sensed
inductor current reaches the threshold determined by
the error amplifier output and ramp compensation, the
high-side MOSFET is turned off. After a non-overlapping
delay of 62ns, the low-side MOSFET is turned on.
The supply voltages for the high-side gate drivers are
obtained from two diode-capacitor bootstrap circuits. If
the bootstrap capacitor is charged from VCC, then the
high-side gate drive voltage will swing from approximately
2VCC to the ground. The outputs of the low-side gate
drivers swing from VCC to the ground.
All three converters in the SC2441 have internal rampcompensation to prevent sub-harmonic oscillation when
operating above 50% duty cycle. The internal
compensating ramp is designed for an inductor ripplecurrent of between ¼ to 1/3 of the maximum inductor
current and the peak-to-peak current-sense voltage (CSPCSN of the step-down controllers) of between ¼ to 1/3
of the current-limit threshold (50mV). The current-limits
of all three converters are unaffected by the
compensation ramps.
Current-Sensing
Since the inductor current ramp is used as the modulating
ramp in current-mode control, the inductor current needs
to be sensed. There are two current sensing methods for
the step-down controllers. Since the maximum currentsense voltage (CSP-CSN) is only 50mV, a precision sense
resistor in series with the inductor can be used at the
output without resulting in excessive power dissipation.
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SC2441
POWER MANAGEMENT
Operation (Cont.)
Although accurate and far easier to lay out than highside resistor sensing, a pair of precision sense resistors
adds cost to the converter. The SC2441 has provision to
reconstruct a differential voltage proportional to the
inductor current at the output of the converter. The
voltage to current ratio or the equivalent sense resistance
Req is a combination of high-side and low-side MOSFET
RDS(ON) ’s and the inductor series resistance (hence the
name “combi-sense”). The SC2441 provides the virtual
phase voltages VPN1 and VPN2 (these are unloaded
versions of their respective phase voltages) for current
sensing. This method does not require precision sense
resistor. It is cheaper to implement but is less accurate
than resistor current sensing. Since the sensed voltage
is developed at the output of the step-down converter, it
is less prone to switching transient spikes. This method
will be described in more details in the Applications
Information section.
Boost switch current is sensed with an integrated sense
resistor with a current-limit of 1.7A.
Error Amplifiers
All error amplifiers in the SC2441 are transconductance
amplifiers. Converters are compensated with series RC
network from the COMP pins to the ground. An additional
small parallel capacitor may be required for stability.
In closed loop operation, the step-down error amplifiers
output range from 1.7V to 3.5V. There is no control (highside) gate drive until the COMP voltage exceeds 1.6V.
Both non-inverting inputs of the feedback amplifiers are
tied to an internal 0.5V voltage reference.
The error amplifier of the step-up converter has 1.25V
as its reference voltage. Its output voltage ranges from
0.8V to 1.35V in closed-loop operation.
Current-Limit
The maximum current sense voltage of +50mV is the
cycle-by-cycle peak current limit when the load is drawing
current from the converter.
Soft-Start and Overload Protection
The undervoltage lockout circuit discharges the SS/EN
capacitors. After VCC rises above 4.65V, the SS/EN
capacitors are slowly charged by internal 2.3µA current
sources. With internal PNP transistors, the SS/EN voltages
clamp the error amplifier outputs. When the error amplifier
output rises to 1.7V, the high-side MOSFET starts to switch.
As the SS/EN capacitor continues to charge, the COMP
voltage follows. The converter gradually delivers increasing
power to the output. The inductor current follows the COMP
voltage envelope until the output goes into regulation. The
SS/EN clamp on COMP is released.
After the SS/EN capacitor is charged above 3.25V (high
enough for the error amplifier to provide full load current),
the overload detection circuit is activated. If the output
voltage falls below 70% of its set value, an overload latch
will be set and both the top and the bottom MOSFET’s
will be turned off. The SS/EN capacitor is slowly
discharged with an internal 1.4µA current sink. The
overload latch is reset when the SS/EN capacitor is
discharged below 0.47V. The SS/EN capacitor is then
recharged with the 2.3µA current source and the converter
undergoes soft-start. If overload persists, the step-down
converters will undergo repetitive shutdown and restart
(hiccup). Soft-start process should be slow enough to allow
the output to reach 70% of its final value before the SS/
EN capacitor is charged above 3.25V (see Figure 4).
If the output is short-circuited, the inductor current will
not increase indefinitely between the time the inductor
current reaching its current limit and shutdown. This is
due to cycle skipping reduces the actual operating
frequency.
The SS/EN pin can also be used as the enable input for
that channel. Both the high-side and the low-side
MOSFET’s will be turned off if the SS/EN pin is pulled
below 0.5V.
2005 Semtech Corp.
12
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SC2441
POWER MANAGEMENT
Applications Information
The SC2441 consists of two current-mode synchronous
buck controllers and an auxiliary boost converter. The
SC2441 can be used to generate
1) two independent step-down outputs or
2) dual phase single output with current sharing and
3) a step-up output
The application information using SC2441 for the control
of step-down and step-up converters are described below.
Step-down Converter
Specifications of a step-down converter are given by the
followings
Input voltage range: Vin ∈ [ Vin,min , Vin,max ]
Input voltage ripple (peak-to-peak): ∆Vin
Output voltage: Vo
Output voltage accuracy: ε
Output voltage ripple (peak-to-peak): ∆Vo
Nominal output (load) current: Io
Maximum output current limit: Io,max
Output (load) current transient slew rate: dIo (A/s)
Circuit efficiency: η.
Based on these converter specifications, selection criteria
and design procedures for the following components are
described.
1) output inductor (L) type and value,
2) output capacitor (Co) type and value,
3) input capacitor (Cin) type and value,
4) power switch MOSFET’s,
5) current sensing and limiting circuitry,
6) voltage sensing circuitry,
7) loop compensation circuitry.
To illustrate the design process, the following example is
used:
Vin=3.3V, Vo=1.2V, Io=4A, fs=500kHz.
Operating Frequency (fs)
The switching frequency in the SC2441 is userprogrammable. The advantages of constant frequency
operation are simple passive component selection and fast
transient response with simple frequency compensation.
Before setting the operating frequency, the following tradeoffs should be considered.
2005 Semtech Corp.
1) passive component sizes
2) converter efficiency
3) EMI
4) Minimum switch on time and
5) Maximum duty ratio
For a given output power, the sizes of the passive
components are inversely proportional to the switching
frequency, whereas MOSFET’s/Diodes switching losses are
proportional to the operating frequency. Other issues such
as heat dissipation, packaging and the cost issues are
also to be considered. The frequency bands for signal
transmission should be avoided because of EM
interference.
Minimum Switch On Time Limitation
In both step-down controllers, the falling edge of the
clock turns on the top MOSFET. The inductor current
ramps up so does the sensed voltage. After the sensed
voltage crosses a threshold determined by the error
amplifier output, the top MOSFET is turned off. The
propagation delay time from the turn-on of the controlling
FET to its turn-off is the minimum switch on time. The
SC2441 has a minimum on time of about 180ns at room
temperature. This is the shortest on interval of the
controlling FET. The controller either does not turn on the
top MOSFET at all or turns it on for at least 180ns.
For a synchronous step-down converter, the operating
duty cycle is V /V . So the required on time for the top
o IN
MOSFET is V /(V fS). If the frequency is set such that
o
IN
the required pulse width is less than 180ns, then the
converter will start skipping cycles. Due to minimum on
time limitation, simultaneously operating at very high
switching frequency and very short duty cycle is not
practical. If the input voltage is 3.3V and the operating
frequency is 1MHz, the lowest output voltage will be 0.6V.
There will not be enough modulation headroom if the on
time is simply made equal to the minimum on time of the
SC2441. For ease of control, we recommend the required
pulse width to be at least 1.5 times the minimum on time.
Maximum Duty-cycle Consideration
When operating at 500KHz, the maximum top MOSFET
on duty-cycle is 90%. The top MOSFET therefore turns off
for at least 200ns every cycle regardless of the switching
frequency. This places an upper bound on the voltage
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SC2441
POWER MANAGEMENT
Applications Information (Cont.)
conversion ratio at a given switching frequency. If the
desired output voltage requires high operating duty-cycle,
then operating frequency will have to be lowered to allow
modulating headroom.
L=
The peak current in the inductor becomes (1+δ/2)*Io
and the RMS current is
Setting the Step-down Channel Frequency
IL,rms = Io 1 +
The switching frequency of both step-down controllers is
set with an external resistor from Pin 10 to the ground.
The set frequency is inversely proportional to the resistor
value (Figure 5).
800
700
fs (kHz)
600
500
400
300
200
100
0
0
50
100
150
200
Vo (1 − D)
.
δIo fs
250
Rosc (k Ohm)
δ2
.
12
The followings are to be considered when choosing
inductors.
a) Inductor core material: For high efficiency applications
above 350KHz, ferrite, Kool-Mu and polypermalloy
materials should be used. Low-cost powdered iron cores
can be used for cost sensitive-applications below 350KHz
but with attendant higher core losses.
b) Select inductance value: Sometimes the calculated
inductance value is not available off-the-shelf. The designer
can choose the adjacent (larger) standard inductance
value. The inductance varies with temperature and DC
current. It is a good engineering practice to re-evaluate
the resultant current ripple at the rated DC output current.
c) Current rating: The saturation current of the inductor
should be at least 1.5 times of the peak inductor current
under all conditions.
Output Capacitor (Co) and Vout Ripple
Figure 5. Step-down Channel Free-running frequency vs.
ROSC.
Inductor (L) and Ripple Current
Both step-down controllers in the SC2441 operate in
synchronous continuous-conduction mode (CCM) regardless
of the output load. The output inductor selection/design
is based on the output DC and transient requirements.
Both output current and voltage ripples are reduced with
larger inductors but it takes longer to change the inductor
current during load transients. Conversely smaller inductors
results in lower DC copper losses but the AC core losses
(flux swing) and the winding AC resistance losses are
higher. A compromise is to choose the inductance such
that peak-to-peak inductor ripple-current is 20% to 30% of
the rated output load current.
Assuming that the inductor current ripple (peak-to-peak)
is δ*Io, the inductance will then be
2005 Semtech Corp.
The output capacitor provides output current filtering in
steady state and serves as a reservoir during load transient.
The output capacitor can be modeled as an ideal capacitor
in series with its parasitic ESR (Resr) and ESL (Lesl) (Figure
6).
Co
Lesl
Resr
Figure 6. Co equivalent circuit
If the current through the branch is ib(t), the voltage across
the terminals will then be
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SC2441
POWER MANAGEMENT
Applications Information (Cont.)
δIo
t
di ( t )
1
v o ( t ) = Vo +
ib ( t )dt + L esl b + R esr ib ( t ).
Co 0
dt
∫
This basic equation illustrates the effects of ESR, ESL and
Co on the output voltage.
The first term is the DC voltage across Co at time t=0. The
second term is the ripple-voltage caused by the inductor
ripple-current. The third term is the voltage ripple due to
ESL and the fourth term is the voltage ripple due to ESR.
The total output voltage ripple is then a vector sum of the
last three terms.
Since the inductor current is a triangular waveform with
peak-to-peak value δ*Io, the ripple-voltage caused by
inductor current ripples is
∆v C ≈
δIo
.
8Co fs
The ripple-voltage due to ESL is
∆v ESL = L esl fs
δIo
D
and the ESR ripple-voltage is
∆v ESR = R esr δIo .
Aluminum capacitors (e.g. electrolytic, solid OS-CON,
POSCAP, tantalum) have high capacitances and low ESL’s.
The ESR has the dominant effect on the output ripple
voltage. It is therefore very important to minimize the ESR.
When determining the ESR value, both the steady state
ripple-voltage and the dynamic load transient need to be
considered. To keep the steady state output ripple-voltage
< ∆Vo, the ESR should satisfy
R esr1 <
∆Vo
.
δIo
To limit the dynamic output voltage overshoot/undershoot
within α (say 3%) of the steady state output voltage) under
0 to full load current swing, the ESR value should be
R esr 2
αVo
<
.
Io
The required ESR value of the output capacitors should
be
Resr = min{Resr1,Resr2 }.
In the aluminum capacitor selection, the working voltage
rating is normally suggested to be greater than 1.5Vo.
The allowable current ripple (RMS) should be greater than
2005 Semtech Corp.
2 3
.
Usually it is necessary to have several capacitors of the
same type in parallel to satisfy the ESR requirement. The
voltage ripple cause by the capacitor charge/discharge
should be an order of magnitude smaller than the voltage
ripple caused by the ESR. To guarantee this, the
capacitance should satisfy
Co >
10
.
2πfsR esr
In many application circuits, several low ESR ceramic
capacitors are added in parallel with the aluminum
capacitors to further reduce ESR and improve high
frequency decoupling. Since the capacitances and the
ESR’s of ceramic and aluminum capacitors are different,
the following remarks are made to clarify some practical
issues.
Remark 1: High frequency ceramic capacitors may not carry
most of the ripple current. It also depends on the capacitor
value. Only when the capacitor value is set properly, the
effect of ceramic capacitor low ESR starts to be significant.
For example, if a 10µF, 4mΩ ceramic capacitor is
connected in parallel with 2x1500µF, 90mΩ electrolytic
capacitors, the ripple current in the ceramic capacitor is
only about 42% of the current in the electrolytic capacitors
at the ripple frequency. If a 100µF, 2mΩ ceramic capacitor
is used, the ripple current in the ceramic capacitor will be
about 4.2 times of that in the electrolytic capacitors. When
two 100µF, 2mΩ ceramic capacitors are used, the current
ratio increases to 8.3. In this case most of the ripple
current flows in the ceramic decoupling capacitor. The ESR
of the ceramic capacitors will then determine the output
ripple-voltage.
Remark 2: The total equivalent capacitance of the filter
bank is not simply the sum of all the paralleled capacitors.
The total equivalent ESR is not simply the parallel
combination of all the individual ESR’s either. Instead they
should be calculated using the following formulae.
2
C eq (ω) :=
15
2
(R1a + R1b )2 ω2C1a C1b + (C1a + C1b )2
2
2
(R1a C1a + R1b C1b )ω2 C1a C1b + (C1a + C1b )
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SC2441
POWER MANAGEMENT
Applications Information (Cont.)
2
R eq (ω) :=
2
2
2
R1aR1b (R1a + R1b )ω2C1a C1b + (R1b C1b + R1a C1a )
2
2
(R1a + R1b )2 ω2 C1a C1b + (C1a + C1b )2
In Figure 8 the DC input voltage source has an internal
impedance Rin and the input capacitor Cin has an ESR
denoted as Resr. MOSFET and input capacitor current
waveforms, ESR voltage ripple and input voltage ripple
are shown in Figure 9.
where R 1a and C 1a are the ESR and capacitance of
electrolytic capacitors, and R1b and C1b are the ESR and
capacitance of the ceramic capacitors respectively (Figure
7).
C1a
R1a
C1b
R1b
Ceq
Req
Figure 9. Typical waveforms at the input of a buck
converter.
Figure 7. Equivalent RC branch.
Req and Ceq are both functions of frequency. For rigorous
design, the equivalent ESR should be evaluated at the
ripple frequency for voltage ripple calculation when both
ceramic and electrolytic capacitors are used. If R1a = R1b =
R1 and C1a = C1b = C1, then Req and Ceq will be frequencyindependent and
Req = 1/2 R1 and Ceq = 2C1.
It can be seen that the current in the input capacitor pulses
with high di/dt. Capacitors with low ESL should be used. It
is also important to place the input capacitor close to the
MOSFET’s on the PC board to reduce trace inductances
around the pulse current loop.
The RMS value of the capacitor current is approximately
ICin = Io D[(1 +
Input Capacitor (Cin)
The input supply to the converter usually comes from a
pre-regulator. Since the input supply is not ideal, input
capacitors are needed to filter the current pulses at the
switching frequency. A simple buck converter is shown in
Figure 8.
Figure 8. Buck converter input model
2005 Semtech Corp.
δ2
D
D
)(1 − )2 + 2 (1 − D) ].
η
12
η
The power losses at the input capacitors is then
PCin = ICin2Resr.
For reliable operation, the maximum power dissipation in
the capacitors should not result in more than 10oC of
temperature rise. Many manufacturers specify the
maximum allowable ripple current (ARMS) rating of the
capacitor at a given ripple frequency and ambient
temperature. The input capacitance should be high enough
to handle the ripple current. For higher power applications,
multiple capacitors are placed in parallel to increase the
ripple current handling capability.
Sometimes meeting tight input voltage ripple specifications
may require the use of larger input capacitance. At full
load, the peak-to-peak input voltage ripple due to the ESR
is
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SC2441
POWER MANAGEMENT
Applications Information (Cont.)
δ
∆v ESR = R esr (1 + )Io .
2
If D1>0.5 and D2 > 0.5, then
The peak-to-peak input voltage ripple due to the capacitor
is
∆v C ≈
DIo
.
Cin fs
2
Power MOSFET Selection and Gate Drive
From these two expressions, CIN can be found to meet the
input voltage ripple specification. In a multi-phase
converter, channel interleaving can be used to reduce ripple.
The two step-down channels of the SC2441 operate at
180 degrees from each other. If both step-down channels
in the SC2441 are connected in parallel, both the input
and the output RMS currents will be reduced.
Main considerations in selecting the MOSFET’s are power
dissipation, cost and packaging. Switching losses and
conduction losses of the MOSFET’s are directly related to
the total gate charge (Cg) and channel on-resistance
(Rds(on)). In order to judge the performance of MOSFET’s,
the product of the total gate charge and on-resistance is
used as a figure of merit (FOM). Transistors with the same
FOM follow the same curve in Figure 10.
Ripple cancellation effect of interleaving allows the use of
smaller input capacitors. When converter outputs are
connected in parallel and interleaved, smaller inductors
and capacitors can be used for each channel. The total
output ripple-voltage remains unchanged. Smaller
inductors speeds up output load transient.
Gate Charge (nC)
50
When two channels with a common input are interleaved,
the total DC input current is simply the sum of the individual
DC input currents. The combined input current waveform
depends on duty ratio and the output current waveform.
Assuming that the output current ripple is small, the
following formula can be used to estimate the RMS value
of the ripple current in the input capacitor.
Let the duty ratios and output currents of Channel 1 and
Channel 2 be D1, D2 and Io1, Io2 respectively.
If D1<0.5 and D2<0.5, then
2
2
ICin ≈ D1Io1 + D 2Io2 .
If D1>0.5 and (D1-0.5) < D2<0.5, then
2
2
ICin ≈ 0.5Io1 + (D1 − 0.5)(Io1 + Io 2 )2 + (D 2 − D1 + 0.5)Io 2 .
If D1>0.5 and D2 < (D1-0.5) < 0.5, then
2
2
ICin ≈ 0.5Io1 + D 2 (Io1 + Io 2 )2 + (D1 − D 2 − 0.5)Io 2 .
2005 Semtech Corp.
2
ICin ≈ (D1 + D 2 − 1)(Io1 + Io 2 )2 + (1 − D 2 )Io1 + (1 − D1 )Io2 .
40
Cg( 100 , Rds)
Cg( 200 , Rds)
Cg( 500 , Rds)
20
1
0
0
5
15
20
1
Rds
On-resistance (mOhm)
10
20
FOM:100*10^{-12}
FOM:200*10^{-12}
FOM:500*10^{-12}
Figure 10. Figure of merit curves.
The closer the curve is to the origin, the lower is the FOM.
This means lower switching loss or lower conduction loss
or both. It may be difficult to find MOSFET’s with both low
Cg and low Rds(on. Usually a trade-off between Rds(on and Cg
has to be made.
MOSFET selection also depends on applications. In many
applications, either switching loss or conduction loss
dominates for a particular MOSFET. For synchronous buck
converters with high input to output voltage ratios, the top
MOSFET is hard switched but conducts with very low duty
cycle. The bottom switch conducts at high duty cycle but
switches at near zero voltage. For such applications,
MOSFET’s with low Cg are used for the top switch and
MOSFET’s with low Rds(on) are used for the bottom switch.
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SC2441
POWER MANAGEMENT
Applications Information (Cont.)
The losses in power MOSFET’s consist of
a) conduction loss due to the channel resistance Rds(on),
b) switching loss due to the switch rise time tr and fall time
tf and
c) the gate loss due to the gate resistance RG.
Top Switch:
The RMS value of the top switch current is
IQ1,rms = Io D(1 +
δ2
12
).
In Figure 11,
Qgs1 is the gate charge needed to bring the gate-to-source
voltage Vgs to the threshold Vgs_th,
Qgs2 is the additional gate charge required for the switch
current to reach its full-scale value Ids and
.
Qgd is the charge needed to charge gate-to-drain (Miller)
capacitance when Vds is falling.
Switching losses occur during the time interval [t1, t3].
Defining tr = t3-t1. tr can be approximated as
tr =
Its conduction loss is then
Ptc = IQ1,rms2 Rds(on).
Rds(on) varies with temperature and gate-source voltage.
Curves showing R ds(on) variations can be found in
manufacturers’ data sheet. From the Si7882DP datasheet,
Rds(on) is less than 4.5mΩ when Vgs is greater than 5V.
However Rds(on) increases by nearly 40% as the junction
temperature increases from 25°C to 125°C.
The switching losses can be estimated using the simple
formula
Vcc − Vgsp
.
where Rgt is the total resistance from the driver supply rail
to the gate of the MOSFET. It includes the gate driver internal
impedance R gi, external resistance Rge and the gate
resistance Rg within the MOSFET i.e.
Rgt = Rgi+Rge+Rg.
Vgsp is the Miller plateau voltage shown in Figure 11.
Similarly an approximate expression for tf is
tf =
Pts = 21 ( t r + t f )(1 + 2δ )Io Vin f s .
where tr is the rise time and tf is the fall time of the switching
process. Different manufactures have different definitions
and test conditions for t and t . To clarify these, we sketch
r
f
the typical MOSFET switching characteristics under clamped
inductive mode in Figure 11.
(Q gs 2 + Q gd )R gt
(Q gs 2 + Q gd )R gt
Vgsp
.
Only a portion of the total losses Pg = QgVccfs is dissipated in
the MOSFET package. Here Qg is the total gate charge
specified in the datasheet. The power dissipated within
the MOSFET package is
Ptg =
Rg
R gt
Q g Vcc fs .
The total power loss of the top switch is then
Pt = Ptc+Pts+Ptg.
If the input supply of the power converter varies over a
wide range, then it will be necessary to weigh the relative
importance of conduction and switching losses. This is
because conduction loss is inversely proportional to the
input voltage. Switching loss however increases with the
input voltage. The total power loss of MOSFET should be
calculated and compared for high-line and low-line
cases. The worst case is then used for thermal design.
charge
Figure 11. MOSFET switching characteristics
Bottom Switch:
The RMS current in bottom switch can be shown to be
IQ 2,rms = Io (1 − D)(1 +
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δ2
12
).
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SC2441
POWER MANAGEMENT
Applications Information (Cont.)
The conduction loss is then
Pbc=IQ2,rms2 Rds(on),
where Rds(on) is the channel resistance of bottom MOSFET.
If the input voltage to output voltage ratio is high (e.g.
Vin=12V, Vo=1.5V), the duty ratio D will be small. Since the
bottom switch conducts with duty ratio (1-D), the
corresponding conduction losses can be quite high.
Due to non-overlapping conduction between the top and
the bottom MOSFET’s, the internal body diode or the
external Schottky diode across the drain and source
terminals always conducts prior to the turn on of the bottom
MOSFET. The bottom MOSFET switches on with only a diode
voltage between its drain and source terminals. The
switching loss
Pbs = 21 ( t r + t f )(1 + 2δ )Io Vd fs
is negligible due to near zero-voltage switching.
The gate loss is estimated as
Pbg =
Rg
R gt
Q g Vcc fs .
The total bottom switch loss is then
Pb=Pbc+Pbs+Pbg.
Tj,max − Ta,max
Ploss
.
θja depends on the die to substrate bonding, packaging
material, the thermal contact surface, thermal compound
property, the available effective heat sink area and the air
flow condition (free or forced convection). Actual temperature
measurement of the prototype should be carried out to
verify the thermal design.
Integrated Power MOSFET Drivers
There are four internal MOSFET drivers in step-down
section of the SC2441 for driving all the MOSFET’s in a
dual-channel step-down converter.
2005 Semtech Corp.
To prevent shoot-through between the top and the bottom
MOSFET’s during commutation, one MOSFET should be
completely turned off before the other is turned on. In the
SC2441 the top and the bottom gate drive pulses are made
non-overlapping. When not driving any load, the nonoverlapping commutation intervals from the top to the
bottom and from the bottom to the top gate drives are set
at 62ns and 74ns respectively. If MOSFET’s are driven from
the SC2441, the non-overlapping commutation times will
decrease due to finite gate-source voltage rise and fall times.
The gate-source voltage waveforms of the MOSFET’s should
not overlap above their respective thresholds when driven
from the SC2441. Use of low gate charge MOSFET’s reduces
transition times and the tendency of shoot-through. The
combined rise and fall times during both commutations
should be less than the preset non-overlapping intervals
Current Sensing (Combi-Sense)
Once the power losses Ploss for the top (Pt) and bottom (Pb)
MOSFET’s are known, thermal and package design at
component and system level should be done to verify that
the maximum die junction temperature (Tj,max, usually
125oC) is not exceeded under the worst-case conditions.
The equivalent thermal impedance from junction to
ambient (θja) should satisfy
θ ja ≤
Using low gate charge MOSFET’s reduces switching loss.
It is possible to trade driver IC losses for MOSFET
switching losses by adjusting the gate resistance. Lower
gate resistance results in higher gate driving current and
faster MOSFET switching. However the driver incurs
higher losses. Conversely higher gate drive resistance
limits the gate drive current, thus lowering the driver
dissipation. MOSFET switching loss is higher.
Inductor current sensing is required for the current-mode
control. Although the inductor current can be sensed with
a precision resistor in series with the inductor, a novel
(US patent 6,441,597) lossless combi-sense technique
can also be used in the SC2441. This Semtech proprietary
technique has the following advantages
1) lossless current sensing
2) higher signal-to-noise ratio and
3) preventing thermal run-away.
The basic arrangement of the combi-sense is shown in
Figure 12.
In Figure 12 RL is the equivalent series resistance of the
output inductor. Rs and Cs form a RC network for inductor
current sensing. This branch is driven from a small totem
pole driver (Q3 and Q4) within the SC2441. The base
driving signals Vbe3 and Vbe4
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SC2441
POWER MANAGEMENT
Applications Information (Cont.)
Vin
Vin
Q1
Vgs1
i L (t )
L
RL
Rs
Cs
PN
C in
Q2
iL(t)
PN
Vo
C ou t
C
L
RL
Rs
Cs
i n
R l o ad
v C (t )
Vgs2
Rds2
Vo
VP N
C ou t
Rload
vC (t)
Vbe 3
Q3
Figure 13. b) Equivalent sub-circuit.
VP N
Q4
Vbe 4
Figure 12. The basic structure of combi-sense.
follow the gate drive signals Vgs1 and Vgs2 respectively
with minimal delay. The transition edges at the Virtual
Phase Node (VPN) therefore matches closely to those of
the Phase Node (PN).
When Q1/Q3 are on and Q2/Q4 are off, the circuit in Figure
12 is reduced to that of Figure 13 a). Here Rds1 is the onresistance of the top MOSFET. The branches {(Rds1+RL),
L} and {Rs, CS}, are in parallel. The DC voltage across L and
the DC current through CS are both zero. There is no DC
voltage across Rs either. Therefore on average, the voltage
drop (Rds1+RL)Io equals VCs. The DC inductor current can
be sensed from VCs if (Rds1+RL) is known.
When Q1/Q3 are off and Q2/Q4 are on, the equivalent
circuit of Figure 12 reduces to the sub-circuit in Figure
13b). Here Rds2 is the channel resistance of the bottom
MOSFET. In this case, the branch {Rs, Cs} is in parallel with
{(Rds2+RL), L} and VCs=(Rds2+RL)Io. Averaging over one
switching cycle,
VCs=[D(Rds1+RL)+(1-D)(Rds2+RL)]Io
or
VCs=[D Rds1+(1-D)Rds2+RL]Io:=ReqIo.
The DC voltage across VCs is independent of L, Rs and Cs. If
only the average load current is needed (as in average
current-mode control), this current sensing method will be
sufficient without any additional time-constant matching
constraint.
In peak current-mode control, the voltage ripple on Cs is
used as the modulating ramp. The VCs peak-to-peak
amplitude (denoted as ∆VCs) directly affects the signalto-noise ratio of the PWM operation. Small ∆VCs leads to
lower signal-to-noise ratio and more jittery operation.
Large ∆VCs leads to more circuit (power stage) sensitive
operation. A good compromise is to make
∆VCs~ReqδIo.
The above condition holds if the following time-constants
are made equal.
L
≈ R sC s .
R eq
Vin
Rds1
iL(t)
L
RL
Rs
Cs
PN
Cin
Vo
VPN
Cout
Rload
vC(t)
If Rds1=Rds2, then Req = Rds1+ RL. For example, in the
application circuit, L=1.3µH, RL=1.56mΩ and
Rds1=Rds2=8mΩ , the time constant RsCs should be set
as 136µs. If Cs=33nF, then Rs=4.12kΩ.
Figure 13. a) Equivalent sub-circuit.
2005 Semtech Corp.
20
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SC2441
POWER MANAGEMENT
Applications Information (Cont.)
Setting the Current Limit
Rs=11.8kΩ and Rs1=6.36kΩ.
When the voltage difference between CS1+(CS2+) and
CS1- (CS2-) exceeds 50 mV, the top MOSFET will be
turned OFF and the bottom MOSFET will be turned ON to
limit the output inductor current. In the circuit of Figure
12, the converter output current limit is
b) The required current limit ILM is less than ILMcp. Rs1 is
deleted from Figure 14. Rs is given by
ILMcp =
50mV
.
R eq
Q1
V gs1
iL(t)
L
RL
PN
Cin
Rs
Rs 1
Vo
Q2
Cs
C out
Rload
V gs2
vC(t)
Q3
VP N
Q4
Lastly Rs2 is computed from
R s2 =
R s 3R s
.
R s3 − R s
Remark 3: If the current limit ILM is lower than ILMcp, the
circuit designer will have the option to use MOSFET’s with
higher Rds(ON) to reduce the cost. As a result, Req is increased
and ILMcp is reduced. Although the use of low-cost MOSFET’s
is always preferred, the current-limit setting technique
described above allows quick adjustment on a well-tested
prototype without the need to replace the power MOSFET’s.
Over Current Protection and Hiccup Mode
+ 1
ISEN
Rs
VO = 50mV,
R s3
If the current limit is to be set to ILM=2.5A with Vo=1.2V
and Cs=33nF in the same example, then Rs=4.12 kΩ,
Rs3=190 kΩ and Rs2=4.21 kΩ.
Vin
V be4
L
,
R eq
Rs3 is obtained from
ILMR eq +
In the application circuit, Req = 9.56mΩ so ILM = 5.23A. In
other applications, different current limits may be required.
The circuit in Figure 14 allows the user to set current-limit
different from 50mV/Req.
V be3
R sC s =
Rs 2
- 2
R s3
Figure 14. Circuit for setting current-limit different
from 50mV/Req
a) The required current limit ILM is higher than ILMcp. Rs3 is
deleted from Figure 14. Rs2 is given by
R s 2C s =
L
,
R eq
Rs is obtained from
ILMR eq
R s2
= 50mV,
Rs
Rs1 is then computed from
R s1 =
R s 2R s
.
R s − R s2
If the current limit is to be set to ILM=15A in the example
given in last section with Cs=33nF, then Rs2=4.12kΩ,
2005 Semtech Corp.
During start-up, the capacitor from the SS/EN pin to ground
functions as a soft-start capacitor. After the converter starts
and enters regulation, the same capacitor operates as
overload shutoff timing capacitor. As the load current
increases, the cycle-by-cycle current-limit comparator will
first limit the inductor current. Further increase in loading
will cause the output voltage (hence the feedback voltage)
to fall. If the feedback voltage falls to less than 70% of the
normal, the controller will shut off both the top and the
bottom MOSFET’s. Meanwhile an internal current source
(1.4µA) discharges the soft start capacitor C 32(C 33 )
connected to the SS/EN pin.
When the capacitor is discharged to 0.47V, a 2.3µA
current source recharges the SS/EN capacitor and the
controller re-initiates soft-start. If the overload persists,
the controller will shut down the converter as the soft
start capacitor voltage exceeds 3.25V. The converter will
repeatedly start and shut off until it is no longer
overloaded. This hiccup mode of overload protection is a
21
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SC2441
POWER MANAGEMENT
Applications Information (Cont.)
form of foldback current limiting. The following
calculations estimate the average inductor current when
the converter output is shorted to the ground.
a) The time taken to discharge the capacitor from 3.25V
to 0.47V is
t ssf
(3.25 − 0.47)V
.
= C32
1.4µA
resistance may not be available as a standard value
resistor. As a result, there will be a set error in the
converter output voltage. This non-random error is
caused by the feedback voltage divider ratio. It cannot
be corrected by the feedback loop.
The following table lists a few standard resistor
combinations for realizing some commonly used output
voltages.
If C32 = 0.1µF, tssf will then be 200ms.
b) The soft-start time from 0.47V to 3.25V is
t ssr = C 32
( 3 .25 − 0 . 47 ) V
.
2 .3µ A
If C32 = 0.1µF, tssr will then be 121ms. Note that during
soft-start, the converter only starts switching when the
voltage at SS/EN exceeds 1.3V.
c) The effective start-up time is
t sso = C32
(3.25 − 1.3)V
.
2.3µA
The average inductor current is then
ILeff = ILMcp
t sso
.
t ssf + t ssr
I Leff = 0.27I LMcp and is independent of the soft start
capacitance. The converter will not overheat in hiccup.
Setting the Output Voltage
The non-inverting inputs of the error amplifiers are
internally biased to 0.5V voltage reference. A simple
voltage divider (Ro1 at top and Ro2 at bottom) sets the
converter output voltage. Ro2 can be expressed as a
function of the voltage feedback gain h=0.5/Vo and Ro1
Ro2 =
h
R o1.
1− h
Once either Ro1 or Ro2 is chosen, the other can be calculated
for the desired output voltage Vo. Since the number of
standard resistance values is limited, the calculated
2005 Semtech Corp.
Vo (V)
0.6
0.9
1.2
1.5
1.8
2.5
3.3
(1- h)/h
0.2
0.8
1.4
2
2.6
4
5.6
Ro1 (Ohm) 200
806
1.4K
2K
2.61K 4.02K 5.62K
Ro2 (Ohm) 1K
1K
1K
1K
1K
1K
1K
Only the voltages in boldface can be precisely set with
standard 1% resistors.
The input bias current of the error amplifier also causes
an error in the output voltage. The inverting input bias
currents of error amplifiers 1 and 2 are –160nA and –
260nA respectively. Since the non-inverting input is biased
to 0.5V, the percentage error in the second output voltage
will be –100% · (0.26µA) · R R /[0.5 · (R +R )]. To
o1 o2
o1 o2
keep this error below 0.2%, R
< 4kΩ.
o2
Loop Compensation
The SC2441 uses current-mode control for both step-down
channels. Current-mode control is a dual-loop control
system in which the inductor peak current is loosely
controlled by the inner current-loop. The higher gain outer
loop regulates the output voltage. Since the current loop
makes the inductor appear as a current source, the complex
high-Q poles of the output LC networks is split into a
dominant pole determined by the output capacitor and
the load resistance and a high frequency pole. This polesplitting property of current-mode control greatly simplifies
loop compensation.
The inner current-loop is unstable (sub-harmonic oscillation)
unless the inductor current up-slope is steeper than the
inductor current down-slope. For stable operation above
50% duty-cycle, a compensation ramp is added to the
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SC2441
POWER MANAGEMENT
Applications Information (Cont.)
sensed-current. In the SC2441 the compensation ramp
is made duty-ratio dependent. The compensation ramp
is approximately
Iramp = De
1.1D
For the rated output current Io, the first-order gain k is
determined as
k=
* 4.8µA.
The incremental slope of such current ramp is then
Se = (1 + 1.1D)e1.1D fs * 4.8µA.
∆Io
.
∆Vc
Furthermore the transfer function from the voltage error
amplifier output vc to the converter output vo can be
derived from Figure 15.
s
Vo (s)
s z1
,
:= Gvc (s) = kR o
s
Vc (s)
1+
sp1
Once the inner current loop is stabilized, the output voltage
is then regulated with the outer voltage feedback loop. An
equivalent circuit of current-mode Buck converter is shown
in Figure 15.
1+
where the single dominant-pole is
sp1 =
1
(R o + R oesr )Co
and the zero associated with the output capacitor ESR is
s z1 =
1
.
R oesr C o
The dominant-pole changes with the converter output load.
The controller transfer function (from the converter output
vo to the voltage error amplifier output vc) is
k
gmh
C(s) =
s(C 2 + C 3 )
Figure 15. A simple model of current-mode buck converter
The voltage transconductance error amplifier (in the
SC2441) has a g m of 400µA/V. C2, C 3 and R 2 of the
compensation network are to be determined for stable
operation with optimized load transient response.
The feedback gain h and the resistor values are determined
using the equations given in the “Setting the Output
Voltage” section with
0.5
h=
.
Vo
2005 Semtech Corp.
s
s z2
,
s
1+
sp2
1+
where
sz2 =
1
R 2C 2
and
sp2 =
1
.
C 2C 3
R2
C 2 + C3
The loop transfer function is then
T(s)=Gvc(s)C(s).
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SC2441
POWER MANAGEMENT
Applications Information (Cont.)
P2 is a pole for suppressing high-frequency switching
noise. So P2 >> Z2. To simplify design, one usually assumes
that C3<<C2, Roesr<<Ro, Sp1=Sz2 and specifies the loop
crossover frequency fc. The loop crossover frequency
determines the converter dynamic response. With these
assumptions, the controller parameters are determined
as follows
C2 =
gmhkR o
,
2πfc
R2 =
R oCo
C2
and
C3 =
R oesr C o
.
R2
For example, if Vin=3.3V, V o=1.2V, I o=4A, f s=500kHz,
Co=390µF, Roesr=16mΩ, one can calculate that
Ro =
h=
Vo
= 300m Ω,
Io
0.5
= 0.42
Vo
and
k=
∆Io
= 2.60.
∆Vc
If the converter crossover frequency is set around 1/10
of the switching frequency, f c=50kHz, the controller
parameters then can be calculated.
C2 =
gmhkR o
≈ 0.497nF,
2πfc
use C2=0.47nF.
R2 =
R oCo
≈ 150 .8kΩ,
C2
use R2=150kΩ.
It is further calculated that
R C
C 3 = oesr o ≈ 4.97pF,
R2
use C3=5pF. The Bode plots of the loop transfer function
(magnitude and phase) are shown in Figure 16.
2005 Semtech Corp.
Figure 16. Bode plots of the loop response.
The resulting crossover frequency is about 49.2kHz with
phase margin 90o.
If the circuit noise makes the converter jitter, a larger C3
than the calculated value can be used. Effectively the
converter bandwidth is reduced to reject high frequency
noises. The final circuit should be checked for stability
under load transients at different line voltages. The load
transient also needs to be measured to ensure that the
output voltage is within the specification window.
Step-up Converter
The step-up regulator in the SC2441 is integrated with a
1.7A power switch. Switch current sensing and ramp
compensation are implemented internally. The switching
frequency fs3 of the step-up regulator is twice those of
the step-down controllers.
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SC2441
POWER MANAGEMENT
Applications Information (Cont.)
Given the input voltage Vin, the output voltage Vo3 and
the load current Io3, the following circuit parameters are
to be determined.
Inductor Selection
For a specified inductor current ripple (peak-to-peak) δ3,
the inductor value is
L3 =
Vin
V V
(1 − in ) in .
fs3 δ 3Io3
Vo3 Vo3
If Vin = 3.3V, Vo3 = 5V and Io3 = 1A withδ3 = 0.3 and fs3 =
1MHz, then, L3 = 2.5µH.
For operation above 1MHz, Ferrite core material should
be used for lower core losses and better circuit efficiency.
The peak inductor current is
Maximum Output Current
Figure 4 shows that the boost switch current is sensed
with an internal sense resistor Rs. With a current limit
threshold voltage of 14mV, the maximum output current
is
(1 − D 3 )14mV
.
δ
R s (1 + 3 )
2
The boost switch current limit is internally set at 1.7A.
Io3,max =
Voltage Feedback
With the internal reference voltage Vref3=1.25V, the voltage
feedback gain is
h3 =
(1+0.5*δ3)Io3.
The saturation current rating of the selected inductor
should be at least 1.2~1.5 times of the calculated peak
current value. In the example above, the peak inductor
current is 1.74A.
Capacitor Selection
Input capacitor:: The input capacitance should be large
such that the input transients due to both the step-up
and the step-down converters do not trip the UVLO
threshold 1.59V. Since the SC2441 controls a 2-phase
low input voltage step-down converter, the input
capacitance is sized to handle the input ripple current of
the buck converter. This is usually sufficient for the auxiliary
boost converter because the input current in a boost
converter is continuous. A small (< 1uF) ceramic bypass
capacitor can be soldered close to the PVIN pin for high
frequency filtering.
Vref 3 1.25
=
= 0.25.
Vo3
5
The values of the feedback resistors can be determined
from the equation in “Setting the Output Voltage” section.
Loop Compensation
A simple small signal model for current-mode boost
converter in continuous-conduction mode is shown in
Figure 17.
SL 3
(I − D 3 ) I −
2
(I − D 3 ) R O 3
Output capacitor: Unlike buck converter, pulse current is
delivered to the output of a boost converter. To reduce the
output ripple voltage, low ESR capacitors should be used.
The output capacitor should also be able handle the output
ripple current. The SC2441 is designed to use multi-layer
ceramic capacitor as the sole output capacitor.
Figure 17. Small signal model of Boost converter.
2005 Semtech Corp.
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SC2441
POWER MANAGEMENT
Applications Information (Cont.)
In Figure 17, Co3 and Resr3 are the capacitance and the
ESR of the output capacitor, gm3 is the error amplifier
transconductance and k3 is the current loop gain. If one
specifies the loop crossover frequency f c , the
compensation component values are readily calculated
as
C 4 = h 3 gm3k 3 (1 − D 3 )
R4 =
Bode plots of the loop response are shown in Figure 18.
R o3
f
R esr 3
1
| 1− c |
,
2
fz1 2πfc R esr 3 + 0.5R o3
1
R
Co3 (R esr 3 + o3 )
C4
2
and
C5 = C 4
2R esr 3
Ro3
with
fz1 =
(1 − D 3 )2 R o3
.
2πL 3
Figure 18. Typical loop transfer function Bode plot of
the Boost converter.
2005 Semtech Corp.
26
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SC2441
POWER MANAGEMENT
Applications Information (Cont.)
PC Board Layout Issues
Circuit board layout is very important for the proper
operation of high frequency switching power converters. A
power ground plane is required to reduce ground bounces.
The followings are suggested for proper layout.
Power Stage
1) Separate the power ground from the signal ground. In
SC2441 the power ground PGND should be tied to the
source terminal of lower MOSFETs. The signal ground AGND
should be tied to the negative terminal of the output
capacitor (ouput return terminal).
2) Minimize the size of pulse current loop. Place the top
MOSFET, the bottom MOSFET and the input capacitors
close to each other with short and wide traces. In addition
to the aluminum energy storage capacitors, add multi-layer
ceramic (MLC) capacitors from the input to the power
ground to improve high frequency bypass.
3) Reduce high frequency voltage ringing. Widen and
shorten the drain and source traces of the MOSFET’s to
reduce stray inductances. Add a small RC snubber if
necessary to reduce the high frequency ringing at the phase
node. Sometimes slowing down the gate drive signal also
helps in reducing the high frequency ringing at the phase
node.
4) Shorten the gate driver path. Integrity of the gate drive
(voltage level, leading and falling edges) is important for
circuit operation and efficiency. Short and wide gate drive
traces reduce trace inductances. Bond wire inductance is
about 2~3nH. If the length of the PCB trace from the gate
driver to the MOSFET gate is 1 inch, the trace inductance
will be about 25nH. If the gate drive current is 2A with
10ns rise and falling times, the voltage drops across the
bond wire and the PCB trace will be 0.6V and 5V
respectively. This may slow down the switching transient of
the MOSFET’s. These inductances may also ring with the
gate capacitance.
5) Put the decoupling capacitor for the gate drive power
supplies (BST and VCC) close to the IC and power ground.
Control Section
6) The frequency-setting resistor Rosc should be placed
close to Pin 10. Trace length from this resistor to the analog
ground should be minimized.
7) Solder the VCC decoupling capacitor next to the VCC
and power ground PGND pins.
8) Place the combi-sense components away from the power
circuit and close to the corresponding CS+ and CS- pins.
Use X7R type ceramic capacitors for combi-sensing due
to their thermal stability.
9) Use an isolated local ground plane for the controller
and tie it to the negative side of output capacitor bank.
A note for Vin = 12V application
Figure 21 shows an application where the input voltage is 12V. A LDO is used to provide 5V bias for SC2441. The
voltages at BST1 (Pin 25) and BST2 (Pin 18) should not exceed their maximum voltage rating (20V).
2005 Semtech Corp.
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SC2441
POWER MANAGEMENT
Application Information
V in : 3.3V
VinGND
R33
J1
4
3
2
1
= V o 3: 5V /0.5A
R14
C11
C7
C4+
C34
L3
D1
C10
C8
IN
27
R4
Q1
L1
FB3
COMP3
PH3
21
C17
C22
C1+
D6
+
VO1: 1.2V/4A
R15
C2
1
+
+
C35
C12
C13
C38
C40
C3
D2
C14
+
C5
C6+
+
25
23
VCC
PVIN
BST1
BST2
GDH1
GDH2
GDL1
GDL2
7
R12
8
C29
28
D7
C23
VO1GND
R8
Q2
R6
R11
22
24
R13
R3
Q5
VO2: 2.5V/1A
L2
VPN1
4
5
C39
11
RCS-2
12
C28
R19
R16
R7
20
Q6
D5
VPN2
CS1+
CS2+
CS1-
CS2-
FB1
FB2
COMP1
COMP2
R10
2
R20
9
SYNC
GND
SS1/EN1
U1
SS2/EN2
R9
RCS+1
VO2GND
15
14
RCS-1
13
C27
C30
Rosc
C26
C20
16
C31
10
C25
C19
R5
PGND
26
RCS+2
+
C18
18
19
C24
C21
C9
+
+
R18
R17
6
3
17
C33
R30
C32
SC2441
Figure 19. Two independent buck converters with auxiliary boost
Vin: 3.3V
VinGND
R 33
J1
= Vo3: 5V/0.5A
4
3
2
1
R 14
C 11
C7
C6+
+
C5
C 38
+
C4 +
C 34
D2
C 14
+
L3
C 22
27
21
25
R4
Q1
L1
23
IN
F B3
P H3
COMP3
VC C
PVIN
BST1
BST2
G DH1
G DH2
7
8
R 12
C 29
+
28
C 21
R 11
D7
R8
Q2
Q4
R6
24
R 13
26
R CS +2
4
5
C 39
11
R CS -2
C 28
R 19
R 16
22
12
GD L1
GD L2
20
R3
VPN2
CS1+
CS2+
CS1-
CS2-
F B1
F B2
COMP1
COMP2
C9
+
VO1
Q5
L2
R7
Q6
P GN D
VPN1
+
C 18
18
19
C 24
C 23
VO1GND
C 10
C8
+
C 17
VO1: 1.2V/20A
D1
C2
D6
C 12
C 13
C1 +
C 35
1
+
R 15
C 40
C3
Q8
D5
C 25
C 19
R5
C 26
C 20
R 10
2
R CS +1
VO1GND
16
15
R CS -1
14
13
C 31
10
Rosc
S YN C
GN D
SS1 /E N1
U1
SS2 /E N2
R 20
9
6
3
17
C 33
C 32
SC2441
Figure 20. Dual-phase single output buck (current sharing) with single boost
2005 Semtech Corp.
28
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29
VO1GND
C22
C24
VO1: 1.2V/4A
R16
R11
+
+
C14
L1
C21
+
RCS-2
RCS+2
C13
C12
R6
C17
C23
D2
R13
C4+
R19
D7
C3
C31
C28
Q2
Q1
C34
R20
R8
R4
C35
9
10
12
11
5
4
26
24
22
23
25
21
27
1
+
C6+
FB3
6
13
14
15
16
2
20
19
18
28
R7
R3
C32
VinGND
C33
3
SS1/EN1
U1
17
SS2/EN2
SYNC
COMP2
SC2441
GND
Rosc
COMP1
FB2
CS2-
CS1FB1
CS2+
VPN2
GDL2
GDH2
BST2
PVIN
8
7
C38
COMP3
+
C5
CS1+
VPN1
PGND
GDL1
GDH1
BST1
VCC
PH3
IN
C7
R30
C30
C27
Q6
Q5
C2
R18
SC LDO
R10
D5
C1+
C19
1 OUT
IN 8
FB 7
SENSE
2
GND
TAP 6
ERRORB 5
SHDN
R5
C18
D1
3
2005 Semtech Corp.
4
Vin: 12V
L2
RCS-1
RCS+1
C20
R12
+
C8
C10
R17
R9
C25
+
C9
VO2GND
C26
VO2: 2.5V/1A
+
SC2441
POWER MANAGEMENT
Typical Application Circuit
Figure 21. Dual output Buck with 12V input
www.semtech.com
SC2441
POWER MANAGEMENT
Evaluation Board - Bill of Materials
R ef
Qty
Reference
1
1
C7
150uF, 6.3V, 30mohm, Alum. or
OS-CON
Sanyo P/N: 6SP150M
2
3
C2,C3,C6
22uF, 6.3V, X5R, Ceramic 1210
Taiyo Yuden P/N: YMK325BJ226MM
4
1
C11
47uF, 6.3V, X5R, Ceramic
TDK P/N: C3225X5R0J476MJ
5
1
C 12
100uF, 6.3V, X5R, Ceramic
TDK P/N: C3225X5R0J107M
6
2
C17,C18
0.33uF, 50V, X5R (or X7R) 1206
Vishay P/N:
VJ1206Y334KXAAT
7
2
C19,C23
2.2nF, X5R, Ceramic, 0805
Any
8
1
C 20
22nF, X5R, Ceramic, 0805
Any
9
1
C 21
10nF, 16V, X5R, Ceramic, 0805
Any
10
2
C22,C25
22uF, 6.3,V X5R, Ceramic, 1210
Taiyo Yuden P/N: YMK325BJ226MM
11
3
C24,C26,C34
10uF, 6.3V,X5R, Ceramic, 1206
TDK P/N: C3216X5R0J106MT
12
1
C 27
10pF, X5R, Ceramic, 0805
Any
13
1
C 28
10pF, Ceramic, 0805
Any
14
1
C 29
1nF, 16V, X5R, Ceramic, 0805
Any
15
1
C 30
0.22nF, X5R, Ceramic, 0805
Any
16
1
C 31
0.47nF, X5R, Ceramic, 0805
Any
17
2
C32,C33
100nF, X5R, Ceramic, 0805
Any
18
1
C 35
1uF, 16V, X5R, Ceramic, 0805
Any
19
1
C 40
100pF, 16V, X5R, Ceramic, 0805
Any
20
2
D1,D2
40V, 1A, Schottky
General Semi P/N: 1N5819M, MELF
Motorola P/N: MBRS140T3
21
1
D6
40V, 3A, B340A SMA, Shottky,
SOD-123
Diode Inc.
22
1
L1
1.8uH, 14A, 3.3mohm
Panasonic P/N: ETQP6F1R8BFA
23
1
L2
6.8uH, 1.5A, 52mohm
Panasonic P/N: ELL6SH6R8M
24
1
L3
9uH, 1.9A, 57mohm
Pulse Eng. P/N: P1167.123T
2005 Semtech Corp.
Part Number/Value
30
Manufacturer
www.semtech.com
SC2441
POWER MANAGEMENT
Evaluation Board - Bill of Materials
R ef
Qty
Reference
Part Number/Value
Manufacturer
25
2
(Q1,Q2), (Q5,Q6)
12V, 11.8A, 17mohm, Power
p a ck
Vishay P/N: Si7940DP
26
1
RCS+1
2K , 0805
Any
27
1
RCS+2
5.1K, 0805
Any
28
1
RCS-1
100 Ohm, 0805
Any
29
1
RCS-2
10K , 0805
Any
30
4
R3,R4,R7,R8
1 Ohm 5%, 0805
Any
31
2
R5,R6
1 5 k, 0 8 0 5
Any
32
1
R9
3.92K, 1%, 0805
Any
33
2
R10,R13
5.1 Ohm, 0805
Any
34
2
R11,R14
4.02K, 1%, 0805
Any
35
1
R12
33.2K, 1%, 0805
Any
36
1
R15
1.43K, 1%. 0805
Any
37
1
R16
3.01K, 1%. 0805
Any
38
1
R17
1.02K, 1%. 0805
Any
39
1
R18
301K , 0805
Any
40
1
R19
150K , 0805
Any
41
1
R20
47.5K, 1%. 0805
Any
42
1
R33
0 Ohm, 0805
Any
43
1
U1
S C 2441
Semtech Corp.
* Dual output Buck with single Boost.
2005 Semtech Corp.
31
www.semtech.com
SC2441
POWER MANAGEMENT
Typical Characteristics
Typical waveforms in the evaluation circuit board
Channel 1: Vo=1.2V @ 4A
No load start up
Overload protection
Output shorted
Load transient response
Loading: 0.4A to 3.6A to 0.4A, 2.5A/uS
output short persists
Shut down
Output short removed
2005 Semtech Corp.
32
www.semtech.com
SC2441
POWER MANAGEMENT
Typical Characteristics (Cont.)
Typical waveforms in the evaluation circuit board
Channel 2: Vo=2.5V @ 1A
Full load start up
Overload protection
Output shorted
Load transient response
Loading: 0.1A to 0.9A to 0.1A at 2.5A/uS
Output short persists
Shut down
Output short removed
2005 Semtech Corp.
33
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SC2441
POWER MANAGEMENT
Typical Characteristics (Cont.)
Typical waveforms in the evaluation circuit board
Channel 3: Vo=5V @ 0.4A
Start up
Load transient response
Loading: 0.04A to 0.36A to 0.04A at 2.5A/uS
Shut down
2005 Semtech Corp.
34
www.semtech.com
SC2441
POWER MANAGEMENT
Outline Drawing - TSSOP-28
Land Pattern - TSSOP-28
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012-8790
Phone: (805)498-2111 FAX (805)498-3804
2005 Semtech Corp.
35
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