54LVX4245 8-Bit Dual Supply Translating Transceiver with TRI-STATE ® Outputs General Description Features The LVX4245 is a dual-supply, 8-bit translating transceiver that is designed to interface between a 5V bus and a 3V bus in a mixed 3V/5V supply environment. The Transmit/Receive (T/R) input determines the direction of data flow. Transmit (active-HIGH) enables data from A ports to B ports; Receive (active-LOW) enables data from B ports to A ports. The Output Enable input, when HIGH, disables both A and B ports by placing them in a TRI-STATE condition. The A port interfaces with the 5V bus; the B port interfaces with the 3V bus. The LVX4245 is suitable for mixed voltage applications such as systems using 3.3V memories which must interface with existing buses or other components operating at 5.0V. n n n n n n n n Bidirectional interface between 5V and 3V buses Control inputs compatible with TTL level 5V data flow at A port and 3V data flow at B port Outputs source/sink 24 mA Available in Ceramic DIP and Flatpack packages Implements patented EMI reduction circuitry Functionally compatible with the 54 series 245 Standard Microcircuit Drawing (SMD) 5962-9860601 Ordering Code Order Number Package Number Package Description 54LVX4245J-QML J24F 24-Lead Ceramic Dual-in-line 54LVX4245W-QML W24C 24-Lead Cerpack Logic Symbol Connection Diagram Pin Assignment for CDIP and Cerpack DS101021-1 Pin Descriptions Pin Names Description OE Output Enable Input T/R Transmit/Receive Input A0–A7 Side A Inputs or TRI-STATE Outputs B0–B7 Side B Inputs or TRI-STATE Outputs DS101021-2 TRI-STATE ® is a registered trademark of National Semiconductor © 2001 National Semiconductor Corporation DS101021 www.national.com 54LVX4245 8-Bit Dual Supply Translating Transceiver with TRI-STATE Outputs March 1999 54LVX4245 Connection Diagram (Continued) Inputs OE Outputs T/R L L Bus B Data to Bus A L H Bus A Data to Bus B H X HIGH-Z State H = High Voltage Level L = Low Voltage Level X = Immaterial Logic Diagram DS101021-6 www.national.com 2 Recommended Operating Conditions (Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCCA, VCCB) DC Input Voltage (VI) @ OE , T/R DC Input/Output Voltage (VI/O) @ A(n) @ B(n) DC Input Diode Current (IIN) @ OE , T/R DC Output Diode Current (IOK) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) and Max Current @ ICCA @ ICCB Storage Temperature Range (TSTG) 54LVX4245 Absolute Maximum Ratings (Note 1) Supply Voltage VCCA VCCB Input Voltage (VI) @ OE , T/R Input/Output Voltage (VI/O) @ A(n) @ B(n) Free Air Operating Temperature (TA) 54LVX Minimum Input Edge Rate (∆t/∆V) VIN from 30% to 70% of VCC VCC @ 3.0V, 4.5V, 5.5V −0.5V to +7.0V −0.5V to VCCA + 0.5V −0.5V to VCCA + 0.5V −0.5V to VCCB + 0.5V ± 20 mA ± 50 mA ± 50 mA 4.5V to 5.5V 2.7V to 3.6V 0V to VCCA 0V to VCCA 0V to VCCB −55˚C to +125˚C 8 ns/V Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. ± 50 mA ± 200 mA ± 200 mA Note 2: Unused inputs must he held HIGH or LOW. They may not float. −65˚C to +150˚C DC Electrical Characteristics Symbol Parameter VCCA (V) VCCB (V) 5.5 3.3 TA = −55˚C to +125˚C Units Conditions Guaranteed Limits VIHA Minimum High Level OE 4.5 3.3 2.0 VIHB Input Voltage B(n) 5.0 3.6 2.0 5.0 2.7 2.0 VILA VILB VOHA A(n), T/R , Maximum A(n), T/R , 5.5 3.3 0.8 Low Level OE 4.5 3.3 0.8 Input Voltage B(n) VOUT ≤ 0.1V or ≥ VCC − 0.1V V VOUT ≤ 0.1V or ≥ VCC −0.1V 5.0 2.7 0.8 3.6 0.8 4.5 2.7 4.4 5.5 3.6 5.4 IOH = −100 µA 4.5 3.0 3.7 IOH = −24 mA 4.5 2.7 2.6 5.5 3.6 3.5 IOH = −100 µA 4.5 2.7 2.2 IOH = −12 mA 4.5 3.0 2.4 IOH = −12 mA 4.5 3.0 2.2 Maximum Low Level 4.5 2.7 0.1 Output Voltage 5.5 3.6 0.1 Minimum High Level VOHB VOLB V 5.0 Output Voltage VOLA 2.0 V V IOH = −100 µA IOH = −100 µA IOH = −24 mA V IOL =100 µA IOL =100 µA 4.5 3.0 0.4 IOL = 24 mA 4.5 2.7 0.1 IOL = 100 µA 5.5 3.6 0.1 4.5 2.7 0.4 IOL = 12 mA 4.5 3.0 0.3 IOL = 12 mA 4.5 3.0 0.4 IOL = 24 mA 3 V IOL = 100 µA www.national.com 54LVX4245 DC Electrical Characteristics Symbol Parameter (Continued) VCCA (V) VCCB (V) TA = −55˚C to +125˚C Units Conditions Guaranteed Limits IIN Maximum Input VI = VCCA, GND 3.6 ± 1.0 5.5 3.6 ± 5.0 µA Output Leakage @ B(n) 5.5 3.6 ± 5.0 µA VO = VCCB, GND Maximum ICCT/Input 5.5 3.6 1.5 mA VI = VCCA − 2.1V, Leakage Current 5.5 µA @ OE , T/R IOZA Maximum TRI-STATE Output Leakage @ A(n) IOZB ∆ICC T/R = 0.0V, Maximum TRI-STATE T/R = 5.5V, @ A(n), T/R , OE Input @ B(n) ICCA T/R = 5.5V 5.5 3.6 0.5 mA 5.5 3.6 40 µA Quiescent VCCA Supply Current VO = VCCA, GND VI = VCCB − 0.6V, T/R = 0.0V B(n) = VCCB or GND, OE = GND, T/R = 0.0V ICCB Quiescent VCCB Supply Current A(n) = VCCA or GND, 5.5 3.6 10 µA OE = GND, T/R = 5.5V VOLPA Quiet Output Maximum 5.0 3.3 1.5 VOLPB Dynamic VOL 5.0 3.3 0.8 VOLVA Quiet Output Minimum 5.0 3.3 -1.1 VOLVB Dynamic VOL 5.0 3.3 -0.7 Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: Worst case package. Note 5: Max number of outputs defined as (n). Data inputs are driven 0V to VCC level; one output at GND. www.national.com 4 V (Notes 4, 5) V (Notes 4, 5) Symbol Parameters TA = −55˚C to +125˚C TA = −55˚C to +125˚C CL = 50 pF CL = 50 pF VCCA = 5V (Note 6) VCCA = 5V (Note 6) VCCB = 3.3V (Note 7) Min Units VCCB = 2.7V Max Min Max tPHL Propagation Delay 1.0 7.5 1.0 8.5 tPLH A to B 1.0 7.5 1.0 8.5 tPHL Propagation Delay 1.0 8.5 1.0 9.0 tPLH B to A 1.0 8.5 1.0 9.0 tPZL Output Enable Time 1.0 9.5 1.0 10.0 tPZH OE to B 1.0 9.5 1.0 10.0 tPZL Output Enable Time 1.0 8.0 1.0 8.0 tPZH OE to A 1.0 8.0 1.0 8.0 tPHZ Output Disable Time 1.0 7.5 1.0 7.5 tPLZ OE to B 1.0 7.5 1.0 7.5 tPHZ Output Disable Time 0.5 7.0 0.5 7.0 tPLZ OE to A 0.5 7.0 0.5 7.0 tOSHL Output to Output tOSLH Skew (Note 8) 1.5 ns ns ns ns ns ns 1.5 ns Data to Output Note 6: Voltage Range 5.0V is 5.0V ± 0.5V. Note 7: Voltage Range 3.3V is 3.3V ± 0.3V. Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design. Capacitance Max Units Conditions CIN Symbol Input Capacitance Parameter 10 pF VCC = Open CI/O Input/Output 12 pF VCCA = 5.0V 50 pF VCCA = 5.0V Capacitance CPD VCCB = 3.3V Power Dissipation Capacitance VCCB = 3.3V CPD is measured at 10 MHz 8-Bit Dual Supply Translating Transceiver The LVX4245 is a dual supply device capable of bidirectional signal translation. This level shifting ability provides an efficient interface between low voltage CPU local bus with memory and a standard bus defined by 5V I/O levels. The device control inputs can be controlled by either the low voltage CPU and core logic or a bus arbitrator with 5V I/O levels. Manufactured on a sub-micron CMOS process, the LVX4245 is ideal for mixed voltage applications using 3.3V devices and 5V buses or IC’s. DS101021-3 5 www.national.com 54LVX4245 AC Electrical Characteristics 54LVX4245 Applications: Mixed Mode Dual Supply Interface Solution shown in Figure 1, the designer could use this device in either a 3V system or a 5V system without any further work to re-layout the board. LVX4245 is designed to solve 3V/5V interfacing issues when CMOS devices cannot tolerate I/O levels above their applied VCC. If an I/O pin of 3V ICs is driven by 5V ICs, the P-Channel transistor in 3V ICs will conduct causing current flow from I/O bus to the 3V power supply. The resulting high current flow can cause destruction of 3V ICs through latchup effects. To prevent this problem, a current limiting resistor is used typically under direct connection of 3V ICs and 5V ICs, but it causes speed degradation. In a better solution, the LVX4245 configures two different output levels to handle the dual supply interface issues. The “A” port is a dedicated 5V port to interface 5V ICs. The “B” port is a dedicated port to interface 3V ICs. Figure 2 shows how LVX4245 fits into a system with 3V subsystem and 5V subsystem. This device is also configured as an 8-bit 245 transceiver, giving the designer TRI-STATE capabilities and the ability to select either bidirectional or unidirectional modes. Since the center 20 pins are also pin compatible to 54 series 245, as DS101021-4 FIGURE 1. LVX4245 Pin Arrangement is Compatible to 20-Pin 54 Series 245 DS101021-5 FIGURE 2. LVX4245 Fits into a System with 3V Subsystem and 5V Subsystem www.national.com 6 54LVX4245 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Ceramic Dual-in-line Package Number J24F 24-Lead Cerpack Package Number W24C 7 www.national.com 54LVX4245 8-Bit Dual Supply Translating Transceiver with TRI-STATE Outputs Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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