NSC 74ACT899QMQB

74AC899 # 54ACT/74ACT899
9-Bit Latchable Transceiver
with Parity Generator/Checker
General Description
Features
The ’AC/’ACT899 is a 9-bit to 9-bit parity transceiver with
transparent latches. The device can operate as a feedthrough transceiver or it can generate/check parity from the
8-bit data busses in either direction. The ’AC/’ACT899 features independent latch enables for the A-to-B direction and
the B-to-A direction, a select pin for ODD/EVEN parity, and
separate error signal output pins for checking parity.
Y
Y
Y
Y
Y
Y
Y
Y
Y
Logic Symbol
Latchable transceiver with output sink of 24 mA
Option to select generate parity and check or ‘‘feedthrough’’ data/parity in directions A-to-B or B-to-A
Independent latch enable for A-to-B and B-to-A directions
Select pin for ODD/EVEN parity
ERRA and ERRB output pins for parity checking
Ability to simultaneously generate and check parity
May be used in system applications in place of the ’280
May be used in system applications in place of the ’657
and ’373 (no need to change T/R to check parity)
4 kV minimum ESD immunity
Connection Diagram
Pin Assignment for PCC and LCC
TL/F/10637 – 1
TL/F/10637 – 2
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
FACTTM is a trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/F/10637
RRD-B30M75/Printed in U. S. A.
74AC899 # 54ACT/74ACT899
9-Bit Latchable Transceiver with Parity Generator/Checker
August 1994
Pin Names
Description
A 0 – A7
B 0 – B7
APAR, BPAR
ODD/EVEN
A Bus Data Inputs/Data Outputs
B Bus Data Inputs/Data Outputs
A and B Bus Parity Inputs
ODD/EVEN Parity Select, Active
LOW for EVEN Parity
Output Enables for A or B Bus,
Active LOW
Select Pin for Feed-Through or
Generate Mode, LOW for Generate
Mode
Latch Enables for A and B Latches,
HIGH for Transparent Mode
Error Signals for Checking
Generated Parity with Parity In,
LOW if Error Occurs
GBA, GAB
SEL
LEA, LEB
ERRA, ERRB
Functional Description
The ’AC/’ACT899 has three principal modes of operation
which are outlined below. These modes apply to both the Ato-B and B-to-A directions.
Ð Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If
LEB (LEA) is HIGH and the Mode Select (SEL) is LOW,
the parity generated from B[0:7] (A[0:7]) can be
checked and monitored by ERRB (ERRA).
Ð Bus A (B) communicates to Bus B (A) in a feed-through
mode if SEL is HIGH. Parity is still generated and
checked as ERRA and ERRB in the feed-through mode
(can be used as an interrupt to signal a data/parity bit
error to the CPU).
Ð Independent Latch Enables (LEA and LEB) allow other
permutations of generating/checking (see Function Table below).
Function Table
Inputs
Operation
GAB GBA SEL LEA LEB
H
H
X
X
X
Busses A and B are TRI-STATEÉ.
H
L
L
L
H
Generates parity from B[0:7] based on O/E (Note 1). Generated parity
x APAR. Generated parity checked against BPAR and output as
ERRB.
H
L
L
H
H
Generates parity from B[0:7] based on O/E. Generated parity x
APAR. Generated parity checked against BPAR and output as ERRB.
Generated parity also fed back through the A latch for generate/check
as ERRA.
H
L
L
X
L
Generates parity from B latch data based on O/E. Generated parity
x APAR. Generated parity checked against latched BPAR and
output as ERRB.
H
L
H
X
H
BPAR/B[0:7] x APAR/A0:7] Feed-through mode. Generated parity
checked against BPAR and output as ERRB.
H
L
H
H
H
BPAR/B[0:7] x APAR/A[0:7]
Feed-through mode. Generated parity checked against BPAR and
output as ERRB. Generated parity also fed back through the A latch for
generate/check as ERRA.
L
H
L
H
L
Generates parity for A[0:7] based on O/E. Generated parity x
BPAR. Generated parity checked against APAR and output as ERRA.
L
H
L
H
H
Generates parity from A[0:7] based on O/E. Generated parity x
BPAR. Generated parity checked against APAR and output as ERRA.
Generated parity also fed back through the B latch for generate/check
as ERRB.
L
H
L
L
X
Generates parity from A latch data based on O/E. Generated parity
x BPAR. Generated parity checked against latched APAR and
output as ERRA.
L
H
H
H
L
APAR/A[0:7] x BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and
output as ERRA.
L
H
H
H
H
APAR/A[0:7] x BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and
output as ERRA. Generated parity also fed back through the B latch for
generate/check as ERRB.
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Note 1: O/E e ODD/EVEN
2
Functional Block Diagram
TL/F/10637 – 3
AC Path
An, APAR
(Bn, BPAR
TL/F/10637 – 4
x Bn, BPAR
x An, APAR)
FIGURE 1
3
AC Path (Continued)
An
(Bn
x BPAR
x APAR)
TL/F/10637 – 5
FIGURE 2
An
(Bn
x ERRA
x ERRB)
TL/F/10637 – 6
FIGURE 3
O/E
O/E
x ERRA
x ERRB
TL/F/10637 – 7
FIGURE 4
4
AC Path (Continued)
O/E
(O/E
x BPAR
x APAR)
TL/F/10637 – 8
FIGURE 5
APAR
(BPAR
x ERRA
x ERRB)
FIGURE 6
TL/F/10637 – 9
TL/F/10637 – 10
ZH, HZ
FIGURE 7
5
AC Path (Continued)
TL/F/10637 – 11
ZL, LZ
FIGURE 8
SEL
(SEL
TL/F/10637 – 12
x BPAR
x APAR)
FIGURE 9
LEA
(LEB
TL/F/10637 – 13
x BPAR, B[0:7]
x APAR, A[0:7])
FIGURE 10
6
AC Path (Continued)
TS(H), TH(H)
LEA
(LEB
TL/F/10637 – 14
x APAR, A[0:7]
x BPAR, B[0:7])
FIGURE 11
TS(L), TH(L)
LEA
(LEB
TL/F/10637 – 15
x APAR, A[0:7]
x BPAR, B[0:7])
FIGURE 12
TL/F/10637 – 16
FIGURE 13
7
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI e b0.5V
VI e VCC a 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO e b0.5V
VO e VCC a 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
DC Latch-Up Source or
Sink Current
Supply Voltage (VCC)
’AC
’ACT
Input Voltage (VI)
b 0.5V to a 7.0V
b 20 mA
a 20 mA
0V to VCC
0V to VCC
Output Voltage (VO)
Operating Temperature (TA)
74AC/ACT
54ACT
b 0.5V to VCC a 0.5V
b 20 mA
a 20 mA
b 40§ C to a 85§ C
b 55§ C to a 125§ C
Minimum Input Edge Rate DV/Dt
’AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.0V, 4.5V, 5.5V
Minimum Input Edge Rate DV/Dt
’ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
b 0.5V to VCC a 0.5V
g 50 mA
g 50 mA
b 65§ C to a 150§ C
125 mV/ns
125 mV/ns
Note: PLCC packaging is not recommended for applications requiring greater than 2000 temperature cycles from b 40§ C to a 125§ C.
g 300 mA
Junction Temperature (TJ)
CDIP
PDIP
2.0V to 6.0V
4.5V to 5.5V
175§ C
140§ C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT TM circuits outside databook specifications.
DC Electrical Characteristics for ’AC Family Devices
Symbol
Parameter
VCC
(V)
74AC
74AC
TA e a 25§ C
TA e
b 40§ C to a 85§ C
Typ
VIH
VIL
VOH
IIN
Conditions
Guaranteed Limits
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT e 0.1V
or VCC b 0.1V
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT e 0.1V
or VCC b 0.1V
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
V
2.56
3.86
4.86
2.46
3.76
4.76
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
5.5
0.36
0.36
0.36
0.44
0.44
0.44
V
5.5
g 0.1
g 1.0
mA
3.0
4.5
5.5
VOL
Units
Maximum Low Level
Output Voltage
Maximum Input
Leakage Current
3.0
4.5
5.5
0.002
0.001
0.001
*Maximum of 9 outputs loaded; thresholds on input associated with output under test.
8
IOUT e b50 mA
V
*VIN e VIL or VIH
b 12 mA
b 24 mA
IOH
b 24 mA
IOUT e 50 mA
V
*VIN e VIL or VIH
12 mA
24 mA
IOL
24 mA
VI e VCC, GND
(Note)
DC Electrical Characteristics for ’AC Family Devices (Continued)
Symbol
VCC
(V)
Parameter
74AC
74AC
TA e a 25§ C
TA e
b 40§ C to a 85§ C
Typ
IOLD
IOHD
² Minimum Dynamic
Output Current
ICC
Maximum Quiescent
Supply Current
IOZ
Maximum TRI-STATE
Leakage Current
Units
Conditions
Guaranteed Limits
5.5
75
mA
VOLD e 1.65V Max
5.5
b 75
mA
VOHD e 3.85V Min
5.5
8.0
80.0
mA
VIN e VCC
or GND (Note)
5.5
g 0.5
g 5.0
mA
VI(OE) e VIL, VIH
VI e VCC, GND
VO e VCC, GND
² Maximum test duration 2.0 ms, one output loaded at a time.
Note: IIN and ICC
@
3.0V are guaranteed to be less than or equal to the respective limit
@
5.5V VCC. ICC for 54AC
@
25§ C is identical to 74AC
@
25§ C.
DC Electrical Characteristics for ’ACT Family Devices
Symbol
Parameter
VCC
(V)
74ACT
54ACT
74ACT
TA e a 25§ C
TA e
b 55§ C to a 125§ C
TA e
b 40§ C to a 85§ C
Typ
Units
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT e 0.1V
or VCC b 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT e 0.1V
or VCC b 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
0.1
0.1
0.1
0.1
0.1
0.1
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
V
V
IOUT e b50 mA
*VIN e VIL or VIH
b 24 mA
IOH
b 24 mA
IOUT e 50 mA
*VIN e VIL or VIH
IOL
24 mA
24 mA
IIN
Maximum Input
Leakage Current
5.5
g 0.1
g 1.0
g 1.0
mA
IOZ
Maximum TRI-STATE
Leakage Current
5.5
g 0.5
g 10.0
g 5.0
mA
VI e VIL, VIH
VO e VCC, GND
ICCT
Maximum ICC/Input
5.5
1.6
1.5
mA
VI e VCC b 2.1V
IOLD
² Minimum Dynamic
5.5
50
75
mA
VOLD e 1.65V Max
b 50
b 75
mA
VOHD e 3.85V Min
160.0
80.0
mA
VIN e VCC
or GND (Note)
IOHD
Output Current
5.5
ICC
Maximum Quiescent
Supply Current
5.5
0.6
8.0
*Maximum of 9 outputs loaded; thresholds on input associated with output under test.
² Maximum test duration 2.0 ms, one output loaded at a time.
Note: ICC for 54ACT
@
25§ C is identical to 74ACT
@
25§ C.
9
VI e VCC, GND
AC Electrical Characteristics
Symbol
Parameter
VCC*
(V)
74AC
74AC
TA e a 25§ C
CL e 50 pF
TA e b40§ C
to a 85§ C
CL e 50 pF
Units
Fig.
No.
Min
Typ
Max
Min
Max
tPLH
tPHL
Propagation Delay
An, Bn to Bn, An
3.3
5.0
2.5
1.5
12.0
7.0
15.0
10.0
2.5
1.5
15.5
10.5
ns
1
tPLH
tPHL
Propagation Delay
APAR, BPAR to BPAR, APAR
3.3
5.0
2.5
1.5
9.5
5.5
12.0
8.0
2.5
1.5
12.5
8.5
ns
1
tPLH
tPHL
Propagation Delay
An, Bn to BPAR, APAR
3.3
5.0
3.0
2.0
13.5
8.0
16.5
11.0
3.0
2.0
17.0
11.5
ns
2
tPLH
tPHL
Propagation Delay
An, Bn to ERRA, ERRB
3.3
5.0
2.5
1.5
12.5
7.5
15.5
10.5
2.5
1.5
16.5
11.0
ns
3
tPLH
tPHL
Propagation Delay
ODD/EVEN to ERRA, ERRB
3.3
5.0
2.5
1.5
12.5
7.5
15.5
10.5
2.5
1.5
16.5
11.0
ns
4
tPLH
tPHL
Propagation Delay
ODD/EVEN to APAR, BPAR
3.3
5.0
3.0
2.0
12.5
7.5
15.5
10.5
3.0
2.0
16.5
11.0
ns
5
tPLH
tPHL
Propagation Delay
APAR, BPAR to ERRA, ERRB
3.3
5.0
2.0
1.5
12.5
7.5
15.5
10.5
2.0
1.5
16.5
11.0
ns
6
tPLH
tPHL
Propagation Delay
SEL to APAR, BPAR
3.3
5.0
2.0
1.5
10.0
6.0
12.5
8.5
2.0
1.5
13.5
9.0
ns
9
tPLH
tPHL
Propagation Delay
LEB, LEA to An, Bn
3.3
5.0
4.0
2.5
12.0
7.0
15.5
10.5
4.0
2.5
16.5
11.0
ns
10, 11
tPLH
tPHL
Propagation Delay
LEB, LEA to APAR, BPAR
3.3
5.0
3.0
2.0
13.5
8.0
17.0
11.5
3.0
2.0
18.0
12.0
ns
10, 11
tPLH
tPHL
Propagation Delay
LEB, LEA to ERRA, ERRB
3.3
5.0
4.0
2.5
13.5
8.0
17.0
11.5
4.0
2.5
18.0
12.0
ns
12
tPZH
tPZL
Output Enable Time
GBA, GAB to An, Bn
3.3
5.0
3.0
2.0
12.5
7.5
15.5
10.5
3.0
2.0
16.5
11.0
ns
7, 8
tPZH
tPZL
Output Enable Time
GBA, GAB to APAR, BPAR
3.3
5.0
2.5
1.5
10.5
6.0
13.5
9.0
2.5
1.5
14.0
9.5
ns
7, 8
tPHZ
tPLZ
Output Disable Time
GBA, GAB to An, Bn
3.3
5.0
1.5
1.0
11.0
6.5
14.0
9.5
1.5
1.0
14.0
9.5
ns
7, 8
tPHZ
tPHL
Output Disable Time
GBA, GAB to APAR, BPAR
3.3
5.0
1.5
1.0
11.0
6.5
14.0
9.5
1.5
1.0
14.0
9.5
ns
7, 8
*Voltage Range 5.0 is 5.0V g 0.5V.
Voltage Range 3.3 is 3.3V g 0.3V.
10
AC Operating Requirements
74AC
74AC
TA e b40§ C
to a 85§ C
CL e 50 pF
Parameter
VCC*
(V)
TA e a 25§ C
CL e 50 pF
ts
Setup Time, HIGH or LOW
An, Bn, PAR to LEA, LEB
3.3
5.0
3.0
3.0
th
Hold Time, HIGH or LOW
An, Bn, PAR to LEA, LEB
3.3
5.0
tw
Pulse Width for LEA, LEB
3.3
5.0
Symbol
Units
Fig.
No.
3.0
3.0
ns
11, 12
2.0
1.5
2.0
1.5
ns
11, 12
4.0
4.0
4.0
4.0
ns
13
Guaranteed Minimum
*Voltage Range 5.0 is 5.0V g 0.5V.
Voltage Range 3.3 is 3.3V g 0.3V.
AC Electrical Characteristics
Symbol
Parameter
VCC*
(V)
74ACT
54ACT
74ACT
TA e a 25§ C
CL e 50 pF
TA e b55§ C
to a 125§ C
CL e 50 pF
TA e b40§ C
to a 85§ C
CL e 50 pF
Min
Typ
Max
Min
Max
Min
Max
Units
Fig.
No.
tPLH
tPHL
Propagation Delay
An, Bn to Bn, An
5.0
2.5
7.5
11.5
1.5
13.5
2.5
12.0
ns
1
tPLH
tPHL
Propagation Delay
APAR, BPAR to BPAR , APAR
5.0
1.5
6.0
8.5
1.5
11.0
1.5
9.0
ns
1
tPLH
tPHL
Propagation Delay
An, Bn to BPAR, APAR
5.0
2.5
8.5
12.0
1.5
16.0
2.5
12.5
ns
2
tPLH
tPHL
Propagation Delay
An, Bn to ERRA, ERRB
5.0
2.0
8.0
11.5
1.5
16.0
2.0
12.0
ns
3
tPLH
tPHL
Propagation Delay
ODD/EVEN to ERRA, ERRB
5.0
2.0
8.0
11.5
1.5
16.0
2.0
12.0
ns
4
tPLH
tPHL
Propagation Delay
ODD/EVEN to APAR, BPAR
5.0
2.5
8.0
11.5
1.5
14.5
2.5
12.0
ns
5
tPLH
tPHL
Propagation Delay
APAR, BPAR to ERRA, ERRB
5.0
1.5
7.5
10.5
1.5
11.5
1.5
11.5
ns
6
tPLH
tPHL
Propagation Delay
SEL to APAR, BPAR
5.0
1.5
6.5
9.0
1.5
12.5
1.5
9.5
ns
9
tPLH
tPHL
Propagation Delay
LEB to An, Bn
5.0
2.5
7.0
10.5
1.5
13.5
2.5
11.0
ns
10, 11
tPLH
tPHL
Propagation Delay
LEA to APAR, BPAR
5.0
2.0
8.0
11.5
1.5
16.0
2.0
12.0
ns
10, 11
tPLH
tPHL
Propagation Delay
LEA, LEB to ERRA, ERRB
5.0
2.5
8.0
11.5
1.5
16.0
2.5
12.0
ns
12
tPZH
tPZL
Output Enable Time
GBA or GAB to An, Bn
5.0
2.5
7.0
10.5
1.5
16.0
2.5
11.0
ns
7, 8
tPZH
tPZL
Output Enable Time
GBA or GAB to BPAR or APAR
5.0
1.5
6.0
9.0
1.5
11.0
1.5
9.5
ns
7, 8
tPHZ
tPHL
Output Disable Time
GBA or GAB to An, Bn
5.0
1.5
6.5
9.5
1.5
11.0
1.5
9.5
ns
7, 8
tPHZ
tPLZ
Output Disable Time
GBA or GAB to BPAR, APAR
5.0
1.5
6.5
9.5
1.5
11.0
1.5
9.5
ns
7, 8
*Voltage Range 5.0 is 5.0V g 0.5V.
11
AC Operating Requirements
Symbol
Parameter
VCC*
(V)
74ACT
54ACT
74ACT
TA e a 25§ C
CL e 50 pF
TA e b55§ C
to a 125§ C
CL e 50 pF
TA e b40§ C
to a 85§ C
CL e 50 pF
Units
Fig.
No.
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
An, Bn, PAR to LEA, LEB
5.0
3.0
3.0
3.0
ns
11, 12
th
Hold Time, HIGH or LOW
An, Bn, PAR to LEA, LEB
5.0
1.5
3.0
1.5
ns
11, 12
tw
Pulse Width for LEB, LEA
5.0
4.0
4.0
4.0
ns
13
*Voltage Range 5.0 e 5.0V g 0.5V.
Capacitance
Parameter
Typ
Units
Conditions
CIN
Symbol
Input Capacitance
4.5
pF
VCC e 5.0V
CPD
Power Dissipation
Capacitance
210
pF
VCC e 5.0V
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74ACT
899
Temperature Range Family
74AC e Commercial
74ACT e Commercial TTL-Compatible
54ACT e Military TTL-Compatible
Q
C
X
Special Variations
X e Devices shipped in 13× reels
QB e Military grade with environmental
and burn-in processing shipped
in tubes
Device Type
Temperature Range
C e Commercial (b40§ C to a 85§ C)
M e Military (b55§ C to a 125§ C)
Package Code
Q e Plastic Leaded Chip Carrier (PCC)
12
13
74AC899 # 54ACT/74ACT899
9-Bit Latchable Transceiver with Parity Generator/Checker
Physical Dimensions inches (millimeters)
Lit. Ý 115200
28-Lead Plastic Chip Carrier (Q)
NS Package Number V28A
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