NSC 54ACT534

54ACT/74ACT534
Octal D Flip-Flop with TRI-STATEÉ Outputs
General Description
Features
The ’ACT534 is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and
TRI-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all
flip-flops. The ’ACT534 is the same as the ’ACT374 except
that the outputs are inverted.
Y
Y
Y
Y
Y
Y
Y
ICC and IOZ reduced by 50%
Edge-triggered D-type inputs
Buffered positive edge-triggered clock
TRI-STATE outputs for bus-oriented applications
Outputs source/sink 24 mA
’ACT534 has TTL-compatible inputs
Inverted output version of ’ACT374
Logic Symbols
Connection Diagrams
IEEE/IEC
Pin Assignment
for DIP, Flatpak and SOIC
TL/F/9965–1
TL/F/9965 – 2
TL/F/9965 – 3
Pin Names
D0 – D7
CP
OE
O0 – O7
Description
Pin Assignment
for LCC
Data Inputs
Clock Pulse Input
TRI-STATE Output Enable Input
Complementary TRI-STATE Outputs
TL/F/9965 – 4
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
FACTTM is a trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/F/9965
RRD-B30M75/Printed in U. S. A.
54ACT/74ACT534 Octal D Flip-Flop with TRI-STATE Outputs
March 1993
Functional Description
transition. With the Output Enable (OE) LOW, the contents
of the eight flip-flops are available at the outputs. When the
OE is HIGH, the outputs go to the high impedance state.
Operation of the OE input does not affect the state of the
flip-flops.
The ’ACT534 consists of eight edge-triggered flip-flops with
individual D-type inputs and TRI-STATE complementary
outputs. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold times requirements on the LOW-to-HIGH Clock (CP)
Logic Diagram
TL/F/9965 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Function Table
Inputs
Output
CP
OE
D
O
L
L
L
X
L
L
L
H
H
L
X
X
L
H
O0
Z
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
L e LOW-to-HIGH Clock Transition
Z e High Impedance
O0 e Value stored from previous clock cycle
2
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI e b0.5V
VI e VCC a 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO e b0.5V
VO e VCC a 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
Junction Temperature (TJ)
CDIP
PDIP
Supply Voltage (VCC)
’ACT
Input Voltage (VI)
b 0.5V to a 7.0V
4.5V to 5.5V
0V to VCC
0V to VCC
Output Voltage (VO)
Operating Temperature (TA)
74ACT
54ACT
b 20 mA
a 20 mA
b 0.5V to VCC a 0.5V
b 40§ C to a 85§ C
b 55§ C to a 125§ C
Minimum Input Edge Rate (DV/Dt)
’ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
b 20 mA
a 20 mA
b 0.5V to VCC a 0.5V
125 mV/ns
g 50 mA
g 50 mA
b 65§ C to a 150§ C
175§ C
140§ C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT TM circuits outside databook specifications.
DC Characteristics for ’ACT Family Devices
74ACT
Symbol
Parameter
VCC
(V)
TA e
a 25§ C
54ACT
74ACT
TA e
TA e
Units
b 55§ C to a 125§ C b 40§ C to a 85§ C
Typ
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VOUT e 0.1V
or VCC b 0.1V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOUT e 0.1V
or VCC b 0.1V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
V
3.86
4.86
3.70
4.70
3.76
4.76
V
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
5.5
g 0.1
g 1.0
g 1.0
mA
VI e VCC, GND
VI e VIL, VIH
VO e VCC, GND
4.5
5.5
VOL
Maximum Low Level
Output Voltage
4.5
5.5
IIN
Maximum Input Leakage Current
IOZ
Maximum TRI-STATEÉ
Current
5.5
ICCT
Maximum
ICC/Input
5.5
0.001
0.001
g 0.25
0.6
*All outputs loaded; thresholds on input associated with output under test.
3
g 5.0
g 2.5
mA
1.6
1.5
mA
IOUT e b50 mA
*VIN e VIL or VIH
b 24 mA
IOH
b 24 mA
IOUT e 50 mA
*VIN e VIL or VIH
24 mA
IOL
24 mA
VI e VCC b 2.1V
DC Characteristics for ’ACT Family Devices (Continued)
Symbol
Parameter
VCC
(V)
74ACT
54ACT
74ACT
TA e
a 25§ C
TA e
b 55§ C to a 125§ C
TA e
b 40§ C to a 85§ C
Typ
IOLD
IOHD
ICC
² Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
Units
Conditions
Guaranteed Limits
5.5
50
75
mA
VOLD e 1.65V Max
5.5
b 50
b 75
mA
VOHD e 3.85V Min
80.0
40.0
mA
VIN e VCC
or GND
5.5
4.0
² Maximum test duration 2.0 ms, one output loaded at a time.
Note: ICC for 54ACT
@
25§ C is identical to 74ACT
@
25§ C.
AC Electrical Characteristics
Symbol
Parameter
VCC*
(V)
Min
74ACT
54ACT
74ACT
TA e a 25§ C
CL e 50 pF
TA e b55§ C
to a 125§ C
CL e 50 pF
TA e b40§ C
to a 85§ C
CL e 50 pF
Typ
Max
Min
Max
Min
Units
Max
fmax
Maximum Clock
Frequency
5.0
tPLH
Propagation Delay
CP to Qn
5.0
2.5
6.5
11.5
1.5
14.0
2.0
12.5
ns
tPHL
Propagation Delay
CP to Qn
5.0
2.0
6.0
10.5
1.5
13.0
2.0
12.0
ns
tPZH
Output Enable Time
5.0
2.5
6.5
12.0
1.5
14.0
2.0
12.5
ns
tPZL
Output Enable Time
5.0
2.0
6.0
11.0
1.5
13.0
2.0
11.5
ns
tPHZ
Output Disable Time
5.0
1.5
7.0
12.5
1.5
14.5
1.0
13.5
ns
tPLZ
Output Disable Time
5.0
1.5
5.5
10.5
1.5
11.5
1.0
10.5
ns
100
85
120
MHz
*Voltage Range 5.0 is 5.0V g 0.5V
AC Operating Requirements
Symbol
Parameter
VCC*
(V)
74ACT
54ACT
74ACT
TA e a 25§ C
CL e 50 pF
TA e b55§ C
to a 125§ C
CL e 50 pF
TA e b40§ C
to a 85§ C
CL e 50 pF
Typ
Units
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Dn to CP
5.0
1.0
3.5
5.0
4.0
ns
th
Hold Time, HIGH or LOW
Dn to CP
5.0
b 1.0
1.0
3.0
1.5
ns
tw
CP Pulse Width
HIGH or LOW
5.0
2.0
3.5
5.0
3.5
ns
*Voltage Range 5.0 is 5.0V g 0.5V
4
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
VCC e OPEN
CPD
Power Dissipation
Capacitance
40.0
pF
VCC e 5.0V
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74ACT
534
P
Temperature Range Family
74ACT e Commercial TTL-Compatible
54ACT e Military TTL-Compatible
C
QR
Special Variations
X e Devices shipped in 13× reels
QR e Commercial grade device with
burn-in
QB e Military grade device with
environmental and burn-in
processing shipped in tubes
Device Type
Package Code
P e Plastic DIP
D e Ceramic DIP
F e Flatpak
L e Leadless Ceramic Chip Carrier (LCC)
S e Small Outline (SOIC)
Temperature Range
C e Commercial (b40§ C to a 85§ C)
M e Military (b55§ C to a 125§ C)
Physical Dimensions inches (millimeters)
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
5
Physical Dimensions inches (millimeters) (Continued)
16 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
16 Lead Small Outline Integrated Circuit (S)
NS Package Number M16A
6
Physical Dimensions inches (millimeters) (Continued)
16 Lead Plastic Dual-In-Line Package (P)
NS Package Number N16E
7
54ACT/74ACT534 Octal D Flip-Flop with TRI-STATE Outputs
Physical Dimensions inches (millimeters) (Continued)
16 Lead Ceramic Flatpak (F)
NS Package Number W16A
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