FAIRCHILD 74ABT899CMSA

Revised January 1999
74ABT899
9-Bit Latchable Transceiver
with Parity Generator/Checker
General Description
■ Ability to simultaneously generate and check parity
The ABT899 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through
transceiver or it can generate/check parity from the 8-bit
data busses in either direction.
■ May be used in system applications in place of the
657 and 373 (no need to change T/R to check parity)
The ABT899 features independent latch enables for the Ato-B direction and the B-to-A direction, a select pin for
ODD/EVEN parity, and separate error signal output pins for
checking parity.
■ May be used in systems applications in place of the
543 and 280
■ Guaranteed output skew
■ Guaranteed multiple output switching specifications
■ Output switching specified for both 50 pF and
250 pF loads
Features
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Latchable transceiver with output sink of 64 mA
■ Guaranteed latchup protection
■ Option to select generate parity and check or
“feed-through” data/parity in directions A-to-B or B-to-A
■ High impedance glitch free bus loading during entire
power up and power down cycle
■ Independent latch enables for A-to-B and B-to-A
directions
■ Nondestructive hot insertion capability
■ Select pin for ODD/EVEN parity
■ ERRA and ERRB output pins for parity checking
■ Disable time less than enable time to avoid bus
contention
Ordering Code:
Order Number
74ABT899CSC
74ABT899CMSA
74ABT899CQC
Package Number
Package Description
M28B
28-Lead Small Outline Integrated Circuit (SOIC), MS-013, 0.300” Wide Body
MSA28
28-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignment for
SOIC and SSOP
Pin Assignment
for PLCC
© 1999 Fairchild Semiconductor Corporation
DS011509.prf
www.fairchildsemi.com
74ABT899 9-Bit Latchable Transceiver with Parity Generator/Checker
November 1992
74ABT899
Pin Descriptions
Pin Names
Functional Description
The ABT899 has three principal modes of operation which
are outlined below. These modes apply to both the A-to-B
and B-to-A directions.
Descriptions
A0–A7
A Bus Data Inputs/Data Outputs
B0–B7
B Bus Data Inputs/Data Outputs
APAR, BPAR
A and B Bus Parity Inputs/Outputs
ODD/EVEN
ODD/EVEN Parity Select,
Active LOW for EVEN Parity
GBA, GAB
Output Enables for A or B Bus,
Active LOW
SEL
Select Pin for Feed-Through or
Generate Mode, LOW for Generate
Mode
LEA, LEB
Latch Enables for A and B Latches,
HIGH for Transparent Mode
ERRA, ERRB
Error Signals for Checking Generated
Parity with Parity In, LOW if Error
Occurs
• Bus A (B) communicates to Bus B (A), parity is generated and passed on to the B (A) Bus as BPAR (APAR). If
LEB (LEA) is HIGH and the Mode Select (SEL) is LOW,
the parity generated from B[0:7] (A[0:7]) can be checked
and monitored by ERRB (ERRA).
• Bus A (B) communicates to Bus B (A) in a feed-through
mode if SEL is HIGH. Parity is still generated and
checked as ERRA and ERRB in the feed-through mode
(can be used as an interrupt to signal a data/parity bit
error to the CPU).
• Independent Latch Enables (LEA and LEB) allow other
permutations of generating/checking (see Function
Table below).
Function Table
Inputs
Operation
GAB GBA SEL LEA LEB
H
H
X
X
X
Busses A and B are 3-STATE.
H
L
L
L
H
Generates parity from B[0:7] based on O/E (Note 1). Generated parity → APAR.
Generated parity checked against BPAR and output as ERRB.
H
L
L
H
H
Generates parity from B[0:7] based on O/E. Generated parity → APAR. Generated parity checked against BPAR and output as ERRB. Generated parity also
fed back through the A latch for generate/check as ERRA.
H
L
L
X
L
Generates parity from B latch data based on O/E. Generated parity → APAR.
Generated parity checked against latched BPAR and output as ERRB.
H
L
H
X
H
BPAR/B[0:7] → APAR/A0:7] Feed-through mode. Generated parity checked
against BPAR and output as ERRB.
H
L
H
H
H
BPAR/B[0:7] → APAR/A[0:7]
Feed-through mode. Generated parity checked against BPAR and output as
ERRB. Generated parity also fed back through the A latch for generate/check as
ERRA.
L
H
L
H
L
Generates parity for A[0:7] based on O/E. Generated parity → BPAR. Generated parity checked against APAR and output as ERRA.
L
H
L
H
H
Generates parity from A[0:7] based on O/E. Generated parity → BPAR. Generated parity checked against APAR and output as ERRA. Generated parity also
fed back through the B latch for generate/check as ERRB.
L
H
L
L
X
Generates parity from A latch data based on O/E. Generated parity → BPAR.
Generated parity checked against latched APAR and output as ERRA.
L
H
H
H
L
APAR/A[0:7] → BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and output as
ERRA.
L
H
H
H
H
APAR/A[0:7] → BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and output as
ERRA. Generated parity also fed back through the B latch for generate/check as
ERRB.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Note 1: O/E = ODD/EVEN
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2
74ABT899
Functional Block Diagram
3
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74ABT899
Absolute Maximum Ratings(Note 2)
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
−55°C to +125°C
Over Voltage Latchup (I/O)
10V
Recommended Operating
Conditions
Junction Temperature under Bias
−55°C to +150°C
Plastic
−500 mA
DC Latchup Source Current
−40°C to +85°C
Free Air Ambient Temperature
VCC Pin Potential to
+4.5V to +5.5V
−0.5V to +7.0V
Supply Voltage
Input Voltage (Note 3)
−0.5V to +7.0V
Minimum Input Edge Rate (∆V/∆t)
Input Current (Note 3)
−30 mA to +5.0 mA
Ground Pin
Voltage Applied to Any Output
−0.5V to +5.5V
−0.5V to VCC
in the HIGH State
50 mV/ns
Enable Input
20 mV/ns
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
in the Disable or PowerOff State
Data Input
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
VCC
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
−1.2
V
Min
IIN = −18 mA (Non I/O Pins)
V
Min
IOH = −3 mA, (An, B n, APAR, BPAR)
V
Min
IOL = 64 mA, (An, Bn, APAR, BPAR)
V
0.0
IID = 1.9 µA, (Non-I/O Pins)
µA
Max
Output HIGH
2.5
Voltage
2.0
VOL
Output LOW Voltage
VID
Input Leakage Test
IIH
Input HIGH Current
V
Conditions
Input HIGH Voltage
VOH
2.0
Units
VIH
Recognized HIGH Signal
Recognized LOW Signal
IOH = −32 mA, (An, Bn, APAR, BPAR)
0.55
4.75
All Other Pins Grounded
5
VIN = 2.7V (Non-I/O Pins) (Note 4)
VIN = VCC (Non-I/O Pins)
IBVI
Input HIGH Current
7
µA
Max
VIN = 7.0V (Non-I/O Pins)
100
µA
Max
VIN = 5.5V (An, Bn, APAR, BPAR)
−5
µA
Max
Breakdown Test
IBVIT
Input HIGH Current
Breakdown Test (I/O)
IIL
Input LOW Current
VIN = 0.5V (Non-I/O Pins) (Note 4)
VIN = 0.0V (Non-I/O Pins)
IIH + IOZH Output Leakage Current
50
µA
0V–5.5V VOUT = 2.7V (An, Bn);
IIL + IOZL
Output Leakage Current
−50
µA
0V–5.5V VOUT = 0.5V (An, Bn);
IOS
Output Short-Circuit Current
−275
mA
Max
ICEX
Output HIGH Leakage Current
50
µA
Max
VOUT = VCC (An, Bn, APAR, BPAR)
IZZ
Bus Drainage Test
100
µA
0.0V
VOUT = 5.5V (An, Bn, APAR, BPAR);
ICCH
Power Supply Current
250
µA
Max
All Outputs HIGH
ICCL
Power Supply Current
34
mA
Max
All Outputs LOW, ERRA/B = HIGH (Note 5)
ICCZ
Power Supply Current
250
µA
Max
Outputs 3-STATE All Others at VCC or GND
ICCT
Additional ICC/Input
2.5
mA
Max
VI = VCC − 2.1V All Others at VCC or GND
ICCD
Dynamic ICC:
0.4
mA/MHz
Max
Outputs Open
GAB and GBA = 2.0V
GAB and GBA = 2.0V
−100
VOUT = 0V (An, B n, APAR, BPAR)
All Others GND
No Load
GAB or GBA = GND, LE = HIGH
(Note 4)
Non-I/O = GND or VCC
One bit toggling, 50% duty cycle
Note 4: Guaranteed, but not tested.
Note 5: Add 3.75 mA for each ERR LOW.
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4
(PLCC package)
Symbol
Parameter
Min
Typ
Max
Units
VCC
0.8
1.1
Conditions
CL = 50 pF, RL = 500Ω
VOLP
Quiet Output Maximum Dynamic VOL
V
5.0
TA = 25°C (Note 6)
VOLV
Quiet Output Minimum Dynamic VOL
−1.3
−0.8
V
5.0
TA = 25°C (Note 6)
VOHV
Minimum HIGH Level Dynamic Output Voltage
2.5
3.0
V
5.0
TA = 25°C (Note 8)
VIHD
Minimum HIGH Level Dynamic Input Voltage
2.2
1.8
V
5.0
TA = 25°C (Note 7)
VILD
Maximum LOW Level Dynamic Input Voltage
V
5.0
TA = 25°C (Note 7)
0.8
0.5
Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 7: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD).
Guaranteed, but not tested.
Note 8: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and PLCC Package)
Symbol
Parameter
TA = +25°C
TA = −40°C to +85°C
VCC = +5.0V
VCC = 4.5V–5.5V
CL = 50 pF
CL = 50 pF
Min
Typ
Max
Min
Max
tPLH
Propagation Delay
1.5
3.0
4.8
1.5
4.8
tPHL
An, to Bn
1.5
3.5
4.8
1.5
4.8
tPLH
Propagation Delay
2.5
5.9
9.2
2.5
9.2
tPHL
An, Bn to BPAR, APAR
2.5
5.8
9.2
2.5
9.2
Units
ns
ns
tPLH
Propagation Delay
2.5
5.4
8.5
2.5
8.5
tPHL
An, Bn to ERRA, ERRB
2.5
5.4
8.5
2.5
8.5
ns
tPLH
Propagation Delay
1.5
3.7
6.0
1.5
6.0
tPHL
APAR, BPAR to ERRA, ERRB
1.5
3.7
6.0
1.5
6.0
tPLH
Propagation Delay
2.0
4.4
6.9
2.0
6.9
tPHL
ODD/EVEN to APAR, BPAR
2.0
4.4
6.9
2.0
6.9
tPLH
Propagation Delay
1.8
4.0
6.0
1.8
6.0
tPHL
ODD/EVEN to ERRA, ERRB
1.8
4.0
6.0
1.8
6.0
tPLH
Propagation Delay
1.5
3.8
6.0
1.5
6.0
tPHL
SEL to APAR, BPAR
1.5
3.8
6.0
1.5
6.0
tPLH
Propagation Delay
1.5
3.2
4.6
1.5
4.6
tPHL
LEA, LEB to Bn, An
1.5
3.2
4.6
1.5
4.6
tPLH
Propagation Delay
2.5
5.9
8.8
2.5
8.8
tPHL
LEA, LEB to BPAR, APAR
2.5
5.7
8.8
2.5
8.8
ns
ns
ns
ns
ns
ns
ns
Generate Mode
tPLH
Propagation Delay
1.5
3.6
5.1
1.5
5.1
tPHL
LEA, LEB to BPAR, APAR,
1.5
3.6
5.1
1.5
5.1
Feed Thru Mode
tPLH
Propagation Delay
1.6
5.4
8.4
1.6
8.4
tPHL
LEA, LEB to ERRA, ERRB
1.6
5.4
8.4
1.6
8.4
tPZH
Output Enable Time
1.5
3.6
6.0
1.5
6.0
tPZL
GBA or GAB to An,
1.5
3.4
6.0
1.5
6.0
tPHZ
Output Disable Time
1.0
4.0
6.0
1.0
6.0
tPLZ
GBA or GAB to An,
1.0
3.3
6.0
1.0
6.0
tPLHtPHL
Propagation Delay
1.5
3.3
5.4
1.5
5.4
APAR to BPAR, BPAR to APAR
1.5
3.8
5.4
1.5
5.4
ns
ns
APAR or Bn, BPAR
ns
APAR or Bn, BPAR
5
ns
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74ABT899
DC Electrical Characteristics
74ABT899
AC Electrical Characteristics
(SSOP Package)
Symbol
Parameter
TA = +25°C
TA = −40°C to +85°C
VCC = +5.0V
VCC = 4.5V–5.5V
CL = 50 pF
CL = 50 pF
Min
Typ
Max
Min
Max
tPLH
Propagation Delay
1.5
3.0
5.3
1.5
5.3
tPHL
An, to Bn
1.5
3.5
5.3
1.5
5.3
tPLH
Propagation Delay
2.5
5.9
9.9
2.5
9.9
tPHL
An, Bn to BPAR, APAR
2.5
5.8
9.9
2.5
9.9
tPLH
Propagation Delay
2.5
5.4
9.4
2.5
9.4
tPHL
An, Bn to ERRA, ERRB
2.5
5.4
9.4
2.5
9.4
tPLH
Propagation Delay
1.5
3.7
6.5
1.5
6.5
tPHL
APAR, BPAR to ERRA, ERRB
1.5
3.7
6.5
1.5
6.5
tPLH
Propagation Delay
2.0
4.4
7.4
2.0
7.4
tPHL
ODD/EVEN to APAR, BPAR
2.0
4.4
7.4
2.0
7.4
tPLH
Propagation Delay
1.8
4.0
6.5
1.8
6.5
tPHL
ODD/EVEN to ERRA, ERRB
1.8
4.0
6.5
1.8
6.5
Units
ns
ns
ns
ns
ns
ns
tPLH
Propagation Delay
1.5
3.8
6.5
1.5
6.5
tPHL
SEL to APAR, BPAR
1.5
3.8
6.5
1.5
6.5
ns
tPLH
Propagation Delay
1.5
3.2
5.1
1.5
5.1
tPHL
LEA, LEB to Bn, An
1.5
3.2
5.1
1.5
5.1
tPLH
Propagation Delay
2.5
5.9
9.2
2.5
9.2
tPHL
LEA, LEB to BPAR, APAR
2.5
5.7
9.2
2.5
9.2
ns
ns
ns
Generate Mode
tPLH
Propagation Delay
1.5
3.6
5.6
1.5
5.6
tPHL
LEA, LEB to BPAR, APAR,
1.5
3.6
5.6
1.5
5.6
Feed Thru Mode
tPLH
Propagation Delay
1.6
5.4
8.9
1.6
8.9
tPHL
LEA, LEB to ERRA, ERRB
1.6
5.4
8.9
1.6
8.9
tPZH
Output Enable Time
1.5
3.6
6.5
1.5
6.5
tPZL
GBA or GAB to An,
1.5
3.4
6.5
1.5
6.5
ns
ns
APAR or Bn, BPAR
tPHZ
Output Disable Time
1.0
4.0
6.5
1.0
6.5
tPLZ
GBA or GAB to An,
1.0
3.3
6.5
1.0
6.5
ns
APAR or Bn, BPAR
tPLH
Propagation Delay
1.5
3.3
5.9
1.5
5.9
tPHL
APAR to BPAR, BPAR to APAR
1.5
3.8
5.9
1.5
5.9
ns
AC Operating Requirements
Symbol
Parameter
TA = +25°C
TA = −40°C to +85°C
VCC = +5.0V
VCC = 4.5V–5.5V
CL = 50 pF
CL = 50 pF
Min
Max
Min
tS(H)
Setup Time, HIGH or LOW An,
1.5
1.5
tS(L)
APAR to LEA or Bn, BPAR to LEB
1.5
1.5
tH(H)
Hold Time, HIGH or LOW An,
1.0
1.0
tH(L)
APAR to LEA or Bn, BPAR to LEB
1.0
1.0
tW(H)
Pulse Width, HIGH
3.0
3.0
LEA or LEB
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6
Units
Max
ns
ns
ns
74ABT899
Extended AC Electrical Characteristics
(SOIC and PLCC Package)
TA = +25°C
Symbol
Parameter
TA = −40°C to +85°C TA = −40°C to +85°C
VCC = +5.0V
VCC = 4.5V–5.5V
VCC = 4.5V–5.5V
CL = 50 pF
CL = 250 pF
CL = 250 pF
9 Outputs Switching
(Note 9)
Min
fTOGGLE
Max Toggle Frequency
tPLH
Propagation Delay
Typ
(Note 10)
(Note 11)
Max
Min
Max
Min
Max
6.2
2.0
7.2
2.5
9.5
100
1.5
Units
1 Output Switching 9 Outputs Switching
MHz
tPHL
An to Bn
1.5
6.2
2.0
7.2
2.5
9.5
tPLH
Propagation Delay
1.5
6.8
2.0
8.0
2.5
10.0
tPHL
APAR to BPAR
1.5
6.8
2.0
8.0
2.0
10.0
tPLH
Propagation Delay
2.5
10.0
3.0
12.5
3.5
13.5
tPHL
An, Bn to BPAR, APAR
2.5
10.0
3.0
12.5
3.5
13.5
tPLH
Propagation Delay
3.0
12.0
tPHL
An, Bn to ERRA, ERRB
3.0
12.0
tPLH
Propagation Delay
2.0
9.0
tPHL
APAR, BPAR to ERRA, ERRB
2.0
9.0
tPLH
Propagation Delay
2.5
9.9
tPHL
ODD/EVEN to APAR, BPAR
2.5
9.9
tPLH
Propagation Delay
2.0
8.8
tPHL
ODD/EVEN to ERRA, ERRB
2.0
8.8
tPLH
Propagation Delay
tPHL
SEL to APAR, BPAR
tPLH
Propagation Delay
1.5
tPHL
LEA, LEB to Bn, An
1.5
tPLH
Propagation Delay
tPHL
LEA, LEB to BPAR, APAR
tPLH
Propagation Delay
tPHL
LEA, LEB to ERRA, ERRB
tPZH
Output enable time
1.5
7.0
2.0
8.5
2.5
10.5
tPZL
GBA or GAB to An,
1.5
7.0
2.0
8.5
2.5
10.5
(Note 13)
(Note 13)
(Note 13)
(Note 13)
(Note 13)
ns
(Note 13)
ns
(Note 13)
ns
(Note 13)
ns
(Note 13)
ns
(Note 13)
ns
2.0
9.5
2.0
9.5
5.7
2.0
7.9
2.5
10.0
5.7
2.0
7.9
2.5
10.0
1.5
9.5
2.0
12.0
2.5
13.0
1.5
9.5
2.0
12.0
2.5
13.0
2.0
11.5
2.0
11.5
(Note 13)
ns
ns
(Note 13)
ns
ns
ns
ns
APAR or Bn, BPAR
tPHZ
Output disable time
1.0
6.5
tPLZ
GBA or GAB to An,
1.0
6.5
(Note 12)
(Note 12)
ns
APAR or Bn, BPAR
Note 9: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.).
Note 10: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only.
Note 11: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load
Note 12: The 3-STATE delay time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet.
Note 13: Not applicable for multiple output switching.
7
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74ABT899
Extended AC Electrical Characteristics
(SSOP Package)
TA = +25°C
Symbol
Parameter
TA = −40°C to +85°C TA = −40°C to +85°C
VCC = +5.0V
VCC = 4.5V–5.5V
VCC = 4.5V–5.5V
CL = 50 pF
CL = 250 pF
CL = 250 pF
9 Outputs Switching
(Note 14)
Min
fTOGGLE
Max Toggle Frequency
tPLH
Propagation Delay
Typ
(Note 15)
(Note 16)
Max
Min
Max
Min
Max
6.7
2.0
7.7
2.5
10.1
100
1.5
Units
1 Output Switching 9 Outputs Switching
MHz
tPHL
An to Bn
1.5
6.7
2.0
7.7
2.5
10.1
tPLH
Propagation Delay
1.5
7.3
2.0
8.5
2.5
10.6
tPHL
APAR to BPAR
1.5
7.3
2.0
8.5
2.0
10.6
tPLH
Propagation Delay
2.5
10.7
3.0
13.2
3.5
14.3
tPHL
An, Bn to BPAR, APAR
2.5
10.7
3.0
13.2
3.5
14.3
tPLH
Propagation Delay
tPHL
An, Bn to ERRA, ERRB
tPLH
Propagation Delay
tPHL
APAR, BPAR to ERRA, ERRB
tPLH
Propagation Delay
tPHL
ODD/EVEN to APAR, BPAR
tPLH
Propagation Delay
tPHL
ODD/EVEN to ERRA, ERRB
tPLH
Propagation Delay
tPHL
SEL to APAR, BPAR
tPLH
Propagation Delay
1.5
tPHL
LEA, LEB to Bn, An
1.5
tPLH
Propagation Delay
tPHL
LEA, LEB to BPAR, APAR
tPLH
Propagation Delay
tPHL
LEA, LEB to ERRA, ERRB
tPZH
Output enable time
1.5
7.5
2.0
9.0
2.5
11.1
tPZL
GBA or GAB to An,
1.5
7.5
2.0
9.0
2.5
11.1
(Note 18)
(Note 18)
(Note 18)
(Note 18)
(Note 18)
3.0
12.9
3.0
12.9
2.0
9.5
2.0
9.5
2.5
10.4
2.5
10.4
2.0
9.3
2.0
9.3
ns
(Note 18)
ns
(Note 18)
ns
(Note 18)
ns
(Note 18)
ns
2.0
10.0
10.0
6.2
2.0
8.4
2.5
10.6
6.2
2.0
8.4
2.5
10.6
1.5
10.0
2.0
12.5
2.5
13.6
1.5
10.0
2.0
12.5
2.5
13.6
2.0
12.0
2.0
12.0
ns
(Note 18)
2.0
(Note 18)
ns
ns
(Note 18)
ns
ns
ns
ns
APAR or Bn, BPAR
tPHZ
Output disable time
1.0
7.0
tPLZ
GBA or GAB to An,
1.0
7.0
(Note 17)
(Note 17)
ns
APAR or Bn, BPAR
Note 14: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.).
Note 15: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only.
Note 16: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load
Note 17: The 3-STATE delay time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet.
Note 18: Not applicable for multiple output switching.
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8
74ABT899
Skew
(PLCC package) (Note 2)
Symbol
TA = −40°C to +85°C
TA = −40°C to +85°C
VCC = 4.5V–5.5V
VCC = 4.5V–5.5V
CL = 50 pF
CL = 250 pF
9 Outputs Switching
9 Outputs Switching
(Note 19)
(Note 20)
Max
Max
1.0
2.0
ns
1.1
2.1
ns
2.0
3.5
ns
2.0
3.5
ns
3.0
4.0
ns
Parameter
tOSHL
Pin to Pin Skew
(Note 21)
HL Transitions
tOSLH
Pin to Pin Skew
(Note 21)
LH Transitions
tPS
Duty Cycle
(Note 22)
LH–HL Skew
tOST
Pin to Pin Skew
(Note 21)
LH/HL Transitions
tPV
Device to Device Skew
(Note 23)
LH/HL Transitions
Units
Note 19: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-toHIGH, HIGH-to-LOW, etc.).
Note 20: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 21: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH to LOW (tOSHL), LOW to HIGH (t OSLH), or any combination switching LOW to HIGH and/or HIGH to
LOW (tOST). This specification is guaranteed but not tested. Skew applies to propagation delays individually; i.e., An to Bn separate from LEA to An.
Note 22: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 23: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not
tested.
Capacitance
Symbol
Parameter
Typ
Units
Conditions
TA = 25°C
CIN
Input Pin Capacitance
5.0
pF
VCC = 0V
CI/O (Note 24)
Output Capacitance
11.0
pF
VCC = 5.0V
Note 24: CI/O is measured at frequency, f = 1 MHz, per MIL-STD-883B, Method 3012.
9
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74ABT899
AC Path
An, APAR → Bn, BPAR
(Bn, BPAR → An, APAR)
FIGURE 1.
An → BPAR
(Bn → APAR)
FIGURE 2.
An → ERRA
(Bn → ERRB)
FIGURE 3.
O/E → ERRA
O/E → ERRB
FIGURE 4.
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10
74ABT899
AC Path
(Continued)
O/E → BPAR
(O/E → APAR)
FIGURE 5.
APAR → ERRA
(BPAR → ERRB)
FIGURE 6.
FIGURE 7.
ZH, HZ
FIGURE 8.
11
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74ABT899
AC Path
(Continued)
ZL, LZ
FIGURE 9.
SEL → BPAR
(SEL → APAR)
FIGURE 10.
LEA → BPAR, B[0:7]
(LEB → APAR, A[0:7])
FIGURE 11.
TS(H), TH(H)
LEA → APAR, A[0:7]
(LEB → BPAR, B[0:7])
FIGURE 12.
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12
74ABT899
AC Path
(Continued)
TS(L), TH(L)
LEA → APAR, A[0:7]
(LEB → BPAR, B[0:7])
FIGURE 13.
FIGURE 14.
13
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74ABT899
AC Loading
*Includes jig and probe capacitance
VM = 1.5V
FIGURE 15. Standard AC Test Load
FIGURE 16.
Input Pulse Requirements
Amplitude
Rep. Rate
tW
tr
tf
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 17. Test Input Signal Requirements
AC Waveforms
FIGURE 18. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 20. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 19. Propagation Delay,
Pulse Width Waveforms
FIGURE 21. Setup Time, Hold Time
and Recovery Time Waveforms
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14
74ABT899
Physical Dimensions inches (millimeters) unless otherwise noted
28-Lead Small Outline Integrated Circuit (SOIC), MS-013, 0.300” Wide Body
Package Number M28B
28-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA28
15
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74ABT899 9-Bit Latchable Transceiver with Parity Generator/Checker
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450” Square
Package Number V28A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or systems
device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
body, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.