ETC 24267A

AMD PowerNow!™
Technology
Platform Design
Guide for
Embedded
Processors
Application Note
Publication # 24267
Issue Date: December 2000
Rev: A
Amendment/0
© 2000 Advanced Micro Devices, Inc. All rights reserved.
The contents of this document are provided in connection with Advanced Micro
Devices, Inc. (“AMD”) products. AMD makes no representations or warranties
with respect to the accuracy or completeness of the contents of this publication
and reserves the right to make changes to specifications and product descriptions
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Trademarks
AMD, the AMD logo, and combinations thereof, AMD-K6, 3DNow!, and AMD PowerNow! are trademarks, and
FusionE86 is a service mark of Advanced Micro Devices, Inc.
Microsoft, Windows, and Windows NT are registered trademarks of Microsoft Corporation.
Other product names used in this publication are for identification purposes only and may be trademarks of their
respective companies.
Preliminary Information
24267A/0—December 2000
Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
AMD PowerNow!™ Technology Initiative . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Overview of this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Enhanced Power Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Enhanced Power Management Register (EPMR) . . . . . . . . . . . . . . . . 3
EPM 16-Byte I/O Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Dynamic Core Frequency and Core Voltage Control . . . . . . . . . . . . . . . . . . . 7
Effective Bus Divisors EBF[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
BF[2:0] Strapping Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Dynamic Core Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Voltage Identification (VID) Outputs . . . . . . . . . . . . . . . . . . . . . . . . . 12
Guaranteed CPU Core Voltage at Power On . . . . . . . . . . . . . . . . . . . 14
Dynamic Core Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
AMD PowerNow! Technology Initialization . . . . . . . . . . . . . . . . . . . . 16
Hardware Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Safe Voltage and Frequency Combination at Reset . . . . . . . . . . . . . 20
Voltage Versus Frequency Options. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
VID[4:0] Modification for Maximum BF[2:0] Boot Option . . . . . . . . 24
Gating PGOOD During a Voltage Transition . . . . . . . . . . . . . . . . . . . 26
Software Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Using an RTOS Enabled for AMD PowerNow!™ Technology . . . . . 28
Using an SMM Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Using a Microsoft® Windows® Driver Supporting
AMD PowerNow! Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Using a BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AMD PowerNow!™ Technology Descriptor Table. . . . . . . . . . . . . . . 30
Event Sequence for AMD PowerNow!™ Technology
State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Pinout Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Documentation and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Appendix A—Frequently Asked Questions . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Contents
iii
24267A/0—December 2000
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
iv
Enhanced Power Management Register (EPMR) . . . . . . . . . . . . 4
EPM 16-Byte I/O Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Bus Divisor and Voltage ID Control (BVC) Field . . . . . . . . . . . 11
Example Hardware Implementation . . . . . . . . . . . . . . . . . . . . . 19
VID[4:0] Modification for Maximum Frequency
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Gating the PGOOD Signal with Maximum Frequency
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
List of Figures
Preliminary Information
24267A/0—December 2000
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
List of Tables
Basic Set of AMD PowerNow!™ Technology
Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Enhanced Power Management Register (EPMR) Definition . . 4
EPM 16-Byte I/O Block Definition . . . . . . . . . . . . . . . . . . . . . . . . 6
Processor-to-Bus Clock Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus Divisor and Voltage ID Control (BVC) Definition . . . . . . . 11
VID [4:0] Input-to-Output Voltage Codes (Typical for
DC/DC Regulators). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Regulator Solution Using a Subset of CPU VID Outputs . . . . 13
Alternative Components for AMD PowerNow!™ Technology
Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Supported Voltages and Operating Frequencies for Low-Power
AMD-K6™-2E+ Processors Enabled with
AMD PowerNow!™ Technology . . . . . . . . . . . . . . . . . . . . . . . . . 23
Supported Voltages and Operating Frequencies for Low-Power
AMD-K6™-IIIE+ Processors Enabled with
AMD PowerNow!™ Technology . . . . . . . . . . . . . . . . . . . . . . . . . 23
AMD PowerNow!™ Technology Descriptor Table . . . . . . . . . . 31
Pins Added for AMD PowerNow!™ Technology . . . . . . . . . . . . 33
CPGA Pin Designations by Functional Grouping . . . . . . . . . . . 34
CPGA Pin Designations for No Connect, Reserved,
Power, and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
OBGA Pin Designations by Functional Grouping . . . . . . . . . . . 36
OBGA Pin Designations for No Connect, Reserved,
Power, and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
v
Preliminary Information
24267A/0—December 2000
Revision History
Date
Rev
December 2000
A
vi
Description
Initial public release.
Revision History
Preliminary Information
24267A/0—December 2000
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
Application Note
AMD PowerNow!™
Technology
Platform Design Guide
for Embedded Processors
AMD PowerNow!™ Technology Initiative
AMD’s latest power-saving initiative, AMD PowerNow!™
technology, enables embedded system designers to offer
superior performance.
AMD PowerNow! technology uses combinations of CPU core
voltage and frequency (AMD PowerNow! technology states) to
enable maximum performance in any thermal environment,
while providing the embedded system designer with the ability
to finely tune performance dependent upon the specific
demands of the application.
Table 1 on page 2 shows the basic set of AMD PowerNow!
t e ch n o l o gy o p e ra t i o n a l m o d e s o r s t a t e s . H o w e ve r,
AMD PowerNow! technology is not restricted to the operation
modes listed.
Additionally, AMD PowerNow! technology can be used in
conjunction with existing power management schemes, such as
Advanced Configuration and Power Interface (ACPI). This
a l l ow s A M D Pow e r N ow ! t e ch n o l o gy t o o p t i m i z e t h e
performance and power savings of a device.
AMD PowerNow!™ Technology Initiative
1
Preliminary Information
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
Table 1.
24267A/0—December 2000
Basic Set of AMD PowerNow!™ Technology Operational Modes
Operational Mode
Description
Application Power
High-Performance
Operation at peak frequency and voltage, maximizing performance
within thermal constraints
< 12 W
Automatic
Core voltage and frequency are scaled to exactly meet application
demand and conserve power usage
3–11 W
Power-Saver
Operation at lowest supported frequency and voltage to maximize power
efficiency
<3W
Overview of this Document
This document identifies and describes the key components of
AMD PowerNow! technology as they apply to embedded system
designers desiring to incorporate AMD PowerNow! technology
features. Unless otherwise noted, the terms CPU or processor
refer to the AMD-K6™-2E+ and/or the AMD-K6™-IIIE+
processor built in 0.18-micron process technology.
Specifically, this document addresses the following:
Identification of the Enhanced Power Management (EPM)
features designed in the 0.18-micron AMD-K6-2E+ and the
AMD-K6-IIIE+ processors for supporting AMD PowerNow!
technology.
■
Description of how the EPM features can be incorporated to
create embedded platforms enabled with AMD PowerNow!
technology.
■
Description of design considerations including new
processor pinouts, voltage regulator recommendations, and
other implementation options specific to designing with
AMD PowerNow! technology.
Note: The information presented in this document is preliminary
and subject to change.
■
2
AMD PowerNow!™ Technology Initiative
Preliminary Information
24267A/0—December 2000
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
Enhanced Power Management Features
AMD-K6-2E+ and AMD-K6-IIIE+ low-power processors enabled
with AMD PowerNow! technology include two new features
sp e c if i c a lly d es ig n ed t o e n h a n c e p owe r m a n a g e m e n t
functionality:
■
■
Dynamic core frequency control
Core voltage control
These enhanced power management (EPM) features are
accessed and controlled through an aligned 16-byte block of I/O
address space that is defined by a model-specific register
(MSR) called the Enhanced Power Management Register
(EPMR).
Enhanced Power Management Register (EPMR)
The EPMR register allows software to access the aligned EPM
16-byte block of I/O address space, which contains bits for
enabling, controlling, and monitoring the EPM features. All
accesses to the EPM 16-byte I/O block must be aligned dword
accesses. Valid accesses to the EPM 16-byte block do not
generate I/O cycles on the host bus, keeping EPMR accesses
local to the CPU, while non-aligned and non-dword accesses are
passed to the host bus.
Figure 1 on page 4 and Table 2 define the EPMR register. The
EPMR can be addressed at MSR location C000_0086h.
An assertion of RESET clears all of the bits of the 16-byte I/O
block to 0 (excluding the Voltage ID Output bits which default
to 01010b). BIOS or the real-time operating system (RTOS)
must always initialize the EPMR register and EPM features
after the processor comes out of RESET.
Enhanced Power Management Features
3
Preliminary Information
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
63
24267A/0—December 2000
4 3 2 1 0
16 15
IOBASE
G
S E
B N
C
Reserved
Symbol
IOBASE
GSBC
EN
Description
I/O Base Address
Generate Special Bus Cycle
Enable AMD PowerNow! Technology
Management
Bit
5-4
1
0
Figure 1. Enhanced Power Management Register (EPMR)
Table 2.
Bit
63–16
Enhanced Power Management Register (EPMR) Definition
Description
Reserved
15-4
I/O BASE Address (IOBASE)
3-2
Reserved
1
Generate Special Bus Cycle (GSBC)
0
Enable AMD PowerNow! Technology
Management (EN)
R/W Function1
R
R/W
R
All reserved bits are always read as 0.
IOBASE defines a base address for a 16-byte block of I/O address
space accessible for enabling, controlling, and monitoring the EPM
features.
All reserved bits are always read as 0.
R/W
This bit controls whether a special bus cycle is generated upon
dword accesses within the EPM 16-byte I/O block. If set to 1, an
EPM special bus cycle is generated, where BE[7:0]# = BFh and
A[4:3] = 00b.
R/W
This bit controls access to the I/O-mapped address space for the
AMD PowerNow! technology EPM features. Clearing this bit to
zero does not affect the state of bits defined in the EPM 16-byte I/O
block.
Notes:
1. All bits default to 0 when RESET is asserted.
4
Enhanced Power Management Features
Preliminary Information
24267A/0—December 2000
IOBASE Field
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
The EPM 16-byte I/O block is located at the I/O address
specified by the IOBASE field and is initialized during poweron self test (POST) by the BIOS or RTOS. The EPM 16-byte I/O
block is then used to access the EPM features.
The EPM features are hidden from all application software and
need only be accessible by an RTOS or an SMM handler for
Microsoft® operating systems. Therefore, the BIOS does not
need to report the I/O range to the operating system.
GSBC Bit
If the GSBC bit is enabled (set to 1), a special bus cycle is
generated once a dword access is made within the EPM 16-byte
I/O block. The EPM special bus cycle is defined by the processor
driving D/C# low, M/IO# low, W/R# high, BE[7:0]# to BFh and
A[31:3] to 0000h. The system logic must return BRDY# in
response to all processor special cycles.
EN Bit
The Enable AMD PowerNow! Technology Management (EN) bit
should only be enabled (set to 1) by the RTOS, BIOS, or SMM
handler when attempting to access the EPM features.
Upon exiting, the EN bit should be disabled to protect the EPM
16-byte I/O block from spurious activity. When the EN bit is
disabled, accesses to the EPM block 16-byte I/O block are
passed to the host bus.
Enhanced Power Management Features
5
Preliminary Information
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
EPM 16-Byte I/O Block
The EPM 16-byte I/O block contains a single 4-byte field for
enabling, controlling, and monitoring the EPM features. This
Bus Divisor and Voltage ID Control (BVC) field (see Figure 2,
“Dynamic Core Frequency Control” on page 10, and Figure 3 on
page 11) is the control center for supported state transitions.
Table 3 defines the functions supported by each of the bytefields within the EPM 16-byte I/O block.
8
12 11
15
7
0
BVC
Reserved
Symbol Description
BVC
Bus Divisor and Voltage ID Control
Bytes
11-8
Figure 2. EPM 16-Byte I/O Block
Table 3.
EPM 16-Byte I/O Block Definition
Byte
Description
15-12
Reserved
11-8
Bus Divisor and Voltage ID Control (BVC)
7-0
Reserved
R/W Function1
R
R/W
R
All reserved bits are always read as 0.
The bit fields within the BVC bytes allow software to change the
processor bus divisor and core voltage. See “Dynamic Core Frequency Control” on page 10 and Figure 3 on page 11 for detailed
information about this field.
All reserved bits are always read as 0.
Notes:
1. All bits default to 0 when RESET is asserted
6
Enhanced Power Management Features
Preliminary Information
24267A/0—December 2000
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
Dynamic Core Frequency and Core Voltage Control
AMD-K6-2E+ and AMD-K6-IIIE+ processors enabled with
AMD PowerNow! technology support the ability to change the
bus frequency divisor and core voltage seamlessly during run
time. These features are implemented in conjunction with a
new clock control state—the EPM Stop Grant state.
To invoke an AMD PowerNow! technology state transition, the
desired settings for core voltage and processor frequency are
written to the Voltage ID Output (VIDO) and Internal BF
Divisor (IBF) fields of the BVC field. The EPM Stop Grant state
and state transition then occur automatically by writing a 1 to
the Generate Special Bus Cycle (GSBC) bit in the EPMR and a
non-zero value to the Stop Grant Time-out Counter (SGTC)
field.
For Microsoft operating systems, the EPMR register should be
accessed using an SMM handler. In these environments, the
SMM handler can initiate a special bus cycle for core voltage
and frequency transitions by writing a 1 to the GSBC field in the
EPMR and a non-zero value to the SGTC.
■
■
This action enables the processor to enter the EPM Stop
Grant State and transitions the CPU core voltage and
frequency to the values specified in the VIDO and IIBF
fields of the BVC field.
Once the SGTC period has expired, the EPM Stop Grant
state is exited and the AMD PowerNow! technology state
transition is completed.
Dynamic Core Frequency and Core Voltage Control
7
Preliminary Information
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Effective Bus Divisors EBF[2:0]
The processor core frequency is controlled by the Effective Bus
Frequency Divisor—EBF[2:0]—which dictates the processor-tobus clock ratio supplied to the processor’s internal PLL. This
processor-to-bus clock ratio is multiplied by the external bus
frequency to set the frequency of operation for the processor
core.
■
■
At the fall of RESET, the EBF[2:0] value is determined by
the state of the processor BF[2:0] input pins.
Afterwards, the EBF[2:0] value can be dynamically
controlled through AMD PowerNow! technology state
transitions.
Table 4 lists valid EBF[2:0] states and equivalent processor- tobus clock ratios.
Table 4.
Processor-to-Bus Clock Ratios
State of EBF[2:0]
Processor-to-Bus Clock Ratio
100b
2.0x1
101b
3.0x
110b
6.0x
111b
3.5x
000b
4.5x
001b
5.0x
010b
4.0x
011b
5.5x
Notes:
1. The 0.18-micron processors do not support the 2.5x ratio supported by earlier processors.
Instead, a ratio of 2.0x is selected when EBF[2:0] equals 100b
8
Dynamic Core Frequency and Core Voltage Control
Preliminary Information
24267A/0—December 2000
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
BF[2:0] Strapping Considerations
Systems that do not use the AMD PowerNow! technology
dynamic core frequency control mechanism should strap the
BF[2:0] inputs of the CPU (with pull-up/pull-down resistors) to
select the desired CPU operating frequency at power up.
Systems that use AMD PowerNow! technology dynamic core
frequency control mechanisms have two primary strapping
options for the BF[2:0] inputs:
Selecting Maximum
CPU Core Frequency
■
Strap the BF[2:0] inputs to select the maximum CPU core
frequency at power up (recommended)
■
Strap the BF[2:0] inputs to select the minimum CPU core
frequency at power up
Systems can strap the BF[2:0] inputs to allow the processor to
boot at its maximum rated frequency when RESET is asserted.
BIOS can then determine the maximum frequency of the
processor by reading the PSOR model-specific register, which
stores the state of the EBF[2:0] bits. For more information on
the PSOR register, see the Embedded AMD-K6™ Processors BIOS
Design Guide Application Note, order# 23913.
See “Safe Voltage and Frequency Combination at Reset” on
page 20 for the advantages and disadvantages of booting at
maximum core frequency.
Selecting Minimum
CPU Core Frequency
Systems that strap the processor BF[2:0] inputs to 100b allow
the processor to boot with a core frequency of 2.0x the
processor bus frequency when RESET is asserted. If a different
CPU core frequency is desired prior to loading the OS, it is the
responsibility of the BIOS, early in the POST routine, to
transition the processor core frequency and voltage to the
desired performance level.
See “Safe Voltage and Frequency Combination at Reset” on
page 20 for the advantages and disadvantages of booting at a
minimum core frequency.
Dynamic Core Frequency and Core Voltage Control
9
Preliminary Information
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Dynamic Core Frequency Control
For Microsoft operating systems, the BVC field of the EPM 16byte I/O block is accessed through an SMM handler.
To invoke a new processor core frequency, the SMM handler
initiates core voltage and frequency transitions by writing a
1 to the GSBC field in the EPMR and a non-zero value to the
SGTC.
■
This action initiates a special bus cycle to place the
processor into the EPM Stop Grant state and transitions the
CPU core voltage and frequency to the values specified in
the VIDO and IBF fields of the BVC field.
Note: System-initiated inquire (snoop) cycles are not supported
and must be prevented by the BIOS or operating system
while in the EPM Stop Grant state.
■
BVC Field
10
Figure 3 on page 11 shows the format and Table 5 defines the
function of each bit of the BVC field located within the EPM 16byte I/O block.
Dynamic Core Frequency and Core Voltage Control
Preliminary Information
24267A/0—December 2000
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
5 4
12 11 10 9 8 7
31
B V
V I
C D
M C
SGTC
BDC
IBF[2:0]
0
VIDO
Reserved
Symbol
SGTC
BVCM
VIDC
BDC
IBF[2:0]
VIDO
Description
Stop Grant Time-out Counter
Bus Divisor and VID Change Mode
Voltage ID Control
Bus Divisor Control
Internal BF Divisor
Voltage ID Output
Bits
31-12
11
10
9-8
7-5
4-0
Figure 3. Bus Divisor and Voltage ID Control (BVC) Field
Table 5.
Bit
31-12
11
10
Bus Divisor and Voltage ID Control (BVC) Definition
Description
Stop Grant Time-out Counter (SGTC)
Bus Divisor and VID Change Mode
(BVCM)
Voltage ID Control (VIDC)
R/W Function1
W
Writing a non-zero value to this field causes the processor to enter
the EPM Stop Grant state internally. This 20-bit value is multiplied
by 4096 to determine the duration of the EPM Stop Grant state,
measured in processor bus clocks.
R/W
This bit controls the mode in which the bus-divisor and the voltage
control bits are allowed to change. If BVCM=0, the Bus Divisor and
Voltage ID changes take effect only upon entering the EPM Stop
Grant state as a result of the SGTC field being programmed.
BVCM=1 is reserved.
R/W
This bit controls the mode of Voltage ID control. If VIDC=0, the processor VID[4:0] pins are unchanged upon entering the EPM Stop
Grant state. If VIDC=1, the processor VID[4:0] pins are programmed to the VIDO value upon entering the EPM Stop Grant
state. BIOS should initialize this bit to 1 during the POST routine.
9-8
Bus Divisor Control (BDC)
R/W
This 2-bit field controls the mode of Bus Divisor control. If
BDC[1:0]=00b, the BF[2:0] pins are sampled at the falling edge of
RESET. If BDC[1:0]=1xb, the IBF[2:0] field is sampled upon entering
the EPM Stop Grant state. BDC[1:0]=01b is reserved. BIOS should
initialize these bits to 10b during the POST routine.
7-5
Internal BF Divisor (IBF)
R/W
If BDC[1:0]=1xb, the processor EBF[2:0] field of the PSOR is programmed to the IBF[2:0] value upon entering the EPM Stop Grant
state.
R/W
This 5-bit value is driven out on the processor VID[4:0] pins upon
entering the EPM Stop Grant state if the VIDC bit=1. These bits are
initialized to 01010b and driven on the processor VID[4:0] pins at
RESET.
4-0
Voltage ID Output (VIDO)
Notes:
1. All bits default to 0 when RESET is asserted, except the VIDO bits which default to 01010b
Dynamic Core Frequency and Core Voltage Control
11
Preliminary Information
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Voltage Identification (VID) Outputs
AMD-K6-2E+ and AMD-K6-IIIE+ low-power processors enabled
with AMD PowerNow! technology feature Voltage ID (VID)
outputs to support dynamic control of the core voltage. These
outputs should serve as inputs to a DC/DC regulator that
supplies the processor core voltage. Based on its VID[4:0]
inputs, the regulator outputs a corresponding voltage. (See
“Hardware Implementation” on page 18 for more detailed
information on using the VID outputs in embedded systems.)
For regulators that do not support VID inputs, the processor’s
VID[4:0] outputs must be used to manipulate the regulator’s
feedback voltage to vary the regulator output voltage.
It is not necessary to drive all of the processor VID[4:0] outputs
to the voltage select inputs of the DC/DC regulator. Any voltage
select inputs of the DC/DC regulator that are not driven by the
processor VID[4:0] outputs should be tied to ground.
All VID[4:0] Output
Pins Used
System implementations that incorporate all processor VID
outputs typically support a voltage range of 0.925 V to 2.0 V.
Table 6 on page 13 lists VID[4:0] codes that are typical for
DC/DC regulators.
Subset of VID[4:0]
Outputs Used
System implementations that use a subset of the processor VID
outputs will require external logic to translate the processor
VID pins into a full five-bit DC/DC regulator input code.
One solution that is recommended for a maximum BF[2:0] boot
strap option (see page 9) requires that regulator D[4] and D[0]
inputs be connected to GND while inputs D[3:1] are connected
to t h e p ro ce ssor V ID [4 ], V ID [ 2], an d V ID [0 ] out p ut s,
respectively, through external logic.
For a 2.1-V core voltage implementation, the available core
voltage is thereby limited to a range of 1.36 V to 2.1 V in
approximately 100-mV increments, but the rework and external
logic cost is minimal. Table 7 on page 13 shows the voltage
translation using the Max1711 DC/DC regulator.
Unused VID[4:0]
Outputs
12
System designs that do not use the dynamic core voltage control
feature provided in AMD PowerNow! technology should simply
leave the processor VID[4:0] outputs as no-connects (NC) on the
motherboard.
Dynamic Core Frequency and Core Voltage Control
Preliminary Information
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Table 6.
VID [4:0] Input-to-Output Voltage Codes (Typical for DC/DC Regulators)
VID Inputs
VID Inputs
D[4]
D[3]
D[2]
D[1]
D[0]
Output
Voltage
0
0
0
0
0
2.00 V
1
0
0
0
0
1.275 V
0
0
0
0
1
1.95 V
1
0
0
0
1
1.250 V
0
0
0
1
0
1.90 V
1
0
0
1
0
1.225 V
0
0
0
1
1
1.85 V
1
0
0
1
1
1.200 V
0
0
1
0
0
1.80 V
1
0
1
0
0
1.175 V
0
0
1
0
1
1.75 V
1
0
1
0
1
1.150 V
0
0
1
1
0
1.70 V
1
0
1
1
0
1.125 V
0
0
1
1
1
1.65 V
1
0
1
1
1
1.100 V
0
1
0
0
0
1.60 V
1
1
0
0
0
1.075 V
0
1
0
0
1
1.55 V
1
1
0
0
1
1.050 V
0
1
0
1
0
1.50 V
1
1
0
1
0
1.025 V
0
1
0
1
1
1.45 V
1
1
0
1
1
1.000 V
0
1
1
0
0
1.40 V
1
1
1
0
0
0.975 V
0
1
1
0
1
1.35 V
1
1
1
0
1
0.950 V
0
1
1
1
0
1.30 V
1
1
1
1
0
0.925 V
0
1
1
1
1
Shutdown1
1
1
1
1
1
Shutdown1
D[4]
D[3]
D[2]
D[1]
D[0]
Output
Voltage
Notes:
1. If the voltage regulator is to be powered when the processor is to be powered off (for example, during Suspend to RAM), it is necessary
to assert the regulator’s shutdown pin to power off the processor.
.
Table 7.
Regulator Solution Using a Subset of CPU VID Outputs
Max1711 Regulator
D[4:0] Inputs
Connection to CPU VID
Outputs
CPU VID[4:0]
Outputs1
Regulator D[4:0]
Inputs2
Voltage Selected3
D[4]
GND
0x0x0
00000
2.00 V
D[3]
CPU VID[4]4
0x0x1
00010
1.90 V
D[2]
CPU VID[2]4
0x1x0
00100
1.80 V
D[1]
CPU VID[0]4
0x1x1
00110
1.70 V
D[0]
GND
1x0x0
01000
1.60 V
1x0x1
01010
1.50 V
1x1x0
01100
1.40 V
1x1x1
01110
1.30 V
Notes:
1.
2.
3.
4.
CPU VID[3] and VID[1] are each treated as an NC (no-connect) and represented by “x”.
Regulator D[4] and D[0] are tied to GND.
Assumes a resistor divide circuit is used with the regulator to support a 2.1-V core voltage.
CPU VID[4], VID[2], and VID[0] are connected to the regulator through external logic.
Dynamic Core Frequency and Core Voltage Control
13
Preliminary Information
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Guaranteed CPU Core Voltage at Power On
The processor VID[4:0] outputs are initialized to a default state
of 01010b, but they are only initialized after RESET is asserted,
the CPU input clock is running, and an I/O voltage is applied.
As a result, it is necessary to drive the input select pins of the
DC/DC regulator from a source other than the CPU during
system power up.
This can be accomplished by placing external logic between the
VID[4:0] outputs of the processor and the voltage select inputs
of the DC/DC regulator. The System Power Good (SPWRGD)
signal can then be used as an input to the external logic to strap
the DC/DC regulator’s voltage select inputs to the desired state
until the processor’s VID[4:0] outputs have been initialized.
When SPWRGD is negated, the external logic drives the
selected strap value to the regulator’s D[4:0] inputs.
■
When SPWRGD is asserted, the external logic allows the
CPU VID[4:0] outputs to drive the regulator’s D[4:0] inputs.
Note: The SPWRGD signal must only assert after all power good
signals (I/O, core, +5-V, etc.) are asserted.
■
For a minimum BF[2:0] boot strap option (see page 9), a
multiplexer and the SPWRGD signal can be used for this
purpose.
For a maximum BF[2:0] boot strap option (see page 9), a
multiplexer function is incorporated through the recommended
AND-gate solution discussed in "Subset of VID[4:0] Outputs
Used" on page 12.
In both cases, the SPWRGD signal, when equal to 0, forces the
VID[4:0] outputs of the external logic to a value equivalent to
the output state that the processor drives on its VID[4:0] pins
when SPWRGD transitions to a 1. Once RESET is negated,
BIOS is free to transition the processor core frequency and
voltage as needed.
Figure 5 on page 25 helps to illustrate the concept of
implementing a guaranteed CPU core voltage at power on.
14
Dynamic Core Frequency and Core Voltage Control
Preliminary Information
24267A/0—December 2000
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
Dynamic Core Voltage Control
For Microsoft operating systems, the BVC field of the EPM 16byte I/O block is accessed through an SMM handler. To invoke a
new processor core voltage, the SMM handler initiates core
voltage and frequency transitions by writing a 1 to the GSBC
field in the EPMR and a non-zero value to the SGTC. This action
automatically places the processor into the EPM Stop Grant
state and transitions the CPU core voltage to the value
specified in the VIDO field of the BVC field.
Note: System-initiated inquire (snoop) cycles are not supported
and must be prevented by the BIOS or operating system
while in the EPM Stop Grant state. This is typically
accomplished through the use of the ACPI-defined ARB_DIS
control bit, which turns off the PCI bus arbiter in the north
bridge.
The VID[4:0] outputs are determined by the value stored in the
VIDO field within the BVC field of the 16-byte I/O block during
AMD PowerNow! technology state transitions. For more
information on the format and definition of the BVC field, see
“BVC Field” on page 10.
Dynamic Core Frequency and Core Voltage Control
15
Preliminary Information
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
AMD PowerNow! Technology Initialization
Initialization of the AMD-K6-2E+ and AMD-K6-IIIE+ low-power
processors is straightforward. Below is a complete summary
illustrating the actions required to properly initialize these
processors for implementation of AMD PowerNow! technology.
Software
Initialization
Detailed information for effective software control of devices
enabled with AMD PowerNow! technology is provided in the
“Software Implementation” section, beginning on page 28.
To initialize the software:
Write the I/O base address (IOBASE) field (EPMR[15:4]) for
the 16-byte EPM I/O block. This sets up the location in the
I/O map where the EPM I/O block will reside. Be sure to
locate the EPM I/O block so that it does not conflict with
other system I/O-mapped resources. The EPMR is accessed
at MSR location C000_0086h.
■
Clear the Enable AMD PowerNow! Technology Management
(EN) bit (EPMR[0]) to disable address decodes of the EPM
I/O block fields. Clearing EPMR[0] ensures that errant
writes to I/O space do not accidentally change the
AMD PowerNow! technology state. For Windows desktopbased operating systems, the SMI handler will set
EPMR[0]=1b only when SMM is entered for the purpose of
doing an AMD PowerNow! technology state transition. Realtime operating systems should set EPMR[0]=1b only when
attempting an AMD PowerNow! technology state transition.
This bit may be cleared in the same MSR write that
initializes the EPM I/O block base.
Note: EPMR[0] should be cleared upon completing any
AMD PowerNow! technology state transition to ensure errant
writes to I/O space do not inadvertently alter the
AMD PowerNow! technology state of the processor.
■
■
16
The VIDC bit (BVC[10]) should be set to 1 at power-on self
test (POST). All subsequent writes to this field should
ensure that this bit equals 1b at all times. Initializing this bit
causes a read/modify-bit/write operation on the BVC field.
After reading the BVC field and setting the VIDC bit during
initialization, be sure to clear all bits in the SGTC field
before writing the BVC field back out. This is required
because the data returned in the SGTC field is invalid, as it
is a write-only field.
Dynamic Core Frequency and Core Voltage Control
Preliminary Information
24267A/0—December 2000
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
Note: Both the VIDC and BDC bits may be initialized at the same
time.
The BDC field (BVC [9:8]) should be set to 10b at POST. All
subsequent writes to this field should ensure that these bits
remain 10b at all times. After reading the BVC field and
setting the BDC bits during initialization, be sure to clear all
bits in the SGTC field before writing the BVC field back out.
This is required because the data returned in the SGTC field
is invalid, as it is a write-only field.
Note: Both the VIDC and BDC bits may be initialized at the same
time.
■
■
Hardware
Initialization
Make the AMD PowerNow!™ Technology Descriptor Table
(see page 30) visible in the system memory map on a 16-byte
boundary within the range of 0x0C0000–0x0FFFFF or within
the first Kbyte of the extended BIOS data area.
Information on implementing an efficient AMD PowerNow!
t e ch n o l o gy d ev i c e i s p rov i d e d i n t h e “ H a rd wa re
Implementation” section, beginning on page 18.
To initialize the hardware:
■
■
■
Strap the system for one of the recommended power-up
configurations: maximum CPU frequency or minimum CPU
frequency setting. See “Safe Voltage and Frequency
Combination at Reset” on page 20 for details.
At reset, both the AMD-K6-2E+ and AMD-K6-IIIE+ lowpower processors drive 01010b on the VID[4:0] pins. The
VID-capable voltage regulator and implementation must be
equipped to handle this signaling at reset. See “Safe Voltage
and Frequency Combination at Reset” on page 20 for
details.
Logic AND gates should be used in conjunction with the
SPWRGD signal to ensure voltage continuity from the
voltage regulator at reset.
Dynamic Core Frequency and Core Voltage Control
17
Preliminary Information
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Hardware Implementation
Embedded system designs can be modified to support
AMD PowerNow! technology with minimal design changes.
New traces must be added to route the new processor output
pins to the proper hardware components. Based on the desired
implementation of the AMD PowerNow! technology features,
additional hardware may be required; and depending on the
current system design, the voltage regulator may need to be
updated to properly support AMD PowerNow! technology
voltage transitions.
Figure 4 on page 19 illustrates an AMD PowerNow! technology
design which uses the Maxim 1711 DC/DC regulator. Obviously,
other devices can be used in exchange for those used in this
example. Alternative components and matching input pins are
provided in Table 8 on page 19.
18
Hardware Implementation
Preliminary Information
24267A/0—December 2000
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
MAX1711
DC/DC Regulator
D[4]
D[3]
D[2]
D[1]
D[0]
VCC2
BF2
BF1
BF0
AMD-K6™-2E+ or
AMD-K6™-IIIE+
Processor
74LVC08
VID[4]
VID[2]
VID[0]
1
2
3
D[3]
4
5
6
D[2]
10
9
8
D[1]
SPWRGD
Figure 4. Example Hardware Implementation
Table 8.
Alternative Components for AMD PowerNow!™ Technology Hardware Implementation
Component
Model and Input Pin Information
Maxim 1711
DC/DC
Voltage
Regulator
Maxim 1714b
Pin Name
Pin No.
Pin Name
Pin No.
Comment
D[4:0]
16-20
n/a
n/a
1714b does not use VID[4:0] inputs
PGOOD
12
PGOOD
7
Hardware Implementation
19
Preliminary Information
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Safe Voltage and Frequency Combination at Reset
A safe voltage and frequency combination at reset is a
combination that provides functional processor operation
conditions when RESET is negated.
Minimum Frequency
Initialization
Systems that strap the processor BF[2:0] inputs to 100b
configure the processor to boot with a core frequency of 2.0x
the processor bus frequency upon RESET, which is the lowest
supported frequency, are set for the minimum frequency
initialization.
■
The advantage to this implementation is that any supported
AMD-K6-2E+ and AMD-K6-IIIE+ processor core voltage can
be used for proper operation for the minimum frequency
setting with the BF multiplier of 2.0x.
■
The disadvantage of this method is that the maximum rated
frequency of the processor cannot be determined by the
state of the BF[2:0] pins.
Connecting the processor’s VID[4:0] outputs to the regulator’s
D[4:0] inputs through a multiplexer that selects the processor’s
VID[4:0] outputs when SPWRGD = 1 will result in a CPU
voltage of 1.5 V. If the processor’s VID[4:0] outputs are mapped
with a one-to-one correspondence to the regulator’s D[4:0]
inputs, it is required that the multiplexer drive 01010b to the
D[4:0] regulator inputs, respectively, when SPWRGD = 0. This
maintains V CC2 continuity at 1.5 V for the core voltage as
SPWRGD transitions from unstable to good. The combination of
1.5 V and a 2.0x bus frequency multiplier provides a voltage and
frequency at power up that guarantees functional operating
conditions.
If the BF[2:0] inputs are strapped to select a 2.0x bus frequency
multiplier, but a higher performance level is desired before
loading the OS, then it is the responsibility of the BIOS or the
RTOS to adjust the processor’s core frequency and voltage to
the desired operational level early in the POST routine.
20
Hardware Implementation
Preliminary Information
24267A/0—December 2000
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
Maximum Frequency
Initialization
(Recommended)
Systems that strap the processor BF[2:0] inputs so that the
processor runs at the highest supported frequency are set for
maximum frequency.
■
The advantage of this implementation is that it does allow
the BIOS to directly determine the CPU’s maximum
frequency by the state of the BF[2:0] pins.
■
The disadvantage of this method is that it limits the number
of regulator VID[4:0] input combinations and the output
core voltage range available. It is also important to note that
the VCC2 voltage will be initialized to 2.0 V.
If it is desired to have the processor run at its maximum
frequency whenever RESET is asserted, all of the processor’s
VID[4:0] outputs cannot be tied directly to the regulator’s
D[4:0] inputs using this method. A total one-to-one VID[4:0]
correspondence results in a core voltage supply of 1.5 V, which
does not guarantee functional operation conditions at the
processor’s maximum frequency.
In the case that the BF[2:0] inputs to the processor are strapped
to select the maximum CPU core frequency, additional logic is
required to translate the CPU’s default VID[4:0] output into a
regulator input that is interpreted as a voltage that provides
functional operation conditions at the processor’s maximum
frequency. The recommended solution is shown in Figure 4 on
page 19.
For a step-by-step example of how to modify an existing design
for this recommended implementation, see “VID[4:0]
Modification for Maximum BF[2:0] Boot Option” on page 24.
Hardware Implementation
21
Preliminary Information
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Voltage Versus Frequency Options
In addition to initializing the processor at the minimum or
maximum frequencies, intermediate frequency/voltage
combinations can be selected, thereby allowing for additional
flexibility in performance and power consumption.
Table 9 on page 23 and Table 10 list the minimum core voltage
required to support various frequencies of a particular speed
grade. For example, an AMD-K6-IIIE+ processor rated to run at
500 MHz at a nominal core voltage of 1.8 V is designed to run
between 200 and 300 MHz with a nominal core voltage of 1.4 V.
22
Hardware Implementation
Preliminary Information
24267A/0—December 2000
Table 9.
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
Supported Voltages and Operating Frequencies for Low-Power AMD-K6™-2E+ Processors
Enabled with AMD PowerNow!™ Technology
Ordering Part Number1
AMD-K6-2E+/450APZ
AMD-K6-2E+/400xTZ
AMD-K6-2E+/350xUZ
Core Voltage
Range of Supported
Operating Frequencies2
Active Power3
1.7 V
450–200 MHz
8.70–4.90 W
1.6 V
400–200 MHz
6.90–4.20 W
1.5 V
350–200 MHz
5.60–3.70 W
1.4 V
300–200 MHz
4.30–2.95 W
1.6 V
400–200 MHz
6.90–4.20 W
1.5 V
350–200 MHz
5.60–3.70 W
1.4 V
300–200 MHz
4.30–2.95 W
1.5 V
350–200 MHz
5.60–3.70 W
1.4 V
300–200 MHz
4.30–2.95 W
Notes:
1. An x in this column represents the package type. See the processor data sheet for a full description of ordering part number notation.
2. AMD PowerNow! technology enables the operating frequency to step down in increments corresponding to the available bus frequency
multipliers. Note that 250-MHz operation is not supported due to exclusion of 2.5 bus frequency multiplier.
3. Active application power dissipation for highest and lowest supported frequency at specified voltage.
Table 10. Supported Voltages and Operating Frequencies for Low-Power AMD-K6™-IIIE+ Processors
Enabled with AMD PowerNow!™ Technology
Ordering Part Number1
AMD-K6-IIIE+500ANZ
AMD-K6-IIIE+450APZ
AMD-K6-IIIE+400xTZ
Core Voltage
Range of Supported
Operating Frequencies2
Active Power3
1.8 V
500–200 MHz
11.40–5.80 W
1.7 V
450–200 MHz
8.95–4.90 W
1.6 V
400–200 MHz
7.10–4.20 W
1.5 V
350–200 MHz
5.60–3.70 W
1.4 V
300–200 MHz
4.30–2.95 W
1.7 V
450–200 MHz
8.95–4.90 W
1.6 V
400–200 MHz
7.10–4.20 W
1.5 V
350–200 MHz
5.60–3.70 W
1.4 V
300–200 MHz
4.30–2.95 W
1.6 V
400–200 MHz
7.10–4.20 W
1.5 V
350–200 MHz
5.60–3.70 W
1.4 V
300–200 MHz
4.30–2.95 W
Notes:
1. An x in this column represents the package type. See the processor data sheet for a full description of ordering part number notation.
2. AMD PowerNow! technology enables the operating frequency to step down in increments corresponding to the available bus frequency
multipliers. Note that 250-MHz operation is not supported due to exclusion of 2.5 bus frequency multiplier.
3. Active application power dissipation for highest and lowest supported frequency at specified voltage.
Hardware Implementation
23
Preliminary Information
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
VID[4:0] Modification for Maximum BF[2:0] Boot Option
The following section discusses a step-by-step process for
modifying a design to accommodate the recommended
maximum BF[2:0] boot option using the Maxim 1711 DC/DC
voltage regulator. An assisting diagram is provided in Figure 5
on page 25.
■
■
■
■
■
■
■
■
■
■
■
■
■
24
Disconnect processor output pins: AH32, AN35, R34, E25,
and E17 from any current destinations
Leave processor output pins AN35 and E25 unconnected
Connect the Maxim 1711 DAC inputs D4 (pin16) and D0 (pin
20) directly to GND
Add a 74LVC08 quadruple 2-input AND gate, connecting
VCC (pin 14) to +3.3V and GND (pin 7) to GND.
Connect processor VID[4] (pin E17) to 74LVC08 pin 1
Connect processor VID[2] (pin R34) to 74LVC08 pin 4
Connect processor VID[0] (pin AH32) to 74LVC08 pin 10
Add 10K-Ohm pull-up resistors on 74LVC08 pins 1, 4, 10 to
+3.3V
Connect SPWRGD (system power good) to 74LVC08 pins 2,
5, and 9
Connect 74LVC08 pin 8 to Maxim 1711 DAC input D[1] (pin
19)
Connect 74LVC08 pin 6 to Maxim 1711 DAC input D[2] (pin
18)
Connect 74LVC08 pin 3 to Maxim 1711 DAC input D[3] (pin
17)
Connect 74LVC08 pins 12 and 13 to GND to prevent the
unused inputs from floating
Hardware Implementation
Preliminary Information
24267A/0—December 2000
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
MAX1711
DC/DC Regulator
16
17
18
19
20
D[4]
D[3]
D[2]
D[1]
D[0]
PGOOD
VPWRGD
12
Logic to generate
SPWRGD
VCC2
+3.3 V
10 K 10 K 10 K
AMD-K6™-2E+ or
AMD-K6™-IIIE+
Processor
+3.3 V
VID[4]
VID[3]
VID[2]
VID[1]
VID[0]
74LVC08
1
2
3
D[3]
4
5
6
D[2]
10
9
8
D[1]
SPWRGD
Figure 5. VID[4:0] Modification for Maximum Frequency Initialization
Hardware Implementation
25
Preliminary Information
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Gating PGOOD During a Voltage Transition
Most DC/DC regulators, such as the Maxim 1711, have an output
to indicate a stable core voltage (PGOOD) that may glitch low
during AMD PowerNow! technology voltage transitions.
PGOOD can be used by system logic to generate the SPWRGD
(system power good) signal. Because the south bridge asserts
CPURST when SPWRGD is negated, any glitches of PGOOD
during these state transitions must be intercepted in order to
prevent a CPU reset.
The recommended solution for intercepting PGOOD and
e n s u r i n g t h a t a s y s t e m re s e t d o e s n o t o c c u r d u r i n g
AMD PowerNow! technology core voltage transitions is to
logically OR the PGOOD output with the PCIRST# signal.
However, since the regulator’s PGOOD signal is gated, this
solution does not allow the system to monitor the CPU core
voltage for guarding against an out-of-spec condition.
Figure 6 on page 27 illustrates the necessary modifications for
i n t e rc e p t i n g t h e D C / D C re g u l a t o r P G O O D s i g n a l
AMD PowerNow! technology voltage transitions.
26
Hardware Implementation
Preliminary Information
24267A/0—December 2000
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
+5 V
MAX1711
DC/DC Regulator
+3.3 V
10 K
16
17
18
19
20
D[4]
D[3]
D[2]
D[1]
D[0]
PGOOD
74LVC32
1
12
VPWRGD
3
2
Logic to generate
SPWRGD
PCIRST#
10 K
VCC2
+3.3 V
+3.3 V
AMD-K6™-2E+ or
AMD-K6™-IIIE+
Processor
10 K 10 K 10 K
VID[4]
VID[3]
VID[2]
VID[1]
VID[0]
74LVC08
1
2
3
D[3]
4
5
6
D[2]
10
9
8
D[1]
SPWRGD
Figure 6. Gating the PGOOD Signal with Maximum Frequency Initialization
Hardware Implementation
27
Preliminary Information
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Software Implementation
CPU frequency and voltage setting combinations, called
AMD PowerNow! technology states, are dependent upon a
number of factors. The hardware design directly influences
what states are available and supported in the system. These
may be dependent upon performance preferences, power
requirements or, most often, a combination of both.
A p a r t f ro m t h e h a rd wa re d e s i g n i s t h e s o f t wa re
implementation. How and what is implemented in software
directly impacts when a state transition takes place and what
voltage and frequency settings are invoked by the hardware.
Some software components that can be utilized to implement a
fully ACPI-compliant power management scheme include:
■
■
■
■
Real-time operating system (RTOS) enabled for
AMD PowerNow! technology
SMM handler
Microsoft Windows® driver that supports AMD PowerNow!
technology
BIOS
Using an RTOS Enabled for AMD PowerNow!™ Technology
Some real-time operating systems supporting AMD PowerNow!
technology will not require BIOS support or even a BIOS. In
these instances, all the software required to invoke the EPM
Stop Grant State and change the settings for voltage and
frequency, or both, resides in the RTOS.
28
Software Implementation
Preliminary Information
24267A/0—December 2000
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
Using an SMM Handler
The AMD PowerNow! technology BIOS SMI API is the AMDdefined method for a driver to communicate with the BIOS in a
Microsoft desktop operating system or with embedded
Windows NT.
■
If a driver is used, it will search for a BIOS-supplied table of
information, which includes the address of the SMI
command port.
■
With the command port established, the driver then sets up
parameters in general-purpose registers (the function and
sub-function placed in the CX register) and generates an
SMI by writing to the SMI command port.
As the SMI command port mapping is specific to the south
bridge, the BIOS/SMM developer must assign an eight-bit
code to properly execute the SMM handler and enter SMM.
Values are then returned in general-purpose registers, and
SMM is entered.
The driver can use “AMD PowerNow! technology BIOS calls”
in SMM to invoke AMD PowerNow! technology state
transitions, where these BIOS calls function in a similar
manner to the BIOS INTn functions supported by Microsoft.
■
■
■
Using a Microsoft® Windows® Driver Supporting
AMD PowerNow! Technology
The AMD PowerNow! technology-specific Microsoft Windows
driver is the device driver that allows the communication of
AMD PowerNow! technology preferences from the system to the
B I OS or S M M c o d e . A ny B I O S t h a t c o m p l i e s w i t h t h e
AMD PowerNow! technology BIOS SMI API specification is
expected to support driver requests from any operating system
or utility system that is able to make the proper calls.
The AMD PowerNow! technology driver also:
■
■
Software Implementation
Updates the memory table that is used to communicate user
performance preferences to BIOS.
Communicates system preferences or changes to the BIOS.
This involves invoking the SMM handler (via the south
bridge’s SMI command port) when a state transition is
desired.
29
Preliminary Information
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Using a BIOS
The BIOS should contain the following:
■
Table of AMD PowerNow! technology supported states used
by the driver and SMM handler
■
Data reflecting the current AMD PowerNow! technology
settings
The mapping information required by the driver to access
the SMI command port in the system’s south bridge.
■
AMD PowerNow!™ Technology Descriptor Table
The AMD PowerNow! technology descriptor table is a data
structure typically built in the BIOS memory area at POST. It is
used to convey information to an AMD PowerNow! technology
enabled operating system kernel, device driver, or other
interested application software.
After searching for, locating, and reading the table during
initialization after POST, the AMD PowerNow! technology
controlling software will have all the platform-specific
i n f o r m a t i o n a n d w i l l k n ow h ow t o a c c e s s i t t h ro u g h
AMD PowerNow! technology control features.
The signature for the table is located on a 16-byte boundary in
the area from 0x0C0000 to 0x0FFFFF or within the first 1 Kbyte
of the extended BIOS data area.
Table 11 on page 31 provides the field definitions for the
AMD PowerNow! technology descriptor table.
30
Software Implementation
Preliminary Information
24267A/0—December 2000
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
Table 11. AMD PowerNow!™ Technology Descriptor Table
Offset
Length
0
4
Signature: “GBDT”
4
1
Length, in bytes, of the entire AMD PowerNow! technology BIOS descriptor table
(no larger than 256 bytes.)
5
1
AMD PowerNow! technology BIOS API revision in BCD. Tens = major, Ones = minor
6
1
Checksum; entire table must sum to zero
7
1
Reserved
8
2
Bus speed in binary MHz (66, 75, 83, 92, 100, 112, 133, 150, 200, etc.)
10
2
Maximum CPU frequency for current processor in binary MHz
1
Maximum AMD PowerNow! technology state support by system (“N”). There are N+1
possible states and N<16. The minimum state is always zero.
12
Description
AMD PowerNow! Technology SMI Command Port Information
SMI Command Port Type/Size:
Bit 0: Address Space, where 0 = x86 I/O address, and 1 = memory-mapped address.
13
1
Bits 6–4: Data Size, where 001 = 8 bits (byte access), 010 = 16 bits, 100 = 32 bits.
Bits 3–1, 7, and 8 are reserved and must be 0.
14
4
Address of SMI command port
18
4
AMD PowerNow! Technology_Code (Load ESI register with this number before making SMI call.
Currently the code is defined as 9800_0089h.)
22
2
State 0 CPU Voltage (A.BCD format)
24
2
State 0 CPU Frequency (in binary MHz)
26
1
State 0 VID[4:0]
27
1
State 0 BF[2:0]
28
2
State 1 CPU Voltage
30
2
State 1 CPU Frequency
32
1
State 1 VID[4:0]
33
1
State 1 BF[2:0]
34
2
State 2 CPU Voltage
36
2
State 2 CPU Frequency
38
1
State 2 VID[4:0]
39
1
State 2 BF[2:0]
xx
2
State N CPU Voltage
xx
2
State N CPU Frequency
xx
1
State N VID[4:0]
xx
1
State N BF[2:0]
Voltage/Frequency to State Map for Current System
Software Implementation
31
Preliminary Information
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Event Sequence for AMD PowerNow!™ Technology State Transitions
The following is a summary sequence of events outlining what
must occur for a successful AMD PowerNow! technology state
transition:
An SMM handler or BIOS or operating system function may
be called to carry out the AMD PowerNow! technology state
transition.
■
Set the ACPI-defined ARB_DIS bit in the north bridge to
prevent PCI and AGP bus masters from being granted the
bus and access to system memory while the
AMD PowerNow! technology state transition is taking place.
This is necessary because the processor is not capable of
responding to cache snoops while its core voltage and/or
frequency are being transitioned.
Note: All bus activity to the processor must cease before initiating
the AMD PowerNow! technology state transition. This is
critical as a bus transaction may be in progress when the
ARB_DIS bit is set. Additionally, there may be several
memory accesses queued, which must be completed prior to
entering EPM Stop Grant State.
■
■
■
■
■
■
■
32
Enable the EN bit of the EPMR register, making the
frequency and voltage control fields accessible within the
EPM 16-byte I/O block.
Write the desired values for the requested operating voltage
and frequency settings in the BVC field.
Initiate the AMD PowerNow! technology state transition by
writing a non-zero value to the SGTC field within the BVC
field of the EPM 16-byte I/O block. This action causes the
processor to enter the EPM Stop Grant state.
After the AMD PowerNow! technology state transition,
disable the EN bit of the EPMR register, which renders the
frequency and voltage control fields invisible within I/O
space.
Clear the ARB_DIS bit in the north bridge to allow system
memory accesses.
If an SMM handler is used to invoke EPM Stop Grant State, a
RSM instruction should be executed to return the CPU to
normal operation.
Software Implementation
Preliminary Information
24267A/0—December 2000
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
Pinout Information
AMD-K6-2E+ and AMD-K6-IIIE+ low-power processors enabled
with AMD PowerNow! technology use the AMD standard, 321pin CPGA package and are also available in a 349-ball OBGA
package.
To support AMD PowerNow! technology, five new output pins
have been added that replace pins previously designated as
either NC or INC pins.
Table 12 lists the new pins added to support AMD PowerNow!
technology. Table 13 on page 34 and Table 14 on page 35 list the
CPGA processor pins. Table 15 on page 36 and Table 16 on
page 37 list the OBGA processor pins.
Table 12. Pins Added for AMD PowerNow!™ Technology
AMD PowerNow!™
Technology Function
Voltage ID Control
Pinout Information
Pin Name
CPGA
Pin
Number
OBGA
Pin
Number
VID[4]
E-17
A-11
VID[3]
E-25
C-15
VID[2]
R-34
L-19
VID[1]
AN-35
W-16
VID[0]
AH-32
W-17
Description
These voltage identification outputs are used to drive the
VID inputs of the DC/DC converter that generates the core
voltage for the processor. The processor VID[4:0] outputs
default to 01010b when RESET is asserted.
33
Preliminary Information
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Table 13. CPGA Pin Designations by Functional Grouping
Pin Name
Pin Number
Control
A20M#
ADS#
ADSC#
AHOLD
APCHK#
BE0#
BE1#
BE2#
BE3#
BE4#
BE5#
BE6#
BE7#
BF0
BF1
BF2
BOFF#
BRDY#
BRDYC#
BREQ
CACHE#
CLK
D/C#
EADS#
EWBE#
FERR#
FLUSH#
HIT#
HITM#
HLDA
HOLD
IGNNE#
INIT
INTR
INV
KEN#
LOCK#
M/IO#
NA#
NMI
PCD
PCHK#
PWT
RESET
SCYC
SMI#
SMIACT#
STPCLK#
VCC2DET
VCC2H/L#
W/R#
WB/WT#
34
AK-08
AJ-05
AM-02
V-04
AE-05
AL-09
AK-10
AL-11
AK-12
AL-13
AK-14
AL-15
AK-16
Y-33
X-34
W-35
Z-04
X-04
Y-03
AJ-01
U-03
AK-18
AK-04
AM-04
W-03
Q-05
AN-07
AK-06
AL-05
AJ-03
AB-04
AA-35
AA-33
AD-34
U-05
W-05
AH-04
T-04
Y-05
AC-33
AG-05
AF-04
AL-03
AK-20
AL-17
AB-34
AG-03
V-34
AL-01
AN-05
AM-06
AA-05
Pin Name
Pin Number
Address
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
AL-35
AM-34
AK-32
AN-33
AL-33
AM-32
AK-30
AN-31
AL-31
AL-29
AK-28
AL-27
AK-26
AL-25
AK-24
AL-23
AK-22
AL-21
AF-34
AH-36
AE-33
AG-35
AJ-35
AH-34
AG-33
AK-36
AK-34
AM-36
AJ-33
Pin Name
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
Pin Number
Data
K-34
G-35
J-35
G-33
F-36
F-34
E-35
E-33
D-34
C-37
C-35
B-36
D-32
B-34
C-33
A-35
B-32
C-31
A-33
D-28
B-30
C-29
A-31
D-26
C-27
C-23
D-24
C-21
D-22
C-19
D-20
C-17
C-15
D-16
C-13
D-14
C-11
D-12
C-09
D-10
D-08
A-05
E-09
B-04
D-06
C-05
E-07
C-03
D-04
E-05
D-02
F-04
Pin Name
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
Pin Number
Data
E-03
G-05
E-01
G-03
H-04
J-03
J-05
K-04
L-05
L-03
M-04
N-03
Test
TCK
TDI
TDO
TMS
TRST#
M-34
N-35
N-33
P-34
Q-33
Parity
AP
DP0
DP1
DP2
DP3
DP4
DP5
DP6
DP7
AK-02
D-36
D-30
C-25
D-18
C-07
F-06
F-02
N-05
Voltage ID
VID0
VID1
VID2
VID3
VID4
AH-32
AN-35
R-34
E-25
E-17
Pinout Information
Preliminary Information
24267A/0—December 2000
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
Table 14. CPGA Pin Designations for No Connect, Reserved, Power, and Ground Pins
No Connect (NC)
VCC2
A-37
C-01
S-33
S-35
W-33
AJ-15
AJ-23
AL-19
A-07
A-09
A-11
A-13
A-15
A-17
B-02
E-15
G-01
J-01
L-01
N-01
Q-01
S-01
U-01
W-01
Y-01
AA-01
AC-01
AE-01
AG-01
AJ-11
AN-09
AN-11
AN-13
AN-15
AN-17
AN-19
Internal No Connect (INC)
H-34
Y-35
Z-34
AC-35
AL-07
AN-01
AN-03
Reserved (RSVD)
J-33
L-35
P-04
Q-03
Q-35
R-04
S-03
S-05
AA-03
AC-03
AC-05
AD-04
AE-03
AE-35
Pinout Information
Pin Numbers
VCC3
A-19
A-21
A-23
A-25
A-27
A-29
E-21
E-27
E-37
G-37
J-37
L-33
L-37
N-37
Q-37
S-37
T-34
U-33
U-37
W-37
Y-37
AA-37
AC-37
AE-37
AG-37
AJ-19
AJ-29
AN-21
AN-23
AN-25
AN-27
AN-29
VSS
VSS
A-03
B-06
B-08
B-10
B-12
B-14
B-16
B-18
B-20
B-22
B-24
B-26
B-28
E-11
E-13
E-19
E-23
E-29
E-31
H-02
H-36
K-02
K-36
M-02
M-36
P-02
P-36
R-02
R-36
T-02
T-36
U-35
V-02
V-36
X-02
X-36
Z-02
Z-36
AB-02
AB-36
AD-02
AD-36
AF-02
AF-36
AH-02
AJ-07
AJ-09
AJ-13
AJ-17
AJ-21
AJ-25
AJ-27
AJ-31
AJ-37
AL-37
AM-08
AM-10
AM-12
AM-14
AM-16
AM-18
AM-20
AM-22
AM-24
AM-26
AM-28
AM-30
AN-37
35
Preliminary Information
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Table 15. OBGA Pin Designations by Functional Grouping
Pin Name
Pin Number
Control
A20M#
ADS#
ADSC#
AHOLD
APCHK#
BE0#
BE1#
BE2#
BE3#
BE4#
BE5#
BE6#
BE7#
BF0
BF1
BF2
BOFF#
BRDY#
BRDYC#
BREQ
CACHE#
CLK
D/C#
EADS#
EWBE#
FERR#
FLUSH#
HIT#
HITM#
HLDA
HOLD
IGNNE#
INIT
INTR
INV
KEN#
LOCK#
M/IO#
NA#
NMI
PCD
PCHK#
PWT
RESET
SCYC
SMI#
SMIACT#
STPCLK#
W/R#
WB/WT#
36
W-4
U-1
T-3
K-4
R-1
U-6
W-5
V-6
W-6
U-7
T-8
U-8
V-8
N-17
M-17
N-19
L-3
K-1
L-1
P-4
J-4
U-9
U-3
V-4
K-3
G-4
T-7
W-3
U-4
T-2
M-3
P-19
P-17
P-16
J-1
K-2
T-1
J-3
L-4
R-17
R-4
P-3
V-2
W-9
W-8
P-18
P-2
M-18
U-5
M-2
Pin Name
Pin Number
Address
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
T-14
T-13
W-15
V-14
U-14
T-12
W-14
V-12
W-13
W-12
U-13
W-11
U-12
T-11
W-10
V-10
U-10
T-10
T-17
T-19
U-19
T-18
V-18
U-17
T-15
R-16
U-16
V-16
U-15
Pin Name
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
Pin Number
Data
H-18
G-19
H-19
F-17
H-17
F-18
F-19
E-16
E-17
E-19
D-19
F-16
D-18
D-14
D-17
D-15
A-17
B-18
C-19
B-16
A-16
D-13
C-16
A-15
C-14
C-13
A-14
C-12
A-13
A-12
B-12
D-11
B-10
A-10
D-10
C-10
D-9
A-9
C-9
A-8
A-7
B-8
D-7
C-7
B-6
A-6
C-6
A-5
D-6
C-5
C-4
B-2
Pin Name
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
Pin Number
Data
A-3
D-5
C-3
E-3
D-2
E-4
D-3
D-1
E-1
F-3
F-2
F-4
Test
TCK
TDI
TDO
TMS
TRST#
J-19
K-19
J-16
K-18
K-17
Parity
AP
DP0
DP1
DP2
DP3
DP4
DP5
DP6
DP7
R-3
G-17
C-17
B-14
C-11
C-8
A-4
C-1
F-1
Voltage ID
VID0
VID1
VID2
VID3
VID4
W-17
W-16
L-19
C-15
A-11
Pinout Information
Preliminary Information
24267A/0—December 2000
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
Table 16. OBGA Pin Designations for No Connect, Reserved, Power, and Ground Pins
No Connect (NC)
VCC2
B-4
L-17
M-16
M-19
T-5
T-9
U-11
W-7
C-2
D-4
E-5
F-6
F-7
F-8
F-9
F-10
F-11
G-2
G-5
H-4
H-6
H-7
J-5
K-6
K-7
K-8
K-9
K-10
K-11
L-2
L-5
M-4
M-6
M-7
M-8
M-9
M-10
M-11
N-5
P-6
R-2
R-5
T-4
V-3
V-7
Internal No Connect (INC)
N-16
Reserved (RSVD)
G-1
G-3
G-16
H-1
H-2
H-3
J-17
K-16
M-1
N-1
N-3
N-4
P-1
P-8
R-8
R-19
Pinout Information
Pin Numbers
VCC3
B-13
B-17
E-18
F-14
G-15
H-10
H-11
H-12
H-13
H-14
H-16
J-15
J-18
K-14
L-15
M-14
N-15
N-18
P-11
P-12
P-14
R-10
R-13
U-18
V-11
V-15
VSS
VSS
B-3
B-5
B-7
B-9
B-11
B-15
C-18
D-8
D-12
D-16
E-2
E-6
E-7
E-8
E-9
E-10
E-11
E-12
E-13
E-14
E-15
F-5
F-12
F-13
F-15
G-6
G-7
G-8
G-9
G-10
G-11
G-12
G-13
G-14
G-18
H-5
H-8
H-9
H-15
J-2
J-6
J-7
J-8
J-9
J-10
J-11
J-12
J-13
J-14
K-5
K-12
K-13
K-15
L-6
L-7
L-8
L-9
L-10
L-11
L-12
L-13
L-14
L-16
L-18
M-5
M-12
M-13
M-15
N-2
N-6
N-7
N-8
N-9
N-10
N-11
N-12
N-13
N-14
P-5
P-7
P-9
P-10
P-13
P-15
R-6
R-7
R-9
R-11
R-12
R-14
R-15
R-18
T-6
T-16
U-2
V-5
V-9
V-13
V-17
37
Preliminary Information
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Documentation and Technical Support
The following documents provide additional information
regarding the AMD PowerNow! technology initiative and the
operation of the AMD-K6-2E+ and AMD-K6-IIIE+ processors:
■
■
■
38
Embedded AMD-K6™ Processors BIOS Design
Application Note (order# 23913)
AMD-K6™-2E+ Embedded Processor Data Sheet
(order# 23542)
Guide
AMD-K6™-2E+ Embedded Processor Data Sheet
(order# 23543)
Documentation and Technical Support
Preliminary Information
24267A/0—December 2000
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
Appendix A—Frequently Asked Questions
New Output Pins
Question: Wh a t k i n d o f o u t p u t b u f f e r d o t h e n e w
AMD PowerNow!™ technology output pins have?
Answer: The new processor output pins have standard CMOS
“push-pull” driver buffers. All outputs are always driven.
Question: Are the new AMD PowerNow! technology output pins
5-V-tolerant?
Answer: No. The new AMD PowerNow! technology output pins
adhere to the standard 3.3-V AMD-K6 family I/O voltage
specification.
Question: What should be done for any AMD PowerNow!
technology output pin that is not used?
Answer: Unused AMD PowerNow! technology output pins
should be treated as NCs (no-connects).
AMD PowerNow!™ Technology State Transitions
Question: Are there any design limitations to voltage or bus
frequency transitions?
Answer: Yes. System-initiated inquire (snoop) cycles are not
supported and must be prevented during AMD PowerNow!
technology transitions by setting the ARB_DIS bit in the north
bridge.
Question: Is there a need to stop the CPU clock during state
transitions?
Answer: No. However, state transitions must be performed while
the processor is in the EPM Stop Grant State. The EPM Stop
Grant state is a low-power, clock-control state entered by
writing a non-zero value to the SGTC field for the purpose of
changing the processor core frequency and voltage.
Appendix A—Frequently Asked Questions
39
Preliminary Information
AMD PowerNow!™ Technology Platform Design Guide for Embedded Processors
24267A/0—December 2000
Question: I s t h e re a n e e d t o a s s e r t R E S E T t o p e r fo r m
AMD PowerNow! technology state transitions?
Answer: No. AMD PowerNow! technology state transitions are
designed to operate dynamically and transparent to normal
system operation.
Question: Are there any timing specifications for the length of a
AMD PowerNow! technology transition period?
Answer: The suggest ed duration of time for a complete
AMD PowerNow! technology transition is 200 ms.
Hardware Implementation
Question: I f a m a x i m u m B F [ 2 : 0 ] b o o t s t ra p o p t i o n i s
implemented using the recommended AND-gate logic solution,
is a multiplexer still required to guarantee a deterministic
voltage at power on?
Answer: No. The AND-gate logic solution functions as a
multiplexer. When the system power good (SPWRGD) signal is
L ow, t h e A N D - g a t e l og i c d r ive s t h e re g u l a t o r i n p u t s
appropriately. When SPWRGD is High, the AND-gate logic
allows the processor VID[4:0] outputs to drive the regulator
inputs.
Question: Can a signal other than the SPWRGD be used for
gating the CPU VID[4:0] outputs?
Answer: Yes, the PCI reset pin can also be used to gate the CPU
VID[4:0] outputs to the DC/DC regulator. However, the system
must ensure that PCIRST# is driven low when power is applied
to the processor.
Software Implementation
Question: If the BIOS needs to access the EPMR register during
POST before the SMM handler is installed, can the EPMR
register be accessed outside of SMM?
Answer: Yes. However, the SMM handler must be installed
before SMIs initiated by AMD PowerNow! technology can be
serviced.
40
Appendix A—Frequently Asked Questions
Preliminary Information
24267A/0—December 2000
Index
A
E
AGP Bus
control during state transitions . . . . . . . . . . . . . . . . . . . . . 32
AMD PowerNow!™ Technology
descriptor table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17, 30
documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
enhanced power management features . . . . . . . . . . . . . . . 3
frequently asked questions . . . . . . . . . . . . . . . . . . . . . . . . 39
hardware implementation . . . . . . . . . . . . . . . . . . . . . . . . . 18
initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
initiative. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
operational modes (table) . . . . . . . . . . . . . . . . . . . . . . . . . . 2
pinout information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
software implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 28
state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
AND Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17, 40
API Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
EBF[2:0] Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Effective Bus Divisors EBF[2:0] . . . . . . . . . . . . . . . . . . . . . . . .8
EN Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5, 16
Enable AMD PowerNow! Technology Management (EN)4 , 16
Enhanced Power Management Features . . . . . . . . . . . . . . . . . 3
core voltage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
dynamic core frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
enhanced power management register (EPMR) . . . . . . . . 3
Enhanced Power Management Register (EPMR) . . . . . . . . . 3
EPM 16-Byte I/O Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 6, 16
EPM Stop Grant State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
entering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10–11, 32
exiting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
EPMR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16, 32
accessing outside of SMM. . . . . . . . . . . . . . . . . . . . . . . . . . 40
accessing using SMM handler . . . . . . . . . . . . . . . . . . . . . . . 7
ESI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Extended BIOS Data Area . . . . . . . . . . . . . . . . . . . . . . . 17, 30
B
BDC Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11, 17
BF[2:0] Signals, Strapping Considerations. . . . . . . . . . . . . . . 9
BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
descriptor table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
EPMR access outside of SMM . . . . . . . . . . . . . . . . . . . . . . 40
initializing the EPM I block after reset . . . . . . . . . . . . . . . 5
initializing the EPMR register after reset . . . . . . . . . . . . . 3
reporting I/O range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
using a different CPU core frequency . . . . . . . . . . . . . 9, 20
Boot Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Bus Divisor and VID Change Mode (BVCM) . . . . . . . . . . . . 11
Bus Divisor Control (BDC) . . . . . . . . . . . . . . . . . . . . . . . . 11, 17
Bus Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
BVC Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10, 16
BVCM Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
‰
C
CMOS Push-Pull Driver Buffers . . . . . . . . . . . . . . . . . . . . . . 39
Core Frequency and Voltage Control . . . . . . . . . . . . . . . . . . 20
CPGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
pin designations by function (table) . . . . . . . . . . . . . . . . . 34
CPU Clock, Stopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
CPU Core Voltage, Guaranteed at Power On . . . . . . . . . . . . 14
CPURST Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
CX Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
D
DC DC Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Descriptor Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17, 30–31
Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Dynamic
core frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
core frequency control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
core voltage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 15
‰
F
Frequency
dynamic core frequency control. . . . . . . . . . . . . . . . . . . . . 10
maximum frequency initialization (recommended). . . . . 21
minimum frequency initialization . . . . . . . . . . . . . . . . . . . 20
selecting maximum CPU core frequency . . . . . . . . . . . . . .9
selecting minimum CPU core frequency. . . . . . . . . . . . . . . 9
Frequently Asked Questions . . . . . . . . . . . . . . . . . . . . . . . . . 39
G
Generate Special Bus Cycle (GSBC) . . . . . . . . . . . . . . . . . . . . 4
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–13, 24
Ground
pin designations (table) . . . . . . . . . . . . . . . . . . . . . . . 35, 37
regulator inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12, 24
regulator inputs (table). . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
GSBC Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5, 7
H
Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
core frequency and voltage control . . . . . . . . . . . . . . . . . . 20
example implementation (figure) . . . . . . . . . . . . . . . . . . . 19
gating PGOOD during a voltage transition . . . . . . . . . . . . 26
gating PGOOD signal with maximum frequency initialization (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
logic AND gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17, 40
safe voltage and frequency combination at reset . . . . . . 20
SPWRGD signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 17, 20, 26
VID[4:0] modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
VID[4:0] modification for maximum frequency initialization (figure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
voltage versus frequency options. . . . . . . . . . . . . . . . . . . . 22
41
Preliminary Information
23542A/0—September 2000
I
I/O BASE Address (IOBASE) . . . . . . . . . . . . . . . . . . . . . . . 4, 16
IBF Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 10
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Inquire Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
not supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Internal BF Divisor (IBF) . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 11
IOBASE Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5, 16
M
Maxim 1711 DC ‡C Regulator . . . . . . . . . . . . . . . . . . . . . 18, 24
Memory
completing accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
disabling accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
updating table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Microsoft® Windows® Driver . . . . . . . . . . . . . . . . . . . . . . . . 29
Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
‰
N
NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
unused VID[4:0] outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 12
North Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
O
OBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
pin designations by function (table) . . . . . . . . . . . . . . . . . 36
Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Output Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
P
PCI Bus
control during state transitions . . . . . . . . . . . . . . . . . . . . . 32
reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26, 40
PCIRST# Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26, 40
PGOOD Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
gating during voltage transition . . . . . . . . . . . . . . . . . . . . 26
Pins
new output pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
pinout information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Power-on Self Test (POST) . . . . . . . . . . . . . . . . . . . . . .5, 16–17
Processor
core frequency control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
dynamic core frequency control . . . . . . . . . . . . . . . . . . . . 10
maximum core frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . 9
minimum core frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Processor State Observability Register (PSOR) . . . . . . . . . . 9
Processor-to-Bus Clock Ratios (table) . . . . . . . . . . . . . . . . . . . 8
PSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
R
Real-Time Operating System . . . . . . . . . . . . . . . . . . . . . . . . . 28
Registers
CX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
enhanced power management (EPMR) . . . . . . . . . . . . . 3–4
ESI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
general-purpose. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
processor state observability (PSOR) . . . . . . . . . . . . . . . . . 9
42
Regulator
D[4:0] to VID[4:0] mapping . . . . . . . . . . . . . . . . . . . . .20–21
DC/DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
driving input select pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
external logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Maxim 1711 DC/DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PGOOD signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
pin connections (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
using a subset of CPU VID outputs (table). . . . . . . . . . . . 13
Reserved (RSVD) Pins
pin designations (table) . . . . . . . . . . . . . . . . . . . . . . . 35, 37
Reset
hardware initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
safe voltage and frequency combination . . . . . . . . . . . . . 20
RESET Signal
BVC effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
EBF value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
EPM I/O block effect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
EPMR effect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3–4
selecting maximum CPU core frequency . . . . . . . . . . . . . .9
selecting maximum frequency initialization . . . . . . . . . . 21
selecting minimum CPU core frequency. . . . . . . . . . . . . . . 9
selecting minimum frequency initialization . . . . . . . . . . . 20
state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
VID[4:0] effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
RTOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
enabling AMD PowerNow! technology features . . . . . . . . . 5
initializing the EPM I block after reset . . . . . . . . . . . . . . . 5
initializing the EPMR register after reset . . . . . . . . . . . . .3
using a different CPU core frequency. . . . . . . . . . . . . . . . 20
‰
S
SGTC Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 11, 16–17
Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SMI Command Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29–31
SMM Handler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16, 29
accessing the EPM I block . . . . . . . . . . . . . . . . . . . . . . . . . 10
accessing the EPMR register . . . . . . . . . . . . . . . . . . . . . . . .7
core voltage and frequency transitions . . . . . . . . . . . . 7, 10
dynamic core voltage control . . . . . . . . . . . . . . . . . . . . . . . 15
enabling AMD PowerNow! technology features . . . . . . . . . 5
initiating a special bus cycle . . . . . . . . . . . . . . . . . . . . . . . . 7
using RSM instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Snoop Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
not supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Software Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AMD PowerNow!™ Technology descriptor table . . . . . . . 30
initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
state transition event sequence . . . . . . . . . . . . . . . . . . . . . 32
using a BIOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
using a Microsoft® Windows® driver . . . . . . . . . . . . . . . . 29
using an RTOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
using an SMM handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
South Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26, 29–30
Special Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SPWRGD Signal . . . . . . . . . . . . . . . . . . . . . . 14, 17, 24, 26, 40
State Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
‰
Preliminary Information
24267A/0—December 2000
State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
controlling with BVC field . . . . . . . . . . . . . . . . . . . . . . . . . . 6
event sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Stop Grant Time-Out Counter (SGTC) . . . . . . . . . . . . . . . . . 11
Strapping Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . 9, 14
System Management Mode (SMM) . . . . . . . . . . . . . . . . . . . . 29
System Power Good (SPWRGD) Signal . . . . . . . . . . . . . . . . 14
T
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
V
VCC2 Pins
core voltage of 1.5 V at power-up . . . . . . . . . . . . . . . . . . . 20
initialized to 2.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
pin designations (table) . . . . . . . . . . . . . . . . . . . . . . . . 35, 37
VCC3 Pins
pin designations (table) . . . . . . . . . . . . . . . . . . . . . . . . 35, 37
VID[4:0] Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
input-to-output voltage codes (table) . . . . . . . . . . . . . . . . 13
modification for maximum BF[2:0] boot option . . . . . . . 24
outputs not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11, 14, 33
using all outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
voltage ID control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
voltage ID output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VIDC Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11, 16
VIDO Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 10–11, 15
Voltage
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
dynamic core voltage control. . . . . . . . . . . . . . . . . . . . . . . 15
PGOOD gating during transition. . . . . . . . . . . . . . . . . . . . 26
regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12–13, 17
safe voltage and frequency combination at Reset . . . . . 20
versus frequency options . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Voltage ID Control (VIDC). . . . . . . . . . . . . . . . . . . . . . . . 11, 16
Voltage ID Output (VIDO) . . . . . . . . . . . . . . . . . . . . . . . . . 7, 11
VSS Pins
pin designations (table) . . . . . . . . . . . . . . . . . . . . . . . . 35, 37
W
Windows® Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Preliminary Information
23542A/0—September 2000
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