ETC DHM0850ALS1B

Preliminary Release
TM
Mobile AMD Duron
Processor
Model 7 Data Sheet
Featuring:
Publication # 24068
Rev: F
Issue Date: December 2001
Preliminary Release
© 2001 Advanced Micro Devices, Inc. All rights reserved.
The contents of this document are provided in connection with Advanced
Micro Devices, Inc. (“AMD”) products. AMD makes no representations or
warranties with respect to the accuracy or completeness of the contents of
this publication and reserves the right to make changes to specifications and
product descriptions at any time without notice. No license, whether express,
implied, arising by estoppel or otherwise, to any intellectual property rights
is granted by this publication. Except as set forth in AMD’s Standard Terms
and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims
any express or implied warranty, relating to its products including, but not
limited to, the implied warranty of merchantability, fitness for a particular
purpose, or infringement of any intellectual property right.
AMD’s products are not designed, intended, authorized or warranted for use
as components in systems intended for surgical implant into the body, or in
other applications intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a situation where personal injury, death, or severe property or environmental damage may occur.
AMD reserves the right to discontinue or make changes to its products at any
time without notice.
Trademarks
AMD, the AMD Arrow logo, AMD Athlon, AMD Duron, and combinations thereof, AMD PowerNow!, and 3DNow!
are trademarks of Advanced Micro Devices, Inc.
HyperTransport is a trademark of the HyperTransport Technology Corporation.
MMX is a trademark of Intel Corporation.
Other product names used in this publication are for identification purposes only and may be trademarks of
their respective companies.
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Contents
List of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
2
Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
2.2
2.3
2.4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Push-Pull (PP) Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
AMD Duron System Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1
4.2
4.3
4.4
4.5
Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Working State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Stop Grant States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Probe State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
FID_Change State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Processor Performance States and the FID_Change
Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Connect and Disconnect Protocol . . . . . . . . . . . . . . . . . . . . . . 18
Connect Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SYSCLK Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Special Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5
CPUID Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6
Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1
7.2
7.3
7.4
7.5
Table of Contents
Mobile AMD Duron™ Processor Model 7 Upgrades Versus
the Mobile AMD Duron Processor Model 3 . . . . . . . . . . . . . . . 2
Mobile AMD Duron Processor Model 7 Microarchitecture
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Soft Voltage Identification (SOFTVID[4:0]) . . . . . . . . . . . . . 35
Frequency Identification (FID[3:0]) . . . . . . . . . . . . . . . . . . . . 35
VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . 35
iii
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
8
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Die Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.1
10.2
10.3
iv
Power-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Signal Sequence and Timing Description . . . . . . . . . . . . . . . . 53
Clock Multiplier Selection (FID[3:0]) . . . . . . . . . . . . . . . . . . . 56
Processor Warm Reset Requirements . . . . . . . . . . . . . . . . . . 56
Mobile AMD Duron Processor Model 7 and Northbridge
Reset Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.1
9.2
9.3
10
Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Valid Voltage and Frequency Combinations . . . . . . . . . . . . . 36
VCC_CORE AC and DC Characteristics . . . . . . . . . . . . . . . . 37
Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
VCC_CORE Voltage and Current . . . . . . . . . . . . . . . . . . . . . . 40
SYSCLK and SYSCLK# AC and DC Characteristics . . . . . . 41
AMD Duron System Bus AC and DC Characteristics . . . . . . 43
General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 45
Open Drain Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Thermal Diode Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 48
Reserved Pins DC Characteristics . . . . . . . . . . . . . . . . . . . . . 51
FID_Change Induced PLL Lock Time . . . . . . . . . . . . . . . . . . 52
Signal and Power-Up Requirements . . . . . . . . . . . . . . . . . . . . 53
8.1
9
24068F—December 2001
Pin Diagram and Pin Name Abbreviations . . . . . . . . . . . . . . 61
Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Detailed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
A20M# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
AMD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
AMD Duron System Bus Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Analog Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
CLKFWDRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
CLKIN and RSTCLK (SYSCLK) Pins . . . . . . . . . . . . . . . . . . . 78
CONNECT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
COREFB and COREFB# Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 78
CPU_PRESENCE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
DBRDY and DBREQ# Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
FERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
FID[3:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
FLUSH# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
IGNNE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
INIT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
INTR Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
K7CLKOUT and K7CLKOUT# Pins. . . . . . . . . . . . . . . . . . . . . 80
Table of Contents
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
NMI Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
PLL Bypass and Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
RSVD Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SADDIN[1:0]# and SADDOUT[1:0]# Pins . . . . . . . . . . . . . . . . 81
Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SOFTVID[4:0] and VID[4:0] Pins. . . . . . . . . . . . . . . . . . . . . . . 81
STPCLK# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
SYSCLK and SYSCLK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
THERMDA and THERMDC Pins . . . . . . . . . . . . . . . . . . . . . . . 83
VCCA Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
VREF_SYS Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
ZN and ZP Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
11
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.1
Standard Mobile AMD Duron Processor Model 7
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Appendix A Conventions, Abbreviations, and References . . . . . . . . . . . . . . . . . . . . 87
Signals and Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Data Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Abbreviations and Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Related Publications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
AMD Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Websites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table of Contents
v
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
vi
24068F—December 2001
Table of Contents
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
List of Figures
Figure 1.
Typical Mobile AMD Duron™ Processor Model 7 System
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2.
Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3.
Mobile AMD Duron Processor Model 7 Power Management
States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4.
SOFTVID Transition During the AMD Duron System Bus
Disconnect for FID_Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5.
AMD Duron System Bus Disconnect Sequence in the Stop
Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6.
Exiting the Stop Grant State and Bus Connect Sequence . . . . 21
Figure 7.
Northbridge Connect State Diagram . . . . . . . . . . . . . . . . . . . . . 22
Figure 8.
Processor Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9.
VCC_CORE Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 10. SYSCLK and SYSCLK# Differential Clock Signals . . . . . . . . . 41
Figure 11. SYSCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 12. General ATE Open Drain Test Circuit. . . . . . . . . . . . . . . . . . . . 47
Figure 13. Signal Relationship Requirements During Power-Up
Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 14. Mobile AMD Duron Processor Model 7 CPGA Package. . . . . . 59
Figure 15. Mobile AMD Duron Processor Model 7 Pin Diagram—
Topside View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 16. Mobile AMD Duron Processor Model 7 Pin Diagram—
Bottomside View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 17. OPN Example for the Mobile AMD Duron Processor
Model 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
List of Figures
vii
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
viii
24068F—December 2001
List of Figures
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
List of Tables
List of Tables
Table 1.
FID[4:0] SYSCLK Multiplier Combinations . . . . . . . . . . . . . . . 25
Table 2.
Processor Special Cycle Definition . . . . . . . . . . . . . . . . . . . . . . 27
Table 3.
Thermal Design Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 4.
Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 5.
SOFTVID[4:0] DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 35
Table 6.
FID[3:0] DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 7.
VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 35
Table 8.
Valid Voltage and Frequency Combinations . . . . . . . . . . . . . . 36
Table 9.
VCC_CORE AC and DC Characteristics . . . . . . . . . . . . . . . . . . 37
Table 10.
Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 11.
VCC_CORE Voltage and Current. . . . . . . . . . . . . . . . . . . . . . . . 40
Table 12.
SYSCLK and SYSCLK# DC Characteristics . . . . . . . . . . . . . . . 41
Table 13.
SYSCLK and SYSCLK# AC Characteristics . . . . . . . . . . . . . . . 42
Table 14.
AMD Duron™ System Bus DC Characteristics . . . . . . . . . . . . . 43
Table 15.
AMD Duron System Bus AC Characteristics . . . . . . . . . . . . . . . 44
Table 16.
General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . . 45
Table 17.
Thermal Diode Electrical Characteristics . . . . . . . . . . . . . . . . . 48
Table 18.
Guidelines for Platform Thermal Protection of the
Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 19.
Reserved Pins (N1, N3, and N5) DC Characteristics . . . . . . . . 51
Table 20.
FID_Change Induced PLL Lock Time . . . . . . . . . . . . . . . . . . . . 52
Table 21.
CPGA Mechanical Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 22.
Dimensions for the CPGA Package . . . . . . . . . . . . . . . . . . . . . . 58
Table 23.
Pin Name Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 24.
Cross-Reference by Pin Location . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 25.
SOFTVID[4:0] and VID[4:0] Code to Voltage Definition. . . . . 82
Table 26.
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 27.
Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
ix
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
x
24068F—December 2001
List of Tables
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Revision History
Date
Rev
Description
Updated data sheet for the 1.0 GHz AMD Duron Processor Model 7 release.
Revised the following sections:
December 2001
F
■
■
■
■
November 2001
E
Table 3, “Thermal Design Power,” on page 31
Table 8, “Valid Voltage and Frequency Combinations,” on page 36
Table 11, “VCC_CORE Voltage and Current,” on page 40
“Ordering Information” on page 85
Revised “Thermal Protection Characterization” on page 49.
Updated data sheet for the 950 MHz AMD Duron Processor Model 7 release.
Revised the following sections:
■
■
■
November 2001
D
■
■
■
“Processor Performance States and the FID_Change Protocol” on page 12
“SYSCLK Multipliers” on page 24
“Thermal Diode Characteristics” on page 48
Figure 13, “Signal Relationship Requirements During Power-Up Sequence” on page 53
“Power-Up Timing Requirements” on page 54
“Clock Multiplier Selection (FID[3:0])” on page 56
Added the following sections and figures:
■
■
“Open Drain Test Circuit” and Figure 12, “General ATE Open Drain Test Circuit” on page 47.
“Thermal Protection Characterization” on page 49 and Table 18, “Guidelines for Platform Thermal
Protection of the Processor,” on page 51
September 2001
C
Updated Figure 9 on page 38.
August 2001
B
Initial public release.
Revision History
xi
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
xii
24068F—December 2001
Revision History
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
1
Overview
The Mobile AMD Duron™ Processor Model 7 enables an optimized
PC solution for value-conscious business and home users by
providing the capability and flexibility to meet their computing
needs for both today and tomorrow.
The mobile AMD Duron™ processor model 7 is the latest
offering from AMD designed for the value segment of the
notebook PC market. The innovative design was developed to
accommodate new and more advanced applications, meeting
the requirements of today's most demanding value-conscious
buyers without compromising their budget. Model 7 is the CPU
model number returned by the CPUID instruction for this
processor. See Chapter 5, “CPUID Support” on page 29 for
more information.
Delivered in a CPGA package, the mobile AMD Duron
processor model 7 is the new AMD workhorse processor for
value notebook systems, delivering high performance integer,
floating-point and 3D multimedia capabilities for applications
running on notebook PC platforms. The mobile AMD Duron
processor model 7 provides value-conscious customers with
access to advanced technology that allows their system
investment to last for years to come.
Whether at work or at play, the mobile AMD Duron processor
model 7 provides an optimum balance of performance and
value for today’s advanced operating system software, business
productivity applications, Internet computing and digital
entertainment.
The m obile AMD Duron processor model 7 feat ures a
seventh-generation microarchitecture with a full-speed
integrated L2 cache, which supports the growing processor and
system bandwidth requirements of emerging software,
graphics, I/O, and memory technologies. The high-speed
execution core of the processor includes multiple x86
instruction decoders, a dual-ported 128-Kbyte split level-one
(L1) cache, a 64-Kbyte on-chip L2 cache, three independent
integer pipelines, three address calculation pipelines, and a
s u p e rs c a l a r, f u l ly p i p e l i n e d , o u t -o f -o rd e r, t h re e -way
floating-point engine. The floating-point engine is capable of
delivering 4.0 gigaflops (Gflops) of single-precision and more
than 2.0 Gflops of double-precision floating-point results at
Chapter 1
Overview
1
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
1.0 GHz, for superior performance on numerically complex
applications.
This processor incorporates AMD PowerNow!™ technology,
enabling performance and power saving modes specifically for
notebook designs and is available in a low-profile, lidless CPGA
package.
The mobile AMD Duron processor model 7 microarchitecture
incorporates AMD’s 3DNow!™ Professional technology, a
high-performance cache architecture, and the 200-MHz
1. 6-G igabyt e per se cond A MD D uron s yst em bus. The
AMD Duron system bus combines the latest technological
advances, such as point-to-point topology, source-synchronous
packet-based transfers, and low-voltage signaling, to provide a
powerful, scalable bus architecture.
The mobile AMD Duron processor model 7 is binary-compatible
with existing x86 software and substantially compatible with
applications optimized for 3DNow! Professional, MMX™, and
SSE instructions. AMD’s 3DNow! Professional technology
implemented in the mobile AMD Duron processor model 7
includes new integer mult imedia instructions and
software-directed data movement instructions to deliver
exceptional performance in multimedia applications.
1.1
Mobile AMD Duron™ Processor Model 7 Upgrades Versus the
Mobile AMD Duron™ Processor Model 3
The following features summarize the mobile AMD Duron
processor model 7 feature upgrades and differences from the
mobile AMD Duron processor model 3:
■
■
■
2
AMD PowerNow! technology for improved battery life
• Model Specific Registers (MSRs) and SOFTVID and FID
control pins which are compatible with the mobile
AMD Athlon™ processor model 6
• Automatic load sense
Redesigned core, optimized for lower power and improved
frequency scalability
On-die temperature sensing diode
Overview
Chapter 1
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
1.2
Mobile AMD Duron™ Processor Model 7 Microarchitecture
Summary
The following features summarize the mobile AMD Duron
processor model 7 microarchitecture:
■
Performance on demand and extended battery life
specifically for notebook designs with AMD PowerNow!
technology
■
The industry's first nine-issue, superpipelined, superscalar
x86 processor microarchitecture designed for high clock
frequencies
Multiple x86 instruction decoders
Three
out-of-order,
superscalar,
fully
pipelined
floating-point execution units, which execute all x87
(floating-point), SSE, MMX, and 3DNow! Professional
instructions
Three out-of-order, superscalar, pipelined integer units
Three
out-of-order,
superscalar,
pipelined
address
calculation units
■
■
■
■
■
■
■
■
■
Chapter 1
72-entry instruction control unit
Advanced dynamic branch prediction
3DNow! Professional technology with added instructions to
enable improved integer math calculations for speech or
video encoding and improved data movement for internet
plug-ins and other streaming applications
200-MHz AMD Duron system bus for high-performance main
memory access, multimedia, graphics, and I/O
High-performance cache architecture featuring an
integrated 128-Kbyte L1 cache and a 16-way, on-chip
64-Kbyte L2 cache
Overview
3
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
The mobile AMD Duron processor model 7 delivers superior
n o t eb o ok P C sy s t e m p e r fo rm a n c e in a c o s t -e f f e c t ive ,
industry-standard Socket A compatible 462-pin CPGA package.
Figure 1 shows a typical mobile AMD Duron processor model 7
system block diagram.
Thermal Monitor
Mobile AMD Duron™
Processor Model 7
Programmable
Voltage Regulator
AGP Bus
AMD Duron
System Bus
AGP
Memory Bus
System Controller
(Northbridge)
SDRAM or DDR
PCI Bus
Peripheral Bus
Controller
(Southbridge)
LAN
PC Card
Docking
Controller
Modem / Audio
ISA or LPC
USB
Dual EIDE
Super I/O
Embedded Controller
Battery
Figure 1. Typical Mobile AMD Duron™ Processor Model 7 System Block Diagram
4
Overview
Chapter 1
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
2
2.1
Interface Signals
Overview
The AMD Duron™ system bus architecture is designed to
delive r excellent da ta movement bandwidth for nextgeneration x86 platforms as well as the high-performance
required by enterprise-class application software. The system
bus architecture consists of three high-speed channels (a
unidirectional processor request channel, a unidirectional
probe channel, and a 72-bit bidirectional data channel),
source-synchronous clocking, and a packet-based protocol. In
addition, the system bus supports several control, clock, and
legacy signals. The interface signals use an impedance
controlled push-pull, low-voltage, swing-signaling technology
contained within the Socket A socket.
For more information, see “AMD Duron™ System Bus Signals”
on page 6, Chapter 10, “Pin Descriptions” on page 61, and the
AMD Athlon™ and AMD Duron™ System Bus Specification,
order# 21902.
2.2
Signaling Technology
The AMD Duron system bus uses a low-voltage, swing-signaling
technology, that has been enhanced to provide larger noise
margins, reduced ringing, and variable voltage levels. The
signals are push-pull and impedance compensated. The signal
inputs use differential receivers that require a reference
voltage (VREF). The reference signal is used by the receivers to
determine if a signal is asserted or deasserted by the source.
Termination resistors are not needed because the driver is
impedance-matched to the motherboard and a high impedance
reflection is used at the receiver to bring the signal past the
input threshold.
For more information about pins and signals, see Chapter 10,
“Pin Descriptions” on page 61.
Chapter 2
Interface Signals
5
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
2.3
24068F—December 2001
Push-Pull (PP) Drivers
The mobile AMD Duron processor model 7 supports Push-Pull
(PP) drivers. The system logic configures the processor with the
configuration parameter called SysPushPull (1=PP). The
impedance of the PP drivers is set to match the impedance of
the motherboard by two external resistors connected to the ZN
and ZP pins.
See “ZN and ZP Pins” on page 83 for more information.
2.4
AMD Duron™ System Bus Signals
The AMD Duron system bus is a clock-forwarded, point-to-point
interface with the following three point-to-point channels:
■
■
■
A 13-bit unidirectional output address/command channel
A 13-bit unidirectional input address/command channel
A 72-bit bidirectional data channel
For more information, see Chapter 7, “Electrical Data” on page
33 and the AMD Athlon™ and AMD Duron™ System Bus
Specification, order# 21902.
6
Interface Signals
Chapter 2
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
3
Logic Symbol Diagram
Figure 2 is the logic symbol diagram of the processor. This
diagram shows the logical grouping of the input and output
signals.
Clock
SYSCLK
SYSCLK#
SDATA[63:0]#
SDATAINCLK[3:0]#
Data
SDATAOUTCLK[3:0]#
SDATAINVALID#
SDATAOUTVALID#
FID[3:0]
SFILLVALID#
Probe/SysCMD
Request
Power
Management
and Initialization
SADDIN[14:2]#
SADDINCLK#
SOFTVID[4:0]
VID[4:0]
COREFB
COREFB#
PWROK
Mobile AMD Duron™
Processor Model 7
SADDOUT[14:2]#
SADDOUTCLK#
PROCRDY
CLKFWDRST
CONNECT
STPCLK#
RESET#
FERR
IGNNE#
INIT#
INTR
NMI
A20M#
SMI#
FLUSH#
THERMDA
THERMDC
Voltage
Control
Frequency
Control
Legacy
Thermal
Diode
Figure 2. Logic Symbol Diagram
Chapter 3
Logic Symbol Diagram
7
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
8
Logic Symbol Diagram
24068F—December 2001
Chapter 3
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
4
Power Management
This chapter describes the power management features of the
m o bi l e A M D D u ro n ™ p ro c e s s o r m o d e l 7 . The p owe r
management features of the processor are compliant with the
AC P I 1 . 0 b a n d AC P I 2 . 0 s p e c i f i c a t i o n s a n d s u p p o r t
AMD PowerNow!™ technology.
4.1
Power Management States
The mobile AMD Duron™ processor model 7 has a variety of
operating states that are designed to support different power
management goals. In addition to the standard operating state,
the processor supports low-power Halt and Stop Grant states
and the FID_Change state. These states are used by Advanced
Configuration and Power Interface (ACPI) enabled operating
systems, for processor power management. AMD PowerNow!
software is used to control processor performance states with
operating systems that do not support ACPI 2.0-defined
processor performance state control.
Figure 3 on page 10 shows the power management states of the
processor. The figure includes t he ACPI “Cx” naming
convention for these states.
Chapter 4
Power Management
9
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Write to FidVidCtl MSR
Execute HLT
C1
Halt
C0
Working4
SMI#, INTR, NMI, INIT#, RESET#
Probe Serviced
STPCLK# deasserted
Incoming Probe
STPCLK# asserted
PC
LK
#d
ST
ea
PC
sse
LK
rte
#a
d3
sse
rte
d2
(Read PLVL2 register
or throttling)
Probe Serviced
Incoming Probe
Probe
State1
ST
FID_Change
SIP Stream and
System Bus Connect
ST
ST
PC
LK
#
PC
LK
#
ass
e
de
ass
ert
ed
rte
d
C3/S1
Stop Grant
Cache Not Snoopable
Sleep
C2
Stop Grant
Cache Snoopable
Legend
Hardware transitions
Software transitions
Note:
The AMD DuronTM System Bus is connected during the following states:
1) The Probe state
2) During transitions between the Halt state and the C2 Stop Grant state
3) During transitions between the C2 Stop Grant state and the Halt state
4) C0 Working state
Figure 3. Mobile AMD Duron™ Processor Model 7 Power Management States
The following sections provide an overview of the power
management states. For more details, refer to the AMD Athlon™
and AMD Duron™ System Bus Specification, order# 21902.
Note: In all power management states that the processor is
powered, the system must not stop the system clock
(SYSCLK/SYSCLK#) to the processor.
Working State
The Working state is the state in which the processor is executing
instructions.
Halt State
When the processor executes the HLT instruction, the processor
enters the Halt state and issues a Halt special cycle to the
AMD Duron system bus. The processor only enters the low power
state dictated by the CLK_Ctl MSR if the system controller
(Northbridge) disconnects the AMD Duron system bus in
response to the Halt special cycle.
10
Power Management
Chapter 4
Preliminary Information
24068F—December 2001
Mobile AMD Duron™ Processor Model 7 Data Sheet
If STPCLK# is asserted, the processor will exit the Halt state
and enter the Stop Grant state. The processor will initiate a
system bus connect, if it is disconnected, then issue a Stop
Grant special cycle. When STPCLK# is deasserted, the
processor will exit the Stop Grant state and re-enter the Halt
state. The processor will issue a Halt special cycle when
re-entering the Halt state.
The Halt state is exited when the processor detects the
assertion of INIT#, INTR, NMI, RESET#, or SMI#. When the
Halt state is exited the processor will initiate an AMD Duron
system bus connect if it is disconnected.
Stop Grant States
When the processor executes the HLT instruction, the processor
enters the Halt state and issues a Halt special cycle to the
AMD Duron system bus. The processor only enters the low
power state dictated by the CLK_Ctl MSR if the system
controller (Northbridge) disconnects the AMD Duron system
bus in response to the Halt special cycle.
If STPCLK# is asserted, the processor will exit the Halt state
and enter the Stop Grant state. The processor will initiate a
system bus connect, if it is disconnected, then issue a Stop
Grant special cycle. When STPCLK# is deasserted, the
processor will exit the Stop Grant state and re-enter the Halt
state. The processor will issue a Halt special cycle when
re-entering the Halt state.
The Halt state is exited when the processor detects the
assertion of INIT#, INTR, NMI, RESET#, or SMI#. When the
Halt state is exited the processor will initiate an AMD Duron
system bus connect if it is disconnected.
In C2, probes are allowed, as shown in Figure 3 on page 10.
The operating system places the processor into the C3 Stop
Grant state by reading the P_LVL3 register in the Southbridge.
In C3, the operating system and Northbridge hardware enforce
a policy that prevents the processor from being probed. The
Southbridge will deassert STPCLK# and bring the processor
out of the C3 Stop Grant state if a bus master request, interrupt,
or any other enabled resume event occurs.
The Stop Grant state is also entered for the S1, Powered On
Suspend, system sleep state based on a write to the SLP_TYP
Chapter 4
Power Management
11
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
and SLP_EN fields in the ACPI-defined Power Management 1
control register in the Southbridge. During the S1 sleep state,
system software ensures no bus master or probe activity occurs.
The Southbridge deasserts STPCLK# and brings the processor
out of the S1 Stop Grant state when any enabled resume event
occurs.
Probe State
The Probe state is entered when the Northbridge connects the
AMD Duron system bus to probe the processor (for example, to
snoop the processor caches) when the processor is in the Halt or
Stop Grant state. When in the Probe state, the processor
responds to a probe cycle in the same manner as when it is in
the Working state. When the probe has been serviced, the
processor returns to the same state as when it entered the
Probe state (Halt or Stop Grant state). When probe activity is
completed the processor only returns to a low-power state after
the Northbridge disconnects the AMD Duron system bus again.
FID_Change State
The FID_Change State is part of the AMD Duron system bus
FID_Change Protocol. During the FID_Change state the
Frequency Identification (FID[4:0]) code that determines the
core frequency of the processor and Voltage Identification
(VID[4:0]) driven on the SOFTVID[4:0] pins are transitioned to
change the core frequency and core voltage of the processor.
Note: The FID[3:0] pins of the processor do not transition as part
of the FID_Change protocol.
Processor
Performance States
and the FID_Change
Protocol
The FID_Change protocol is used by AMD PowerNow! software
to transition the processor from one performance state to
another. The FID_Change protocol is also used for ACPI
2.0-compliant processor performance state control.
Processor performance states are combinations of processor
core voltage and core frequency. Processor performance states
are used in mobile systems to optimize the power consumption
of the processor (and therefore battery powered run-time)
based upon processor utilization.
See “Valid Voltage and Frequency Combinations” on page 36
for more information.
The core frequency is determined by a 5-bit Frequency ID (FID)
code. The core voltage is determined by a 5-bit Voltage ID (VID)
code.
12
Power Management
Chapter 4
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
■
Before PWROK is asserted to the processor, the VID[4:0]
outputs of the processor dictate the core voltage level of the
processor.
■
After PWROK is asserted, the core voltage of the processor
is dictated by the SOFTVID[4:0] outputs. The SOFTVID[4:0]
outputs of the processor are not driven to a deterministic
value until after PWROK is asserted to the processor. The
motherboard therefore must provide a ‘VID Multiplexer’ to
drive the VID[4:0] outputs to the DC/DC converter for the
core voltage of the processor before PWROK is asserted and
drive the SOFTVID[4:0] outputs to the DC to DC converter
after PWROK is asserted.
The FID[3:0] signals are valid after PWROK is asserted. The
chipset must not sample the FID[3:0] signals until they
become valid.
■
■
■
After RESET# is deasserted, the FID[3:0] outputs are not
used to transmit FID information for subsequent software
controlled changes in the operating frequency of the
processor.
Processor performance state transitions are required to
occur as two separate transitions. The order of these
transitions depends on whether the transition is to a higher
or lower performance state. When transitioning from a lower
performance state to a higher performance state the order
of the transitions is:
1. The FID_Change protocol is used to transition to the
higher voltage, while keeping the frequency fixed at
the current setting.
2. The FID_Change protocol is then used to transition to
the higher frequency, while keeping the voltage fixed
at the higher setting.
When transitioning from a high performance state to a
lower performance state the order of the transitions is:
1. The FID_Change protocol is used to transition to the
lower frequency, while keeping the voltage fixed at its
current setting.
■
Chapter 4
2. The FID_Change protocol is then used to transition to
the lower voltage, while keeping the frequency fixed at
the lower setting.
The processor provides two MSRs to support the
FID_Change protocol: the FidVidCtl MSR and the
Power Management
13
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
FidVidStatus MSR. For a definition of these MSRs and their
use, refer to the Mobile AMD Athlon™ and Mobile
AMD Duron™ Processors BIOS Developers Application Note,
order# 24141.
FID_Change Protocol Description By Example:
Note: In any FID_Change transition only the core voltage or core
frequency of the processor is transitioned. Two FID_Change
transitions are required to transition the voltage and
frequency to a valid performance state. When the voltage is
being transitioned, the frequency is held constant by
transitioning to the same FID[3:0] as the current FID
reported in the FidVidStatus MSR.
For detailed information on the optimized voltage and
frequency combinations, see “Valid Voltage and Frequency
Combinations” on page 36.
■
■
14
System software determines that a change in processor
performance state is required.
System software executes a WRMSR instruction to write to
the FidVidCtl MSR to dictate:
• The new VID[4:0] code that will be driven to the DC/DC
converter from the SOFTVID[4:0] outputs of the
processor that selects the new core voltage level.
• The new FID[4:0] code that will be used by the processor
to dictate its new operating frequency.
• A Stop Grant Timout Count (SGTC)[19:0] value that
determines how many SYSCLK/SYSCLK# 100-MHz clock
periods the processor will remain in the FID_Change
state. This time accounts for the time that it takes for the
PLL of the processor to lock to the new core frequency
and the time that it takes for the core voltage of the
processor to ramp to the new value.
• The FIDCHGRATIO bit must be set to 1.
• The VIDC bit must be set to a 1 if the voltage is going to
be changed.
• The FIDC bit must be set to a 1 if the frequency is going
to be changed.
Writing the SGTC field to a non-zero value initiates the
FID_Change protocol.
Power Management
Chapter 4
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
■
■
■
■
■
■
■
■
Chapter 4
On the instruction boundary that the SGTC field of the
FidVidCtl MSR is written to a non-zero value, the processor
stops code execution and issues a FID_Change special cycle
on the AMD Duron system bus.
The FID_Change special cycle has a data encoding of
0007_0002h that is passed on SDATA[31:0].
SDATA[36:32] contain the new FID[4:0] code during the
FID_Change special cycle. The Northbridge is required to
capture this FID[4:0] code when the FID_Change special
cycle is run.
In response to receiving the FID_Change special cycle, the
Northbridge is required to disconnect. The Northbridge will
complete any in-progress bus cycles and then disable its
arbiter before disconnecting the AMD Duron system bus so
that it will not initiate a AMD Duron system bus connect
based on bus master or other activity. The Northbridge must
disconnect the AMD Duron system bus or the system will
hang because the processor is not executing any operating
system or application code and is waiting for the
AMD Duron system bus to disconnect so that it can continue
with the FID_Change protocol. The Northbridge initiates an
AMD Duron system bus disconnect in the usual manner: it
deasserts CONNECT.
The processor allows the disconnect to complete by
deasserting PROCRDY. The Northbridge completes the
disconnect by asserting CLKFWDRST.
Once the AMD Duron system bus has been disconnected in
response to a FID_Change special cycle, the Northbridge is
not allowed to initiate a re-connect, the processor is
responsible for the eventual re-connect.
After the AMD Duron system bus is disconnected, the
processor enters a low-power state where the clock grid is
ramped down by a value specified in the CLK_Ctl MSR.
After entering the low-power state, the processor will:
• begin counting down the value that was programmed into
the SGTC field
• drive the new VID[4:0] value on SOFTVID[4:0], causing
its core voltage to transition
• drive the new FID[4:0] value to its PLL, causing the PLL
to lock to the new core frequency.
Power Management
15
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
■
■
■
■
16
24068F—December 2001
When the SGTC count reaches zero, the processor will ramp
its entire clock grid to full frequency (the PLL is already
locked to) and signal that it is ready for the Northbridge to
transmit the new SIP (Serial Initialization Protocol) stream
associated with the new processor core operating frequency.
The processor signals this by pulsing PROCRDY high and
then low.
The Northbridge responds to this high pulse on PROCRDY
by pulsing CLKFWDRST low and then transferring a SIP
stream as it does after PROCRDY is deasserted after the
deassertion of RESET#. The difference is that the SIP
stream that the Northbridge transmits to the processor now
corresponds to the FID[4:0] that was transmitted on
SDATA[36:32] during the FID_Change special cycle.
After the SIP stream is transmitted, the processor initiates
the AMD Duron system bus connect sequence by asserting
PROCRDY. The Northbridge responds by deasserting
CLKFWDRST. The forward clocks are started and the
processor issues a Connect special cycle.
The AMD Duron system bus connection causes the processor
to resume execution of operating system and application
code at the instruction that follows the WRMSR to the
FidVidCtl MSR that started the FID_Change protocol and
processor performance state transition.
Power Management
Chapter 4
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Figure 4 below illustrates the processor SOFTVID transition during the
AMD Duron system bus disconnect in response to a FID_Change
special cycle.
< 100 µs
1.4 V
CPUCOREVCC
SOFTVID[4:0] from the
processor
1.2 V
VID combination that selects 1.2 V
VID combination that
selects 1.4 V
ProcRdy
Connect
ClkFwdRst
The processor core frequency changes and new
SOFTVID[4:0] values are driven after the system
bus interface disconnect occurs and the
processor has entered a low power state. The
duration of the disconnect is dictated by
software programming the FidVidControl MSR in
the processor.
Figure 4. SOFTVID Transition During the AMD Duron™ System Bus Disconnect for FID_Change
Chapter 4
Power Management
17
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
4.2
24068F—December 2001
Connect and Disconnect Protocol
Significant power savings of the processor only occur if the
processor is disconnected from the system bus by the Northbridge
while in the Halt or Stop Grant state. The Northbridge can
optionally initiate a bus disconnect upon the receipt of a Halt or
Stop Grant special cycle. The option of disconnecting is controlled
by an enable bit in the Northbridge. If the Northbridge requires
the processor to service a probe after the system bus has been
disconnected, it must first initiate a system bus connect.
Connect Protocol
In addition to the legacy STPCLK# signal and the Halt and Stop
Grant special cycles, the AMD Duron system bus connect protocol
includes the CONNECT, PROCRDY, and CLKFWDRST signals and
a Connect special cycle.
AMD Duron system bus disconnects are initiated by the
Northbridge in response to the receipt of a Halt, Stop Grant, or
FID_Change special cycle. Reconnect is initiated by the processor
in response to an interrupt for Halt, STPCLK# deassertion, or
completion of a FID_Change transition. Reconnect is initiated by
the Northbridge to probe the processor. The Northbridge contains
BIOS programmable registers to enable the system bus disconnect
in response to Halt and Stop Grant special cycles. When the
Northbridge receives the Halt or Stop Grant special cycle from the
processor and, if there are no outstanding probes or data
movements, the Northbridge deasserts CONNECT a minimum of
eight SYSCLK periods after the last command sent to the
processor. The processor detects the deassertion of CONNECT on a
r i s i n g e d g e o f S YS C L K a n d d e a s s e r t s P RO C R DY t o t h e
Northbridge. In return, the Northbridge asserts CLKFWDRST in
anticipation of reestablishing a connection at some later point.
Note: The Northbridge must disconnect the processor from the
AMD Duron system bus before issuing the Stop Grant special
cycle to the PCI bus or passing the Stop Grant special cycle to
the Southbridge for systems that connect to the Southbridge
with HyperTransport™ technology.
This note applies to current chipset implementation—
alternate chipset implementations that do not require this are
possible.
Note: In response to Halt special cycles, the Northbridge passes the
Halt special cycle to the PCI bus or Southbridge immediately.
18
Power Management
Chapter 4
Preliminary Information
24068F—December 2001
Mobile AMD Duron™ Processor Model 7 Data Sheet
The processor can receive an interrupt after it sends a Halt
special cycle, or STPCLK# deassertion after it sends a Stop
Grant special cycle to the Northbridge but before the
disconnect actually occurs. In this case, the processor sends the
Connect special cycle to the Northbridge, rather than
continuing with the disconnect sequence. In response to the
Connect special cycle, the Northbridge cancels the disconnect
request.
The system is required to assert the CONNECT signal before
returning the C-bit for the connect special cycle (assuming
CONNECT has been deasserted).
For more information, see the AMD Athlon™ and AMD Duron™
System Bus Specification, order# 21902 for the definition of the
C-bit and the Connect special cycle.
Chapter 4
Power Management
19
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Figure 5 shows STPCLK# assertion resulting in the processor in the
Stop Grant state and the AMD Duron system bus disconnected.
STPCLK#
AMD Duron™
System Bus
Stop Grant
CONNECT
PROCRDY
CLKFWDRST
Stop Grant
PCI Bus
Figure 5. AMD Duron™ System Bus Disconnect Sequence in the Stop Grant State
An example of the AMD Duron system bus disconnect sequence is as
follows:
1. The peripheral controller (Southbridge) asserts STPCLK# to
place the processor in the Stop Grant state.
2. When the processor recognizes STPCLK# asserted, it enters the
Stop Grant state and then issues a Stop Grant special cycle.
3. When the special cycle is received by the Northbridge, it
deasserts CONNECT, assuming no probes are pending, initiating
a bus disconnect to the processor.
4. The processor responds to the Northbridge by deasserting
PROCRDY.
5. The Northbridge asserts CLKFWDRST to complete the bus
disconnect sequence.
6. After the processor is disconnected from the bus, the processor
enters a low-power state. The Northbridge passes the Stop Grant
special cycle along to the Southbridge.
20
Power Management
Chapter 4
Preliminary Information
24068F—December 2001
Mobile AMD Duron™ Processor Model 7 Data Sheet
Figure 6 shows the signal sequence of events that takes the
processor out of the Stop Grant state, connects the processor to the
AMD Duron system bus, and puts the processor into the Working
state.
STPCLK#
PROCRDY
CONNECT
CLKFWDRST
Figure 6. Exiting the Stop Grant State and Bus Connect Sequence
The following sequence of events removes the processor from the
Stop Grant state and connects it to the system bus:
1. The Southbridge deasserts STPCLK#, informing the processor of
a wake event.
2. When the processor recognizes STPCLK# deassertion, it exits
the low-power state and asserts PROCRDY, notifying the
Northbridge to connect to the bus.
3. The Northbridge asserts CONNECT.
4. The Northbridge deasserts CLKFWDRST, synchronizing the
forwarded clocks between the processor and the Northbridge.
5. The processor issues a Connect special cycle on the system bus
and resumes operating system and application code execution.
Chapter 4
Power Management
21
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
Connect State
Diagram
24068F—December 2001
Figure 7 and Figure 8 on page 23 describe the Northbridge and
processor connect state diagrams, respectively.
4/A
1
2/A
Disconnect
Pending
Disconnect
Requested
Connect
3
3/C
5/B
8
8
Reconnect
Pending
Disconnect
Probe
Pending 2
7/D,C
6/C
7/D
Probe
Pending 1
Condition
Action
1 A disconnect is requested and probes are still pending.
2 A disconnect is requested and no probes are pending.
A
Deassert CONNECT eight SYSCLK periods
after last SysDC sent.
3 A Connect special cycle from the processor.
B Assert CLKFWDRST.
4 No probes are pending.
C Assert CONNECT.
5 PROCRDY is deasserted.
D Deassert CLKFWDRST.
6 A probe needs service.
7 PROCRDY is asserted.
Three SYSCLK periods after CLKFWDRST is deasserted.
Although reconnected to the system interface, the
8 Northbridge must not issue any non-NOP SysDC
commands for a minimum of four SYSCLK periods after
deasserting CLKFWDRST.
Figure 7. Northbridge Connect State Diagram
22
Power Management
Chapter 4
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Connect
6/B
1
2/B
Connect
Pending 2
Disconnect
Pending
5
Connect
Pending 1
3/A
Disconnect
4/C
Condition
1
Action
CONNECT is deasserted by the Northbridge (for a
previously sent Halt or Stop Grant special cycle).
Processor receives a wake-up event and must cancel
2
the disconnect request.
3 Deassert PROCRDY and slow down internal clocks.
4
Processor wake-up event or CONNECT asserted by
Northbridge.
A CLKFWDRST is asserted by the Northbridge.
B Issue a Connect special cycle.*
C
Return internal clocks to full speed and assert
PROCRDY.
Note:
* The Connect special cycle is only issued after a
5 CLKFWDRST is deasserted by the Northbridge.
6
Forward clocks start three SYSCLK periods after
CLKFWDRST is deasserted.
processor wake-up event (interrupt or STPCLK#
deassertion) occurs. If the AMD Duron™ system
bus is connected so the Northbridge can probe the
processor, a Connect special cycle is not issued at
that time (it is only issued after a subsequent
processor wake-up event).
Figure 8. Processor Connect State Diagram
Chapter 4
Power Management
23
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
4.3
24068F—December 2001
Clock Control
The processor implements a Clock Control (CLK_Ctl) MSR
(address C001_001Bh) that determines the internal clock
divisor when the AMD Duron system bus is disconnected.
Refer to the AMD Athlon™ and AMD Duron™ Processors BIOS,
Software, and Debug Developers Guide, order# 21656, for more
details on the CLK_Ctl register.
4.4
SYSCLK Multipliers
The processor provides two mechanisms for communicating
processor core operating frequency information to the
Northbridge. These are the processor FID[3:0] outputs and the
FID_Change special cycle. The FID[3:0] outputs specify the
core frequency of the processor as a multiple of the 100-MHz
input clock (SYSCLK/SYSCLK#) of the processor.
The FID[3:0] signals are valid after PWROK is asserted. The
chipset must not sample the FID[3:0] signals until they become
valid.The FID[3:0] outputs of the processor provide processor
operating frequency information that the Northbridge uses
when creating the SIP stream that the Northbridge sends to the
processor after RESET# is deasserted. The FID[3:0] outputs
always select a 5x SYSCLK multiplier:
FID[3:0] = 0 1 0 0
Software will use the FID_Change protocol to transition the
processor to the desired performance state.
The FID[3:0] outputs are not used as part of the FID_Change
protocol and do not change from their RESET# value during
software-controlled processor core frequency transitions.
The FID_Change special cycle is used to communicate
processor operating frequency information to the Northbridge
during software-controlled processor core voltage and
frequency (performance state) transitions. The FidVidCtl MSR
a l l ow s s o f t wa re t o s p e c i f y a 5 - b i t F I D va l u e d u r i n g
software-controlled processor performance state transitions.
The additional bit allows transitions to lower SYSCLK
multipliers of 3x to 4x as well as all other SYSCLK multipliers
supported by the processor.
24
Power Management
Chapter 4
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
For a description of the FID_Change protocol refer to the
earlier section in this chapter.
Table 1 lists the FID[4:0] SYSCLK multiplier codes for the
processor used by software to dictate the core frequency of the
processor and the 5-bit value driven on SDATA[36:32]# by the
processor during the FID_Change special bus cycle.
Note: Only clock multipliers associated with operating frequencies
specified in the “Electrical Data” chapter are valid for this
processor.
Note: Software distinguishes the speed grade of the processor by
reading the MFID field of the FidVidStatus MSR.
Table 1.
FID[4:0] SYSCLK Multiplier Combinations1
FID[4:0]2,3,5
Clock Mode
SDATA[36:32]#4
00000
11x
11111
00001
11.5x
11110
00010
12x
11101
00011
12.5x
11100
00100
5x
11011
00101
5.5x
11010
00110
6x
11001
00111
6.5x
11000
01000
7x
10111
01001
7.5x
10110
01010
8x
10101
01011
8.5x
10100
Notes:
1. On power up, the FID[3:0] balls are set to a clock multiplier value of 5x. After reset, software
is responsible for transitioning the processor to the desired frequency.
2. Value programmed into the FidVidCtl MSR.
3. The maximum FID that may be selected by software is reported in the FidVidStatus MSR.
4. Value driven on SDATA[36:32]# balls during the FID_Change special bus cycle. The SDATA
bus is active Low, so the SDATA[36:32]# values listed are what would be observed on the
motherboard with a digital storage scope.
5. BIOS initializes the CLK_Ctl MSR to 6007_9263h during the POST routine. This CLK_Ctl setting
is used with all FID combinations and selects a halt disconnect divisor of 128 and a Stop–Grant
disconnect divisor of 512.
Chapter 4
Power Management
25
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
Table 1.
24068F—December 2001
FID[4:0] SYSCLK Multiplier Combinations1
FID[4:0]2,3,5
Clock Mode
SDATA[36:32]#4
01100
9x
10011
01101
9.5x
10010
01110
10x
10001
01111
10.5x
10000
10000
3x
01111
10001
Reserved
Reserved
10010
4x
01101
10011
Reserved
Reserved
10100
13x
11100
10101
13.5x
11100
10110
14x
11100
10111
Reserved
Reserved
11000
15x
11100
11001
Reserved
Reserved
11010
16x
11100
11011
16.5x
11100
11100
17x
11100
11101
18x
11100
11110
Reserved
Reserved
11111
Reserved
Reserved
Notes:
1. On power up, the FID[3:0] balls are set to a clock multiplier value of 5x. After reset, software
is responsible for transitioning the processor to the desired frequency.
2. Value programmed into the FidVidCtl MSR.
3. The maximum FID that may be selected by software is reported in the FidVidStatus MSR.
4. Value driven on SDATA[36:32]# balls during the FID_Change special bus cycle. The SDATA
bus is active Low, so the SDATA[36:32]# values listed are what would be observed on the
motherboard with a digital storage scope.
5. BIOS initializes the CLK_Ctl MSR to 6007_9263h during the POST routine. This CLK_Ctl setting
is used with all FID combinations and selects a halt disconnect divisor of 128 and a Stop–Grant
disconnect divisor of 512.
26
Power Management
Chapter 4
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
4.5
Special Cycles
I n a dd i t i o n t o t h e s p e c i a l cy c l e s d o c u m e n t e d i n t h e
AMD Athlon™ and AMD Duron™ System Bus Specification,
order# 21902, the processor supports the SMM Enter, SMM
Exit, and FID_Change special cycles.
Table 2 defines the contents of SDATA[31:0] during the special
cycles.
Table 2.
Processor Special Cycle Definition
Special Cycle
Contents of SDATA[31:0]
SMM Enter
0005_0002h
SMM Exit
0006_0002h
FID_Change*
0007_0002h
Note:
*
Chapter 4
The new FID[4:0] taken from the FID[4:0] field of the FidVidCtl MSR is driven on
SDATA[36:32] during the FID_Change special cycle.
Power Management
27
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
28
Power Management
24068F—December 2001
Chapter 4
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
5
CPUID Support
The mobile AMD Duron™ processor model 7 version and
feature set recognition can be performed through the use of the
CPUID instruction, that provides complete information about
the processor—vendor, type, name, etc., and its capabilities.
Software can make use of this information to accurately tune
the system for maximum performance and benefit to users.
For information about the CPUID features supported by the
mobile AMD Duron processor model 7, refer to the following
documents:
■
Chapter 5
AMD Processor Recognition Application Note, order# 20734
CPUID Support
29
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
30
CPUID Support
24068F—December 2001
Chapter 5
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
6
Thermal Design
The mobile AMD Duron™ processor model 7 provides a diode
that can be used in conjunction with an external temperature
sensor to determine the die temperature of the processor.
The diode anode (THERMDA) and cathode (THERMDC) are
available as pins on the processor.
Refer to “Thermal Diode Characteristics” on page 48 and
“THERMDA and THERMDC Pins” on page 83 for more details.
For information about the usage of this diode and thermal
design, including layout and airflow considerations, see the
Mobile System Thermal Design Guidelines, order# 24383.
Table 3 shows the thermal design power.
Table 3.
Thermal Design Power
Frequency
(MHz)
Voltage
Thermal Design
Power1
800
1.50 V
25 W
850
1.50 V
25 W
900
1.45 V
25 W
950
1.45 V
25 W
1000
1.40 V
25 W
Notes:
1. Thermal design power represents the maximum sustained power dissipated while executing
publicly-available software or instruction sequences under normal system operation at
nominal VCC_CORE. Thermal solutions must monitor the temperature of the processor to
prevent the processor from exceeding its maximum die temperature. Specified through
characterization for a die temperature of 95°C.
Chapter 6
Thermal Design
31
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
32
Thermal Design
24068F—December 2001
Chapter 6
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7
Electrical Data
7.1
Conventions
The conventions used in this chapter are as follows:
■
■
7.2
Current specified as being sourced by the processor is
negative.
Current specified as being sunk by the processor is positive.
Interface Signal Groupings
The electrical data in this chapter is presented separately for
each signal group.
Table 4 defines each group and the signals contained in each
group.
Table 4.
Interface Signal Groupings
Signal Group
Signals
Notes
Power
VID[4:0], SOFTVID[4:0], VCCA, VCC_CORE, COREFB, COREFB#
See “” on page 38, “Soft Voltage
Identification (SOFTVID[4:0])” on
page 35, “VCCA AC and DC
Characteristics” on page 35,
“VCC_CORE AC and DC
Characteristics” on page 37,
“COREFB and COREFB# Pins” on
page 78, “SOFTVID[4:0] and
VID[4:0] Pins” on page 81, and
“VCCA Pin” on page 83.
Frequency
FID[3:0]
See “Frequency Identification
(FID[3:0])” on page 35 and
“FID[3:0] Pins” on page 79.
SYSCLK, SYSCLK# (Tied to CLKIN/CLKIN# and
RSTCLK/RSTCLK#), PLLBYPASSCLK, PLLBYPASSCLK#,
See “SYSCLK and SYSCLK# AC and
DC Characteristics” on page 41,
“SYSCLK and SYSCLK#” on
page 83, and “PLL Bypass and Test
Pins” on page 80.
System Clocks
Chapter 7
Electrical Data
33
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
Table 4.
24068F—December 2001
Interface Signal Groupings (continued)
Signal Group
Signals
Notes
SADDIN[14:2]#, SADDOUT[14:2]#, SADDINCLK#,
SADDOUTCLK#, SFILLVALID#, SDATAINVALID#,
SDATAOUTVALID#, SDATA[63:0]#, SDATAINCLK[3:0]#,
SDATAOUTCLK[3:0]#, CLKFWDRST, PROCRDY, CONNECT
See “AMD Duron™ System Bus AC
and DC Characteristics” on page
43 and “CLKFWDRST Pin” on
page 78.
Southbridge
RESET#, INTR, NMI, SMI#, INIT#, A20M#, FERR, IGNNE#,
STPCLK#, FLUSH#
See “General AC and DC
Characteristics” on page 45, “INTR
Pin” on page 79, “NMI Pin” on
page 80, “SMI# Pin” on page 81,
“INIT# Pin” on page 79, “A20M#
Pin” on page 78, “FERR Pin” on
page 79, “IGNNE# Pin” on
page 79, “STPCLK# Pin” on
page 82, and “FLUSH# Pin” on
page 79.
JTAG
TMS, TCK, TRST#, TDI, TDO
See “General AC and DC
Characteristics” on page 45.
PLLTEST#, PLLBYPASS#, PLLMON1, PLLMON2, SCANCLK1,
SCANCLK2, SCANSHIFTEN, SCANINTEVAL, ANALOG
See “General AC and DC
Characteristics” on page 45, “PLL
Bypass and Test Pins” on page 80,
“Scan Pins” on page 81, and
“Analog Pin” on page 78,
Miscellaneous
DBREQ#, DBRDY, PWROK
See “General AC and DC
Characteristics” on page 45,
“DBRDY and DBREQ# Pins” on
page 79, and “PWROK Pin” on
page 80.
Reserved
(RSVD)
Pins N1, N3, and N5
See “Reserved Pins DC
Characteristics” on page 51, and
“RSVD Pins” on page 80.
THERMDA, THERMDC
See “Thermal Diode
Characteristics” on page 48 and
“THERMDA and THERMDC Pins”
on page 83
System Bus
Test
Thermal
34
Electrical Data
Chapter 7
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7.3
Soft Voltage Identification (SOFTVID[4:0])
Table 5 shows the SOFTVID[4:0] DC Characteristics. For more
information, see “SOFTVID[4:0] and VID[4:0] Pins” on
page 81.
Table 5.
SOFTVID[4:0] DC Characteristics
Parameter
Description
Min
IOL
Output Current Low
SOFTVID_VOH
SOFTVID[4:0] Output High Voltage
Max
16 mA
–
2.625V *
Note:
*
7.4
The SOFTVID pins must not be pulled above this voltage by an external pullup resistor.
Frequency Identification (FID[3:0])
Table 6 shows the FID[3:0] DC characteristics. For more
information, see “FID[3:0] Pins” on page 79.
Table 6.
FID[3:0] DC Characteristics
Parameter
Description
Min
IOL
Output Current Low
16 mA
VOH
Output High Voltage
–
Max
2.625 V *
Note:
*
7.5
The FID pins must not be pulled above this voltage by an external pullup resistor.
VCCA AC and DC Characteristics
Table 7 shows the AC and DC characteristics for VCCA. For
more information, see “VCCA Pin” on page 83.
Table 7.
Symbol
VCCA AC and DC Characteristics
Parameter
Min
Nom
Max
Units
Notes
VVCCA
VCCA Pin Voltage (AC and DC)
2.25
2.5
2.75
V
1
IVCCA
VCCA Pin Current
50
mA/GHz
2
0
Notes:
1. Minimum and maximum voltages are absolute. No transients below minimum nor above maxiumum voltages are permitted.
2. Measured at 2.5 V.
Chapter 7
Electrical Data
35
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
7.6
24068F—December 2001
Decoupling
See the AMD Athlon™ Processor-Based Motherboard Design
Guide, order# 24363, or contact your local AMD office for
information about the decoupling required on the motherboard
for use with the mobile AMD Duron™ processor model 7.
7.7
Valid Voltage and Frequency Combinations
Table 8 specifies the valid voltage and frequency combinations
that this processor is characterized to operate. The Maximum
Frequency column corresponds to the rated frequency of the
processor. The Maximum FID (MFID) field in the FidVidStatus
MSR is used by software to determine the maximum frequency
of the processor. Each row in the table shows the maximum
frequency allowable at the voltage specified in each column.
“ Pow e r M a n a g e m e n t ” o n p a g e 9 d e s c r i b e s h o w
A M D Powe r N ow ! ™ s o f t wa re u s e s t h i s i n fo r m a t i o n t o
implement processor performance states.
Table 8.
Valid Voltage and Frequency Combinations
Maximum
Frequency
VCC_CORE_NOM Voltage
1.50 V
1.45 V
1.40 V
1.35 V
1.30 V
1.25 V
1.20 V
800 MHz
800 MHz
700 MHz
650 MHz
600 MHz
550 MHz
500 MHz
≤ 500 MHz
850 MHz
850 MHz
750 MHz
700 MHz
650 MHz
600 MHz
550 MHz
≤ 500 MHz
900 MHz
N/A
900 MHz
800 MHz
750 MHz
700 MHz
650 MHz
≤ 550 MHz
950 MHz
N/A
950 MHz
850 MHz
800 MHz
750 MHz
700 MHz
≤ 600 MHz
1000 MHz
N/A
N/A
1000 MHz
900 MHz
850 MHz
800 MHz
≤ 700 MHz
Notes:
1. All voltages listed are nominal.
2. The “≤” symbol indicates that any BIOS vendor can use any performance state equal to or less than the specified frquency at that
given voltage. For example, “≤ 700 MHz” means that the BIOS may use 700 MHz, 600 MHz, 550 MHz, 500 MHz, 400 Mhz, or
300 Mhz provided that the chipset and system support the chosen processor operating frequencies.
3. The maximum processor die temperature is 95º C for all voltage and frequency combinations.
36
Electrical Data
Chapter 7
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7.8
VCC_CORE AC and DC Characteristics
Table 9 shows the AC and DC characteristics for VCC_CORE.
For more information, see Table 24, “Cross-Reference by Pin
Location,” on page 70 and Figure 9 on page 38.
Table 9.
VCC_CORE AC and DC Characteristics
Limit in Working State2
Units
VCC_CORE_DC_MAX Maximum static voltage above VCC_CORE_NOM1
100
mV
VCC_CORE_DC_MIN Maximum static voltage below VCC_CORE_NOM1
–50
mV
VCC_CORE_AC_MAX Maximum excursion above VCC_CORE_NOM1
150
mV
VCC_CORE_AC_MIN Maximum excursion below VCC_CORE_NOM 1, 3
–100
mV
Symbol
Parameter
tMAX_AC
Positive excursion time for AC transients
10
µs
tMIN_AC
Negative excursion time for AC transients
5
µs
Notes:
1. VCC_CORE nominal values are shown in Table 8, “Valid Voltage and Frequency Combinations,” on page 36.
2. All voltage measurements are taken differentially at the COREFB/COREFB# pins.
3. Absolute minimum allowable VCC_CORE voltage, including all transients, is 1.10 V.
Chapter 7
Electrical Data
37
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Figure 9 shows the processor core voltage (VCC_CORE)
waveform response to perturbation. The tMIN_AC (negative AC
transient excursion time) and tMAX_AC (positive AC transient
excursion time) represent the maximum allowable time below
or above the DC tolerance thresholds.
tmax_AC
VCC_CORE_MAX_AC
VCC_CORE_MAX_DC
VCC_CORE_NOM
VCC_CORE_MIN_DC
VCC_CORE_MIN_AC
tmin_AC
ICORE_MAX
dI /dt
ICORE_MIN
Figure 9. VCC_CORE Voltage Waveform
38
Electrical Data
Chapter 7
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7.9
Absolute Ratings
Do not subject the processor to conditions that exceed the
absolute ratings listed in Table 10, as such conditions may
adversely affect long-term reliability or result in functional
damage.
Table 10. Absolute Ratings
Parameter
Description
Min
Max
VCC_CORE
Mobile AMD Duron™ Processor Model 7 core supply
–0.5 V
VCC_CORE Max + 0.5 V
VCCA
AMD Duron Processor Model 7 PLL supply
–0.5 V
VCCA Max + 0.5 V
VPIN
Voltage on any signal pin
–0.5 V
VCC_CORE Max + 0.5 V
TSTORAGE
Storage temperature of processor
–40ºC
100ºC
Chapter 7
Electrical Data
39
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
7.10
24068F—December 2001
VCC_CORE Voltage and Current
Table 11 shows the voltage and current of the processor during
normal and reduced power states.
Table 11. VCC_CORE Voltage and Current
Frequency
(MHz)
800
Nominal
Voltage
Maximum ICC (Power
Supply Current)
1.50 V
16.70 A
1.45 V
17.20 A
1.40 V
17.90
Die Temperature
Notes
850
900
95°C
950
1000
2.00 A
Halt/Stop Grant C2
Stop Grant C2
Stop Grant C3/S1
1.20 V
1.07 A
0.80 A
1, 2, 3
50°C
1, 2, 3, 4
1, 2, 3, 4
Notes:
1. See also Figure 3, “Mobile AMD Duron™ Processor Model 7 Power Management States” on page 10.
2. The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner of the
process, and are not representative of the typical Stop Grant current that is currently about one-third of the maximum specified
current.
3. These currents occur when the AMD Duron system bus is disconnected and a low power ratio of 1/512 is applied to the core clock
grid of the processor as dictated by a value of 6007_9263h programmed into the Clock Control (CLK_Ctl) MSR.
4. The Stop Grant current consumption is characterized and not tested.
40
Electrical Data
Chapter 7
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7.11
SYSCLK and SYSCLK# AC and DC Characteristics
Table 12 shows the DC characteristics of the SYSCLK and
SYSCLK# differential clocks. The SYSCLK signal represents
CLKIN and RSTCLK tied together while the SYSCLK# signal
represents CLKIN# and RSTCLK# tied together.
Table 12. SYSCLK and SYSCLK# DC Characteristics
Symbol
Description
Min
Max
Units
VThreshold-DC
Crossing before transition is detected (DC)
400
mV
VThreshold-AC
Crossing before transition is detected (AC)
450
mV
ILEAK_P
Leakage current through P-channel pullup to VCC_CORE
–250
µA
ILEAK_N
Leakage current through N-channel pulldown to VSS (Ground)
VCROSS
Differential signal crossover
CPIN
Capacitance
250
µA
VCC_CORE/2
+/– 100
mV
12
pF
4
Figure 10 shows the DC characteristics of the SYSCLK and
SYSCLK# signals.
VCROSS
VThreshold-DC = 400 mV
VThreshold-AC = 450 mV
Figure 10. SYSCLK and SYSCLK# Differential Clock Signals
Chapter 7
Electrical Data
41
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 13 shows the mobile AMD Duron processor model 7
SYSCLK/SYSCLK# differential clock AC characteristics.
Table 13. SYSCLK and SYSCLK# AC Characteristics
Symbol
Description
Clock Frequency
Duty Cycle
Min
Max
Units
50
100
MHz
30%
70%
–
t1
Period
10
ns
t2
High Time
1.8
ns
t3
Low Time
1.8
ns
t4
Fall Time
2
ns
t5
Rise Time
2
ns
± 300
ps
Period Stability
Notes
1, 2
Notes:
1. Circuitry driving the SYSCLK and SYSCLK# inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL to track
the jitter. The –20 dB attenuation point, as measured into a 10-pF or 20-pF load must be less than 500 kHz.
2. Circuitry driving the SYSCLK and SYSCLK# inputs may purposely alter the SYSCLK and SYSCLK# period (spread spectrum clock
generators). In no cases can the period violate the minimum specification above. SYSCLK and SYSCLK# inputs may vary from
100% of the specified period to 99% of the specified period at a maximum rate of 100 kHz.
Figure 11 shows a sample waveform.
t2
VThreshold-AC
VCROSS
t3
t4
t5
t1
Figure 11. SYSCLK Waveform
42
Electrical Data
Chapter 7
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7.12
AMD Duron™ System Bus AC and DC Characteristics
Table 14 shows the DC characteristics of the AMD Duron
system bus.
Table 14. AMD Duron™ System Bus DC Characteristics
Symbol
VREF
Parameter
Condition
Min
Max
(0.5 x VCC_CORE) (0.5 x VCC_CORE)
–50
+50
DC Input Reference Voltage
IVREF_LEAK_P VREF Tristate Leakage Pullup VIN=VREFNominal
V Tristate Leakage
VIN=VREFNominal
IVREF_LEAK_N REF
Pulldown
–100
Units Notes
mV
1
µA
+100
µA
VIH
Input High Voltage
VREF + 200
VCC_CORE + 500
mV
VIL
Input Low Voltage
–500
VREF – 200
mV
VOH
Output High Voltage
IOUT = –200 µA
0.85*VCC_CORE
VCC_CORE+500
mV
2
VOL
Output Low Voltage
IOUT = 1 mA
–500
400
mV
2
ILEAK_P
Tristate Leakage Pullup
VIN= VSS
(Ground)
–250
ILEAK_N
Tristate Leakage Pulldown
VIN= VCC_CORE
Nominal
CIN
Input Pin Capacitance
µA
+250
µA
12
pF
4
Notes:
1. VREF
– VREF is nominally set by a (1%) resistor divider from VCC_CORE.
– The suggested divider resistor values are 100 ohms over 100 ohms to produce a divisor of 0.50.
– Example: VCC_CORE = 1.4 V, VREF = 750 mV (1.4 x 0.50).
– Peak-to-Peak AC noise on VREF (AC) should not exceed 2% of VREF (DC).
2. Specified at T = 95°C and VCC_CORE.
Chapter 7
Electrical Data
43
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
The AC characteristics of the AMD Duron system bus are shown
in Table 15. The parameters are grouped based on the source or
destination of the signals involved.
Table 15. AMD Duron™ System Bus AC Characteristics
Group
Sync
Forward Clocks
All Signals
Symbol
Parameter
Min
Max
Units
Notes
TRISE
Output Rise Slew Rate
1
3
V/ns
1
TFALL
Output Fall Slew Rate
1
3
V/ns
1
TSKEW-SAMEEDGE
Output skew with respect to
the same clock edge
–
385
ps
2
TSKEW-DIFFEDGE
Output skew with respect to a
different clock edge
–
770
ps
2
TSU
Input Data Setup Time
300
–
ps
3
THD
Input Data Hold Time
300
–
ps
3
CIN
Capacitance on input Clocks
4
12
pF
COUT
Capacitance on output Clocks
4
12
pF
T VAL
RSTCLK to Output Valid
250
2000
ps
4, 5
TSU
Setup to RSTCLK
500
–
ps
4, 6
THD
Hold from RSTCLK
1000
–
ps
4, 6
Notes:
1. Rise and fall time ranges are guidelines over which the I/O has been characterized.
2. TSKEW-SAMEEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and its
forward clock, as measured at the package, with respect to the same clock edge.
TSKEW-DIFFEDGE is the maximum skew within a clock forwarded group between any two signals or between any signal and its
forward clock, as measured at the package, with respect to different clock edges.
3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.
4. The synchronous signals include PROCRDY, CONNECT, and CLKFWDRST.
5. T VAL is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF.
6. TSU is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. THD is hold of CONNECT/CLKFWDRST from rising edge of
RSTCLK.
44
Electrical Data
Chapter 7
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7.13
General AC and DC Characteristics
Table 16 shows the mobile AMD Duron processor model 7 AC
and DC characteristics of the Southbridge, JTAG, test, and
miscellaneous pins.
Table 16. General AC and DC Characteristics
Symbol
Parameter Description
Condition
Min
Max
Units
Notes
VIH
Input High Voltage
(VCC_CORE/2) +
200mV
VCC_CORE Max
V
1, 2
VIL
Input Low Voltage
–300
350
mV
1, 2
VOH
Output High Voltage
VCC_CORE – 400
VCC_CORE +
300
mV
VOL
Output Low Voltage
–300
400
mV
ILEAK_P
Tristate Leakage Pullup
ILEAK_N
Tristate Leakage Pulldown
IOH
Output High Current
IOL
Output Low Current
TSU
VIN= VSS (Ground)
–250
VIN= VCC_CORE
Nominal
µA
250
µA
–16
mA
3
16
mA
3
Sync Input Setup Time
2.0
ns
4, 5
THD
Sync Input Hold Time
0.0
ps
4, 5
TDELAY
Output Delay with respect to
RSTCLK
0.0
ns
5
TBIT
Input Time to Acquire
20.0
ns
7, 8
6.1
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Characterized across DC supply voltage range.
Values specified at nominal VCC_CORE. Scale parameters between VCC_CORE Min and VCC_CORE Max.
IOL and IOH are measured at VOL maximum and VOH minimum, respectively.
Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.
These are aggregate numbers.
Edge rates indicate the range over which inputs were characterized.
In asynchronous operation, the signal must persist for this time to enable capture.
This value assumes RSTCLK frequency is 10 ns ==> TBIT = 2*fRST.
The approximate value for standard case in normal mode operation.
This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.
Reassertions of the signal within this time are not guaranteed to be seen by the core.
This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.
This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other
configurations.
14. Time to valid is for any open drain pins. See requirements 7 and 8 in Chapter 8, “Power–Up Timing Requirements,“ for more
information.
Chapter 7
Electrical Data
45
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 16. General AC and DC Characteristics
Symbol
Parameter Description
Condition
Min
Max
Units
Notes
ns
9–13
TRPT
Input Time to Reacquire
40.0
TRISE
Signal Rise Time
1.0
3.0
V/ns
6
TFALL
Signal Fall Time
1.0
3.0
V/ns
6
CPIN
Pin Capacitance
4
12
pF
T VALID
Time to data valid
100
ns
14
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Characterized across DC supply voltage range.
Values specified at nominal VCC_CORE. Scale parameters between VCC_CORE Min and VCC_CORE Max.
IOL and IOH are measured at VOL maximum and VOH minimum, respectively.
Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.
These are aggregate numbers.
Edge rates indicate the range over which inputs were characterized.
In asynchronous operation, the signal must persist for this time to enable capture.
This value assumes RSTCLK frequency is 10 ns ==> TBIT = 2*fRST.
The approximate value for standard case in normal mode operation.
This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.
Reassertions of the signal within this time are not guaranteed to be seen by the core.
This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.
This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other
configurations.
14. Time to valid is for any open drain pins. See requirements 7 and 8 in Chapter 8, “Power–Up Timing Requirements,“ for more
information.
46
Electrical Data
Chapter 7
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7.14
Open Drain Test Circuit
Figure 12 is a test circuit that may be used on Automated Test
Equipment (ATE) to test for validity on open drain pins.
Refer to Table 16, “General AC and DC Characteristics,” on
page 45 for timing requirements.
VTermination1
50 Ω ±3%
Open Drain Pin
IOL = Output Current2
Notes:
1. VTermination = 1.2 V for VID and FID pins
2. IOL = –16 mA for VID and FID pins
Figure 12. General ATE Open Drain Test Circuit
Chapter 7
Electrical Data
47
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
7.15
24068F—December 2001
Thermal Diode Characteristics
Thermal Diode Electrical Characteristics. Table 17 shows the mobile
AMD Duron processor model 7 electrical characteristics of the
on-die thermal diode.
Table 17. Thermal Diode Electrical Characteristics
Symbol
Parameter Description
Min
Ifw
Forward bias current
5
n
Diode ideality factor
1.002
Nom
1.008
Max
Units
Notes
300
µA
1
1.016
2, 3, 4, 5
Notes:
1.
2.
3.
4.
The sourcing current should always be used in forward bias only.
Characterized at 95°C with a forward bias current pair of 10 µA and 100 µA.
Not 100% tested. Specified by design and limited characterization.
The diode ideality factor, n, is a correction factor to the ideal diode equation.
For the following equations, use the following variables and constants:
n
Diode ideality factor
k
Boltzmann constant
q
Electron charge constant
T
Diode temperature (Kelvin)
VBE Voltage from base to emitter
Collector current
IC
Saturation current
IS
N
Ratio of collector currents
The equation for VBE is:
IC
nkT
V BE = --------- ⋅ ln æ -----ö
è
IS ø
q
By sourcing two currents and using the above equation, a difference in base emitter voltage
can be found that leads to the following equation for temperature:
∆V BE
T = ---------------------------k
n ⋅ ln ( N ) ⋅ --q
5. If a different sourcing current pair is used other than 10 µA and 100 µA, the following equation
should be used to correct the temperature. Subtract this offset from the temperature measured
by the temperature sensor.
For the following equations, use the following variables and constants:
Ihigh High sourcing current
Ilow
Low sourcing current
Toffset (in °C) can be found using the following equation:
( I high – I low )
4
T offset = ( 6.0 ⋅ 10 ) ⋅ -------------------------------- – 2.34
I high
ln æ -----------ö
è I low ø
48
Electrical Data
Chapter 7
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Thermal Protection Characterization. The following section describes
parameters relating to thermal protection. The implementation
of thermal control circuitry to control processor temperature is
left to the manufacturer to determine how to implement.
Thermal limits in motherboard design are necessary to protect
the processor from thermal damage. T S HU TD OW N is the
temperature for thermal protection circuitry to initiate
shutdown of the processor. T SD_DELAY is the maximum time
allowed from the detection of the over-temperature condition to
processor shutdown to prevent thermal damage to the
processor.
Systems that do not implement thermal protection circuitry or
that do not react within the time specified by TSD_DELAY can
cause thermal damage to the processor during the unlikely
events of fan failure or powering up the processor without a
heat-sink. The processor relies on thermal circuitry on the
motherboard to turn off the regulated core voltage to the
processor in response to a thermal shutdown event.
Thermal protection circuitry reference designs and thermal
solution guidelines are found in the following documents:
■
■
■
■
AMD Athlon™ Processor-Based Motherboard Design Guide,
order# 24363
Thermal Diode Monitoring Circuits, order# 25658
AMD Thermal, Mechanical, and Chassis Cooling Design Guide,
order# 23794
http://www1.amd.com/products/athlon/thermals
Mobile specific thermal documentation:
■
■
■
Chapter 7
Measuring Processor and system Power in a Mobile System,
order# 24353
Mobile System Thermal Design Guide, order# 24383
Measuring Temperature on AMD Athlon™ and AMD Duron™
Pin Grid Array Processors with and without an On-Die Thermal
Diode, order#24228
Electrical Data
49
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 18 shows the TSHUTDOWN and TSD_DELAY specifications
for circuitry in motherboard design necessary for thermal
protection of the processor.
Table 18. Guidelines for Platform Thermal Protection of the Processor
Symbol
Parameter Description
TSHUTDOWN Thermal diode shutdown temperature for processor protection
TSD_DELAY
Maximum allowed time from TSHUTDOWN detection to processor
shutdown
Max
Units
Notes
125
°C
1, 2, 3
500
ms
1, 3
Notes:
1. The thermal diode is not 100% tested, it is specified by design and limited characterization.
2. The thermal diode is capable of responding to thermal events of 40°C/s or faster.
3. The mobile AMD Duron™ processor model 7 provides a thermal diode for measuring die temperature of the processor. The
processor relies on thermal circuitry on the motherboard to turn off the regulated core voltage to the processor in response to a
thermal shutdown event. Refer to Thermal Diode Monitoring Circuits, order# 25658, for thermal protection circuitry designs.
50
Electrical Data
Chapter 7
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
7.16
Reserved Pins DC Characteristics
Table 19 shows the DC characteristics of the Reserved (RSVD)
pins.
Table 19. Reserved Pins (N1, N3, and N5) DC Characteristics
Symbol
Parameter Description
ILEAK_P
Tristate Leakage Pullup
ILEAK_N
Tristate Leakage Pulldown
Min
Max
–250
250
Units
Note
µA
*
µA
*
Note:
*
Chapter 7
Measured at 2.5 V
Electrical Data
51
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
7.17
24068F—December 2001
FID_Change Induced PLL Lock Time
Table 20 shows the time required for the PLL of the processor to
lock at the new frequency specified in a FID_Change transition.
Software must program the SGTC field of the FidVidCtl MSR to
produce a FID_Change duration equal to or greater than the
FID_Change induced PLL lock time.
For more information about the FID_Change protocol, see
“Power Management” on page 9.
Table 20. FID_Change Induced PLL Lock Time
Parameter Description
FID_Change Induced PLL Lock Time
52
Electrical Data
Max
Units
50
µs
Chapter 7
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
8
Signal and Power-Up Requirements
This chapter describes the mobile AMD Duron™ processor
model 7 power-up requirements during system power-up and
warm resets.
8.1
Power-Up Requirements
Signal Sequence and
Timing Description
Figure 13 shows the relationship between key signals in the
system during a power-up sequence. This figure details the
requirements of the processor.
3.3 V Supply
VCCA (2.5 V)
(for PLL)
VCC_CORE
(Processor Core)
2
1
RESET#
Warm reset
condition
6
4
NB_RESET#
5
PWROK
7
8
FID[3:0]
3
System Clock
Figure 13. Signal Relationship Requirements During Power-Up Sequence
Notes:
1. Figure 13 represents several signals generically by using names not necessarily consistent
with any pin lists or schematics.
2. Requirements 1–8 in Figure 13 are described in “Power-Up Timing Requirements” on
page 54.
Chapter 8
Signal and Power-Up Requirements
53
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Power-Up Timing Requirements. The signal timing requirements are
as follows:
1. RESET# must be asserted before PWROK is asserted.
The mobile AMD Duron™ processor model 7 does not set
the correct clock multiplier if PWROK is asserted prior to a
RESET# assertion. It is recommended that RESET# be
asserted at least 10 nanoseconds prior to the assertion of
PWROK.
In practice, Southbridges will assert RESET# milliseconds
before PWROK is deasserted.
2. All motherboard voltage planes must be within
specification before PWROK is asserted.
PWROK is an output of the voltage regulation circuit on the
motherboard. PWROK indicates that VCC_CORE and all
other voltage planes in the system are within specification.
The motherboard is required to delay PWROK assertion for
a minimum of 3 milliseconds from the 3.3 V supply being
within specification. This ensures that the system clock
(SYSCLK/SYSCLK#) is operating within specification when
PWROK is asserted.
The processor core voltage, VCC_CORE, must be within
specification before PWROK is asserted as dictated by the
VID[4:0] pins strapped on the processor package. Before
PWROK assertion, the processor is clocked by a ring
oscillator. Before PWROK is asserted, the SOFTVID[4:0]
outputs of the processor are not driven to a deterministic
value. The processor drives the SOFTVID[4:0] outputs to
the same value as dictated by the VID[4:0] pins within 20
nanoseconds of PWROK assertion.
The processor PLL is powered by VCCA. The processor PLL
does not lock if VCCA is not high enough for the processor
logic to switch for some period before PWROK is asserted.
VCCA must be within specification at least 5 microseconds
before PWROK is asserted.
In practice VCCA, VCC_CORE, and all other voltage planes
must be within specification for several milliseconds before
PWROK is asserted.
After PWROK is asserted, the processor PLL locks to its
operational frequency.
3. The system clock (SYSCLK/SYSCLK#) must be running
before PWROK is asserted.
54
Signal and Power-Up Requirements
Chapter 8
Preliminary Information
24068F—December 2001
Mobile AMD Duron™ Processor Model 7 Data Sheet
When PWROK is asserted, the processor switches from
driving the internal processor clock grid from the ring
oscillator to driving from the PLL. The reference system
clock must be valid at this time. The system clocks are
guaranteed to be running after 3.3 V has been within
specification for 3 milliseconds.
4. PWROK assertion to deassertion of RESET#
The duration of RESET# assertion during cold boots is
intended to satisfy the time it takes for the PLL to lock with
a less than 1 ns phase error. The processor PLL begins to
run after PWROK is asserted and the internal clock grid is
switched from the ring oscillator to the PLL. The PLL lock
time may take from hundreds of nanoseconds to tens of
microseconds. It is recommended that the minimum time
between PWROK assertion to the deassertion of RESET# be
at least 1.0 milliseconds. Southbridges enforce a delay of
1.5 to 2.0 milliseconds between PWRGD (Southbridge
version of PWROK) assertion and NB_RESET# deassertion.
5. PWROK must be monotonic and meet the timing
requirements as defined in Table 16, “General AC and DC
Characteristics,” on page 45. The processor should not
switch between the ring oscillator and the PLL after the
initial assertion of PWROK.
6. NB_RESET# must be asserted (causing CONNECT to also
assert) before RESET# is deasserted. In practice all
Southbridges enforce this requirement.
If NB_RESET# does not assert until after RESET# has
deasserted, the processor misinterprets the CONNECT
assertion (due to NB_RESET# being asserted) as the
beginning of the SIP transfer. There must be sufficient
overlap in the resets to ensure that CONNECT is sampled
asserted by the processor before RESET# is deasserted.
7. The FID[3:0] signals are valid within 100 ns after PWROK is
asserted. The chipset must not sample the FID[3:0] signals
until they become valid. Refer to the AMD Athlon™
Processor-Based Motherboard Design Guide, order# 24363, for
the specific implementation and additional circuitry
required.
Chapter 8
Signal and Power-Up Requirements
55
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
8. The FID[3:0] signals become valid within 100 ns after
RESET# is asserted. Refer to the AMD Athlon™ ProcessorBased Motherboard Design Guide, order# 24363, for the
specific implementation and additional circuitry required.
Clock Multiplier
Selection (FID[3:0])
The chipset samples the FID[3:0] signals in a chipset-specific
manner from the processor and uses this information to
determine the correct Serial Initialization Packet (SIP). The
chipset then sends the SIP information to the processor for
configuration of the AMD Duron system bus for the clock
multiplier that determines the processor frequency indicated
by the FID[3:0] code. The SIP is sent to the processor using the
SIP protocol. This protocol uses the PROCRDY, CONNECT, and
CLKFWDRST signals, that are synchronous to SYSCLK.
For more information, seeSee “FID[3:0] Pins” on page 79.
Serial Initialization Packet (SIP) Protocol. Refer to AMD Athlon™ and
AMD Duron™ System Bus Specification, order# 21902 for details
of the SIP protocol.
8.2
Processor Warm Reset Requirements
Mobile AMD Duron™
Processor Model 7
and Northbridge
Reset Pins
56
RESET# cannot be asserted to the processor without also being
asserted to the Northbridge. RESET# to the Northbridge is the
same as PCI RESET#. The minimum assertion for PCI RESET#
is one millisecond. Southbridges enforce a minimum assertion
of RESET# for the processor, Northbridge, and PCI of 1.5 to 2.0
milliseconds.
Signal and Power-Up Requirements
Chapter 8
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
9
9.1
Mechanical Data
Introduction
The mobile AMD Duron processor model 7 connects to the
motherboard through a CPGA socket named Socket A. For more
information, see the AMD Athlon™ Processor-Based Motherboard
Design Guide, order# 24363.
9.2
Die Loading
The processor die on the CPGA package is exposed at the top of
the package. This is done to facilitate heat transfer from the die
to an approved heat sink. It is critical that the mechanical
loading of the heat sink does not exceed the limits shown in
Table 21. Any heat sink design should avoid loads on corners
and edges of die. The CPGA package has compliant pads that
serve to bring surfaces in planar contact.
Table 21. CPGA Mechanical Loading1
Location
Dynamic (MAX)
Static (MAX)
Units
Note
Die Surface
100
30
lbf
2
Die Edge
10
10
lbf
3
Notes:
1. Tool-assisted zero insertion force sockets should be designed such that no load is placed on
the ceramic substrate of the package.
2. Load specified for coplanar contact to die surface.
3. Load defined for a surface at no more than a two degree angle of inclination to die surface.
Chapter 9
Mechanical Data
57
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
9.3
24068F—December 2001
Package Description
Figure 14 on page 59 shows the mechanical drawing of the
C P G A p a ck a g e . Tab le 2 2 p rov id e s t h e d i m e n s io n s i n
millimeters assigned to the letters and symbols shown in the
Figure 14 diagram.
Table 22. Dimensions for the CPGA Package
Letter or
Symbol
D/E
Maximum
Minimum
1
Dimension Dimension1
49.27
49.78
Letter or
Symbol
Maximum
Minimum
1
Dimension Dimension1
E9
1.66
1.96
—
4.50
D1/E1
45.72 BSC
G/H
D2
11.698 REF
A
2.24 REF
D3
3.30
3.60
A1
1.27
1.53
D4
11.84
12.39
A2
0.80
0.88
D5
11.84
12.39
A3
0.116
—
D6
5.91
6.46
A4
—
1.90
D7
10.65
11.20
φP
—
6.60
D8
3.05
3.35
φb
0.43
0.50
E2
φb1
9.034 REF
1.40 REF
E3
2.35
2.65
S
1.435
2.375
E4
7.25
7.80
L
3.05
3.31
E5
7.25
7.80
M
37
E6
8.86
9.41
N
453 (pins)
E7
8.86
9.41
e
1.27 BSC
E8
15.59
16.38
e1
2.54 BSC
Note:
1. Dimensions are given in millimeters.
58
Mechanical Data
Chapter 9
Preliminary Information
24068F—December 2001
Mobile AMD Duron™ Processor Model 7 Data Sheet
Figure 14. Mobile AMD Duron™ Processor Model 7 CPGA Package
Chapter 9
Mechanical Data
59
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
60
Mechanical Data
24068F—December 2001
Chapter 9
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
10
10.1
Pin Descriptions
Pin Diagram and Pin Name Abbreviations
Figure 15 on page 62 shows the staggered pin grid array (SPGA)
for the mobile AMD Duron processor model 7. Because some of
the pin names are too long t o fit in the g rid, they are
abb revi at e d . Tab l e 23 o n p ag e 6 4 l is t s a l l t h e p i n s i n
alphabetical order by pin name, along with the abbreviation
where necessary.
Chapter 10
Pin Descriptions
61
62
Pin Descriptions
Z
X
V
T
R
P
AK
AN
AM
AL
1
INTR
IGNNE#
FERR
A20M#
STPC#
DBRDY
FID[2]
FID[0]
TDI
SCNCK1
TCK
RSVD
VID[0]
SAO#0
SAO#10
SAO#11
SAO#7
1
2
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
2
3
3
NMI
FLUSH#
INIT#
RESET#
PWROK
PLTST#
DBREQ#
FID[3]
FID[1]
TRST#
SCNINV
TMS
RSVD
VID[1]
SAO#1
SAO#14
SAOC#
SAO#9
SAO#12
4
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
4
5
5
SMI#
VCC
VCC
NC
ZP
ZN
NC
NC
VREF_S
TDO
SCNCK2
SCNSN
RSVD
VID[2]
NC
SAO#13
SAO#4
SAO#8
SAO#5
6
VSS
CPR#
AMD
NC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
SVID[2]
VSS
VSS
VSS
6
7
8
NC
NC
NC
NC
NC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
SVID[1]
SVID[3]
SVID[0]
VCC
VCC
8
9
9
NC
NC
NC
KEY
KEY
SD#52
SD#54
SD#55
10
VCC
VCC
VCC
NC
SVID[4]
VSS
VSS
VSS
10
11
11
NC
NC
NC
COREFB
NC
SD#50
SDOC#3
SD#61
12
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
12
13
13
PLMN1
PLMN2
ANLOG
COREFB#
NC
SD#49
NC
SD#53
14
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
14
15
15
PLBYC
PLBYC#
NC
KEY
KEY
SDIC#3
SD#51
SD#63
17
KEY
SD#48
SD#60
SD#62
VSS
VSS
VSS
VSS
18
NC
SD#58
SD#59
NC
19
VCC
VCC
VCC
VCC
20
21
NC
SD#36
SD#56
SD#57
VSS
VSS
VSS
VSS
22
23
KEY
SD#46
SD#37
SD#39
16
VSS
VSS
VSS
VSS
17
CLKIN
CLKIN#
NC
KEY
18
VCC
VCC
VCC
VCC
19
RCLK
RCLK#
NC
NC
20
VSS
VSS
VSS
VSS
21
K7CO#
K7CO
CLKFR
NC
22
VCC
VCC
VCC
VCC
23
PRCRDY
CNNCT
VCCA
NC
Mobile AMD Duron™
Processor Model 7
Topside View
VCC
VCC
VCC
VCC
16
24
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
24
25
25
NC
NC
PLBYP#
NC
KEY
NC
SD#47
SD#35
26
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
26
27
27
NC
NC
NC
KEY
NC
SDIC#2
SD#38
SD#34
28
VSS
VSS
VSS
NC
NC
VCC
VCC
VCC
28
29
29
SAI#12
SAI#1
SAI#0
KEY
NC
SD#33
SD#45
SD#44
30
VCC
VCC
NC
NC
NC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
NC
NC
NC
VSS
VSS
30
Figure 15. Mobile AMD Duron™ Processor Model 7 Pin Diagram—Topside View
7
NC
NC
NC
KEY
NC
NC
KEY
KEY
NC
THDC
THDA
KEY
KEY
VID[3]
VID[4]
KEY
SAO#6
SAO#2
SAO#3
31
SAI#14
SDOV#
SFILLV#
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SD#32
SD#43
NC
31
32
VSS
VSS
VSS
NC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
NC
VCC
VCC
VCC
32
33
33
SDINV#
SAI#8
SAIC#
SAI#2
SAI#5
SD#10
SD#8
NC
SDIC#0
SD#5
SD#7
SD#24
SD#25
SD#26
SD#19
SD#20
NC
SD#42
SDOC#2
34
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
34
35
35
SAI#13
SAI#4
SAI#6
SAI#11
SDOC#0
SD#14
SD#0
SD#3
SD#2
SD#4
SD#15
SD#17
SD#27
NC
SDIC#1
SD#23
SD#31
SD#41
SD#40
36
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
36
37
37
SAI#9
SAI#10
SAI#3
SAI#7
SD#9
SD#11
SD#13
SD#12
SD#1
NC
SD#6
SD#16
SD#18
SD#28
SD#29
SD#21
SD#22
SDOC#1
SD#30
Z
X
V
T
R
P
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
K
H
F
D
B
M
W
U
S
Q
N
L
J
G
E
C
A
Mobile AMD Duron™ Processor Model 7 Data Sheet
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
K
H
F
D
B
M
W
U
S
Q
N
L
J
G
E
C
A
Preliminary Information
24068F—December 2001
Chapter 10
Chapter 10
8
6
4
2
10
Pin Descriptions
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
C
C
A
SD#41
SD#42
SD#43
SD#45
SD#38
SD#47
SD#37
SD#56
SD#59
SD#60
SD#51
NC
SDOC#3
SD#54
SAO#2
SAO#8
SAO#9
SAO#7
SDOC#1
B
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
B
SD#30
SD#40
SDOC#2
NC
SD#44
SD#34
SD#35
SD#39
SD#57
NC
SD#62
SD#63
SD#53
SD#61
SD#55
SAO#3
SAO#5
SAO#12
A
D
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
D
E
E
SD#22
SD#31
NC
SD#32
SD#33
SDIC#2
NC
SD#46
SD#36
SD#58
SD#48
SDIC#3
SD#49
SD#50
SD#52
SAO#6
SAO#4
SAOC#
SAO#11
F
VCC
VCC
VCC
NC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
SVID[0]
VSS
VSS
VSS
F
G
G
SD#21
SD#23
SD#20
NC
NC
NC
KEY
KEY
NC
NC
KEY
KEY
NC
NC
KEY
KEY
H
VSS
VSS
NC
NC
NC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
SVID[4]
SVID[3]
SVID[2]
VCC
VCC
H
J
J
SD#29
SDIC#1
SD#19
NC
VID[4]
NC
SAO#1
SAO#0
K
VCC
VCC
VCC
NC
SVID[1]
VSS
VSS
VSS
K
L
L
SD#28
NC
SD#26
NC
VID[3]
VID[2]
VID[1]
VID[0]
M
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
M
N
N
SD#18
SD#27
SD#25
NC
KEY
RSVD
RSVD
RSVD
P
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
P
Q
Q
SD#16
SD#17
SD#24
NC
KEY
SCNSN
TMS
TCK
R
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
R
S
VSS
VSS
VSS
VSS
T
U
THDC
TDO
TRST#
TDI
VCC
VCC
VCC
VCC
V
W
NC
VREF_S
FID[1]
FID[0]
VSS
VSS
VSS
VSS
X
Y
KEY
NC
FID[3]
FID[2]
VCC
VCC
VCC
VCC
Z
S
SD#6
SD#15
SD#7
NC
T
VCC
VCC
VCC
VCC
U
NC
SD#4
SD#5
NC
V
VSS
VSS
VSS
VSS
W
SD#1
SD#2
SDIC#0
NC
X
VCC
VCC
VCC
VCC
Y
SD#12
SD#3
NC
NC
Z
VSS
VSS
VSS
VSS
Mobile AMD Duron™
Processor Model 7
Bottomside View
THDA
SCNCK2
SCNINV
SCNCK1
AA
AA
SD#13
SD#0
SD#8
NC
KEY
NC
DBREQ#
DBRDY
AB
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
AB
AC
AC
SD#11
SD#14
SD#10
NC
NC
ZN
PLTST#
STPC#
AD
VSS
VSS
VSS
NC
NC
VCC
VCC
VCC
AD
AE
AE
SD#9
SDOC#0
SAI#5
NC
NC
ZP
PWROK
A20M#
AF
VCC
VCC
NC
NC
NC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
NC
NC
NC
VSS
VSS
AF
AG
AG
SAI#7
SAI#11
SAI#2
NC
KEY
KEY
NC
NC
NC
NC
KEY
KEY
COREFB#
COREFB
KEY
KEY
NC
RESET#
FERR
AH
VSS
VSS
VSS
NC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
NC
AMD
VCC
VCC
AH
Figure 16. Mobile AMD Duron™ Processor Model 7 Pin Diagram—Bottomside View
SAO#13
SAO#14
SAO#10
AJ
AJ
SAI#3
SAI#6
SAIC#
SFILLV#
SAI#0
NC
PLBYP#
VCCA
CLKFR
NC
NC
NC
ANLOG
NC
NC
NC
VCC
INIT#
IGNNE#
AK
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
NC
CPR#
VSS
VSS
AK
AL
AL
SAI#10
SAI#4
SAI#8
SDOV#
SAI#1
NC
NC
CNNCT
K7CO
RCLK#
CLKIN#
PLBYC#
PLMN2
NC
NC
NC
VCC
FLUSH#
INTR
AM
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
NC
VSS
VSS
VCC
AM
AN
SAI#9
SAI#13
SDINV#
SAI#14
SAI#12
NC
NC
PRCRDY
K7CO#
RCLK
CLKIN
PLBYC
PLMN1
NC
NC
NC
SMI#
NMI
AN
8
6
4
2
10
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
9
7
5
3
1
24068F—December 2001
20
19
18
17
16
15
14
13
12
11
9
7
5
3
1
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
63
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
Table 23. Pin Name Abbreviations
Abbreviation
ANLOG
CLKFR
CNNCT
CPR#
K7CO
K7CO#
64
Full Name
A20M#
AMD
ANALOG
CLKFWDRST
CLKIN
CLKIN#
CONNECT
COREFB
COREFB#
CPU_PRESENCE#
DBRDY
DBREQ#
FERR
FID[0]
FID[1]
FID[2]
FID[3]
FLUSH#
IGNNE#
INIT#
INTR
K7CLKOUT
K7CLKOUT#
KEY
KEY
KEY
KEY
KEY
KEY
KEY
KEY
KEY
KEY
KEY
KEY
KEY
KEY
KEY
KEY
24068F—December 2001
Table 23. Pin Name Abbreviations (continued)
Pin
AE1
AH6
AJ13
AJ21
AN17
AL17
AL23
AG11
AG13
AK6
AA1
AA3
AG1
W1
W3
Y1
Y3
AL3
AJ1
AJ3
AL1
AL21
AN21
G7
G9
G15
G17
G23
G25
N7
Q7
Y7
AA7
AG7
AG9
AG15
AG17
AG27
AG29
Abbreviation
Pin Descriptions
Full Name
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Pin
A19
A31
C13
E25
E33
F30
G11
G13
G19
G21
G27
G29
G31
H28
H30
H32
J5
J31
K30
L31
L35
N31
Q31
S31
U31
U37
W7
W31
Y5
Y31
Y33
AA5
AA31
AC7
AC31
AD8
AD30
AE7
AE31
Chapter 10
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 23. Pin Name Abbreviations (continued)
Abbreviation
PLBYP#
PLBYC
PLBYC#
PLMN1
PLMN2
Chapter 10
Full Name
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NMI
PLLBYPASS#
PLLBYPASSCLK
PLLBYPASSCLK#
PLLMON1
PLLMON2
Pin
AF6
AF8
AF10
AF28
AF30
AF32
AG5
AG19
AG21
AG23
AG25
AG31
AH8
AH30
AJ7
AJ9
AJ11
AJ15
AJ17
AJ19
AJ27
AK8
AL7
AL9
AL11
AL25
AL27
AM8
AN7
AN9
AN11
AN25
AN27
AN3
AJ25
AN15
AL15
AN13
AL13
Table 23. Pin Name Abbreviations (continued)
Abbreviation
PLTST#
PRCRDY
RCLK
RCLK#
SAI#0
SAI#1
SAI#2
SAI#3
SAI#4
SAI#5
SAI#6
SAI#7
SAI#8
SAI#9
SAI#10
SAI#11
SAI#12
SAI#13
SAI#14
SAIC#
SAO#0
SAO#1
SAO#2
SAO#3
SAO#4
SAO#5
SAO#6
SAO#7
SAO#8
SAO#9
SAO#10
SAO#11
SAO#12
SAO#13
Pin Descriptions
Full Name
PLLTEST#
PROCREADY
PWROK
RSVD
RSVD
RSVD
RESET#
RSTCLK
RSTCLK#
SADDIN[0]#
SADDIN[1]#
SADDIN[2]#
SADDIN[3]#
SADDIN[4]#
SADDIN[5]#
SADDIN[6]#
SADDIN[7]#
SADDIN[8]#
SADDIN[9]#
SADDIN[10]#
SADDIN[11]#
SADDIN[12]#
SADDIN[13]#
SADDIN[14]#
SADDINCLK#
SADDOUT[0]#
SADDOUT[1]#
SADDOUT[2]#
SADDOUT[3]#
SADDOUT[4]#
SADDOUT[5]#
SADDOUT[6]#
SADDOUT[7]#
SADDOUT[8]#
SADDOUT[9]#
SADDOUT[10]#
SADDOUT[11]#
SADDOUT[12]#
SADDOUT[13]#
Pin
AC3
AN23
AE3
N1
N3
N5
AG3
AN19
AL19
AJ29
AL29
AG33
AJ37
AL35
AE33
AJ35
AG37
AL33
AN37
AL37
AG35
AN29
AN35
AN31
AJ33
J1
J3
C7
A7
E5
A5
E7
C1
C5
C3
G1
E1
A3
G5
65
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 23. Pin Name Abbreviations (continued)
Table 23. Pin Name Abbreviations (continued)
Abbreviation
SAO#14
SAOC#
SCNCK1
SCNCK2
SCNINV
SCNSN
SD#0
SD#1
SD#2
SD#3
SD#4
SD#5
SD#6
SD#7
SD#8
SD#9
SD#10
SD#11
SD#12
SD#13
SD#14
SD#15
SD#16
SD#17
SD#18
SD#19
SD#20
SD#21
SD#22
SD#23
SD#24
SD#25
SD#26
SD#27
SD#28
SD#29
SD#30
SD#31
SD#32
Abbreviation
SD#33
SD#34
SD#35
SD#36
SD#37
SD#38
SD#39
SD#40
SD#41
SD#42
SD#43
SD#44
SD#45
SD#46
SD#47
SD#48
SD#49
SD#50
SD#51
SD#52
SD#53
SD#54
SD#55
SD#56
SD#57
SD#58
SD#59
SD#60
SD#61
SD#62
SD#63
SDIC#0
SDIC#1
SDIC#2
SDIC#3
SDINV#
SDOC#0
SDOC#1
SDOC#2
66
Full Name
SADDOUT[14]#
SADDOUTCLK#
SCANCLK1
SCANCLK2
SCANINTEVAL
SCANSHIFTEN
SDATA[0]#
SDATA[1]#
SDATA[2]#
SDATA[3]#
SDATA[4]#
SDATA[5]#
SDATA[6]#
SDATA[7]#
SDATA[8]#
SDATA[9]#
SDATA[10]#
SDATA[11]#
SDATA[12]#
SDATA[13]#
SDATA[14]#
SDATA[15]#
SDATA[16]#
SDATA[17]#
SDATA[18]#
SDATA[19]#
SDATA[20]#
SDATA[21]#
SDATA[22]#
SDATA[23]#
SDATA[24]#
SDATA[25]#
SDATA[26]#
SDATA[27]#
SDATA[28]#
SDATA[29]#
SDATA[30]#
SDATA[31]#
SDATA[32]#
Pin
G3
E3
S1
S5
S3
Q5
AA35
W37
W35
Y35
U35
U33
S37
S33
AA33
AE37
AC33
AC37
Y37
AA37
AC35
S35
Q37
Q35
N37
J33
G33
G37
E37
G35
Q33
N33
L33
N35
L37
J37
A37
E35
E31
Pin Descriptions
Full Name
SDATA[33]#
SDATA[34]#
SDATA[35]#
SDATA[36]#
SDATA[37]#
SDATA[38]#
SDATA[39]#
SDATA[40]#
SDATA[41]#
SDATA[42]#
SDATA[43]#
SDATA[44]#
SDATA[45]#
SDATA[46]#
SDATA[47]#
SDATA[48]#
SDATA[49]#
SDATA[50]#
SDATA[51]#
SDATA[52]#
SDATA[53]#
SDATA[54]#
SDATA[55]#
SDATA[56]#
SDATA[57]#
SDATA[58]#
SDATA[59]#
SDATA[60]#
SDATA[61]#
SDATA[62]#
SDATA[63]#
SDATAINCLK[0]#
SDATAINCLK[1]#
SDATAINCLK[2]#
SDATAINCLK[3]#
SDATAINVALID#
SDATAOUTCLK[0]#
SDATAOUTCLK[1]#
SDATAOUTCLK[2]#
Pin
E29
A27
A25
E21
C23
C27
A23
A35
C35
C33
C31
A29
C29
E23
C25
E17
E13
E11
C15
E9
A13
C9
A9
C21
A21
E19
C19
C17
A11
A17
A15
W33
J35
E27
E15
AN33
AE35
C37
A33
Chapter 10
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 23. Pin Name Abbreviations (continued)
Abbreviation
SDOC#3
SDOV#
SFILLV#
SVID[0]
SVID[1]
SVID[2]
SVID[3]
SVID[4]
STPC#
THDA
THDC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Chapter 10
Full Name
SDATAOUTCLK[3]#
SDATAOUTVALID#
SFILLVALID#
SMI#
SOFTVID[0]
SOFTVID[1]
SOFTVID[2]
SOFTVID[3]
SOFTVID[4]
STPCLK#
TCK
TDI
TDO
THERMDA
THERMDC
TMS
TRST#
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
Pin
C11
AL31
AJ31
AN5
F8
K8
H6
H8
H10
AC1
Q1
U1
U5
S7
U7
Q3
U3
B4
B8
B12
B16
B20
B24
B28
B32
B36
D2
D4
D8
D12
D16
D20
D24
D28
D32
F12
F16
F20
F24
Table 23. Pin Name Abbreviations (continued)
Abbreviation
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Pin Descriptions
Full Name
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
Pin
F28
F32
F34
F36
H2
H4
H12
H16
H20
H24
K32
K34
K36
M2
M4
M6
M8
P30
P32
P34
P36
R2
R4
R6
R8
T30
T32
T34
T36
V2
V4
V6
V8
X30
X32
X34
X36
Z2
Z4
67
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
Table 23. Pin Name Abbreviations (continued)
Abbreviation
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
68
Full Name
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
Pin
Z6
Z8
AB30
AB32
AB34
AB36
AD2
AD4
AD6
AF14
AF18
AF22
AF26
AF34
AF36
AH2
AH4
AH10
AH14
AH18
AH22
AH26
AJ5
AK10
AK14
AK18
AK22
AK26
AK30
AK34
AK36
AL5
AM2
AM10
AM14
AM18
AM22
AM26
AM30
24068F—December 2001
Table 23. Pin Name Abbreviations (continued)
Abbreviation
VCC
VREF_S
Pin Descriptions
Full Name
VCC_CORE
VCCA
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VREF_SYS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Pin
AM34
AJ23
L1
L3
L5
L7
J7
W5
B2
B6
B10
B14
B18
B22
B26
B30
B34
D6
D10
D14
D18
D22
D26
D30
D34
D36
F2
F4
F6
F10
F14
F18
F22
F26
H14
H18
H22
H26
H34
Chapter 10
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 23. Pin Name Abbreviations (continued)
Abbreviation
Full Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Chapter 10
Pin
H36
K2
K4
K6
M30
M32
M34
M36
P2
P4
P6
P8
R30
R32
R34
R36
T2
T4
T6
T8
V30
V32
V34
V36
X2
X4
X6
X8
Z30
Z32
Z34
Z36
AB2
AB8
AB4
AB6
AD32
AD34
AD36
Table 23. Pin Name Abbreviations (continued)
Abbreviation
Pin Descriptions
Full Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ZN
ZP
Pin
AF12
AF16
AF2
AF20
AF24
AH16
AH34
AF4
AH12
AH20
AH24
AH28
AH32
AH36
AK2
AK4
AK12
AK16
AK20
AK24
AK28
AK32
AM4
AM6
AM12
AM16
AM20
AM24
AM28
AM32
AM36
AC5
AE5
69
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
10.2
Pin List
Table 24 cross-references Socket A pin location to signal name.
The “L” (Level) column shows the electrical specification for
this pin. “P” indicates a push-pull mode driven by a single
source. “O” indicates open-drain mode that allows devices to
share the pin.
Note: Socket A AMD Duron processors support push-pull drivers.
For more information, see “Push-Pull (PP) Drivers” on
page 6.
The “P” (Port) column indicates if this signal is an input (I),
output (O), or bidirectional (B) signal. The “R” (Reference)
column indicates if this signal should be referenced to VSS (G)
or VCC_CORE (P) planes for the purpose of signal routing with
respect to the current return paths. The “–” is used to indicate
that this description is not applicable for this pin.
Table 24. Cross-Reference by Pin Location
Pin
Name
Table 24. Cross-Reference by Pin Location
Description
L
P
R
page 80
–
–
–
A35
Pin
Name
Description
L
P
R
SDATA[40]#
P
B
G
A1
No Pin
A3
SADDOUT[12]#
P
O
G
A37
SDATA[30]#
P
B
P
A5
SADDOUT[5]#
P
O
G
B2
VSS
–
-
-
A7
SADDOUT[3]#
P
O
G
B4
VCC_CORE
-
-
-
A9
SDATA[55]#
P
B
P
B6
VSS
-
-
-
A11
SDATA[61]#
P
B
P
B8
VCC_CORE
-
-
-
A13
SDATA[53]#
P
B
G
B10
VSS
-
-
-
A15
SDATA[63]#
P
B
G
B12
VCC_CORE
-
-
-
A17
SDATA[62]#
P
B
G
B14
VSS
-
-
-
A19
NC Pin
-
-
-
B16
VCC_CORE
-
-
-
A21
SDATA[57]#
P
B
G
B18
VSS
-
-
-
A23
SDATA[39]#
P
B
G
B20
VCC_CORE
-
-
-
A25
SDATA[35]#
P
B
P
B22
VSS
-
-
-
A27
SDATA[34]#
P
B
P
B24
VCC_CORE
-
-
-
A29
SDATA[44]#
P
B
G
B26
VSS
-
-
-
A31
NC Pin
-
-
-
B28
VCC_CORE
-
-
-
A33
SDATAOUTCLK[2]#
P
O
P
B30
VSS
-
-
-
Chapter 10
page 80
page 80
Pin Descriptions
70
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 24. Cross-Reference by Pin Location (continued)
Table 24. Cross-Reference by Pin Location
Pin
Name
Description
L
P
R
Pin
Name
Description
L
P
R
B32
VCC_CORE
-
-
-
D26
VSS
-
-
-
B34
VSS
-
-
-
D28
VCC_CORE
-
-
-
B36
VCC_CORE
-
-
-
D30
VSS
-
-
-
C1
SADDOUT[7]#
P
O
G
D32
VCC_CORE
-
-
-
C3
SADDOUT[9]#
P
O
G
D34
VSS
-
-
-
C5
SADDOUT[8]#
P
O
G
D36
VSS
-
-
-
C7
SADDOUT[2]#
P
O
G
E1
SADDOUT[11]#
P
O
P
C9
SDATA[54]#
P
B
P
E3
SADDOUTCLK#
P
O
G
C11
SDATAOUTCLK[3]#
P
O
G
E5
SADDOUT[4]#
P
O
P
C13
NC Pin
-
-
-
E7
SADDOUT[6]#
P
O
G
C15
SDATA[51]#
P
B
P
E9
SDATA[52]#
P
B
P
C17
SDATA[60]#
P
B
G
E11
SDATA[50]#
P
B
P
C19
SDATA[59]#
P
B
G
E13
SDATA[49]#
P
B
G
C21
SDATA[56]#
P
B
G
E15
SDATAINCLK[3]#
P
I
G
C23
SDATA[37]#
P
B
P
E17
SDATA[48]#
P
B
P
C25
SDATA[47]#
P
B
G
E19
SDATA[58]#
P
B
G
C27
SDATA[38]#
P
B
G
E21
SDATA[36]#
P
B
P
C29
SDATA[45]#
P
B
G
E23
SDATA[46]#
P
B
P
C31
SDATA[43]#
P
B
G
E25
NC Pin
-
-
-
C33
SDATA[42]#
P
B
G
E27
SDATAINCLK[2]#
P
I
G
C35
SDATA[41]#
P
B
G
E29
SDATA[33]#
P
B
P
C37
SDATAOUTCLK[1]#
P
O
G
E31
SDATA[32]#
P
B
P
D2
VCC_CORE
-
-
-
E33
NC Pin
-
-
-
D4
VCC_CORE
-
-
-
E35
SDATA[31]#
P
B
P
D6
VSS
-
-
-
E37
SDATA[22]#
P
B
G
D8
VCC_CORE
-
-
-
F2
VSS
-
-
-
D10
VSS
-
-
-
F4
VSS
-
-
-
D12
VCC_CORE
-
-
-
F6
VSS
-
-
-
D14
VSS
-
-
-
F8
SOFTVID[0]
O
O
-
D16
VCC_CORE
-
-
-
F10
VSS
-
-
-
D18
VSS
-
-
-
F12
VCC_CORE
-
-
-
D20
VCC_CORE
-
-
-
F14
VSS
-
-
-
D22
VSS
-
-
-
F16
VCC_CORE
-
-
-
D24
VCC_CORE
-
-
-
F18
VSS
-
-
-
Chapter 10
page 80
Pin Descriptions
page 80
page 80
page 81
71
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 24. Cross-Reference by Pin Location (continued)
Table 24. Cross-Reference by Pin Location
Pin
Name
Description
L
P
R
Pin
Name
Description
L
P
R
F20
VCC_CORE
-
-
-
H14
VSS
-
-
-
F22
VSS
-
-
-
H16
VCC_CORE
-
-
-
F24
VCC_CORE
-
-
-
H18
VSS
-
-
-
F26
VSS
-
-
-
H20
VCC_CORE
-
-
-
F28
VCC_CORE
-
-
-
H22
VSS
-
-
-
F30
NC Pin
-
-
-
H24
VCC_CORE
-
-
-
F32
VCC_CORE
-
-
-
H26
VSS
-
-
-
F34
VCC_CORE
-
-
-
H28
NC Pin
page 80
-
-
-
F36
VCC_CORE
-
-
-
H30
NC Pin
page 80
-
-
-
G1
SADDOUT[10]#
P
O
P
H32
NC Pin
page 80
-
-
-
G3
SADDOUT[14]#
P
O
G
H34
VSS
-
-
-
G5
SADDOUT[13]#
P
O
G
H36
VSS
-
-
-
G7
Key Pin
page 80
-
-
-
J1
SADDOUT[0]#
page 81
P
O
-
G9
Key Pin
page 80
-
-
-
J3
SADDOUT[1]#
page 81
P
O
-
G11
NC Pin
page 80
-
-
-
J5
NC Pin
page 80
-
-
-
G13
NC Pin
page 80
-
-
-
J7
VID[4]
page 81
O
O
-
G15
Key Pin
page 80
-
-
-
J31
NC Pin
page 80
-
-
-
G17
Key Pin
page 80
-
-
-
J33
SDATA[19]#
P
B
G
G19
NC Pin
page 80
-
-
-
J35
SDATAINCLK[1]#
P
I
P
G21
NC Pin
page 80
-
-
-
J37
SDATA[29]#
P
B
P
G23
Key Pin
page 80
-
-
-
K2
VSS
-
-
-
G25
Key Pin
page 80
-
-
-
K4
VSS
-
-
-
G27
NC Pin
page 80
-
-
-
K6
VSS
-
-
-
G29
NC Pin
page 80
-
-
-
K8
SOFTVID[1]
page 81
O
O
-
G31
NC Pin
page 80
-
-
-
K30
NC Pin
page 80
-
-
-
G33
SDATA[20]#
P
B
G
K32
VCC_CORE
-
-
-
G35
SDATA[23]#
P
B
G
K34
VCC_CORE
-
-
-
G37
SDATA[21]#
P
B
G
K36
VCC_CORE
-
-
-
H2
VCC_CORE
-
-
-
L1
VID[0]
page 81
O
O
-
H4
VCC_CORE
-
-
-
L3
VID[1]
page 81
O
O
-
H6
SOFTVID[2]
page 81
O
O
-
L5
VID[2]
page 81
O
O
-
H8
SOFTVID[3]
page 81
O
O
-
L7
VID[3]
page 81
O
O
-
H10
SOFTVID[4]
page 81
O
O
-
L31
NC Pin
page 80
-
-
-
H12
VCC_CORE
-
-
-
L33
SDATA[26]#
P
B
P
72
page 80
Pin Descriptions
Chapter 10
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 24. Cross-Reference by Pin Location (continued)
Table 24. Cross-Reference by Pin Location
Pin
Name
Description
L
P
R
Pin
page 80
-
-
-
R2
Name
Description
L
P
R
VCC_CORE
-
-
-
L35
NC Pin
L37
SDATA[28]#
P
B
P
R4
VCC_CORE
-
-
-
M2
VCC_CORE
-
-
-
R6
VCC_CORE
-
-
-
M4
VCC_CORE
-
-
-
R8
VCC_CORE
-
-
-
M6
VCC_CORE
-
-
-
R30
VSS
-
-
-
M8
VCC_CORE
-
-
-
R32
VSS
-
-
-
M30
VSS
-
-
-
R34
VSS
-
-
-
M32
VSS
-
-
-
R36
VSS
-
-
-
M34
VSS
-
-
-
S1
SCANCLK1
page 81
P
I
-
M36
VSS
-
-
-
S3
SCANINTEVAL
page 81
P
I
-
N1
RSVD
page 80
-
-
-
S5
SCANCLK2
page 81
P
I
-
N3
RSVD
page 80
-
-
-
S7
THERMDA
page 83
-
-
-
N5
RSVD
page 80
-
-
-
S31
NC Pin
page 80
-
-
-
N7
Key Pin
page 80
-
-
-
S33
SDATA[7]#
P
B
G
N31
NC Pin
page 80
-
-
-
S35
SDATA[15]#
P
B
P
N33
SDATA[25]#
P
B
P
S37
SDATA[6]#
P
B
G
N35
SDATA[27]#
P
B
P
T2
VSS
-
-
-
N37
SDATA[18]#
P
B
G
T4
VSS
-
-
-
P2
VSS
-
-
-
T6
VSS
-
-
-
P4
VSS
-
-
-
T8
VSS
-
-
-
P6
VSS
-
-
-
T30
VCC_CORE
-
-
-
P8
VSS
-
-
-
T32
VCC_CORE
-
-
-
P30
VCC_CORE
-
-
-
T34
VCC_CORE
-
-
-
P32
VCC_CORE
-
-
-
T36
VCC_CORE
-
-
-
P34
VCC_CORE
-
-
-
U1
TDI
page 79
P
I
-
P36
VCC_CORE
-
-
-
U3
TRST#
page 79
P
I
-
Q1
TCK
page 79
P
I
-
U5
TDO
page 79
P
O
-
Q3
TMS
page 79
P
I
-
U7
THERMDC
page 83
-
-
-
Q5
SCANSHIFTEN
page 81
P
I
-
U31
NC Pin
page 80
-
-
-
Q7
Key Pin
page 80
-
-
-
U33
SDATA[5]#
P
B
G
Q31
NC Pin
page 80
-
-
-
U35
SDATA[4]#
P
B
G
Q33
SDATA[24]#
P
B
P
U37
NC Pin
-
-
-
Q35
SDATA[17]#
P
B
G
V2
VCC_CORE
-
-
-
Q37
SDATA[16]#
P
B
G
V4
VCC_CORE
-
-
-
Chapter 10
Pin Descriptions
page 80
73
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 24. Cross-Reference by Pin Location (continued)
Table 24. Cross-Reference by Pin Location
Pin
Name
Description
L
P
R
Pin
Name
Description
L
P
R
V6
VCC_CORE
-
-
-
Z30
VSS
-
-
-
V8
VCC_CORE
-
-
-
Z32
VSS
-
-
-
V30
VSS
-
-
-
Z34
VSS
-
-
-
V32
VSS
-
-
-
Z36
VSS
-
-
-
V34
VSS
-
-
-
AA1
DBRDY
page 79
P
O
-
V36
VSS
-
-
-
AA3
DBREQ#
page 79
P
I
-
W1
FID[0]
page 79
O
O
-
AA5
NC Pin
page 80
-
-
-
W3
FID[1]
page 79
O
O
-
AA7
Key Pin
page 80
-
-
-
W5
VREF_SYS
page 83
P
-
-
AA31
NC Pin
page 80
-
-
-
W7
NC Pin
page 80
-
-
-
AA33
SDATA[8]#
P
B
P
W31
NC Pin
page 80
-
-
-
AA35
SDATA[0]#
P
B
G
W33
SDATAINCLK[0]#
P
I
G
AA37
SDATA[13]#
P
B
G
W35
SDATA[2]#
P
B
G
AB2
VSS
-
-
-
W37
SDATA[1]#
P
B
P
AB4
VSS
-
-
-
X2
VSS
-
-
-
AB6
VSS
-
-
-
X4
VSS
-
-
-
AB8
VSS
-
-
-
X6
VSS
-
-
-
AB30
VCC_CORE
-
-
-
X8
VSS
-
-
-
AB32
VCC_CORE
-
-
-
X30
VCC_CORE
-
-
-
AB34
VCC_CORE
-
-
-
X32
VCC_CORE
-
-
-
AB36
VCC_CORE
-
-
-
X34
VCC_CORE
-
-
-
AC1
STPCLK#
page 81
P
I
-
X36
VCC_CORE
-
-
-
AC3
PLLTEST#
page 80
P
I
-
Y1
FID[2]
page 79
O
O
-
AC5
ZN
page 83
P
-
-
Y3
FID[3]
page 79
O
O
-
AC7
NC Pin
page 80
-
-
-
Y5
NC Pin
page 80
-
-
-
AC31
NC Pin
page 80
-
-
-
Y7
Key Pin
page 80
-
-
-
AC33
SDATA[10]#
P
B
P
Y31
NC Pin
page 80
-
-
-
AC35
SDATA[14]#
P
B
G
Y33
NC Pin
page 80
-
-
-
AC37
SDATA[11]#
P
B
G
Y35
SDATA[3]#
P
B
G
AD2
VCC_CORE
-
-
-
Y37
SDATA[12]#
P
B
P
AD4
VCC_CORE
-
-
-
Z2
VCC_CORE
-
-
-
AD6
VCC_CORE
-
-
-
Z4
VCC_CORE
-
-
-
AD8
NC Pin
page 80
-
-
-
Z6
VCC_CORE
-
-
-
AD30
NC Pin
page 80
-
-
-
Z8
VCC_CORE
-
-
-
AD32
VSS
-
-
-
74
Pin Descriptions
Chapter 10
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 24. Cross-Reference by Pin Location (continued)
Table 24. Cross-Reference by Pin Location
Pin
Name
Description
L
P
R
Pin
Name
Description
L
P
R
AD34
VSS
-
-
-
AG13
COREFB#
page 78
-
-
-
AD36
VSS
-
-
-
AG15
Key Pin
page 80
-
-
-
AE1
A20M#
P
I
-
AG17
Key Pin
page 80
-
-
-
AE3
PWROK
P
I
-
AG19
NC Pin
page 80
-
-
-
AE5
ZP
page 83
P
-
-
AG21
NC Pin
page 80
-
-
-
AE7
NC Pin
page 80
-
-
-
AG23
NC Pin
page 80
-
-
-
AE31
NC Pin
page 80
-
-
-
AG25
NC Pin
page 80
-
-
-
AE33
SADDIN[5]#
P
I
G
AG27
Key Pin
page 80
-
-
-
AE35
SDATAOUTCLK[0]#
P
O
P
AG29
Key Pin
page 80
-
-
-
AE37
SDATA[9]#
P
B
G
AG31
NC Pin
page 80
-
-
-
AF2
VSS
-
-
-
AG33
SADDIN[2]#
P
I
G
AF4
VSS
-
-
-
AG35
SADDIN[11]#
P
I
G
AF6
NC Pin
page 80
-
-
-
AG37
SADDIN[7]#
P
I
P
AF8
NC Pin
page 80
-
-
-
AH2
VCC_CORE
-
-
-
AF10
NC Pin
page 80
-
-
-
AH4
VCC_CORE
-
-
-
AF12
VSS
-
-
-
AH6
AMD Pin
page 78
-
-
-
AF14
VCC_CORE
-
-
-
AH8
NC Pin
page 80
-
-
-
AF16
VSS
-
-
-
AH10
VCC_CORE
-
-
-
AF18
VCC_CORE
-
-
-
AH12
VSS
-
-
-
AF20
VSS
-
-
-
AH14
VCC_CORE
-
-
-
AF22
VCC_CORE
-
-
-
AH16
VSS
-
-
-
AF24
VSS
-
-
-
AH18
VCC_CORE
-
-
-
AF26
VCC_CORE
-
-
-
AH20
VSS
-
-
-
AF28
NC Pin
page 80
-
-
-
AH22
VCC_CORE
-
-
-
AF30
NC Pin
page 80
-
-
-
AH24
VSS
-
-
-
AF32
NC Pin
page 80
-
-
-
AH26
VCC_CORE
-
-
-
AF34
VCC_CORE
-
-
-
AH28
VSS
-
-
-
AF36
VCC_CORE
-
-
-
AH30
NC Pin
-
-
-
AG1
FERR
P
O
-
AH32
VSS
-
-
-
AG3
RESET#
-
I
-
AH34
VSS
-
-
-
AG5
NC Pin
page 80
-
-
-
AH36
VSS
-
-
-
AG7
Key Pin
page 80
-
-
-
AJ1
IGNNE#
page 79
P
I
-
AG9
Key Pin
page 80
-
-
-
AJ3
INIT#
page 79
P
I
-
AG11
COREFB
page 78
-
-
-
AJ5
VCC_CORE
-
-
-
Chapter 10
page 79
Pin Descriptions
page 80
75
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 24. Cross-Reference by Pin Location (continued)
Table 24. Cross-Reference by Pin Location
Pin
Name
Description
L
P
R
Pin
Name
Description
L
P
R
AJ7
NC Pin
page 80
-
-
-
AL1
INTR
page 79
P
I
-
AJ9
NC Pin
page 80
-
-
-
AL3
FLUSH#
page 79
P
I
-
AJ11
NC Pin
page 80
-
-
-
AL5
VCC_CORE
-
-
-
AJ13
Analog
page 78
-
-
-
AL7
NC Pin
page 80
-
-
-
AJ15
NC Pin
page 80
-
-
-
AL9
NC Pin
page 80
-
-
-
AJ17
NC Pin
page 80
-
-
-
AL11
NC Pin
page 80
-
-
-
AJ19
NC Pin
page 80
-
-
-
AL13
PLLMON2
page 80
O
O
-
AJ21
CLKFWDRST
page 78
P
I
P
AL15
PLLBYPASSCLK#
page 80
P
I
-
AJ23
VCCA
page 83
-
-
-
AL17
CLKIN#
page 78
P
I
P
AJ25
PLLBYPASS#
page 80
P
I
-
AL19
RSTCLK#
page 78
P
I
P
AJ27
NC Pin
page 80
-
-
-
AL21
K7CLKOUT
page 80
P
O
-
AJ29
SADDIN[0]#
page 81
P
I
-
AL23
CONNECT
page 78
P
I
P
AJ31
SFILLVALID#
P
I
G
AL25
NC Pin
page 80
-
-
-
AJ33
SADDINCLK#
P
I
G
AL27
NC Pin
page 80
-
-
-
AJ35
SADDIN[6]#
P
I
P
AL29
SADDIN[1]#
page 81
P
I
-
AJ37
SADDIN[3]#
P
I
G
AL31
SDATAOUTVALID#
P
O
P
AK2
VSS
-
-
-
AL33
SADDIN[8]#
P
I
P
AK4
VSS
-
-
-
AL35
SADDIN[4]#
P
I
G
AK6
CPU_PRESENCE#
page 78
-
-
-
AL37
SADDIN[10]#
P
I
G
AK8
NC Pin
page 80
-
-
-
AM2
VCC_CORE
-
-
-
AK10
VCC_CORE
-
-
-
AM4
VSS
-
-
-
AK12
VSS
-
-
-
AM6
VSS
-
-
-
AK14
VCC_CORE
-
-
-
AM8
NC Pin
-
-
-
AK16
VSS
-
-
-
AM10
VCC_CORE
-
-
-
AK18
VCC_CORE
-
-
-
AM12
VSS
-
-
-
AK20
VSS
-
-
-
AM14
VCC_CORE
-
-
-
AK22
VCC_CORE
-
-
-
AM16
VSS
-
-
-
AK24
VSS
-
-
-
AM18
VCC_CORE
-
-
-
AK26
VCC_CORE
-
-
-
AM20
VSS
-
-
-
AK28
VSS
-
-
-
AM22
VCC_CORE
-
-
-
AK30
VCC_CORE
-
-
-
AM24
VSS
-
-
-
AK32
VSS
-
-
-
AM26
VCC_CORE
-
-
-
AK34
VCC_CORE
-
-
-
AM28
VSS
-
-
-
AK36
VCC_CORE
-
-
-
AM30
VCC_CORE
-
-
-
76
Pin Descriptions
page 80
Chapter 10
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 24. Cross-Reference by Pin Location (continued)
Pin
Name
Description
L
P
R
AM32
VSS
-
-
-
AM34
VCC_CORE
-
-
-
AM36
VSS
-
-
-
AN1
No Pin
-
-
-
AN3
NMI
P
I
-
AN5
SMI#
P
I
-
AN7
NC Pin
page 80
-
-
-
AN9
NC Pin
page 80
-
-
-
AN11
NC Pin
page 80
-
-
-
AN13
PLLMON1
page 80
O
B
-
AN15
PLLBYPASSCLK
page 80
P
I
-
AN17
CLKIN
page 78
P
I
P
AN19
RSTCLK
page 78
P
I
P
AN21
K7CLKOUT#
page 80
P
O
-
AN23
PROCRDY
P
O
P
AN25
NC Pin
page 80
-
-
-
AN27
NC Pin
page 80
-
-
-
AN29
SADDIN[12]#
P
I
G
AN31
SADDIN[14]#
P
I
G
AN33
SDATAINVALID#
P
I
P
AN35
SADDIN[13]#
P
I
G
AN37
SADDIN[9]#
P
I
G
Chapter 10
page 80
Pin Descriptions
77
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
10.3
24068F—December 2001
Detailed Pin Descriptions
The information in this section pertains to Table 23 on page 64
and Table 24 on page 70.
A20M# Pin
A20M# is an input from the system used to simulate address
wrap-around in the 20-bit 8086.
AMD Pin
AMD Socket A processors do not implement a pin at location
AH6. All Socket A designs must have a top plate or cover that
blocks this pin location. When the cover plate blocks this
location, a non-AMD part (e.g., PGA370) does not fit into the
socket. However, socket manufacturers are allowed to have a
contact loaded in the AH6 position. Therefore, motherboard
socket design should account for the possibility that a contact
could be loaded in this position.
AMD Duron™ System
Bus Pins
See the AMD Athlon™ and AMD Duron™ System Bus
Specification, order# 21902 for information about the system
bus pins — PROCRDY, PWROK, RESET#, SADDIN[14:2]#,
SADDINCLK#, SADDOUT[14:2]#, SADDOUTCLK#,
SDATA[63:0]#, SDATAINCLK[3:0]#, SDATAINVALID#,
SDATAOUTCLK[3:0]#, SDATAOUTVALID#, SFILLVALID#.
Analog Pin
Treat this pin as a NC.
CLKFWDRST Pin
CLKFWDRST resets clock-forward circuitry for both the system
and processor.
CLKIN and RSTCLK
(SYSCLK) Pins
Connect CLKIN (AN17) with RSTCLK (AN19) and name it
SYSCLK. Connect CLKIN# (AL17) with RSTCLK# (AL19) and
name it SYSCLK#. Length match the clocks from the clock
generator to the Northbridge and processor.
See “SYSCLK and SYSCLK#” on page 83 for more information.
CONNECT Pin
CONNECT is an input from the system used for power
management and clock-forward initialization at reset.
COREFB and
COREFB# Pins
COREFB and COREFB# are outputs to the system that provide
processor core voltage feedback to the system.
CPU_PRESENCE# Pin
CPU_PRESENCE# is connected to VSS on the processor
package. If pulled-up on the motherboard, CPU_PRESENCE#
may be used to detect the presence or absence of a processor.
78
Pin Descriptions
Chapter 10
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
DBRDY and DBREQ#
Pins
DBRDY (AA1) and DBREQ# (AA3) are routed to the debug
connector. DBREQ# is tied to VCC_CORE with a pullup
resistor.
FERR Pin
FERR is an output to the system that is asserted for any
unmasked numerical exception independent of the NE bit in
CR0. FERR is a push-pull active High signal that must be
inverted and level shifted to an active Low signal. For more
information about FERR and FERR#, see the “Required
Circuits” chapter of the AMD Athlon™ Processor-Based
Motherboard Design Guide, order# 24363.
FID[3:0] Pins
The FID[3:0] pins drive a value of:
FID[3:0] = 0 1 0 0
that corresponds to a 5x SYSCLK multiplier after PWROK is
asserted to the processor. This information is used by the
Northbridge to create the SIP stream that the Northbridge
sends to the processor after RESET# is deasserted.
For more information, see “SYSCLK Multipliers” on page 24
and “Frequency Identification (FID[3:0])” on page 35 for the
AC and DC characteristics for FID[3:0].
FLUSH# Pin
FLUSH# must be tied to VCC_CORE with a pullup resistor. If a
debug connector is implemented, FLUSH# is routed to the
debug connector.
IGNNE# Pin
IGNNE# is an input from the system that tells the processor to
ignore numeric errors.
INIT# Pin
INIT# is an input from the system that resets the integer
registers without affecting the floating-point registers or the
internal caches. Execution starts at 0FFFF FFF0h.
INTR Pin
INTR is an input from the system that causes the processor to
start an interrupt acknowledge transaction that fetches the
8-bit interrupt vector and starts execution at that location.
JTAG Pins
TCK (Q1), TMS (Q3), TDI (U1), TRST# (U3), and TDO (U5) are
the JTAG interface. Connect these pins directly to the
motherboard debug connector. Pullup TDI, TCK, TMS, and
TRST# to VCC_CORE with pullup resistors.
Chapter 10
Pin Descriptions
79
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
K7CLKOUT and
K7CLKOUT# Pins
K7CLKOUT (AL21) and K7CLKOUT# (AN21) are each run for 2
to 3 inches and then terminated with a resistor pair, 100 ohms to
VCC_CORE and 100 ohms to VSS. The effective termination
resistance and voltage are 50 ohms and VCC_CORE/2.
Key Pins
These 16 locations are for processor type keying for forwards
and backwards compatibility (G7, G9, G15, G17, G23, G25, N7,
Q7, Y7, AA7, AG7, AG9, AG15, AG17, AG27, and AG29).
Motherboard designers should treat key pins like NC (No
Connect) pins. A socket designer has the option of creating a
top mold piece that allows PGA key pins only where designated.
However, sockets that populate all 16 key pins must be allowed,
so the motherboard must always provide for pins at all key pin
locations.
NC Pins
The motherboard should provide a plated hole for an NC pin.
The pin hole should not be electrically connected to anything.
NMI Pin
NMI is an input from the system that causes a non-maskable
interrupt.
PGA Orientation Pins
No pin is present at pin locations A1 and AN1. Motherboard
designers should not allow for a PGA socket pin at these
locations.
For more information, see the AMD Athlon™ Processor-Based
Motherboard Design Guide, order# 24363.
PLL Bypass and Test
Pins
PLLTEST# (AC3), PLLBYPASS# (AJ25), PLLMON1 (AN13),
P L L M O N 2 ( A L 1 3 ) , P L L B Y PA S S C L K ( A N 1 5 ) , a n d
PLLBYPASSCLK# (AL15) are the PLL bypass and test
interface. This interface is tied disabled on the motherboard.
All six pin signals are routed to the debug connector. All four
processor inputs (PLLTEST#, PLLBYPASS#, PLLMON1, and
PLLMON2) are tied to VCC_CORE with pullup resistors.
PWROK Pin
The PWROK input to the processor must not be asserted until
all voltage planes in the system are within specification and all
system clocks are running within specification.
Fo r m o re i n f o r m a t i o n , s e e “ S i g n a l a n d Po w e r -U p
Requirements” on page 53.
RSVD Pins
80
Reserved pins (N1, N3, and N5) must have pulldown resistors to
ground on the motherboards.
Pin Descriptions
Chapter 10
Preliminary Information
24068F—December 2001
Mobile AMD Duron™ Processor Model 7 Data Sheet
SADDIN[1:0]# and
SADDOUT[1:0]# Pins
The mobile AMD Duron processor model 7 does not support
SADDIN[1:0]# or SADDOUT[1:0]#. SADDIN[1]# is tied to VCC
with pullup resistors, if this bit is not supported by the
Northbridge (future models of the mobile AMD Duron
processors may support SADDIN[1]#). SADDOUT[1:0]# are tied
to VCC with pullup resistors if these pins are supported by the
Northbridge. For more information, see the AMD Athlon™ and
AMD Duron™ System Bus Specification, order# 21902.
Scan Pins
SCANSHIFTEN (Q5), SCANCLK1 (S1), SCANINTEVAL (S3),
and SCANCLK2 (S5) are the scan interface. This interface is
AMD internal and is tied disabled with pulldown resistors to
ground on the motherboard.
SMI# Pin
SMI# is an input that causes the processor to enter the system
management mode.
SOFTVID[4:0] and
VID[4:0] Pins
The VID[4:0] (Voltage ID) and SOFTVID[4:0] (Software driven
Voltage ID) outputs are used by the DC to DC power converter
to select the processor core voltage. The VID[4:0] pins are
strapped to ground or left unconnected on the package and
must be pulled up on the motherboard. The SOFTVID[4:0] pins
are open drain and 2.5-V tolerant. The SOFTVID[4:0] pins of
the processor must not be pulled to voltages higher than 2.5 V.
The motherboard is required to implement a VID multiplexer to
select a deterministic voltage for the processor at power–up
before the PWROK input is asserted. Before PWROK is
asserted, the VID multiplexer drives the VID value from
VID[4:0] pins to the DC to DC converter for VCC_CORE. After
PWROK is asserted, the VID multiplexer drives the VID value
from the SOFTVID[4:0] pins to the DC to DC converter for
VCC_CORE of the processor. Refer to the AMD Athlon™
Processor-Based Motherboard Design Guide, order# 24363 for the
recommended VID multiplexer circuit.
The SOFTVID[4:0] pins are driven by the processor to select the
maximum VCC_CORE of the processor as reported by the
Maximum VID field of the FidVidStatus MSR within 20 ns of
P W RO K a s s e r t i o n . B e f o re P W RO K i s a s s e r t e d , t h e
SOFTVID[4:0] outputs are not driven to a deterministic value.
The SOFTVID[4:0] outputs must be used to select VCC_CORE
after PWROK is asserted. Any time the RESET# input is
asserted, the SOFTVID[4:0] pins will be driven to select the
maximum voltage.
Chapter 10
Pin Descriptions
81
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Note: The Start–up VID and Maximum VID fields of the
FidVidStatus MSR report the same value that corresponds
to the nominal voltage that the processor requires to operate
at maximum frequency.
AMD PowerNow!™ technology can use the FID_Change
protocol described in Section on page 9 to transition the
SOFTVID[4:0] outputs and therefore VCC_CORE as part of
processor performance state transitions.
The VID codes used by the mobile AMD Duron processor model
7 are defined in Table 25.
Note: VID codes for the mobile AMD Duron processors are
different from the VID codes for the desktop AMD Duron
processors.
Table 25. SOFTVID[4:0] and VID[4:0] Code to Voltage Definition
STPCLK# Pin
82
VID[4:0]
VCC_CORE (V)
VID[4:0]
VCC_CORE (V)
00000
2.000
10000
1.275
00001
1.950
10001
1.250
00010
1.900
10010
1.225
00011
1.850
10011
1.200
00100
1.800
10100
1.175
00101
1.750
10101
1.150
00110
1.700
10110
1.125
00111
1.650
10111
1.100
01000
1.600
11000
1.075
01001
1.550
11001
1.050
01010
1.500
11010
1.025
01011
1.450
11011
1.000
01100
1.400
11100
0.975
01101
1.350
11101
0.950
01110
1.300
11110
0.925
01111
Shutdown
11111
Shutdown
STPCLK# is an input that causes the processor to enter a lower
power mode and issue a Stop Grant special cycle.
Pin Descriptions
Chapter 10
Preliminary Information
24068F—December 2001
Mobile AMD Duron™ Processor Model 7 Data Sheet
SYSCLK and SYSCLK#
SYSCLK and SYSCLK# are differential input clock signals
provided to the processor’s PLL from a system-clock generator.
See “CLKIN and RSTCLK (SYSCLK) Pins” on page 78 for more
information.
THERMDA and
THERMDC Pins
Thermal Diode anode (THERMDA) and cathode (THERMDC)
pins are used to monitor the actual temperature of the
processor die, providing more accurate temperature control to
the system. See Table 17 on page 48 for more details.
VCCA Pin
VCCA is the processor PLL supply. For information about the
VCCA pin, see Table 7, “VCCA AC and DC Characteristics,” on
page 35 and the AMD Athlon™ Processor-Based Motherboard
Design Guide, order# 24363.
VREF_SYS Pin
VREF_SYS (W5) drives the threshold voltage for the system
bus input receivers. The value of VREF_SYS is system specific.
In addition, to minimize VCC_CORE noise rejection from
V R EF _ SYS , in c lu de de c o u pl ing c ap a c it ors. Fo r m o re
information, see the AMD Athlon™ Processor-Based Motherboard
Design Guide, order# 24363.
ZN and ZP Pins
ZN (AC5) and ZP (AE5) are the push-pull compensation circuit
pins. In Push-Pull mode (selected by the SIP parameter
SysPushPull asserted), ZN is tied to VCC_CORE with a resistor
that has a resistance matching the impedance Z 0 of the
transmission line. ZP is tied to VSS with a resistor that has a
resistance matching the impedance Z0 of the transmission line.
Chapter 10
Pin Descriptions
83
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
84
Pin Descriptions
24068F—December 2001
Chapter 10
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
11
11.1
Ordering Information
Standard Mobile AMD Duron™ Processor Model 7 Products
AMD standard products are available in several operating
ranges. The ordering part number (OPN) is formed by a
combination of the elements shown in Figure 17. This OPN is
given as an example only.
CPGA OPN
D HM 1000 A V S 1 B
Max FSB: B= 200 MHz
Size of L2 Cache: 1=64Kbytes
Die Temperature: S=95ºC
Operating Voltage: L=1.50 V, Q=1.45 V, V=1.40 V
Package Type: A = CPGA
Speed: 0800=800 MHz, 0850=850, 0900=900 MHz,
0950=950 MHz, 1000=1000 MHz
Generation: HM = High-Performance Processor for Mobile Systems
Family/Architecture: D = AMD Duron™ Processor Architecture
Note: Spaces are added to the number shown
above for viewing clarity only.
Figure 17. OPN Example for the Mobile AMD Duron™ Processor Model 7
Chapter 11
Ordering Information
85
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
86
Ordering Information
24068F—December 2001
Chapter 11
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Appendix A
Conventions, Abbreviations,
and References
This section contains information about the conventions and
abbreviations used in this document.
Signals and Bits
■
Active-Low Signals—Signal names containing a pound sign,
such as SFILL#, indicate active-Low signals. They are
asserted in their Low-voltage state and negated in their
High-voltage state. When used in this context, High and
Low are written with an initial upper case letter.
■
Signal Ranges—In a range of signals, the highest and lowest
signal numbers are contained in brackets and separated by
a colon (for example, D[63:0]).
Reserved Bits and Signals—Signals or bus bits marked
reserved must be driven inactive or left unconnected, as
indicated in the signal descriptions. These bits and signals
are reserved by AMD for future implementations. When
software reads registers with reserved bits, the reserved bits
must be masked. When software writes such registers, it
must first read the register and change only the
non-reserved bits before writing back to the register.
Three-State—In timing diagrams, signal ranges that are
high impedance are shown as a straight horizontal line
half-way between the high and low levels.
■
■
Appendix A
87
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
■
24068F—December 2001
Invalid and Don’t-Care—In timing diagrams, signal ranges
that are invalid or don't-care are filled with a screen
pattern.
Data Terminology
The following list defines data terminology:
■
■
■
■
■
■
■
88
Quantities
• A word is two bytes (16 bits)
• A doubleword is four bytes (32 bits)
• A quadword is eight bytes (64 bits)
• A mobile AMD Duron processor model 7 cache line is
eight quadwords (64 bytes)
Addressing—Memory is addressed as a series of bytes on
eight-byte (64-bit) boundaries in which each byte can be
separately enabled.
Abbreviations—The following notation is used for bits and
bytes:
• Kilo (K, as in 4-Kbyte page)
• Mega (M, as in 4 Mbits/sec)
• Giga (G, as in 4 Gbytes of memory space)
See Table 26 for more abbreviations.
Little-Endian Convention—The byte with the address
xx...xx00 is in the least-significant byte position (little end).
In byte diagrams, bit positions are numbered from right to
left—the little end is on the right and the big end is on the
left. Data structure diagrams in memory show low addresses
at the bottom and high addresses at the top. When data
items are aligned, bit notation on a 64-bit data bus maps
directly to bit notation in 64-bit-wide memory. Because byte
addresses increase from right to left, strings appear in
reverse order when illustrated.
Bit Ranges—In text, bit ranges are shown with a dash (for
example, bits 9–1). When accompanied by a signal or bus
name, the highest and lowest bit numbers are contained in
brackets and separated by a colon (for example, AD[31:0]).
Bit Values—Bits can either be set to 1 or cleared to 0.
Hexadecimal and Binary Numbers—Unless the context
makes interpretation clear, hexadecimal numbers are
followed by an h and binary numbers are followed by a b.
Appendix A
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Abbreviations and Acronyms
Table 26 contains the definitions of abbreviations used in this
document.
Table 26.
Abbreviations
Appendix A
Abbreviation
Meaning
A
Ampere
F
Farad
G
Giga–
Gbit
Gigabit
Gbyte
Gigabyte
H
Henry
h
Hexadecimal
K
Kilo–
Kbyte
Kilobyte
M
Mega–
Mbit
Megabit
Mbyte
Megabyte
MHz
Megahertz
m
Milli–
ms
Millisecond
mW
Milliwatt
µ
Micro–
µA
Microampere
µF
Microfarad
µH
Microhenry
µs
Microsecond
µV
Microvolt
n
nano–
nA
nanoampere
nF
nanofarad
nH
nanohenry
ns
nanosecond
ohm
Ohm
pF
picofarad
pH
picohenry
ps
picosecond
89
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
Table 26.
24068F—December 2001
Abbreviations (continued)
Abbreviation
Meaning
s
Second
V
Volt
W
Watt
Table 27 contains the definitions of acronyms used in this
document.
Table 27.
Acronyms
90
Abbreviation
Meaning
ACPI
Advanced Configuration and Power Interface
AGP
Accelerated Graphics Port
APCI
AGP Peripheral Component Interconnect
API
Application Programming Interface
BIOS
Basic Input/Output System
BIST
Built-In Self-Test
BIU
Bus Interface Unit
CPGA
Ceramic Pin Grid Array
DDR
Double-Data Rate
DIMM
Dual Inline Memory Module
DMA
Direct Memory Access
DRAM
Direct Random Access Memory
EIDE
Enhanced Integrated Device Electronics
EISA
Extended Industry Standard Architecture
EPROM
Enhanced Programmable Read Only Memory
FIFO
First In, First Out
GART
Graphics Address Remapping Table
HSTL
High-Speed Transistor Logic
IDE
Integrated Device Electronics
ISA
Industry Standard Architecture
JEDEC
Joint Electron Device Engineering Council
JTAG
Joint Test Action Group
LAN
Large Area Network
LRU
Least-Recently Used
LVTTL
Low Voltage Transistor to Transistor Logic
MSB
Most Significant Bit
MTRR
Memory Type and Range Registers
Appendix A
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Table 27.
Appendix A
Acronyms (continued)
Abbreviation
Meaning
MUX
Multiplexer
NMI
Non-Maskable Interrupt
OBGA
Organic Ball Grid Array
OD
Open Drain
PBGA
Plastic Ball Grid Array
PA
Physical Address
PCI
Peripheral Component Interconnect
PDE
Page Directory Entry
PDT
Page Directory Table
PLL
Phase Locked Loop
PMSM
Power Management State Machine
POS
Power-On Suspend
POST
Power-On Self-Test
RAM
Random Access Memory
ROM
Read Only Memory
RXA
Read Acknowledge Queue
SDI
System DRAM Interface
SDRAM
Synchronous Direct Random Access Memory
SIP
Serial Initialization Packet
SMbus
System Management Bus
SPD
Serial Presence Detect
SRAM
Synchronous Random Access Memory
SROM
Serial Read Only Memory
TLB
Translation Lookaside Buffer
TOM
Top of Memory
TTL
Transistor to Transistor Logic
VAS
Virtual Address Space
VPA
Virtual Page Address
VGA
Video Graphics Adapter
USB
Universal Serial Bus
ZDB
Zero Delay Buffer
91
Preliminary Information
Mobile AMD Duron™ Processor Model 7 Data Sheet
24068F—December 2001
Related Publications
The following books discuss various aspects of computer
architecture that may enhance your understanding of AMD
products:
AMD Publications
Mobile AMD Athlon™ and Mobile AMD Duron™ Processor
System Requirements, order# 24106
Mobile AMD Athlon™ and Mobile AMD Duron™ Processor Power
Module Supply Design Guide, order# 24125
Mobile System Thermal Design Guide, order# 24383
Measuring Temperature on AMD Athlon™ and AMD Duron™ Pin
Grid Array Processors with and without an On-die Thermal Diode,
order# 24228
Thermal Characterization of Notebook PCs, order# 24382
Methodologies for Measuring Power, order# 24353
Methodologies for Measuring Temperature on AMD Athlon™ and
AMD Duron™ Processors, order# 24228
Instruction Sheet for Mobile Thermal Kits, order# 24400
AMD Mobile Thermal Kit Documentation and Software CD–ROM,
order# 24406
Websites
Visit the AMD website for documentation of AMD products.
www.amd.com
Other websites of interest include the following:
■
■
■
92
JEDEC home page—www.jedec.org
IEEE home page—www.computer.org
AGP Forum—www.agpforum.org
Appendix A