Revised February 2002 74ALVC16835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs General Description Features The ALVC16835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. ■ Compatible with PC100 DIMM module specifications Data flow is controlled by output-enable (OE), latch-enable (LE), and clock (CLK) inputs. The device operates in Transparent Mode when LE is held HIGH. The device operates in clocked mode when LE is LOW and CLK is toggled. Data transfers from the Inputs (In) to Ouputs (O n) on a Positive Edge Transition of the Clock. When OE is LOW, the output data is enabled. When OE is HIGH the output port is in a high impedance state. The 74ALVC16835 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V. The 74ALVC16835 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. ■ 1.65V to 3.6V VCC supply operation ■ 3.6V tolerant inputs and outputs ■ tPD (CLK to O n) 4.5 ns max for 3.0V to 3.6V VCC 5.5 ns max for 2.3V to 2.7V VCC 9.2 ns max for 1.65V to 1.95V VCC ■ Power-off high impedance inputs and outputs ■ Supports live insertion/withdrawal (Note 1) ■ Latchup conforms to JEDEC JED78 ■ ESD performance: Human body model > 2000V Machine model >200V Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC (OE to GND) through a pulldown resistor; the minimum value of the resistor is determined by the current sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74ALVC16835MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2002 Fairchild Semiconductor Corporation DS500645 www.fairchildsemi.com 74ALVC16835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs September 2001 74ALVC16835 Connection Diagram Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW) LE Latch Enable Input CLK Clock Input I1 - I18 Data Inputs O1 - O18 3-STATE Outputs NC No Connect Truth Table Inputs Outputs LE CLK In H X X X L H X L L L H X H H L L ↑ L L L L ↑ H H L L H X O0 (Note 2) L L L X O0 (Note 3) OE On Z H = Logic HIGH L = Logic LOW X = Don’t Care, but not floating Z = High Impedance ↑ = LOW-to-HIGH Clock Transition Note 2: Output level before the indicated steady-state input conditions were established provided that CLK was HIGH before LE went LOW. Note 3: Output level before the indicated steady-state input conditions were established. Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions (Note 6) −0.5V to +4.6V Supply Voltage (VCC) −0.5V to 4.6V DC Input Voltage (VI) Output Voltage (VO) (Note 5) Power Supply −0.5V to VCC +0.5V Operating DC Input Diode Current (IIK) VI < 0V −50 mA 0V to VCC Output Voltage (VO) DC Output Diode Current (IOK) 0V to VCC Free Air Operating Temperature (TA) VO < 0V −50 mA −40°C to +85°C Minimum Input Edge Rate (∆t/∆V) VIN = 0.8V to 2.0V, VCC = 3.0V DC Output Source/Sink Current ±50 mA (IOH/IOL) ±100 mA Supply Pin (ICC or GND) 10 ns/V Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. DC VCC or GND Current per Storage Temperature Range (TSTG) 1.65V to 3.6V Input Voltage (VI) −65°C to +150°C Note 5: IO Absolute Maximum Rating must be observed, limited to 4.6V. Note 6: Floating or unused control inputs must be held HIGH or LOW. DC Electrical Characteristics Symbol VIH VIL VOH VOL Parameter Conditions HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage IOH = −100 µA VCC (V) Min 1.65 - 1.95 0.65 x VCC 2.3 - 2.7 1.7 2.7 - 3.6 2.0 Max V 1.65 - 1.95 0.35 x VCC 2.3 - 2.7 0.7 2.7 - 3.6 0.8 1.65 - 3.6 V VCC - 0.2 IOH = −4 mA 1.65 1.2 IOH = −6 mA 2.3 2.0 IOH = −12 mA 2.3 1.7 2.7 2.2 V 3.0 2.4 IOH = −24 mA 3.0 2 IOL = 100 µA 1.65 - 3.6 0.2 1.65 0.45 IOL = 4 mA Units IOL = 6 mA 2.3 0.4 IOL = 12 mA 2.3 0.7 2.7 0.4 IOL = 24 mA 3.0 0.55 V II Input Leakage Current 0 ≤ VI ≤ 3.6V 3.6 ±5.0 µA IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 3.6V 3.6 ±10 µA ICC Quiescent Supply Current VI = V CC or GND, IO = 0 3.6 40 µA ∆ICC Increase in ICC per Input VIH = VCC − 0.6V 3 - 3.6 750 µA 3 www.fairchildsemi.com 74ALVC16835 Absolute Maximum Ratings(Note 4) 74ALVC16835 AC Electrical Characteristics TA = −40°C to +85°C, RL = 500Ω Symbol CL = 50 pF Parameter VCC = 3.3V ± 0.3V Min fCLOCK Clock Frequency tW Pulse Width LE High tS Setup Time Data Before CLK ↑ Hold Time Max 3.3 Min 3.3 3.3 4.0 2.1 2.2 2.5 1.6 1.9 1.1 1.3 0.7 0.6 0.6 1.4 1.7 1.4 Maximum Clock Frequency 100 1.7 1.5 tPHL, tPLH Propagation Delay 150 I to O 150 Max MHz 4.0 3.3 1.0 or Low Min 3.3 CLK Low CLK High Max 150 Data Before LE ↓ CLK High Data After CLK ↑ Units VCC = 2.5V ± 0.2V VCC = 1.8V ± 0.15V 150 3.3 Data After LE ↓ fMAX Min 150 CLK High or Low tH Max CL = 30 pF VCC = 2.7V ns ns 1.0 ns 150 100 MHz 1 3.6 4.2 1.0 4.2 1.5 8.4 LE to O 1.3 4.2 4.9 1.3 5.0 1.5 9.8 CLK to O 1.4 4.5 5.2 1.4 5.5 2 9.2 tPZL, tPZH Output Enable Time 1.1 4.6 5.6 1.4 5.5 1.5 9.8 ns tPLZ, tPHZ Output Disable Time 1.3 3.9 4.3 1.0 4.5 1.5 7.6 ns ns AC Electrical Characteristics Over Load (Note 7) RL = 500Ω, VCC = 3.3 ± 0.15V TA = −0°C to +85°C TA = −0°C to +65°C CL = 0 pF CL = 50 pF Units Symbol Parameter Min Max Min Max tPHL, tPLH Propagation Delay Bus to Bus 0.9 2.0 1.0 4.0 ns tPHL, tPLH Propagation Delay Clock to Bus 1.5 2.9 1.7 4.5 ns Note 7: This parameter is guaranteed by characterization but not tested. Capacitance Symbol CIN Parameter Input Capacitance COUT Output Capacitance CPD Power Dissipation Capacitance www.fairchildsemi.com Conditions TA = +25°C Units VCC Typical Control VI = 0V or VCC 3.3 3 Data VI = 0V or VCC 3.3 6 VI = 0V or VCC 3.3 7 Outputs Enabled f = 10 MHz, CL = 0 pF 3.3 31 2.5 26 Outputs Disabled f = 10 MHz, CL = 0 pF 3.3 14 2.5 12 4 pF pF pF 74ALVC16835 IOUT - VOUT Characteristics IOH versus VOH FIGURE 1. Characteristics for Output - Pull Up Driver IOL versus VOL FIGURE 2. Characteristics for Output - Pull Down Driver 5 www.fairchildsemi.com 74ALVC16835 AC Loading and Waveforms TABLE 1. TEST SWITCH tPLH, tPHL Open tPZL, tPLZ VL tPZH, tPHZ GND FIGURE 3. AC Test Circuit TABLE 2. Variable Matrix (Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50Ω) Symbol VCC 3.3V ± 0.3V 2.7V 2.5V ± 0.2V 1.8 ± 0.15V Vmi 1.5V 1.5V VCC/2 VCC/2 Vmo 1.5V 1.5V VCC/2 VCC/2 VX VOL + 0.3V VOL + 0.3V VOL + 0.15V VOL + 0.15V VY VOH − 0.3V VOH − 0.3V VOH − 0.15V VOH − 0.15V VL 6V 6V VCC/*2 VCC/*2 FIGURE 5. 3-STATE Output High Enable and Disable Times for Low Voltage Logic tr = tf ≤ 2.0ns, 10% to 90% FIGURE 4. Waveform for Inverting and Non-inverting Functions tr = tf ≤ 2.0ns, 10% to 90% FIGURE 6. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic tr = tf ≤ 2.0ns, 10% to 90% www.fairchildsemi.com 6 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com 74ALVC16835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted