Revised October 2004 74VCX16601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs General Description Features The VCX16601 is an 18-bit universal bus transceiver which combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. ■ 3.6V tolerant inputs and outputs Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH-toLOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. When OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA. The VCX16601 is designed for low voltage (1.4V to 3.6V) VCC applications with I/O capability up to 3.6V. The VCX16601 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. ■ 1.4V to 3.6V VCC supply operation ■ tPD (A to B, B to A) 2.9 ns max for 3.0V to 3.6V VCC ■ Power-down high impedance inputs and outputs ■ Supports live insertion/withdrawal (Note 1) ■ Static Drive (IOH/IOL) ±24 mA @ 3.0V VCC ■ Uses patented noise/EMI reduction circuitry ■ Latchup performance exceeds 300 mA ■ ESD performance: Human body model > 2000V Machine model >200V ■ Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number 74VCX16601GX (Note 2) 74VCX16601MTD (Note 3) Package Number BGA54A (Preliminary) MTD56 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 2: BGA package available in Tape and Reel only. Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2004 Fairchild Semiconductor Corporation DS500126 www.fairchildsemi.com 74VCX16601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs March 1998 74VCX16601 Connection Diagrams Pin Descriptions Pin Assignment for TSSOP Pin Names Description OEAB, OEBA Output Enable Inputs (Active LOW) LEAB, LEBA Latch Enable Inputs CLKAB, CLKBA Clock Inputs CLKENAB, CLKENBA Clock Enable Inputs A1–A18 Side A Inputs or 3-STATE Outputs B1–B18 Side B Inputs or 3-STATE Outputs FBGA Pin Assignments 1 2 5 6 A A2 A1 OEAB CLKENAB 3 4 B1 B2 B A4 A3 LEAB CLKAB B3 B4 C A6 A5 VCC VCC B5 B6 D A8 A7 GND GND B7 B8 E A10 A9 GND GND B9 B10 F A12 A11 GND GND B11 B12 G A14 A13 VCC VCC B13 B14 H A16 A15 OEBA CLKBA B15 B16 J A17 A18 LEBA CLKENBA B18 B17 Truth Table (Note 4) Inputs CLKENAB Pin Assignment for FBGA Outputs OEAB LEAB CLKAB An Bn X Z X H X X X L H X L L X L H X H H H L L X X B0 (Note 5) H L L X X B0 (Note 5) L L L ↑ L L L L L ↑ H H L L L L X B0 (Note 5) L L L H X B0 (Note 6) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance (Top Thru View) Note 4: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA. Note 5: Output level before the indicated steady-state input conditions were established. Note 6: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. www.fairchildsemi.com 2 74VCX16601 Logic Diagram 3 www.fairchildsemi.com 74VCX16601 Absolute Maximum Ratings(Note 7) Recommended Operating Conditions (Note 9) Supply Voltage (VCC ) −0.5V to +4.6V DC Input Voltage (VI) −0.5V to +4.6V Power Supply Operating 1.4V to 3.6V −0.5V to +4.6V Input Voltage −0.3V to 3.6V Output Voltage (VO) Outputs 3-Stated Outputs Active (Note 8) −0.5 to VCC + 0.5V DC Input Diode Current (IIK) VI < 0V Output Voltage (VO) −50 mA Output in Active States DC Output Diode Current (IOK) VO < 0V −50 mA VO > VCC +50 mA ±50 mA (IOH/IOL) 0.0V to 3.6V Output Current in IOH/IOL DC Output Source/Sink Current VCC = 3.0V to 3.6V ±24 mA VCC = 2.3V to 2.7V ±18 mA VCC = 1.65V to 2.3V ±6 mA VCC = 1.4V to 1.6V DC VCC or Ground Current per ±100 mA Supply Pin (ICC or Ground) Storage Temperature Range (TSTG) 0V to VCC Output in 3-STATE ±2 mA Free Air Operating Temperature (TA) −65°C to +150 °C −40°C to +85°C Minimum Input Edge Rate (∆t/∆V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V Note 7: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The Recommended Operating Conditions tables will define the conditions for actual device operation. Note 8: IO Absolute Maximum Rating must be observed. Note 9: Floating or unused pin (inputs or I/O's) must be held HIGH or LOW. DC Electrical Characteristics Symbol VIH VIL Parameter Conditions HIGH Level Input Voltage VCC (V) 2.7 - 3.6 LOW Level Input Voltage Min HIGH Level Output Voltage 1.6 1.65 - 2.3 0.65 x VCC 1.4 - 1.6 0.65 x VCC 2.7 - 3.6 0.8 0.7 1.65 - 2.3 0.35 - VCC VCC - 0.2 IOH = −12 mA 2.7 2.2 IOH = −18 mA 3.0 2.4 IOH = −24 mA 3.0 2.2 IOH = −100 µA 2.3 - 2.7 VCC - 0.2 IOH = −6 mA 2.3 2.0 IOH = −12 mA 2.3 1.8 IOH = −18 mA 2.3 1.7 IOH = −100 µA 1.65 - 2.3 VCC - 0.2 IOH = −2 mA www.fairchildsemi.com 4 V 0.35 - VCC 2.7 - 3.6 IOH = −100 µA V 2.3 - 2.7 IOH = −100 µA IOH = −6 mA Units 2.0 2.3 - 2.7 1.4 - 1.6 VOH Max 1.65 1.25 1.4 - 1.6 VCC - 0.2 1.4 1.05 V Symbol (Continued) Parameter Conditions VCC Min Max Units (V) VOL LOW Level Output Voltage IOL = 100 µA 2.7 - 3.6 0.2 IOL = 12 mA 2.7 0.4 IOL = 18 mA 3.0 0.4 IOL = 24 mA 3.0 0.55 IOL = 100 µA 2.3 - 2.7 0.2 IOL = 12 mA 2.3 0.4 IOL = 18 mA 2.3 0.6 IOL = 100 µA 1.65 - 2.3 0.2 1.65 0.3 IOL = 6 mA IOL = 100 µA IOL = 2 mA 1.4 - 1.6 0.2 1.4 0.35 2.7 - 3.6 ±5.0 µA 1.4 - 3.6 ±10.0 µA 0 10.0 µA II Input Leakage Current 0V ≤ VI ≤ 3.6V IOZ 3-STATE Output Leakage 0V ≤ VO ≤ 3.6V IOFF Power Off Leakage Current 0V ≤ (VI, VO) ≤ 3.6V ICC Quiescent Supply Current VI = VCC or GND 1.4 - 3.6 20.0 VCC ≤ (VI, VO) ≤ 3.6V (Note 10) 1.4 - 3.6 ±20.0 VIH = VCC − 0.6V 2.7 - 3.6 750 VI = VIH or VIL ∆ICC Increase in ICC per Input V µA µA Note 10: Outputs disabled or 3-STATE only. 5 www.fairchildsemi.com 74VCX16601 DC Electrical Characteristics 74VCX16601 AC Electrical Characteristics (Note 11) Symbol fMAX Parameter Maximum Clock Frequency tPHL Propagation Delay tPLH Bus-to-Bus tPHL Propagation Delay tPLH Clock-to-Bus Conditions CL = 30 pF Propagation Delay tPLH LE-to-Bus tPZL Output Enable Time Output Disable Time tH tW Setup Time Hold Time Pulse Width tOSHL Output to Output Skew tOSLH (Note 12) Min Max 250 200 1.8 ± 0.15 100 CL = 15 pF 1.5 ± 0.1 80.0 CL = 30 pF, RL = 500Ω 3.3 ± 0.3 0.8 2.5 ± 0.2 1.0 3.5 1.8 ± 0.15 1.5 7.0 CL = 15 pF, RL = 2kΩ 1.5 ± 0.1 1.0 14.0 CL = 30 pF, RL = 500Ω 3.3 ± 0.3 0.8 3.5 2.5 ± 0.2 1.0 4.4 CL = 30 pF, RL = 500Ω 1.5 8.8 1.5 ± 0.1 1.0 17.6 3.3 ± 0.3 0.8 3.5 2.5 ± 0.2 1.0 4.4 1.8 ± 0.15 1.5 8.8 1.5 ± 0.1 1.0 17.6 CL = 30 pF, RL = 500Ω 3.3 ± 0.3 0.8 3.8 2.5 ± 0.2 1.0 4.9 1.8 ± 0.15 1.5 9.8 CL = 15 pF, RL = 2kΩ 1.5 ± 0.1 1.0 19.6 CL = 30 pF, RL = 500Ω 3.3 ± 0.3 0.8 3.7 2.5 ± 0.2 1.0 4.2 1.8 ± 0.15 1.5 7.6 CL = 15 pF, RL = 2kΩ 1.5 ± 0.1 1.0 15.2 CL = 30 pF, RL = 500Ω 3.3 ± 0.3 1.5 2.5 ± 0.2 1.5 1.8 ± 0.15 2.5 1.5 ± 0.1 3.0 CL = 30 pF, RL = 500Ω 3.3 ± 0.3 1.0 2.5 ± 0.2 1.0 1.8 ± 0.15 1.0 CL = 15 pF, RL = 500Ω 1.5 ± 0.1 2.0 CL = 30 pF, RL = 500Ω 3.3 ± 0.3 1.5 2.5 ± 0.2 1.5 1.8 ± 0.15 4.0 CL = 15 pF, RL = 500Ω 1.5 ± 0.1 4.0 CL = 30 pF, RL = 500Ω 3.3 ± 0.3 CL = 15 pF, RL = 2kΩ Figure Number 2.9 1.8 ± 0.15 CL = 15 pF, RL = 500Ω Units MHz CL = 15 pF, RL = 500Ω tPHZ tS TA = −40°C to + 85°C 2.5 ± 0.2 tPZH tPLZ (V) 3.3 ± 0.3 CL = 15 pF, RL = 500Ω tPHL VCC ns Figures 1, 2 Figures 7, 8 ns Figures 1, 2 Figures 7, 8 ns Figures 1, 2 Figures 7, 8 ns Figures 1, 3, 4 Figures 7, 9, 10 ns Figures 1, 3, 4 Figures 7, 9, 10 ns Figure 6 ns Figure 6 ns Figure 5 0.5 2.5 ± 0.2 0.5 1.8 ± 0.15 0.75 1.5 ± 0.1 1.5 ns Note 11: For CL = 50pF, add approximately 300ps to the AC maximum specification. Note 12: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). www.fairchildsemi.com 6 Symbol VOLP VOLV VOHV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Quiet Output Dynamic Valley VOH Conditions CL = 30 pF, VIH = VCC, VIL = 0V CL = 30 pF, VIH = VCC, VIL = 0V CL = 30 pF, VIH = VCC, VIL = 0V VCC TA = +25°C (V) Typical 1.8 0.25 2.5 0.6 3.3 0.8 1.8 −0.25 2.5 −0.6 3.3 −0.8 1.8 1.5 2.5 1.9 3.3 2.2 Units V V V Capacitance Symbol CIN Parameter Input Capacitance Conditions VI = 0V or VCC VCC = 1.8V, 2.5V, or 3.3V CI/O Output Capacitance VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V CPD Power Dissipation Capacitance VI = 0V or VCC, f = 10 MHz VCC = 1.8V, 2.5V or 3.3V 7 TA = +25°C Units 6.0 pF 7.0 pF 20.0 pF www.fairchildsemi.com 74VCX16601 Dynamic Switching Characteristics 74VCX16601 AC Loading and Waveforms (VCC 3.3V ± 0.3V to 1.8V ± 0.15V) FIGURE 1. AC Test Circuit TEST SWITCH tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3V ± 0.3V; VCC x 2 at VCC = 2.5V ± 0.2V; 1.8V ± 0.15V tPZH, tPHZ GND FIGURE 2. Waveform for Inverting and Non-inverting Functions FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic FIGURE 5. Propagation Delay, Pulse Width and trec Waveforms Symbol www.fairchildsemi.com FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic VCC 3.3V ± 0.3V 2.5V ± 0.2V 1.8V ± 0.15V Vmi 1.5V VCC/2 VCC/2 Vmo 1.5V VCC/2 VCC/2 VX VOL + 0.3V VOL + 0.15V VOL + 0.15V VY VOH − 0.3V VOH − 0.15V VOH − 0.15V 8 74VCX16601 AC Loading and Waveforms (VCC 1.5V ± 0.1V) TEST SWITCH tPLH, tPHL Open tPZL, tPLZ VCC x 2 at VCC = 1.5 ± 0.1V tPZH, tPHZ GND FIGURE 7. AC Test Circuit FIGURE 8. Waveform for Inverting and Non-inverting Functions FIGURE 9. 3-STATE Output High Enable and Disable Times for Low Voltage Logic FIGURE 10. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic VCC Symbol 1.5V ± 0.1V VCC/2 Vmi Vmo VCC/2 VX VOL + 0.1V VY VOH − 0.1V 9 www.fairchildsemi.com 74VCX16601 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A (Preliminary) www.fairchildsemi.com 10 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 11 www.fairchildsemi.com 74VCX16601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued)