COP912C/COP912CH 8-Bit Microcontroller General Description CPU/Instruction Set Features The COP912C/COP912CH are members of the COP8TM 8-bit MicroController family. They are fully static Microcontrollers, fabricated using double-metal silicon gate microCMOS technology. These low cost MicroControllers are complete microcomputers containing all system timing, interrupt logic, ROM, RAM, and I/O necessary to implement dedicated control functions in a variety of applications. Features include an 8-bit memory mapped architecture, MICROWlRETM serial I/O, a 16-bit timer/counter with capture register and a multi-sourced interrupt. Each I/O pin has software selectable options to adapt the device to the specific application. The device operates over voltage ranges from 2.3V to 4.0V (COP912C) and from 4.0V to 5.5V (COP912CH). High throughput is achieved with an efficient, regular instruction set operating at a minimum of 2 ms per instruction rate. Y Key Features Y Y Y Y Y Y Y Y Y Y Y Fully Static CMOS Y Y Y Y Emulation and OTP devices Real time emulation and full program debug offered by MetaLink Development System Applications Y Y Y Y Memory mapped I/O Software selectable I/O options (TRI-STATEÉ Output, Push-Pull Output, Weak Pull-Up Input, High Impedance Input) Schmitt trigger inputs on Port G MICROWIRE/PLUSTM Serial I/O Packages: 20 DIP/SO with 16 I/O pins Low current drain (typically k 1 mA) Single supply operation: 2.3V to 4.0V or 4.0V to 5.5V Temperature range: 0§ C to a 70§ C Development Support Y Lowest cost COP8 microcontroller 16-bit multi-function timer supporting Ð PWM mode Ð External event counter mode Ð Input capture mode 768 bytes of ROM 64 bytes of RAM I/O Features Y Y Instruction cycle time of 2 ms for COP912CH and 2.5 ms for COP912C Three multi-sourced interrupts servicing Ð External Interrupt with selectable edge Ð Timer interrupt Ð Software interrupt Versatile and easy to use instruction set 8-bit Stack Pointer (SP)Ðstack in RAM Two 8-bit Register Indirect Memory Pointers (B, X) Y Y Y Y Y Electronic keys and switches Remote Control Timers Alarms Small industrial control units Low cost slave controllers Temperature meters Small domestic appliances Toys and games Block Diagram TL/DD/12060 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. COP8TM , MICROWIRE/PLUSTM , WATCHDOGTM and MICROWIRETM are trademarks of National Semiconductor Corporation. PCÉ is a registered trademark of International Business Machines Corp. iceMasterTM is a trademark of MetaLink Corporation. C1996 National Semiconductor Corporation TL/DD12060 RRD-B30M96/Printed in U. S. A. http://www.national.com COP912C/COP912CH 8-Bit Microcontroller August 1996 Absolute Maximum Ratings Total Current into VCC Pin (Source) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) Voltage at Any Pin 80 mA Total Current out of GND Pin (Sink) Storage Temperature Range 6.0V 80 mA b 65§ C to a 150§ C Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. b 0.3V to VCC a 0.3V DC Electrical Characteristics COP912C/COP912CH; 0§ C s TA s a 70§ C unless other specified Parameter Conditions Operating Voltage 912C 912CH Power Supply Ripple 1 (Note 1) Peak to Peak Supply Current (Note 2) CKI e 4 MHz CKI e 4 MHz HALT Current VCC e 5.5V, tc e 2.5 ms VCC e 4.0V, tc e 2.5 ms VCC e 5.5V, CKI e 0 MHz Min 2.3 4.0 INPUT LEVELS (VIH, VIL) Reset, CKI: Logic High Logic Low All Other Inputs Logic High Logic Low Units 4.0 5.5 0.1 VCC V V V 6.0 2.5 8 mA mA mA 0.1 VCC V V 0.2 VCC V V k1 0.7 VCC VCC e 5.5V Input Pullup Current VCC e 5.5V b2 G-Port Hysteresis Sink (Push-Pull Mode) Max 0.9 VCC Hi-Z Input Leakage/TRI-STATE Leakage Output Current Levels Source (Push-Pull Mode) Typ 0.05 VCC VCC VCC VCC VCC e e e e 4.0V, VOH e 3.8V 2.3V, VOH e 1.8V 4.0V, VOL e 1.0V 2.3V, VOL e 0.4V a2 mA 250 mA 0.35 VCC V 0.4 0.2 4.0 0.7 mA mA mA mA Allowable Sink/Source Current Per Pin Input Capacitance (Note 3) Load Capacitance on D2 (Note 3) Note 1: Rate of voltage change must be less then 0.5 V/ms. Note 2: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open. Note 3: Characterized, not tested. TL/DD/12060 – 2 FIGURE 1. MICROWIRE/PLUS Timing http://www.national.com 2 3 mA 7 pF 1000 pF Typical Performance Characteristics HaltÐIDD DynamicÐIDD (Crystal Clock Option) TL/DD/12060 – 16 TL/DD/12060 – 17 Port L/G Weak Pull-Up Source Current Port L/G Push-Pull Source Current TL/DD/12060 – 19 TL/DD/12060 – 18 Port L/G Push-Pull Sink Current Port D Source Current TL/DD/12060 – 20 TL/DD/12060 – 21 Port D Sink Current TL/DD/12060 – 22 3 http://www.national.com AC Electrical Characteristics COP912C/COP912CH; 0§ C s TA s a 70§ C unless otherwise specified Parameter INSTRUCTION CYCLE TIME (tc) Crystal/Resonator R/C Oscillator Inputs tSetup tHold Output Propagation Delay tPD1, tPD0 SO, SK All Others Conditions Min 4.0V s VCC s 5.5V 2.3V s VCC k 4.0V 4.0V s VCC s 5.5V 2.3V s VCC k 4.0V 2 2.5 3 7.5 4.0V s VCC s 5.5V 2.3V s VCC k 4.0V 4.0V s VCC s 5.5V 2.3V s VCC k 4.0V 200 500 60 150 Typ Max Units DC DC DC DC ms ms ms ms ns ns ns ns RL e 2.2 kX, CL e 100 pF 4.0V s VCC s 5.5V 2.3V s VCC k 4.0V 4.0V s VCC s 5.5V 2.3V s VCC k 4.0V Input Pulse Width Interrupt Input High Time Interrupt Input Low Time Timer Input High Time Timer Input Low Time 0.7 1.75 1 5 ms ms ms ms 220 ns ns ns 1 tc 1 tc 1 tc 1 tc MICROWIRE Setup Time (tmWS) MICROWIRE Hold Time (tmWH) MICROWIRE Output Propagation Delay (tmPD) 20 56 Reset Pulse Width 1.0 ms COP912C/COP912CH Pinout Top View 20 SO Wide 20 DIP TL/DD/12060–3 TL/DD/12060 – 4 Order Number COP912C-XXX/N, COP912CH-XXX/N Order Number COP912C-XXX/WM, COP912CH-XXX/WM FIGURE 2. COP912C/COP912CH Pinout http://www.national.com 4 Pin Description The selection of alternate Port G functions are done through registers PSW [00EF] to enable external interrupt and CNTRL [00EE] to select TIO and MICROWIRE operations. VCC and GND are the power supply pins. CKI is the clock input. This can come from an external source, a R/C generated oscillator or a crystal (in conjunction with CKO). See Oscillator description. RESET is the master reset input. See Reset description. Functional Description The internal architecture is shown in the block diagram. Data paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device. PORT L is an 8-bit I/O port. There are two registers associated to configure the L port: a data register and a configuration register Therefore, each L I/O bit can be individually configured under software control as shown below: Port L Config. Port L Data PORT L Setup 0 0 Hi-Z Input (TRI-STATE) 0 1 Input with Weak Pull-Up 1 0 Push-Pull Zero Output 1 1 Push-Pull One Output ALU AND CPU REGISTERS The ALU can do an 8-bit addition, subtraction, logical or shift operations in one cycle time. There are five CPU registers: A is the 8-bit Accumulator register PC is the 15-bit Program Counter register PU is the upper 7 bits of the program counter (PC) PL is the lower 8 bits of the program counter (PC) B is the 8-bit address register and can be auto incremented or decremented X is the 8-bit alternate address register and can be auto incremented or decremented. SP is the 8-bit stack pointer which points to the subroutine stack (in RAM). B, X and SP registers are mapped into the on chip RAM. The B and X registers are used to address the on chip RAM. The SP register is used to address the stack in RAM during subroutine calls and returns. The SP must be preset by software upon initialization. Three data memory address locations are allocated for this port, one each for data register [00D0], configuration register [00D1] and the input pins [00D2]. PORT G is an 8-bit port with 6 I/O pins (G0–G5) and 2 input pins (G6, G7). All eight G-pins have Schmitt Triggers on the inputs. There are two registers associated to configure the G port: a data register and a configuration register. Therefore each G port bit can be individually configured under software control as shown below: Port G Config. Port G Data PORT G Setup 0 0 Hi-Z Input (TRI-STATE) 0 1 Input with Weak Pull-Up 1 0 Push-Pull Zero Output 1 1 Push-Pull One Output MEMORY The memory is separated into two memory spaces: program and data. PROGRAM MEMORY Program memory consists of 768 x 8 ROM. These bytes of ROM may be instructions or constant data. The memory is addressed by the 15-bit program counter (PC). There are no ‘‘pages’’ of ROM, the PC counts all 15 bits. ROM can be indirectly read by the LAlD instruction for table lookup. Three data memory address locations are allocated for this port, one for data register [00D4], one for configuration register [00D5] and one for the input pins [00D6]. Since G6 and G7 are Hi-Z input only pins, any attempt by the user to configure them as outputs by writing a one to the configuration register will be disregarded. Reading the G6 and G7 configuration bits will return zeroes. Note that the chip will be placed in the Halt mode by writing a ‘‘1’’ to the G7 data bit. Six pins of Port G have alternate features: G0 INTR (an external interrupt) G3 TIO (timer/counter input/output) G4 SO (MICROWIRE serial data output) G5 SK (MICROWIRE clock I/O) G6 SI (MICROWIRE serial data input) G7 CKO crystal oscillator output (selected by mask option) or HALT restart input/general purpose input (if clock option is R/C- or external clock) Pins G1 and G2 currently do not have any alternate functions. DATA MEMORY The data memory address space includes on chip RAM, I/O and registers. Data memory is addressed directly by the instruction or indirectly through B, X and SP registers. The device has 64 bytes of RAM. Sixteen bytes of RAM are mapped as ‘‘registers’’, these can be loaded immediately, decremented and tested. Three specific registers: X, B, and SP are mapped into this space, the other registers are available for general usage. Any bit of data memory can be directly set, reset or tested. I/O and registers (except A and PC) are memory mapped; therefore, I/O bits and register bits can be directly and individually set, reset and tested. RESET The RESET input pin when pulled low initializes the microcontroller. Upon initialization, the ports L and G are placed in the TRl-STATE mode. The PC, PSW and CNTRL registers are cleared. The data and configuration registers for ports L and G are cleared. The external RC network shown in Figure 3 should be used to ensure that the RESET pin is held low until the power supply to the chip stabilizes. 5 http://www.national.com Functional Description (Continued) TABLE I. Crystal Oscillator Configuration R1 (kX) R2 (mX) C1 (pF) C2 (pF) CKI Freq. (MHz) 0 1 30 30 – 36 5 0 1 30 30 – 36 4 5.6 1 200 100 – 150 0.455 TL/DD/12060–5 TABLE II. RC Oscillator Configuration (Part-to-Part Variation, TA e 25§ C) RC l 5 x POWER SUPPLY RISE TIME FIGURE 3. Recommended Reset Circuit OSCILLATOR CIRCUITS The device can be driven by a clock input which can be between DC and 5 MHz. CRYSTAL OSCILLATOR By selecting CKO as a clock output, CKI and CKO can be connected to create a crystal controlled oscillator. Table I shows the component values required for various standard crystal values. R (kX) C (pF) CKI Freq. (MHz) Intr. Cycle (ms) 3.3 82 2.2 to 2.7 3.7 to 4.6 5.6 100 1.1 to 1.3 7.4 to 9 6.8 100 0.9 to 1.1 8.8 to 10.8 Note: 3k s R s 200 kX, 50 pF s C s 200 pF. R/C OSCILLATOR By selecting CKI as a single pin oscillator, CKI can make an R/C oscillator. CKO is available as a general purpose input and/or HALT control. Table II shows variation in the oscillator frequencies as functions of the component (R and C) value. HALT MODE The device is a fully static device. The device enters the HALT mode by writing a one to the G7 bit of the G data register. Once in the HALT mode, the internal circuitry does not receive any clock signal and is therefore frozen in the exact state it was in when halted. In this mode the chip will only draw leakage current. The device supports two different ways of exiting the HALT mode. The first method is with a low to high transition on the CKO (G7) pin. This method precludes the use of the crystal clock configuration (since CKO is a dedicated output), and so may be used either with an RC clock configuration (or an external clock configuration). The second method of exiting the HALT mode is to pull the RESET low. Note: To allow clock resynchronization, it is necessary to program two NOP’s immediately after the device comes out of the HALT mode. The user must program two NOP’s following the ‘‘enter HALT mode’’ (set G7 data bit) instruction. TL/DD/12060–6 FIGURE 4. Clock Oscillator Configurations http://www.national.com 6 Functional Description (Continued) The following table details the different clock rates that may be selected. MICROWIRE/PLUS MICROWIRE/PLUS is a serial synchronous communications interface. The MICROWIRE/PLUS capability enables the device to interface with any of National Semiconductor’s MICROWIRE peripherals (i.e., A/D converters, display drivers, EEPROMS etc.) and with other microcontrollers which support the MICROWIRE interface. It consists of an 8-bit serial shift register (SIO) with serial data input (SI), serial data output (SO) and serial shift clock (SK). Figure 5 shows a block diagram of the MICROWIRE logic. The shift clock can be derived from either the internal source or from an external source. Operating the MICROWIRE arrangement with the internal clock source is called the Master mode of operation. Similarly, operating the MICROWIRE arrangement with an external shift clock is called the Slave mode of operation. The CNTRL register is used to configure and control the MICROWIRE mode. To use the MICROWIRE, the MSEL bit in the CNTRL register is set to one. The SK clock rate is selected by the two bits, SL0 and SL1, in the CNTRL register. SK Divide Clock Rates SL1 SL0 SK 0 0 2 x tc 0 1 4 x tc 1 x 8 x tc Where tc is the instruction cycle clock. MICROWIRE/PLUS OPERATION Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS to start shifting the data. It gets reset when eight data bits have been shifted. The user may reset the BUSY bit by software to allow less than 8 bits to shift. The device may enter the MICROWIRE/PLUS mode either as a Master or as a Slave. Figure 5 shows how two microcontrollers and several peripherals may be interconnected using the MICROWIRE/PLUS arrangement. TL/DD/12060 – 7 FIGURE 5. MICROWIRE/PLUS Application 7 http://www.national.com The user must set the BUSY flag immediately upon entering the slave mode. This will ensure that all data bits sent by the master will be shifted in properly. After eight clock pulses, the BUSY flag will be cleared and the sequence may be repeated. Functional Description (Continued) WARNING: The SIO register should only be loaded when the SK clock is low. Loading the SIO register while the SK clock is high will result in undefined data in the SIO register. Setting the BUSY flag when the input SK clock is high in the MICROWIRE/PLUS slave mode may cause the current SK clock for the SIO shift register to be narrow. For safety, the BUSY flag should only be set when the input SK clock is low. Table III summarizes the settings required to enter the Master/Slave modes of operations. The table assumes that the control flag MSEL is set. Note: In the Slave mode the SIO register does not stop shifting even after the busy flag goes low. Since SK is an external output, the SIO register stops shifting only when SK is turned off by the master. Note: Setting the BUSY flag when the input SK clock is high in the MICROWIRE/PLUS slave mode may cause the current SK clock for the SIO register to be narrow. When the BUSY flag is set, the MICROWIRE logic becomes active with the internal SIO shift clock enabled. If SK is high in slave mode, this will cause the internal shift clock to go from low in standby mode to high in active mode. This generates a rising edge, and causes one bit to be shifted into the SIO register from the SI input. For safety, the BUSY flag should only be set when the input SK clock is low. TABLE III. MICROWIRE/PLUS G Port Configuration G4 G5 (SO) (SK) Config. Config. Bit Bit 1 1 0 1 1 0 0 0 G4 Pin G5 Pin G6 Pin SO Int. SK SI MICROWIRE Master TRI-STATE Int. SK SI MICROWIRE Master Note: The SIO register must be loaded only when the SK shift clock is low. Loading the SIO register while the SK clock is high will result in undefined data in the SIO register. Operation Timer/Counter SO The device has an on board 16-bit timer/counter (organized as two 8-bit registers) with an associated 16-bit autoreload/ capture register (also organized as two 8-bit registers). Both are read/write registers. The timer has three modes of operation: Ext. SK SI MICROWIRE Slave PWM (PULSE WIDTH MODULATION) MODE The timer counts down at the instruction cycle rate (2 ms max). When the timer count underflows, the value in the autoreload register is copied into the timer. Consequently, the timer is programmable to divide by any value from 1 to 65536. Bit 5 of the timer CNTRL register selects the timer underflow to toggle the G3 output. This allows the user to generate a square wave output or a pulse-width-modulated output. The timer underflow can also be enabled to interrupt the processor. The timer PWM mode is shown in Figure 7 . TRI-STATE Ext. SK SI MICROWIRE Slave MICROWIRE/PLUS MASTER MODE OPERATION In MICROWIRE/PLUS Master mode operation, the SK shift clock is generated internally. The MSEL bit in the CNTRL register must be set to allow the SK and SO functions onto the G5 and G4 pins. The G5 and G4 pins must also be selected as outputs by setting the appropriate bits in the Port G configuration register. The MICROWIRE Master mode always initiates all data exchanges. The MSEL bit in the CNTRL register is set to enable MICROWIRE/PLUS. G4 and G5 are selected as output. TL/DD/12060 – 10 FIGURE 7. Timer in PWM Mode TL/DD/12060–8 FIGURE 6. MICROWIRE/PLUS Block Diagram MICROWIRE/PLUS SLAVE MODE In MICROWIRE/PLUS Slave mode operation, the SK shift clock is generated by an external source. Setting the MSEL bit in the CNTRL register enables the SO and SK functions onto the G port. The SK pin must be selected as an input and the SO pin as an output by resetting and setting their respective bits in the G port configuration register. http://www.national.com 8 Functional Description (Continued) grammed to generate an interrupt. The duration of an input signal can be computed by capturing the time of the leading edge, saving this captured value, changing the capture edge, capturing the time of the trailing edge, and then subtracting this trailing edge time from the earlier leading edge time. The Input Capture mode is shown in Figure 9 . EXTERNAL EVENT COUNTER MODE In this mode, the timer becomes a 16-bit external event counter, clocked from an input signal applied to the G3 input. The maximum frequency for this G3 input clock is 250 kHz (half of the 0.5 MHz instruction cycle clock). When the external event counter underflows, the value in the autoreload register is copied into the timer. This timer underflow may also be used to generate an interrupt. Bit 5 of the CNTRL register is used to select whether the external event counter clocks on positive or negative edges from the G3 input. Consequently, half cycles of an external input signal could be counted. The External Event counter mode is shown in Figure 8 . TL/DD/12060 – 12 FIGURE 9. Timer in Input Capture Mode Table IV below details the TIMER modes of operation and their associated interrupts. Bit 4 of CNTRL is used to start and stop the timer/counter. Bits 5, 6 and 7 of the CNTRL register select the timer modes. The ENTI (Enable Timer Interrupt) and TPND (Timer Interrupt Pending) bits in the PSW register are used to control the timer interrupts. Care must be taken when reading from and writing to the timer and its associated autoreload/capture register. The timer and autoreload/capture register are both 16-bit, but they are read from and written to one byte at a time. It is recommended that the timer be stopped before writing a new value into it. The timer may be read ‘‘on the fly’’ without stopping it if suitable precautions are taken. One method of reading the timer ‘‘on the fly’’ is to read the upper byte of the timer first, and then read the lower byte. If the most significant bit of the lower byte is then tested and found to be high, then the upper byte of the timer should be read again and this new value used. TL/DD/12060 – 11 FIGURE 8. Timer in External Event Mode INPUT CAPTURE MODE In this mode, the timer counts down at the instruction clock rate. When an external edge occurs on pin G3, the value in the timer is copied into the capture register. Consequently, the time of an external edge on the G3 pin is ‘‘captured’’. Bit 5 of the CNTRL register is used to select the polarity of the external edge. This external edge capture can also be pro- TABLE IV. Timer Modes and Control Bits CNTRL Bits Timer Interrupt Operation Mode Timer Counts On 7 6 5 0 0 0 External Event Counter with Autoreload Register Timer Underflow TIO Positive Edge 0 0 1 External Event Counter with Autoreload Register Timer Underflow TIO Negative Edge 0 1 0 Not Allowed Not Allowed Not Allowed 0 1 1 Not Allowed Not Allowed Not Allowed 1 0 0 Timer with Autoreload Register Timer Underflow tc 1 0 1 Timer with Autoreload Regiter and Toggle TIO Out Timer Underflow tc 1 1 0 Timer with Capture Register TIO Positive Edge tc 1 1 1 Timer with Capture Register TIO Negative Edge tc 9 http://www.national.com Functional Description (Continued) and falling edges by toggling the state of IEDG bit after each interrupt. TIMER APPLICATION EXAMPLE The timer has an autoreload register that allows any frequency to be programmed in the timer PWM mode. The timer underflow can be programmed to toggle output bit G3, and may also be programmed to generate a timer interrupt. Consequently, a fully programmable PWM output may be easily generated. The timer counts down and when it underflows, the value from the autoreload register is copied into the timer. The CNTRL register is programmed to both toggle the G3 output and generate a timer interrupt when the timer underflows. Following each timer interrupt, the user’s program alternately loads the values of the ‘‘on’’ time and the ‘‘off’’ time into the timer autoreload register. Consequently, a pulse-widthmodulated (PWM) output waveform is generated to a resolution of one instruction cycle time. This PWM application example is shown in Figure 10 . IPND and TPND bits signal which interrupt is pending. After interrupt is acknowledged, the user can check these two bits to determine which interrupt is pending. The user can prioritize the interrupt and clear the pending bit that corresponds to the interrupt being serviced. The user can also enable GIE at this point for nesting interrupts. Two things have to be kept in mind when using the software interrupt. The first is that executing a simple RET instruction will take the program control back to the software interrupt instruction itself. In other words, the program will be stuck in an infinite loop. To avoid the infinite loop, the software interrupt service routine should end with a RETSK instruction or with a JMP instruction. The second thing to keep in mind is that unlike the other interrupt sources, the software interrupt does not reset the GIE bit. This means that the device can be interrupted by other interrupt sources while servicing the software interrupt. Interrupts push the PC to the stack, reset the GIE bit to disable further interrupts and branch to address 00FF. The RETI instruction will pop the stack to PC and set the GIE bit to enable further interrupts. The user should use the RETI or the RET instruction when returning from a hardware (maskable) interrupt subroutine. The user should use the RETSK instruction when returning from a software interrupt subroutine to avoid an infinite loop situation. The software interrupt is a special kind of non-maskable interrupt which occurs when the INTR instruction (opcode 00 used to acknowledge interrupts) is fetched from ROM and placed inside the instruction register. This may happen when the PC is pointing beyond the available ROM address space or when the stack is over-popped. When the software interrupt occurs, the user can re-initialize the stack pointer and do a recovery procedure (similar to reset, but not necessarily containing all of the same initialization procedures) before restarting. Hardware and Software interrupts are treated differently. The software interrupt is not gated by the GIE bit. However, it has the lowest arbitration ranking. Also the fact that all interrupts vector to the same address 00FF Hex means that a software interrupt happening at the same time as a hardware interrupt will be missed. TL/DD/12060–13 FIGURE 10. Timer Based PWM Application Interrupts There are three interrupt sources: 1. A maskable interrupt on external G0 input positive or negative edge sensitive under software control 2. A maskable interrupt on timer underflow or timer capture 3. A non-maskable software/error interrupt on opcode zero. The GIE (global interrupt enable) bit enables the interrupt function. This is used in conjunction with ENI and ENTI to select one or both of the interrupt sources. This bit is reset when interrupt is acknowledged. ENI and ENTI bits select external and timer interrupt respectively. Thus the user can select either or both sources to interrupt the microcontroller when GIE is enabled. IEDG selects the external interrupt edge (1 e rising edge, 0 e falling edge). The user can get an interrupt on both rising Note: There is always the possibility of an interrupt occurring during an instruction which is attempting to reset the GIE bit or any other interrupt enable bit. If this occurs when a single cycle instruction is being used to reset the interrupt enable bit, the interrupt enable bit will be reset but an interrupt may still occur. This is because interrupt processing is started at the same time as the interrupt bit is being reset. To avoid this scenario, the user should always use a two, three, or four cycle instruction to reset interrupt enable bits. TL/DD/12060 – 14 FIGURE 11. Interrupt Block Diagram http://www.national.com 10 Interrupts (Continued) Control Registers DETECTION OF ILLEGAL CONDITIONS Reading of undefined ROM gets zeroes. The opcode for software interrupt is zero. If the program fetches instructions from undefined ROM, this will force a software interrupt, thus signalling that an illegal condition has occurred. CNTRL REGISTER (ADDRESS X’00EE) Note: A software interrupt is acted upon only when a timer or external interrupt is not pending as hardware interrupts have priority over software interrupt. In addition, the Global Interrupt bit is not set when a software interrupt is being serviced thereby opening the door for the hardware interrupts to occur. The subroutine stack grows down for each call and grows up for each return. If the stack pointer is initialized to 2F Hex, then if there are more returns than calls, the stack pointer will point to addresses 30 and 31 (which are undefined RAM). Undefined RAM is read as all 1’s, thus, the program will return to address FFFF. This is a undefined ROM location and the instruction fetched will generate a software interrupt signalling an illegal condition. The device can detect the following illegal conditions: IEDG MSEL The Timer and MICROWIRE control register contains the following bits: SL1 and SL0 Select the MICROWIRE clock divide-by (00 e 2, 01 e 4, 1x e 8) External interrupt edge polarity select Selects G5 and G4 as MICROWIRE signals SK and SO respectively Used to start and stop the timer/counter (1 e run, 0 e stop) Timer Mode Control Bit Timer Mode Control Bit Timer Mode Control Bit TRUN TC1 TC2 TC3 7 1. Executing from undefined ROM 2. Over ‘‘POP’’ing the stack by having more returns than calls. 0 TC1 Illegal conditions may occur from coding errors, ‘‘brown out’’ voltage drops, static, supply noise, etc. When the software interrupt occurs, the user can re-initialize the stack pointer and do a recovery procedure before restarting (this recovery program is probably similar to RESET but might not clear the RAM). Examination of the stack can help in identifying the source of the error. For example, upon a software interrupt, if the SP e 30, 31 it implies that the stack was over ‘‘POP’’ed (with the SP e 2F hex initially). If the SP contains a legal value (less than or equal to the initialized SP value), then the value in the PC gives a clue as to where in the user program an attempt to access an illegal (an address over 300 Hex) was made. The opcode returned in this case is 00 which is a software interrupt. The detection of illegal conditions is illustrated with an example: TC2 TC3 TRUN MSEL IEDG SL1 SL0 PSW REGISTER (ADDRESS X’00EF) The PSW register contains the following select bits: GIE Global interrupt enable (enables interrupts) ENI External interrupt enable BUSY MICROWIRE busy shifting flag IPND External interrupt pending ENTI Timer interrupt enable TPND Timer interrupt pending (timer underflow or capture edge) C Carry Flip/flop HC Half carry Flip/flop 7 0 HC 0043 CLRA 0044 RC 0045 JMP 04FF 0046 NOP When the device is executing this program, it seemingly ‘‘locks-up’’ having executed a software interrupt. To debug this condition, the user takes a look at the SP and the contents of the stack. The SP has a legal value and the contents of the stack are 04FF. The perceptive user immediately realizes that an illegal ROM location (04FF) was accessed and the opcode returned (00) was a software interrupt. Another way to decode this is to run a trace and follow the sequence of steps that ended in a software interrupt. The damaging jump statement is changed. C TPND ENTI IPND BUSY ENI GIE The Half-Carry bit is also effected by all the instructions that effect the Carry flag. The flag values depend upon the instruction. For example, after executing the ADC instruction the values of the Carry and the Half-Carry flag depend upon the operands involved. However, instructions like SET C and RESET C will set and clear both the carry flags. Table V lists out the instructions that effect the HC and the C flags. TABLE V. Instructions Effecting HC and C Flags Instr. HC Flag C Flag ADC Depends on Operands Depends on Operands SUBC Depends on Operands Depends on Operands SETC Set Set RESET C Set Set RRC Depends on Operands Depends on Operands MEMORY MAP All RAM, ports and registers (except A and PC) are mapped into data memory address space. 11 http://www.national.com Control Registers (Continued) Addressing Modes The device has ten addressing modes, six for operand addressing and four for transfer of control. TABLE VI. Memory Map Address Contents 00 to 2F On-chip RAM Bytes (48 Bytes) 30 to 7F Unused RAM Address Space (Reads as all ones) 80 to BF Expansion Space for On-Chip EERAM (Reads Undefined Data) C0 to CF Expansion Space for I/O and Registers D0 Port L Data Register D1 Port L Configuration Register D2 Port L Input Pins (read only) D3 Reserved for Port L D4 Port G Data Register D5 Port G Configuration Register D6 Port G Input Pins (read only) D7 Reserved D8 to DB Reserved DC to DF Reserved E0 to EF On-Chip Functions and Registers E0 to E7 Reserved for Future Parts E8 Reserved E9 MICROWIRE Shift Register EA Timer Lower Byte EB Timer Upper Byte EC Timer Autoreload Register Lower Byte ED Timer Auto reload Register Upper Byte EE CNTRL Control Register EF PSW Register F0 to FF On-Chip RAM Mapped as Registers (16 Bytes) FC X Register FD SP Register FE B Register OPERAND ADDRESSING MODES Register Indirect This is the ‘‘normal’’ addressing mode for the chip. The operand is the data memory addressed by the B or X pointer. Register Indirect With Auto Post Increment Or Decrement This addressing mode is used with the LD and X instructions. The operand is the data memory addressed by the B or X pointer. This is a register indirect mode that automatically post increments or post decrements the B or X pointer after executing the instruction. Direct The instruction contains an 8-bit address field that directly points to the data memory for the operand. Immediate The instruction contains an 8-bit immediate field as the operand. Short Immediate This addressing mode issued with the LD B,Ý instruction, where the immediate Ý is less than 16. The instruction contains a 4-bit immediate field as the operand. Indirect This addressing mode is used with the LAID instruction. The contents of the accumulator are used as a partial address (lower 8 bits of PC) for accessing a data operand from the program memory. TRANSFER OF CONTROL ADDRESSING MODES Relative This mode is used for the JP instruction with the instruction field being added to the program counter to produce the next instruction address. JP has a range from b31 to a 32 to allow a one byte relative jump (JP a 1 is implemented by a NOP instruction). There are no ‘‘blocks’’ or ‘‘pages’’ when using JP since all 15 bits of the PC are used. Absolute This mode is used with the JMP and JSR instructions with the instruction field of 12 bits replacing the lower 12 bits of the program counter (PC). This allows jumping to any location in the current 4k program memory segment. Absolute Long This mode is used with the JMPL and JSRL instructions with the instruction field of 15 bits replacing the entire 15 bits of the program counter (PC). This allows jumping to any location in the entire 32k program memory space. Indirect This mode is used with the JID instruction. The contents of the accumulator are used as a partial address (lower 8 bits of PC) for accessing a location in the program memory. The contents of this program memory location serves as a partial address (lower 8 bits of PC) for the jump to the next instruction. Reading other unused memory locations will return undefined data. http://www.national.com 12 Instruction Set REGISTER AND SYMBOL DEFINITIONS Registers A B X SP S PC PU PL C HC GIE Symbols [B] [X] MD Mem MemI Imm Reg 8-Bit Accumulator Register 8-Bit Address Register 8-Bit Address Register 8-Bit Stack Pointer Register 8-Bit Data Segment Address Register 15-Bit Program Counter Register Upper 7 Bits of PC Lower 8 Bits of PC 1-Bit of PSW Register for Carry 1-Bit of PSW Register for Half Carry 1-Bit of PSW Register for Global Interrupt Enable Bit w Ý 13 Memory Indirectly Addressed by B Register Memory Indirectly Addressed by X Register Direct Addressed Memory Direct Addressed Memory, or B Direct Addressed Memory, B, or Immediate Data 8-Bit Immediate Data Register Memory: Addresses F0 to FF (Includes B, X, and SP) Bit Number (0 to 7) Loaded with Exchanged with http://www.national.com Instruction Set (Continued) TABLE VII. Instruction Set Instr Function Register Operation Reg Ý, Mem Ý, Mem Ý, Mem Add Add with Carry Subtract with Carry Logical AND Logical OR Logical Exclusive-OR IF Equal IF Greater than IF B not Equal Decrement Reg, Skip if Zero Set Bit Reset Bit If Bit A w A a MemI A w A a MemI a C, C w Carry A w A b MemI a C, C w Carry A w A and MemI A w A or MemI A w A xor MemI Compare A and MemI, Do Next if A e MemI Compare A and MemI, Do Next if A l MemI Do Next If Lower 4 Bits of B not e Imm Reg w Reg - 1, Skip if Reg Goes to Zero 1 to Mem.Bit (Bit e 0 to 7 Immediate) 0 to Mem.Bit (Bit e 0 to 7 Immediate) If Mem.Bit is True, Do Next Instruction X LD LD LD A, Mem A, MemI Mem, Imm Reg, Imm Exchange A with Memory Load A with Memory Load Direct Memory Immed. Load Register Memory Immed. A Ý Mem A w MemI Mem w Imm Reg w Imm X X LD LD LD A, [B g ] A, [X g ] A, [B g ] A, [X g ] [B g ], Imm Exchange A with Memory [B] Exchange A with Memory [X] Load A with Memory [B] Load A with Memory [X] Load Memory Immediate A Ý [B] (B w B g 1) A Ý [X] (X w X g 1) A w [B] (B w B g 1) A w [X] (X w X g 1) [B] w Imm (B w B g 1) Clear A Increment A Decrement A Load A Indirect from ROM Decimal Correct A Rotate Right Through Carry Swap Nibbles of A Set C Reset C If C If Not C Aw0 AwA a 1 AwA b 1 A w ROM(PU, A) A w BCD Correction (follows ADC, SUBC) C x A7 x . . . x A0 x C A7 . . . A4 Ý A3 . . . A0 Cw1 Cw0 If C is True, do Next Instruction If C is not True, do Next Instruction Jump Absolute Long Jump Absolute PC w ii (ii e 15 Bits, 0k to 32k) PC11 . . . PC0 w i (i e 12 Bits) PC15 . . . PC12 Remain Unchanged PC w PC a r (r is b31 to a 32, not 1) [SP] w PL, [SPb1] w PU, SPb2, PC w ii [SP] w PL, [SPb1] w PU, SPb2, PC11..PC0 w ii PL w ROM(PU, A) SP a 2, PL w [SP], PU w [SPb1] SP a 2, PL w [SP], PU w [SPb1], Skip next Instr. SP a 2, PL w [SP], PU w [SPb1], GIE w 1 [SP] w PL, [SPb1] w PU, SPb2, PC w 0FF PC w PC a 1 ADD ADC SUBC AND OR XOR IFEQ IFGT IFBNE DRSZ SBIT RBIT IFBIT A, MemI A, MemI A, MemI A, MemI A, MemI A, MemI A, MemI A, MemI CLRA INC DEC LAID DCOR RRC SWAP SC RC IFC IFNC Ý A A A A A JMPL JMP JP JSRL JSR JID RET RETSK Addr. Addr. Disp. Addr. Addr. RETI INTR NOP http://www.national.com Jump Relative Short Jump Subroutine Long Jump Subroutine Jump Indirect Return from Subroutine Return and Skip Return from Interrupt Generate an Interrupt No Operation 14 Instruction Set (Continued) Instructions Using A and C (Bytes/Cycles) # Most instructions are single byte (with immediate addressing mode instructions requiring two bytes). # Most single byte instructions take one cycle time to execute. # Skipped instructions require x number of cycles to be skipped, where x equals the number of bytes in the skipped instruction opcode. The following tables show the number of bytes and cycles for each instruction in the format byte/cycle. Arithmetic and Logic Instructions (Bytes/Cycles) Instr [B] Direct ADD ADC SUBC AND OR XOR IFEQ IFNE IFGT IFBNE DRSZ 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 SBIT RBIT IFBIT 1/1 1/1 1/1 3/4 3/4 3/4 Immediate 2/2 2/2 2/2 2/2 2/2 2/2 2/2 2/2 2/2 Instr Bytes/Cycles CLRA INCA DECA LAID DCOR RRCA SWAPA SC RC IFC IFNC 1/1 1/1 1/1 1/3 1/1 1/1 1/1 1/1 1/1 1/1 1/1 Transfer of Control Instructions (Bytes/Cycles) 1/3 Instr Bytes/Cycles JMPL JMP JP JSRL JSR JID RET RETSK RETI INTR NOP 3/4 2/3 1/3 3/5 2/5 1/3 1/5 1/5 1/5 1/7 1/1 Memory Transfer Instructions (Bytes/Cycles) Instr Register Indirect [B] X A,a LD A,* LD B,Imm LD B,Imm LD Mem,Imm LD Reg,Imm 1/1 1/1 2/2 Direct Immed. [X] Register Indirect Auto Incr and Decr [B a , Bb] 2/3 2/3 1/3 1/3 2/2 1/1b 2/3c 3/3 2/3 1/2 1/2 [X a , Xb] 1/3 1/3 2/2 a. Memory location addressed by B or X directly b. IF B k 16 c. IF B l 15 15 http://www.national.com http://www.national.com 16 JP-19 JP-18 JP-17 JP-16 JP-3 JP-2 JP-1 JP-0 JP-24 JP-8 JP-20 JP-25 JP-9 JP-4 JP-26 JP-10 JP-21 JP-27 JP-11 JP-5 JP-28 JP-12 JP-22 JP-29 JP-13 JP-6 JP-30 JP-14 JP-23 JP-31 JP-15 JP-7 E F LD 0FF,Ýi LD 0FE,Ýi LD 0D,Ýi LD 0FC,Ýi LD 0FB,Ýi LD 0FA,Ýi LD 0F9,Ýi LD 0F8,Ýi LD 0F7,Ýi LD 0F6,Ýi LD 0F5,Ýi LD 0F4,Ýi LD 0F3Ýi LD 0F2,Ýi DRSZ 0FF DRSZ 0FE DRSZ 0D DRSZ 0FC DRSZ 0FB DRSZ 0FA DRSZ 0F9 DRSZ 0F8 DRSZ 0F7 DRSZ 0F6 DRSZ 0F5 DRSZ 0F4 DRSZ 0F3 DRSZ 0F2 DRSZ,0F1 DRSZ 0F0 LD 0F0,Ýi LD 0F1,Ý1 C D * LD A, (X) DIR LD Md, Ýi LDA, X(b) LDA, X( a ) * NOP * XA, (X) * * XA, (Xb) XA (X a ) * RRCA B * LD A, (B) JSRL JMPL LD A, (Bb) LD A, (B a ) * * * XA, (B) JID LAID XA, (Bb) XA, (X a ) SC RC A * LD B, Ýi LD A, Md X A,Md LD (Bb), Ýi LD (B a ), Ýi * LD A, Ýi OR A, Ýi XOR A, Ýi AND A, Ýi ADD A, Ýi IFGT A, Ýi IFEQA, Ýi SUBCA, Ýi ADCA, 3I 9 RETI RET RETSK * DECA INCA IFNC IFC OR A, (B) XOR A, (B) AND A, (B) ADD A, (B) IFGT A, (B) IFEQ, Ýi SUBC A,(B) ADCA, (B) 8 SBIT 7, (B) SBIT 6, (B) SBIT 5, (B) SBIT 4, (B) SBIT 3, (B) SBIT 2, (B) SBIT 1,(B) SBIT 0,(B) IFBIT 7, (B) IFBIT 6, (B) IFBIT 5, (B) IFBIT 4, (B) IFBIT 3, (B) IFBIT A,(B) IFBIT 1,(B) IFBIT 0, (B) 7 RBIT 7, (B) RBIT 6, (B) RBIT 5, (B) RBIT 4, (B) RBIT 3, (B) RBIT 2, (B) RBIT 1(B) RBIT 0, (B) * DCORA SWAPA CLRA * * * * 6 UPPER NIBBLE BITS 7 – 4 LD B, 0 LD B, 1 LD B, 2 LD B, 3 LD B, 4 LD B, 5 LD B, 6 LD B, 7 LD B, 8 LD B, 9 LD B, 0A LD B, 0B LDB, 0C LD B, 0D LD B, 0E LD B, 0F 5 IFBNE 0F IFBNE 0E IFBNE 0D IFBNE 0C IFBNE 0B IFBNE 0A IFBNE 9 IFBNE 8 IFBNE 7 IFBNE 6 IFBNE 5 IFBNE 4 IFBNE 3 IFBNE 2 IFBNE 1 IFBNE 0 4 JSR 0F00 –0FFF JSR 0E00 –0EFF JSR 0D00 –0DFF JSR 0C00 –0CFF JSR 0B00 –0BFF JSR 0A00 –0AFF JSR 0900 –09FF JSR 0800 –08FF JSR 0700 –07FF JSR 0600 –06FF JSR 0500 –05FF JSR 0400 –04FF JSR 0300 –03FF JSR 0200 –02FF JSR 0100-01FF JSR 0000 –00FF 3 JMP 0F00 –0FFF JMP 0E00 –0EFF JMP 0D00 –0DFF JMP 0C00 –0CFF JMP 0B00 –0BFF JMP 0A00 –0AFF JMP 0900 –09FF JMP 0800 –08FF JMP 0700 –07FF JMP 0600 –06FF JMP 0500 –05FF JMP 0400 –04FF JMP 0300 –03FF JMP 0200 –02FF JMP 0100 –01FF JMP 0000 –00FF 2 1 JP a 32 JP a 31 JP a 30 JP a 29 JP a 28 JP a 27 JP a 26 JP a 25 JP a 24 JP a 23 JP a 22 JP a 21 JP a 20 JP a 19 JP a 18 JP a 17 JP a 16 JP a 15 JP a 14 JP a 13 JP a 12 JP a 11 JP a 10 JP a 9 JP a 8 JP a 7 JP a 6 JP a 5 JP a 4 UJP a 3 JP a 2 INTR 0 F E D C B A 9 8 7 6 5 4 3 2 1 0 LOWER NIBBLE BITS 3 – 0 Option List Development Support The mask programmable options are listed out below. The options are programmed at the same time as the ROM pattern to provide the user with hardware flexibility to use a variety of oscillator configuration. SUMMARY # iceMASTERTM : IM-COP8/400ÐFull feature in-circuit emulation for all COP8 products. A full set of COP8 Basic and Feature Family device and package specific probes are available. OPTION 1: CKI INPUT # COP8 Debug Module: Moderate cost in-circuit emulation e 1 Crystal (CKI/10) CKO for crystal configuration e2 NA e 3 R/C and development programming unit. # COP8 Evaluation and Programming Unit: EPUCOP8780Ðlow cost in-circuit simulation and development programming unit. (CKI/10) CKO available as G7 input OPTION 2: BONDING # Assembler: COP8-DEV-IBMA. A DOS installable cross e 1 NA e 2 NA development Assembler, Linker, Librarian and Utility Software Development Tool Kit. e 3 20 pin DIP package e 4 20 pin SO package e 5 NA # C Compiler: COP8C. A DOS installable cross development Software Tool Kit. # OTP/EPROM Programmer Support: Covering needs The following option information is to be sent to National along with the EPROM. from engineering prototype, pilot production to full production environments. Option Data Option 1 ValueÐis: CKI Input Option 2 ValueÐis: COP Bonding 17 http://www.national.com Development Support (Continued) # Watch windows, content updated automatically at each IceMASTER (IM) IN-CIRCUIT EMULATION The iceMASTER IM-COP8/400 is a full feature, PC based, in-circuit emulation tool developed and marketed by MetaLink Corporation to support the whole COP8 family of products. National is a resale vendor for these products. See Figure 12 for configuration. execution break. # Instruction by instruction memory/register changes displayed on source window when in single step operation. # Single base unit and debugger software reconfigurable to support the entire COP8 family; only the probe personality needs to change. Debugger software is processor customized, and reconfigured from a master model file. The iceMASTER IM-COP8/400 with its device specific COP8 Probe provides a rich feature set for developing, testing and maintaining product: # Processor specific symbolic display of registers and bit level assignments, configured from master model file. # Real-time in-circuit emulation; full 2.4V–5.5V operation # Halt/Idle mode notification. # On-Line HELP customized to specific processor using range, full DC-10 MHz clock. Chip options are programmable or jumper selectable. master model file. # Direct connection to application board by package com- # Includes a copy of COP8-DEV-IBMA assembler and link- patible socket or surface assembly. er SDK. # Full 32 kbyte of loadable programming space that overlays (replaces) the on-chip ROM or EPROM. On-chip RAM and I/O blocks are used directly or recreated on the probe as necessary. IM Order Information Base Unit # Full 4k frame synchronous trace memory. Address, in- IM-COP8/400-1 struction, and 8 unspecified, circuit connectable trace lines. Display can be HLL source (e.g., C source), assembly or mixed. iceMASTER Base Unit, 110V Power Supply IM-COP8/400-2 iceMASTER Base Unit, 220V Power Supply # A full 64k hardware configurable break, trace on, trace iceMASTER Probe off control, and pass count increment events. # Tool set integrated interactive symbolic debuggerÐsup- MHW-880C-20DWPC ports both assembler (COFF) and C Compiler (.COD) linked object formats. 20 DIP Adapter for SO Package # Real time performance profiling analysis; selectable MHW-SOIC20 20 SO bucket definition. TL/DD/12060 – 15 FIGURE 12. COP8 iceMASTER Environment http://www.national.com 18 Development Support (Continued) # Debugger software is processor customized, and recon- iceMASTER DEBUG MODULE (DM) The iceMASTER Debug Module is a PC based, combination in-circuit emulation tool and COP8 based OTP/EPROM programming tool developed and marketed by MetaLink Corporation to support the whole COP8 family of products. National is a resale vendor for these products. See Figure 13 for configuration. figured from a master model file. # Processor specific symbolic display of registers and bit level assignments, configured from master model file. # Halt/Idle mode notification. # Programming menu supports full product line of programmable OTP and EPROM COP8 products. Program data is taken directly from the overlay RAM. The iceMASTER Debug Module is a moderate cost development tool. It has the capability of in-circuit emulation for a specific COP8 microcontroller and in addition serves as a programming tool for COP8 OTP and EPROM product families. Summary of features is as follows: # Programming of 44 PLCC and 68 PLCC parts requires external programming adapters. # Includes wallmount power supply. # On-board VPP generator from 5V input or connection to # Real-time in-circuit emulation; full operating voltage external supply supported. Requires VPP level adjustment per the family programming specification (correct level is provided on an on-screen pop-down display). range operation, full DC-10 MHz clock. # All processor I/O pins can be cabled to an application development board with package compatible cable to socket and surface mount assembly. # On-line HELP customized to specific processor using # Full 32 kbyte of loadable programming space that over- # Includes a copy of COP8-DEV-IBMA assembler and link- master model file. lays (replaces) the on-chip ROM or EPROM. On-chip RAM and I/O blocks are used directly or recreated as necessary. er SDK. DM Order Information # 100 frames of synchronous trace memory. The display Debug Module Unit can be HLL source (C source), assembly or mixed. The most recent history prior to a break is available in the trace memory. COP8/DM/880C Cable Adapters # Configured break points; uses INTR instruction which is DM-COP8/20D modestly intrusive. 20 DIP Adapter for SO Package # SoftwareÐonly supported features are selectable. # Tool set integrated interactive symbolic debuggerÐsup- MHW-SOIC20 20 SO ports both assembler (COFF) and C Compiler (.COD) SDK linked object formats. # Instruction by instruction memory/register changes displayed when in single step operation. TL/DD/12060 – 23 FIGURE 13. COP8-DM Environment 19 http://www.national.com Development Support (Continued) COP8 ASSEMBLER/LINKER SOFTWARE DEVELOPMENT TOOL KIT COP8 C COMPILER A C Compiler is developed and marketed by Byte Craft Limited. The COP8C compiler is a fully integrated development tool specifically designed to support the compact embedded configuration of the COP8 family of products. Features are summarized as follows: National Semiconductor offers a relocatable COP8 macro cross assembler, linker, librarian and utility software development tool kit. Features are summarized as follows: # Basic and Feature Family instruction set by ‘‘device’’ type. # # # # # # # # ANSI C with some restrictions and extensions that optimize development for the COP8 embedded application. Nested macro capability. Extensive set of assembler directives. Supported on PC/DOS platform. Generates National standard COFF output files. # BITS data type extension. Register declaration Ýpragma with direct bit level definitions. # C language support for interrupt routines. # Expert system, rule based code generation and optimiza- Integrated Linker and Librarian. Integrated utilities to generate ROM code file outputs. DUMPCOFF utility. This product is integrated as a part of MetaLink tools as a development kit, fully supported by the MetaLink debugger. It may be ordered separately or it is bundled with the MetaLink products at no additional cost. tion. # Performs consistency checks against the architectural definitions of the target COP8 device. # Generates program memory code. # Supports linking of compiled object or COP8 assembled object formats. # Global optimization of linked code. # Symbolic debug load format fully source level supported Order Information Assembler SDK: COP8-DEV-IBMA by the MetaLink debugger. Assembler SDK on installable 3.5× PCÉ/DOS Floppy Disk Drive format. Periodic upgrades and most recent version is available on National’s BBS and Internet. SINGLE CHIP OTP/EMULATOR SUPPORT The COP8 family is supported by single chip OTP emulators. For detailed information refer to the emulator specific datasheet and the emulator selection table below: Approved List Manufacturer North America Europe Asia BP Microsystems (800) 225-2102 (713) 688-4600 Fax: (713) 688-0920 a 49-8152-4183 a 49-8856-932616 a 852-234-16611 a 852-2710-8121 Data I/O (800) 426-1045 (206) 881-6444 Fax: (206) 882-1043 a 44-0734-440011 Call North America HI – LO (510) 623-8860 Call Asia a 886-2-764-0215 Fax: a 886-2-756-6403 ICE Technology (800) 624-8949 (919) 430-7915 a 44-1226-767404 Fax: 0-1226-370-434 MetaLink (800) 638-2423 (602) 926-0797 Fax: (602) 693-0681 a 49-80 9156 96-0 Fax: a 49-80 9123 86 a 852-737-1800 Systems General (408) 263-6667 a 41-1-9450300 a 886-2-917-3005 Fax: a 886-2-911-1283 Needhams (916) 924-8037 Fax: (916) 924-8065 http://www.national.com 20 Development Support (Continued) OTP Emulator Ordering Information Device Number DIAL-A-HELPER via FTP ftp nscmicro.nsc.com Clock Option Package Emulates COP8782CN Programmable 20 N COP912C, COP912CH COP8782CWM Programmable 20 SO COP912C, COP912CH user: password: DIAL-A-HELPER via a WorldWide Web Browser ftp://nscmicro.nsc.com National Semiconductor on the WorldWide Web See us on the WorldWide Web at: http://www.national.com INDUSTRY WIDE OTP/EPROM PROGRAMMING SUPPORT Programming support, in addition to the MetaLink development tools, is provided by a full range of independent approved vendors to meet the needs from the engineering laboratory to full production. CUSTOMER RESPONSE CENTER Complete product information and technical support is available from National’s customer response centers. CANADA/U.S.: Tel: AVAILABLE LITERATURE For more information, please see the COP8 Basic Family User’s Manual, Literature Number 620895, COP8 Feature Family User’s Manual, Literature Number 620897 and National’s Family of 8-bit Microcontrollers COP8 Selection Guide, Literature Number 630009. EUROPE: DIAL-A-HELPER SERVICE Dial-A-Helper is a service provided by the Microcontroller Applications group. The Dial-A-Helper is an Electronic Information System that may be accessed as a Bulletin Board System (BBS) via data modem, as an FTP site on the Internet via standard FTP client application or as an FTP site on the Internet using a standard Internet browser such as Netscape or Mosaic. The Dial-A-Helper system provides access to an automated information storage and retrieval system. The system capabilities include a MESSAGE SECTION (electronic mail, when accessed as a BBS) for communications to and from the Microcontroller Applications Group and a FILE SECTION which consists of several file areas where valuable application software and utilities could be found. Operation: (800) 272-9959 email: support @ tevm2.nsc.com email: europe.support @ nsc.com Deutsch Tel: a 49 (0) 180-530 85 85 English Tel: a 49 (0) 180-532 78 32 Fran3ais Tel: a 49 (0) 180-532 93 58 Italiano Tel: a 49 (0) 180-534 16 80 JAPAN: Tel: a 81-043-299-2309 S.E. ASIA: Beijing Tel: ( a 86) 10-6856-8601 Shanghai Tel: ( a 86) 21-6415-4092 Hong Kong Tel: ( a 852) 2737-1600 DIAL-A-HELPER BBS via a Standard Modem Modem: CANADA/U.S.: (800) NSC-MICRO (800) 672-6427 EUROPE: ( a 49) 0-8141-351332 Baud: Set-up: anonymous username @ yourhost.site.domain Korea Tel: ( a 82) 2-3771-6909 Malaysia Tel: ( a 60-4) 644-9061 Singapore Tel: ( a 65) 255-2226 Taiwan Tel: a 886-2-521-3288 AUSTRALIA: Tel: ( a 61) 3-9558-9999 INDIA: Tel: ( a 91) 80-559-9467 14.4k Length: 8-Bit Parity: None Stop Bit: 1 24 Hours, 7 Days 21 http://www.national.com http://www.national.com 22 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Molded Small Outline Package (M) Order Number COP912C-XXX/WM, COP912CH-XXX/WM NS Package Number M20B 23 http://www.national.com COP912C/COP912CH 8-Bit Microcontroller Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Molded Dual-In-Line Package (N) Order Number COP912C-XXX/N, COP912CH-XXX/N NS Package Number N20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 http://www.national.com 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: a49 (0) 180-530 85 86 Email: europe.support @ nsc.com Deutsch Tel: a49 (0) 180-530 85 85 English Tel: a49 (0) 180-532 78 32 Fran3ais Tel: a49 (0) 180-532 93 58 Italiano Tel: a49 (0) 180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2308 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.