LogiCORE PCI64 Interface v3.0 Interface Data Sheet December 14, 2001 Data Sheet, v3.0.090 LogiCORE Facts Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 URL: www.xilinx.com/ipcenter Support: www.support.xilinx.com Introduction With the Xilinx LogiCORE PCI Interface, a designer can build a customized, fully PCI 2.2 compliant system with the highest possible sustained performance, 528 Mbytes/sec. Features • • • • • • • • • • • Fully PCI 2.2 compliant, 64/32-bit, 66/33 MHz interface. Customizable, programmable, single-chip solution. Pre-defined implementation for predictable timing. Incorporates Xilinx Smart-IP Technology. 3.3 V operation at 0-66 MHz. 5.0 V operation at 0-33 MHz Fully verified design tested with Xilinx proprietary testbench and hardware. Available for configuration and download on the web: - Web-based Configuration and Download Tool - Web-based User Constraint File Generator Tool CardBus Compliant Supported initiator functions: - Configuration Read, Configuration Write - Memory Read, Memory Write, MRM, MRL - Interrupt Acknowledge, Special Cycles - I/O Read, I/O Write Supported target functions: - Type 0 Configuration Space Header - Up to 3 Base Address Registers (MEM or I/O with adjustable block size from 16 bytes to 2 Gbytes) - Medium Decode Speed - Parity Generation, Parity Error Detection - Configuration Read, Configuration Write - Memory Read, Memory Write, MRM, MRL - Interrupt Acknowledge - I/O Read, I/O Write - Target Abort, Target Retry, Target Disconnect December 14, 2001 PCI64 Resource Utilization1 Slice Four Input LUTs 724 Slice Flip Flops 732 IOB Flip Flops 176 IOBs 89 TBUFs 352 GCLKs 12 Provided with Core Documentation PCI Design Guide PCI Implementation Guide Design File Formats Verilog/VHDL Simulation Model NGO Netlist Constraint Files User Constraint Files (UCF) Guide Files (NCD) Example Design Verilog/VHDL Example Design Design Tool Requirements Xilinx Tools v4.1i SP3 Tested Entry and Synplicity Synplify Verification Tools3 Synopsys FPGA Express Exemplar Leonardo Spectrum Cadence Verilog XL Model Technology ModelSim Xilinx provides technical support for this LogiCORE product when used as described in the Design Guide and the Implementation Guide. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices not listed, or if customized beyond that allowed in the product documentation. 1. The resource utilization depends on configuration of the interface and the user design. Unused resources are trimmed by the Xilinx technology mapper. The utilization figures reported in this table are representative of a maximum configuration. 2. Designs running at 66 MHz in devices other than Virtex-II require one GCLKIOB and two GCLKs. 3. See the implementation guide or product release notes for current supported versions. 1 LogiCORE PCI64 Interface v3.0 Interface Data Sheet through extensive simulation and tested in hardware for electrical, functional, and timing compliance. LogiCORE Facts (Cont) Supported Devices Virtex V300BG432-6C Virtex V1000FG680-6C Virtex-E V300EBG432-6C Virtex-E V1000EFG680-6C Virtex-II 2V1000FG456-5C Spartan-II 2S150FG456-6C Spartan-II 2S200FG456-6C Spartan-IIE 2S300EFG456-6C PCI64/33 Virtex V300BG432-5C Virtex V1000FG680-5C Virtex-E V100EBG352-6C Virtex-E V300EBG432-6C Virtex-E V1000EFG680-6C Virtex-II 2V1000FG456-4C Spartan-II 2S100FG456-6C Spartan-II 2S150FG456-6C Spartan-II 2S200FG456-6C Spartan-IIE 2S100EFG456-6C Spartan-IIE 2S150EFG456-6C Spartan-IIE 2S200EFG456-6C Spartan-IIE 2S300EFG456-6C PCI64/66 3.3v only 3.3v only 3.3v only 3.3v only 3.3v only 3.3v only 3.3v only 3.3v only 3.3v, 5.0v 3.3v, 5.0v 3.3v only 3.3v only 3.3v only 3.3v only 3.3v, 5.0v 3.3v, 5.0v 3.3v, 5.0v 3.3v only 3.3v only 3.3v only 3.3v only Note: Universal card implementations require two bitstreams. Note: Virtex-E and Spartan-IIE recommended for CardBus. Note: Commercial devices only; 0 C < Tj < 85 C. Note: For additional Part/Package combinations, see the UCF Generator in the PCI Lounge. Applications • • • • • Embeddedapplicationsinnetworking,industrial,and telecommunication systems. PCI add-in boards such as frame buffers, network adapters, and data acquisition boards. Hot Swap CompactPCI boards. CardBus Compliant Any applications that need a PCI interface. General Description The LogiCORE PCI Interface is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for each device and the relative placement of the internal logic are pre-defined. Critical paths are controlled by constraint and guide files to ensure predictable timing. This significantly reduces the engineering time required to implement the PCI portion of your design. Resources can instead be focused on your unique user application logic in the FPGA and on the system level design. As a result, LogiCORE PCI products minimize your product development time. Xilinx FPGAs enable designs of fully PCI-compliant systems. The devices meet all required electrical and timing parameters including AC output drive characteristics, input capacitance specifications, setup, hold, and clock to output. These devices meet all specifications for both 3.3v (0-66 MHz) and 5.0v PCI (0-33 MHz). The interface is verified 2 The PCI Compliance Checklist has detailed information about electrical compliance. Other features that enable efficient implementation of a complete PCI system include: • • • Block SelectRAM™ memory. Blocks of on-chip ultrafast RAM with synchronous write and dual-port RAM capabilities. Used in PCI designs to implement FIFOs. SelectRAM™ memory. Distributed on-chip ultra-fast RAM with synchronous write option and dual-port RAM capabilities. Used in PCI designs to implement FIFOs. Internal three-state bus capability for data multiplexing. The interface is carefully optimized for best possible performance and utilization in Xilinx FPGA devices. Smart-IP Technology Drawing on the architectural advantages of Xilinx FPGAs, Xilinx Smart-IP technology ensures the highest performance, predictability, repeatability, and flexibility in PCI designs. The Smart-IP technology is incorporated in every LogiCORE PCI Interface. Xilinx Smart-IP technology leverages the Xilinx architectural advantages, such as look-up tables and segmented routing, as well as floorplanning information, such as logic mapping and location constraints. This technology provides the best physical layout, predictability, and performance. Additionally, these features allow for significantly reduced compile times over competing architectures. To guarantee the critical setup, hold, minimum clock to out, and maximum clock to out timing, the PCI interface is delivered with Smart-IP constraint files that are unique for a device and package combination. These constraint files guide the implementation tools so that the critical paths always are within specification. Xilinx provides Smart-IP constraint files for many device and package combinations. Constraint files for unsupported device and package combinations may be generated using the web-based constraint file generator. Functional Description The LogiCORE PCI Interface is partitioned into five major blocks and a user application as shown below: PCI I/O Interface Block The I/O interface block handles the physical connection to the PCI bus including all signaling, input and output synchronization, output three-state controls, and all requestgrant handshaking for bus mastering. User Application The LogiCORE PCI Interface provides a simple, generalpurpose interface for a wide range of applications. December 14, 2001 Xilinx, Inc. Table 1: PCI Configuration Space Header PAR SERR- Parity Generator/ Checker Base Address Register 0 Base Address Register 1 Base Address Register 2 Command/ Status Register PCI I/O INTERFACE AD[63:0] ADIO[63:0] FRAMEIRDYREQGNT- Initiator State Machine REQ64- Interrupt Pin and Line Register Latency Timer Register Vendor ID, Rev ID, Other User Data 31 16 15 Vendor ID 00h Status Command 04h Class Code BIST PCI Configuration Space Header Type ACK64TRDYDEVSEL- 0 Device ID USER APPLICATION PAR64 PERR- Target State Machine Rev ID Latency Timer 08h Cache 0Ch Line Size Base Address Register 0 (BAR0) 10h PCI Configuration Space Base Address Register 1 (BAR1) 14h This block provides the first 64 bytes of Type 0, version 2.2 Configuration Space Header, as shown in Table 1, to support software-driven “Plug-and Play” initialization and configuration. This includes information for Command, Status, and three Base Address Registers (BARs). Base Address Register 2 (BAR2) 18h Base Address Register 3 (BAR3) 1Ch Base Address Register 4 (BAR5) 20h Base Address Register 5 (BAR5) 24h Cardbus CIS Pointer 28h STOP- The capability for extending configuration space has been built into the user application interface. This capability, including the ability to implement a capabilities pointer in configuration space, allows the user to implement functions such as power management and message signaled interrupts in the user application. Subsystem Vendor ID 2Ch Subsystem ID Expansion ROM Base Address Reserved Parity Generator/Checker This block controls the PCI interface initiator functions. The states implemented are a subset of those defined in Appendix B of the PCI Local Bus Specification. The initiator control logic uses one-hot encoding for maximum performance. Target State Machine This block controls the PCI interface target functions. The states implemented are a subset of those defined in Appendix B of the PCI Local Bus Specification. The target control logic uses one-hot encoding for maximum performance. Max Lat Min Gnt Int Pin 34h 38h Reserved This block generates and checks even parity across the AD bus, the CBE# lines, and the parity signals. It also reports data parity errors via PERR# and address parity errors via SERR#. Initiator State Machine CapPtr 30h Int Line Reserved 3Ch 40h-FFh Note: Shaded areas are not implemented and return zero. Interface Configuration The LogiCORE PCI Interface can easily be configured to fit unique system requirements by using the Xilinx Web-based Configuration and Download Tool or by changing the HDL configuration file. The following customization options, among many others, are supported by the interface and are described in the product design guide. • • Base Address Registers (number, size and type) Configuration Space Header ROM Burst Transfer The PCI bus derives its performance from its ability to support burst transfers. The performance of any PCI application depends largely on the size of the burst transfer. Buffers to support PCI burst transfer can efficiently be implemented using on-chip RAM resources. Supported PCI Commands Table 2 illustrates the PCI bus commands supported by the LogiCORE PCI Interface. The PCI Compliance Checklist December 14, 2001 3 LogiCORE PCI64 Interface v3.0 Interface Data Sheet has more details on supported and unsupported commands. Bandwidth The LogiCORE PCI Interface supports fully compliant zero wait-state burst operations for both sourcing and receiving data. This interface supports a sustained bandwidth of up to 528 MBytes/sec. The design can be configured to take advantage of the ability of the LogiCORE PCI Interface to do very long bursts. The flexible user application interface, combined with support for many different PCI features, gives users a solution that lends itself to use in many high-performance applications. The user is not locked into one DMA engine, hence, an optimized design that fits a specific application can be designed. Recommended Design Experience The LogiCORE PCI Interface is pre-implemented allowing engineering focus on the unique user application functions of a PCI design. Regardless, PCI is a high-performance design that is challenging to implement in any technology. Therefore, previous experience with building high-performance, pipelined FPGA designs using Xilinx implementation software, constraint files, and guide files is recommended. The challenge to implement a complete PCI design including user application functions varies depending on configuration and functionality of your application. Contact your local Xilinx representative for a closer review and estimation for your specific requirements. Timing Specifications Xilinx FPGA devices, with the LogiCORE PCI Interface, enable design of fully compliant PCI systems. The maximum speed at which your user design is capable of running can be affected by the size and quality of the design. The following tables show the key timing parameters for the LogiCORE PCI Interface. Table 2: PCI Bus Commands CBE [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PCI Initiator Interrupt Acknowledge Yes Special Cycle Yes I/O Read Yes I/O Write Yes Reserved Ignore Reserved Ignore Memory Read Yes Memory Write Yes Reserved Ignore Reserved Ignore Configuration Read Yes Configuration Write Yes Memory Read Multiple Yes Dual Address Cycle No Memory Read Line Yes Memory Write Invalidate No Command PCI Target Yes Ignore Yes Yes Ignore Ignore Yes Yes Ignore Ignore Yes Yes Yes Ignore Yes Yes Table 3: Timing Parameters, 66MHz Implementations Symbol Tcyc Thigh Tlow Tval Tval Ton Toff Tsu Tsu Th Trstoff Parameter CLK Cycle Time CLK High Time CLK Low Time CLK to Signal Valid Delay (bussed signals) CLK to Signal Valid Delay (point to point signals) Float to Active Delay Active to Float Delay Input Setup Time to CLK (bussed signals) Input Setup Time to CLK (point to point signals) Input Hold Time from CLK Reset Active to Output Float Min 151 6 6 22 Max 30 62 22 62 22 32,3 141 - 52,3 - 02,3 - 40 Notes: 1. Controlled by timespec constraints, included in product. 2. Controlled by SelectIO configured for PCI66_3. 3. Controlled by guide file, included in product. 4 December 14, 2001 Xilinx, Inc. Table 4: Timing Parameters, 33MHz Implementations Ordering Information Symbol This core may be downloaded from the Xilinx IP Center for use with the Xilinx CORE Generator System V4.1 and later. The Xilinx CORE Generator System tool is bundled with all Alliance and Foundation Series Software packages, at no additional charge. Tcyc Thigh Tlow Tval Tval Ton Toff Tsu Tsu Th Trstoff Parameter CLK Cycle Time CLK High Time CLK Low Time CLK to Signal Valid Delay (bussed signals) CLK to Signal Valid Delay (point to point signals) Float to Active Delay Active to Float Delay Input Setup Time to CLK (bussed signals) Input Setup Time to CLK (point to point signals) Input Hold Time from CLK Reset Active to Output Float Min 301 11 11 22 Max 112 22 112 22 72 281 - 102 - 02 - 40 Part Numbers DO-DI-PCI64-IP -Access to V3.0 64-bit 66 MHz PCI Lounge IP only core support Spartan and Virtex Families To order Xilinx software, please visit the Xilinx Silicon Xpresso Cafe or contact your local Xilinx sales representative. Notes: 1. Controlled by timespec constraints, included in product. 2. Controlled by SelectIO configured for PCI33_3 or PCI33_5. December 14, 2001 5