ETC HCF40100

HCF40100B
32-STAGE STATIC LEFT/RIGHT SHIFT REGISTER
■
■
■
■
■
■
■
■
■
■
■
FULLY STATIC OPERATION
SHIFT LEFT/SHIFT RIGHT CAPABILITY
MULTIPLE PACKAGE CASCADING
RECIRCULATE CAPABILITY
LIFO OR FIFO CAPABILITY
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT SPECIF. UP TO 20V
5V, 10V AND 15V PARAMETRIC RATINGS
INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
HCF40100B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF40100B is a 32-stage shift register containing
32 D-Type master slave flip-flops. The data
present at the SHIFT RIGHT INPUT is
synchronously transferred into the first register
stage with the positive CLOCK edge, provided the
LEFT/RIGHT CONTROL is at a low level, the
RECIRCULATE CONTROL is at a high level, and
the CLOCK INHIBIT is low. If the LEFT/RIGHT
control and the RECIRCULATE CONTROL are
both at a high level, data at the SHIFT LEFT
INPUT is synchronously transferred into the 32nd
DIP
SOP
ORDER CODES
PACKAGE
TUBE
T&R
DIP
SOP
HCF40100BEY
HCF40100BM1
HCF40100M013TR
register stage with the positive CLOCK transition,
provided the CLOCK INHIBIT is low. The state of
the LEFT/RIGHT CONTROL, RECIRCULATE
CONTROL, and CLOCK INHIBIT should not be
changed when the CLOCK is high. Data is
synchronously shifted one stage left or one stage
right depending on the state of the LEFT/RIGHT
CONTROL, with the positive CLOCK edge. Data
clocked into the first of 32 register states is
available at the SHIFT LEFT or SHIFT RIGHT
OUTPUT respectively, on the next negative
CLOCK transition (see Data Transfer Table). No
shifting occurs on the positive CLOCK edge if the
CLOCK INHIBIT line is at a high level. With the
RECIRCULATE CONTROL low, data in the 32nd
stage is shifted into the first stage when the LEFT/
RIGHT CONTROL is low and from the 1st stage to
the 32nd stage when the LEFT/RIGHT CONTROL
is high.
PIN CONNECTION
September 2002
1/11
HCF40100B
IINPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
11
6
12
4
3
2
13
9
FUNCTIONAL DIAGRAM
2/11
SYMBOL
SHIFT
RIGHT IN
SHIFT LEFT
IN
SHIFT
RIGHT OUT
SHIFT LEFT
OUT
CLOCK
CLOCK
INHIBIT
LEFT/RIGHT
CONTROL
RECIRCULATE CONTROL
NAME AND FUNCTION
Shift Right In
Shift Left In
Shift Right Out
Shift Left Out
Clock
Clock Inhibit
Left/Right Control
Recirculate Control
1, 5, 7, 10,
14, 15
NC
Not Connected
8
VSS
Negative Supply Voltage
16
VDD
Positive Supply Voltage
HCF40100B
TRUTH TABLES
CONTROL
Left/Right Control
Clock Inhibit
Recirculate Control
Action
Input Bit Origin
H
H
L
L
X
L
L
L
L
H
H
L
H
L
X
Shift Left
Shift Left
Shift Right
Shift Right
No Shift
Shift Left Input
Stage 1
Shift Right Input
Stage 32
-
DATA TRANSFER
INITIAL STATE
CLOCK
Data Input
Clock Inhibit
Internal Stage
L
L
X
Level Change
Resulting State
Internal Stage Q
Output
X
L
NC
L
L
NC
L
H
L
X
H
NC
X
L
H
NC
H
X
H
H
NC
NC
X
X : Don’t Care
NC : No Change
For Shift-Right Mode: Data Input = SHIFT RIGHT INPUT (Pin 11); Internal Stage = Stage1 (Q1); Output = SHIFT LEFT OUTPUT (Pin 4) .
For Shift-Left Mode: Data Input = SHIFT LEFT INPUT (Pin 6); Internal Stage = Stage32 (Q32); Output = SHIFT RIGHT OUTPUT (Pin 12).
3/11
HCF40100B
LOGIC DIAGRAM
4/11
HCF40100B
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
Parameter
Supply Voltage
VI
DC Input Voltage
II
DC Input Current
PD
Value
Unit
-0.5 to +22
V
-0.5 to VDD + 0.5
± 10
V
mA
200
100
mW
mW
Top
Power Dissipation per Package
Power Dissipation per Output Transistor
Operating Temperature
-55 to +125
°C
Tstg
Storage Temperature
-65 to +150
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
Parameter
Supply Voltage
VI
Input Voltage
Top
Operating Temperature
Value
Unit
3 to 20
V
0 to VDD
V
-55 to 125
°C
5/11
HCF40100B
DC SPECIFICATIONS
Test Condition
Symbol
IL
VOH
VOL
VIH
VIL
IOH
IOL
II
CI
Parameter
Quiescent Current
High Level Output
Voltage
Low Level Output
Voltage
VI
(V)
0/5
0/10
0/15
0/20
0/5
0/10
0/15
5/0
10/0
15/0
High Level Input
Voltage
Low Level Input
Voltage
Output Drive
Current
Output Sink
Current
Input Leakage
Current
Input Capacitance
VO
(V)
0/5
0/5
0/10
0/15
0/5
0/10
0/15
0/18
0.5/4.5
1/9
1.5/13.5
4.5/0.5
9/1
13.5/1.5
2.5
4.6
9.5
13.5
0.4
0.5
1.5
Value
|IO| VDD
(µA) (V)
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
Any Input
Any Input
5
10
15
20
5
10
15
5
10
15
5
10
15
5
10
15
5
5
10
15
5
10
15
18
TA = 25°C
Min.
Typ.
Max.
0.04
0.04
0.04
0.08
5
10
20
100
4.95
9.95
14.95
-40 to 85°C
-55 to 125°C
Min.
Min.
150
300
600
3000
4.95
9.95
14.95
0.05
0.05
0.05
4.95
9.95
14.95
3.5
7
11
1.5
3
4
-3.2
-1
-2.6
-6.8
1
2.6
6.8
±0.1
5
7.5
0.05
0.05
0.05
1.5
3
4
-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
6/11
V
V
1.5
3
4
±1
µA
V
3.5
7
11
-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4
±10-5
Max.
150
300
600
3000
0.05
0.05
0.05
3.5
7
11
-1.36
-0.44
-1.1
-3.0
0.44
1.1
3.0
Max.
Unit
V
mA
mA
±1
µA
pF
HCF40100B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
Test Condition
Symbol
Parameter
tPLH tPHL Propagation Delay Time
tTHL tTLH Transition Time
tsetup
thold
tW
tW
fCL
Data Setup Time
Data Hold Time
Clock Input Pulse Width
Low Level
Clock Input Pulse Width
High Level
Maximum Clock Input
Frequency
VDD (V)
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
Value (*)
Unit
Min.
Typ.
Max.
720
330
230
200
100
80
100
20
10
275
100
75
450
230
190
280
150
140
1
2.5
3
360
165
115
100
50
40
50
10
5
170
75
50
225
115
95
140
75
70
2
5
6
ns
ns
ns
ns
ns
ns
MHz
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
7/11
HCF40100B
WAVEFORM : PROPAGATION DELAY, DATA SETUP, TIME, CLOCK PULSE WIDTH (f=1MHz; 50%
duty cycle)
8/11
HCF40100B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm.
inch
DIM.
MIN.
a1
0.51
B
0.77
TYP
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
Z
3.3
0.130
1.27
0.050
P001C
9/11
HCF40100B
SO-16 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
A
a1
inch
MAX.
MIN.
TYP.
1.75
0.1
0.068
0.2
a2
MAX.
0.003
0.007
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45˚ (typ.)
D
9.8
E
5.8
10
0.385
6.2
0.228
0.393
0.244
e
1.27
0.050
e3
8.89
0.350
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
S
0.62
0.024
8 ˚ (max.)
PO13H
10/11
HCF40100B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
© The ST logo is a registered trademark of STMicroelectronics
© 2002 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco
Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.
© http://www.st.com
11/11