May 1988 NS32C201-10/NS32C201-15 Timing Control Units General Description The NS32C201 Timing Control Unit (TCU) is a 24-pin device fabricated using National’s microCMOS technology. It provides a two-phase clock, system control logic and cycle extension logic for the Series 32000É microprocessor family. The TCU input clock can be provided by either a crystal or an external clock signal whose frequency is twice the system clock frequency. In addition to the two-phase clock for the CPU and MMU (PHI1 and PHI2), it also provides two system clocks for general use within the system (FCLK and CTTL). FCLK is a fast clock whose frequency is the same as the input clock, while CTTL is a replica of PHI1 clock. The system control logic and cycle extension logic make the TCU very attractive by providing extremely accurate bus control signals, and allowing extensive control over the bus cycle timing. Y Y Y Y Y Y Y Y Y Y Y Features Y Y Y 4-bit input (WAITn) allowing precise specification of 0 to 15 wait states Cycle Hold for system arbitration and/or memory refresh System timing (FCLK, CTTL) and control (RD, WR, and DBE) outputs General purpose Timing State Output (TSO) that identifies internal states Peripheral cycle to accommodate slower MOS peripherals Provides ‘‘ready’’ (RDY) output for the Series 32000 CPUs Synchronous system reset generation from Schmitt trigger input Phase synchronization to a reference signal High-speed CMOS technology TTL compatible inputs Single 5V power supply 24-pin dual-in-line package Oscillator at twice the CPU clock frequency 2 phase full VCC swing clock drivers (PHI1 and PHI2) Block Diagram TL/EE/8524 – 1 Series 32000É and TRI-STATEÉ are registered trademarks of National Semiconductor Corp. C1995 National Semiconductor Corporation TL/EE/8524 RRD-B30M105/Printed in U. S. A. NS32C201-10/NS32C201-15 Timing Control Units PRELIMINARY Table of Contents 2.0 DEVICE SPECIFICATIONS 1.0 FUNCTIONAL DESCRIPTION 2.1 Pin Descriptions 1.1 Power and Grounding 1.2 Crystal Oscillator Characteristics 1.3 Clocks 1.4 Resetting 1.5 Synchronizing Two or More TCUs 1.6 Bus Cycles 1.7 Bus Cycle Extension 2.1.1 Supplies 2.1.2 Input Signals 2.1.3 Output Signals 2.2 Absolute Maximum Ratings 2.3 Electrical Characteristics 2.4 Switching Characteristics 1.7.1 Normal Wait States 1.7.2 Peripheral Cycle 1.7.3 Cycle Hold 2.4.1 Definitions 2.4.2 Output Loading 2.4.3 Timing Tables 2.4.4 Timing Diagrams 1.8 Bus Cycle Extension Combinations 1.9 Overriding WAIT Wait States List of Illustrations Crystal Connection ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-1 PHI1 and PHI2 Clock Signals ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-2 Recommended Reset Connections (Non Memory-Managed System) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-3a Recommended Reset Connections (Memory-Managed System) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-3b Slave TCU does not use RWEN during Normal Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-4a Slave TCU Uses Both SYNC and RWEN ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-4b Synchronizing Two TCUs ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-5 Synchronizing One TCU to an External Pulse ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-6 Basic TCU Cycle (Fast Cycle) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-7 Wait State Insertion Using CWAIT (Fast Cycle) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-8 Wait State Insertion Using WAITn (Fast Cycle) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-9 Peripheral Cycle ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-10 Cycle Hold Timing DiagramÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-11 Fast Cycle with 12 Wait States ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-12 Peripheral Cycle with Six Wait States ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-13 Cycle Hold with Three Wait StatesÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-14 Cycle Hold of a Peripheral Cycle ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-15 Overriding WAITn Wait States ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-16 Connection DiagramÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-1 Clock Signals (a) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-2 Clock Signals (b) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-3 Control Inputs ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-4 Control Outputs (Fast Cycle)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-5 Control Outputs (Peripheral Cycle) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-6 Control Outputs (TRI-STATE Timing) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-7 Cycle Hold ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-8 Wait States (Fast Cycle) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-9 Wait States (Peripheral Cycle) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-10 Synchronization Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-11 2 1.0 Functional Description 1.1 POWER AND GROUNDING 1.3 CLOCKS The NS32C201 requires a single a 5V power supply, applied to pin 24 (VCC). See Electrical Characteristics. The Logic Ground on pin 12 (GND), is the common pin for the TCU. A 0.1 mF, ceramic decoupling capacitor must be connected across VCC and GND, as close to the TCU as possible. The NS32C201 TCU has four clock output pins. The PHI1 and PHI2 clocks are required by the Series 32000 CPUs. These clocks are non-overlapping as shown in Figure 1-2 . 1.2 CRYSTAL OSCILLATOR CHARACTERISTICS The NS32C201 has an internal oscillator that requires connections of the crystal and bias components to XIN and XOUT as shown in Figure 1-1. It is important that the crystal and the RC components be mounted in close proximity to the XIN, XOUT and VCC pins to keep printed circuit trace lengths to an absolute minimum. Typical Crystal Specifications: TypeÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀAt-Cut ToleranceÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0.005% at 25§ C TL/EE/8524 – 4 FIGURE 1.2. PHI1 and PHI2 Clock Signals Each rising edge of PHI1 defines a transition in the timing state of the CPU. As the TCU generates the various clock signals with very short transition timings, it is recommended that the conductors carrying PHI1 and PHI2 be kept as short as possible. It is also recommended that only the Series 32000 CPU and, if used, the MMU (Memory Management Unit) be connected to the PHI1 and PHI2 clocks. CTTL is a clock signal which runs at the same frequency as PHI1 and is closely balanced with it. FCLK is a clock, running at the frequency of XIN input. This clock has a frequency that is twice the CTTL clock frequency. The exact phase relationship between PHI1, PHI2, CTTL and FLCK can be found in Section 2. Stability ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0.01% from 0§ to 70§ C Resonance ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀFundamental (parallel) Capacitance ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ20 pF Maximum Series ResistanceÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ50X TL/EE/8524–3 CRYSTAL FREQUENCY (MHz) R (OHM) 6-12 12-18 18-24 24-30 470 220 100 47 FIGURE 1-1. Crystal Connection Diagram TL/EE/8524 – 5 FIGURE 1-3a. Recommended Reset Connections (Non Memory-Managed System) TL/EE/8524 – 6 FIGURE 1-3b. Recommended Reset Connections (Memory-Managed System) 3 1.0 Functional Description (Continued) RWEN/SYNC input to the slave TCU(s) is used for synchronization. The Slave TCU samples the RWEN/SYNC input on the rising edge of XIN. When RSTO is low and CTTL is high (see Figure 1-5 ), if RWEN/SYNC is sampled high, the phase of CTTL of the Slave TCU is shifted by one XIN clock cycle. Two possible circuits for TCU synchronization are illustrated in Figures 1-4a and 1-4b . It should be noted that when RWEN/SYNC is high, the RD and WR signals will be TRISTATE on the slave TCU. 1.4 RESETTING The NS32C201 TCU provides circuitry to meet the reset requirements of the Series 32000 CPUs. If the Reset Input line, RSTI is pulled low, the TCU asserts RSTO which resets the Series 32000 CPU. This Reset Output may also be used as a system reset signal. Figure 1-3a illustrates the reset connections for a non Memory-Managed system. Figure 1-3b illustrates the reset connections for a Memory-Managed system. 1.5 SYNCHRONIZING TWO OR MORE TCUs During reset, (when RSTO is low), one or more TCUs can be synchronized with a reference (Master) TCU. The Note: RWEN/SYNC should not be kept constantly high during reset, otherwise the clock will be stopped and the device will not exit reset when RSTI is deasserted. TL/EE/8524 – 7 FIGURE 1-4a. Slave TCU Does Not Use RWEN During Normal Operation TL/EE/8524 – 8 FIGURE 1-4b. Slave TCU Uses Both SYNC and RWEN Note: When two or more TCUs are to be synchronized, the XIN of all the TCUs should be connected to an external clock source. For details on the external clock, see Switching Specifications in Section 2. TL/EE/8524 – 9 FIGURE 1-5. Synchronizing Two TCUs 4 1.0 Functional Description (Continued) TL/EE/8524 – 10 FIGURE 1-6. Synchronizing One TCU to An External Pulse ated. In addition to RD and WR, other signals are provided: DBE and TSO. DBE is used to enable data buffers. The leading edge of DBE is delayed a half clock period during Read cycles to avoid bus conflicts between data buffers and either the CPU or the MMU. This is shown in Figure 1-7 . The Timing State Output (TSO) is a general purpose signal that may be used by external logic for synchronizing to a System cycle. TSO is activated at the beginning of state T2 and returns to the high level at the beginning of state T4 of the CPU cycle. TSO can be used to gate the CWAIT signal when continuous waits are required. Another application of TSO is the control of interface circuitry for dynamic RAMs. In addition to synchronizing two or more TCUs, the RWEN/ SYNC input can be used to ‘‘fix’’ the phase of one TCU to an external pulse. The pulse to be used must be high for only one rising edge of XIN. Independent of CTTL’s state at the XIN rising edge, the CTTL state following the XIN rising edge will be high. Figure 1-6 shows the timing of this sequence. 1.6 BUS CYCLES In addition to providing all the necessary clock signals, the NS32C201 TCU provides bus control signals to the system. The TCU senses the ADS signal from the CPU or MMU to start a bus cycle. The DDIN input signal is also sampled to determine whether a Read or Write cycle is to be gener- Notes: 1. The CPU and TCU view some timing states (T-states) differently. For clarity, references to T-states will sometimes be followed by (TCU) or (CPU). (CPU) also implies (MMU). 2. Arrows indicate when the TCU samples the input. 3. RWEN is assumed low (RD and WR enabled) unless specified differently. 4. For clarity, T-states for both the TCU and CPU are shown above the diagrams. (See Note 1.) TL/EE/8524 – 11 FIGURE 1-7. Basic TCU Cycle (Fast Cycle) 5 1.0 Functional Description (Continued) There are three basic cycle extension modes provided by the TCU, as described below. 1.7 BUS CYCLE EXTENSION The NS32C201 TCU uses the Wait input signals to extend normal bus cycles. A normal bus cycle consists of four PHI1 clock cycles. Whenever one or more Wait inputs to the TCU are activated, a bus cycle is extended by at least one PHI1 clock cycle. The purpose is to allow the CPU to access slow memories or peripherals. The TCU responds to the Wait signals by pulling the RDY signal low as long as Wait States are to be inserted in the Bus cycle. 1.7.1 Normal Wait States This is a normal Wait State insertion mode. It is initiated by pulling CWAIT or any of the WAITn lines low in the middle of T2. Figure 1-8 shows the timing diagram of a bus cycle when CWAIT is sampled high at the end of T1 and low in the middle of T2. TL/EE/8524 – 12 FIGURE 1-8. Wait State Insertion Using CWAIT (Fast Cycle) 6 1.0 Functional Description (Continued) CWAIT is high during the entire bus cycle, then the RDY line goes low for 1 to 15 clock cycles, depending on the binary weighted value of WAITn. If, for example, WAIT1 and WAIT4 are sampled low, then five wait states will be inserted. This is shown in Figure 1-9 . The RDY signal goes low during T2 and remains low until CWAIT is sampled high by the TCU. RDY is pulled high by the TCU during the same PHI1 cycle in which the CWAIT line is sampled high. If any of the WAITn signals are sampled low during T2 and TL/EE/8524 – 13 FIGURE 1-9. Wait State Insertion Using WAITn (Fast Cycle) 7 1.0 Functional Description (Continued) WR signals are also re-shaped so the setup and hold times for address and data will be increased. This may be necessary when slower peripherals must be accessed. 1.7.2 Peripheral Cycle This cycle is entered when the PER signal line is sampled low at the beginning of T2. The TCU adds five wait states identified as TD0 – TD4 into a normal bus cycle. The RD and Figure 1-10 shows the timing diagram of a peripheral cycle. TL/EE/8524 – 14 FIGURE 1-10. Peripheral Cycle 8 1.0 Functional Description (Continued) pulled low, thus causing wait states to be inserted into the bus cycle. The cycle hold feature can be used in applications involving dynamic RAMs. A timing diagram showing the cycle hold feature is shown in Figure 1-11 . 1.7.3 Cycle Hold If the CWAIT input is sampled low at the end of state T1, the TCU will go into cycle hold mode and stay in this mode for as long as CWAIT is kept low. During this mode the control signals RD, WR, TSO and DBE are kept inactive; RDY is TL/EE/8524 – 15 FIGURE 1-11. Cycle Hold Timing Diagram input signal PER is sampled to determine whether a peripheral cycle is requested. Next, the TCU samples CWAIT again and WAITn to check whether additional wait states have to be inserted into the bus cycle. This sampling point depends on whether PER was sampled high or low. If PER was sampled high, then the sampling point will be in the middle of the TCU state T2, (Figure 1-14 ), otherwise it will occur three clock cycles later (Figure 1-15 ). Figures 1-12 to 1-15 show the timing diagrams for different combinations of cycle extensions. 1.8 BUS CYCLE EXTENSION COMBINATIONS Any combination of the TCU input signals used for extending a bus cycle can be activated at one time. The TCU will honor all of the requests according to a certain priority scheme. A cycle hold request is assigned top priority. It follows a peripheral cycle request, and then CWAIT and WAITn respectively. If, for example, all the input signals CWAIT, PER and WAITn are asserted at the beginning of the cycle, the TCU will enter the cycle hold mode. As soon as CWAIT goes high, the 9 1.0 Functional Description (Continued) TL/EE/8524 – 16 FIGURE 1-12. Fast Cycle With 12 Wait States (2 CWAIT and WAIT10) (Read Cycle) 10 1.0 Functional Description (Continued) TL/EE/8524 – 17 FIGURE 1-13. Peripheral Cycle with Six Wait States (1 CWAIT and WAIT5) (Write Cycle) 11 1.0 Functional Description (Continued) TL/EE/8524 – 18 FIGURE 1-14. Cycle Hold with Three Wait States (1 CWAIT and WAIT2) (Read Cycle) 12 1.0 Functional Description (Continued) TL/EE/8524 – 19 FIGURE 1-15. Cycle Hold of a Peripheral Cycle minate a bus cycle, for example, CWAIT must be asserted for at least one clock cycle, and the WAITn inputs must be forced to their inactive state. At least one wait state is always inserted when using this procedure as a result of CWAIT being sampled low. Figure 1-16 shows the timing diagram of a prematurely terminated bus cycle where eleven wait states were being inserted. 1.9 OVERRIDING WAITn WAIT STATES The TCU handles the WAITn Wait States by means of an internal counter that is reloaded with the binary value corresponding to the state of the WAITn inputs each time CWAIT is sampled low, and is decremented when CWAIT is high. This allows to either extend a bus cycle of a predefined number of clock cycles, or prematurely terminate it. To ter- 13 1.0 Functional Description (Continued) TL/EE/8524 – 20 FIGURE 1-16. Overriding WAITn Wait States (Write Cycle) 14 2.0 Device Specifications 2.1 PIN DESCRIPTIONS 2.1.3 Output Signals The following is a description of all NS32C201 pins. The descriptions reference portions of the Functional Description, Section 1. Reset Output (RSTO): Active low. This signal becomes active when RSTI is low, initiating a system reset. RSTO goes high on the first rising edge of PHI1 after RSTI goes high. Section 1.4. Read Strobe (RD): (TRI-STATE) Active low. Identifies a Read cycle. It is decoded from DDIN and TRI-STATE by RWEN/SYNC. Section 1.6. Write Strobe (WR): (TRI-STATE) Active low. Identifies a Write cycle. It is decoded from DDIN and TRI-STATE by RWEN/SYNC. Section 1.6. 2.1.1 Supplies Power (VCC): a 5V positive supply. Section 1.1. Ground (GND): Power supply return. Section 1.1. 2.1.2 Input Signals Reset Input (RSTI): Active low. Schmitt triggered, asynchronous signal used to generate a system reset. Section 1.4. Address Strobe (ADS): Active low. Identifies the first timing state (T1) of a bus cycle. Data Direction Input (DDIN): Active low. Indicates the direction of the data transfer during a bus cycle. Implies a Read when low and a Write when high. Note: RD and WR are mutually exclusive in any cycle. Hence they are never low at the same time. Data Buffer Enable (DBE): Active low. This signal is used to control the data bus buffers. It is low when the data buffers are to be enabled. Section 1.6. Timing State Output (TSO): Active low. The falling edge of TSO signals the beginning of state T2 of a bus cycle. The rising edge of TSO signals the beginning of state T4. Section 1.6. Ready (RDY): Active high. This signal will go low and remain low as long as wait states are to be inserted in a bus cycle. It is normally connected to the RDY input of the CPU. Section 1.7. Fast Clock (FCLK): This is a clock running at the same frequency as the crystal or the external source. Its frequency is twice that of the CPU clocks. Section 1.3. CPU Clocks (PHI1 and PHI2): These outputs provide the Series 32000 CPU with two phase, non-overlapping clock signals. Their frequency is half that of the crystal or external source. Section 1.3. System Clock (CTTL): This is a system version of the PHI1 clock. Hence, it operates at the CPU clock frequency. Section 1.3. Crystal Output (XOUT): This line is used as the return path for the crystal (if used). It must be left open when an external clock source is used to drive XIN. Section 1.2. Note: In Rev. A of the NS32C201 this signal is CMOS compatible. In later revisions it is TTL compatible. Read/Write Enable and Synchronization (RWEN/ SYNC): TRI-STATEÉ the RD and the WR outputs when high and enables them when low. Also used to synchronize the phase of the TCU clock signals, when two or more TCUs are used. Section 1.5. Crystal or External Clock Source (XIN): Input from a crystal or an external clock source. Section 1.3. Continuous Wait (CWAIT): Active low. Initiates a continuous wait if sampled low in the middle of T2 during a Fast cycle, or in the middle of TD2, during a peripheral cycle. If CWAIT is low at the end of T1, it initiates a Cycle Hold. Section 1.7.1. Four-Bit Wait State Inputs (WAIT1, WAIT2, WAIT4 and WAIT8): Active low. These inputs, (collectively called WAITn), allow from zero to fifteen wait states to be specified. They are binary weighted. Section 1.7.1. Peripheral Cycle (PER): Active low. If active, causes the TCU to insert five wait states into a normal bus cycle. It also causes the Read and Write signals to be re-shaped to meet the setup and hold timing requirement of slower MOS peripherals. Section 1.7.2. 15 2.0 Device Specifications (Continued) Note: Absolute maximum ratings indicate limits beyond which permament damage may occur. Continuous operation at these limits is not intended; operation should be limited to those conditions specified under Electrical Characteristics. 2.2 ABSOLUTE MAXIMUM RATINGS (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V b 0.5V to VCC a 0.5V Input Voltages b 0.5V to VCC a 0.5V Output Voltages b 65§ C to a 150§ C Storage Temperature Lead Temperature (Soldering, 10 sec.) 300§ C Continous Power Dissipation 1W 2.3 ELECTRICAL CHARACTERISTICS TA e b40§ C to a 85§ C, VCC e 5V g 5%, GND e 0V Symbol Parameter Conditions Min Typ Max VIL Input Low Voltage All Inputs Except RSTI & XIN VIH Input High Voltage All Inputs Except RSTI & XIN 2.0 VT a RSTI Rising Threshold Voltage VCC e 5.0V 2.5 3.5 V VHYS RSTI Hysteresis Voltage VCC e 5.0V 0.8 1.9 V VXL XIN Input Low Voltage 0.20 VCC V VXH XIN Input High Voltage IIL Input Low Current VIN e 0V b 10 mA IIH Input High Current VIN e VCC 10 mA Output Low Voltage PHI1 & PHI2, I e 1 mA 0.10 VCC V VOL 0.8 Units 0.80 VCC V All Other Outputs Except XOUT, I e 2 mA Output High Voltage All Outputs Except XOUT, I e b1 mA 0.90 VCC IL Leakage Current on RD/WR 0.4V s VIN s VCC b 20 ICC Supply Current fxin e 20 MHz VOH V 100 Note 1: All typical values are for VCC e 5V and TA e 25§ C. Connection Diagram Dual-In-Line Package TL/EE/8524 – 2 Top View Order Number NS32C201D or NS32C201N See NS Package Number D24C or N24A FIGURE 2.1 16 V V a 20 mA 120 mA 2.0 Device Specifications (Continued) 2.4.2 Output Loading Capacitive loading on output pins for the NS32C201. 2.4 SWITCHING CHARACTERISTICS 2.4.1 Definitions RDY, DBE, TSO ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ50 pF RD, WR ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ75 pF CTTL ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ50 d 100 pF FCLK ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ100 pF PHI1, PHI2 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ170 pF All the timing specifications given in this section refer to 2.0V on the rising or falling edges of the clock phases PHI1 and PHI2; to 15% or 85% of VCC on all the CMOS output signals, and to 0.8V or 2.0V on all the TTL input signals, unless specifically stated otherwise. ABBREVIATIONS L.E.ÐLeading Edge T.E.ÐTrailing Edge R.E.ÐRising Edge F.E.ÐFalling Edge 2.4.3 Timing Tables Symbol Figure Description Reference/Conditions NS32C201-10 Min NS32C201-15 Max Min Units Max CLOCK-SIGNALS (XIN, FCLK, PHI1 & PHI2) TIMING tCp 2.2 Clock Period PHI1 R.E. to Next PHI1 R.E. tCLh 2.2 Clock High Time At 90% VCC on PHI1 (Both Edges) 0.5 tCp b 15 ns 0.5 tCp b 7 ns 0.5 tCp b 10 ns 0.5 tCp b 3 ns tCLl 2.2 Clock Low Time At 15% VCC on PHI1 0.5 tCp b 5 ns 0.5 tCp a 10 ns 0.5 tCp b 5 ns 0.5tCP a 6 ns b 10 ns 0.5 tCP b 4 ns 0.5 tCP b 6 ns 0.5 tCP b 4 ns b5 5 b3 3 ns tCLw(1,2) 2.2 tCLwas Clock Pulse Width At 2.0V on PHI1, PHI2 (Both Edges) PHI1, PHI2 Asymmetry (tCLw (1) – tCLw (2)) At 2.0V on PHI1, PHI2 100 0.5 tCP 66 ns tCLR 2.2 Clock Rise Time 15% to 90% VCC on PHI1 R.E. 8 6 ns tCLF 2.2 Clock Fall Time 90% to 15% VCC on PHI1 F.E. 8 6 ns tnOVL (1,2) 2.2 Clock Non-Overlap Time At 15% VCC on PHI1, PHI2 b2 a2 b2 a2 ns Non-Overlap Asymmetry (tnOVL (1) – tnOVL (2)) At 15% VCC on PHI1, PHI2 b4 4 b3 3 ns tnOVLas tXh 2.2 XIN High Time (External Input) At 80% VCC on XIN (Both Edges) 16 10 ns tXl 2.2 XIN Low Time (External Input) At 15% VCC on XIN (Both Edges) 16 10 ns tXFr 2.2 XIN to FCLK R.E. Delay 80% VCC on XIN R.E. to FCLK R.E. 6 29 6 25 ns tXFf 2.2 XIN to FCLK F.E. Delay 15% VCC on XIN F.E. to FCLK F.E. 6 29 6 25 ns tXCr 2.2 XIN to CTTL R.E. Delay 80% VCC on XIN R.E. to CTTL R.E. 6 34 6 25 ns tXPr 2.2 XIN to PHI1 R.E. Delay 80% VCC on XIN R.E. to PHI1 R.E. 6 32 6 25 ns tFCr 2.2 FCLK to CTTL R.E. Delay FCLK R.E. to CTTL R.E. 0 6 0 6 ns tFCf 2.2 FCLK to CTTL F.E. Delay FCLK R.E. to CTTL F.E. b3 4 b3 4 ns tFPr 2.3 FCLK to PHI1 R.E. Delay FCLK R.E. to PHI1 R.E. b3 4 b3 4 ns tFPf 2.3 FCLK to PHI1 F.E. Delay FCLK R.E. to PHI1 F.E. b5 2 b5 2 ns tFw 2.3 FCLK Pulse Width with Crystal At 50% VCC on FCLK (Both Edges) 0.25 tCp b 5 ns 0.25 tCp a 5 ns 0.25 tCp b 5 ns 0.25 tCp a 5 ns tPCf 2.3 PHI2 R.E.to CTTL F.E. Delay PHI2 R.E. to CTTL F.E. b3 4 b3 3 tCTw 2.3 CTTL Pulse Width At 50% VCC on CTTL (Both Edges) 0.5 tCp b 7 ns 0.5 tCp a 1 ns 0.5 tCp b 5 ns 0.5 tCp a 1 ns Note 1: tXCr, tFCr, tFCf, tPCf, tCTh are measured with 100 pF load on CTTL. Note 2: PHI1 and PHI2 are interchangeable for the following parameters: tCp, tCLh, tCLl, tCLw, tCLR, tCLF, tnOVL, tXPr, tFPr, tFPf. 17 ns 2.0 Device Specifications (Continued) 2.4.3 Timing Tables (Continued) Symbol Figure Description Reference/Conditions NS32C201-10 NS32C201-15 Min Max Min Max b2 5 b2 3 ns Units CTTL TIMING (CL e 50 pF) tPCr 2.3 PHI1 to CTTL R.E. Delay PHI1 R.E. to CTTL R.E. tCTR 2.3 CTTL Rise Time 10% to 90% VCC on CTTL R.E. 7 6 ns tCTF 2.3 CTTL Fall Time 90% to 10% VCC on CTTL F.E. 7 6 ns 4 ns CTTL TIMING (CL e 100 pF) tPCr 2.3 PHI1 to CTTL R.E. Delay PHI1 R.E. to CTTL R.E. tCTR 2.3 CTTL Rise Time 10% to 90% VCC on CTTL R.E. b2 6 b2 8 7 ns tCTF 2.3 CTTL Fall Time 90% to 10% VCC on CTTL F.E. 8 7 ns CONTROL INPUTS (RST1, ADS, DDIN) TIMING tRSTs 2.4 RSTI Setup Time Before PHI1 R.E. 20 15 tADs 2.4 ADS Setup Time Before PHI1 R.E. 25 20 tADw 2.4 ADS Pulse Width ADS L.E. to ADS T.E. 25 20 ns tDDs 2.4 DDIN Setup Time Before PHI1 R.E. 15 13 ns ns CONTROL OUTPUTS (RSTO, TSO, RD, WR, DBE & RWEN/SYNC) TIMING tRSTr 2.4 RSTO R.E. Delay After PHI1 R.E. 21 10 ns tTf 2.5 TSO L.E. Delay After PHI1 R.E. 12 8 ns tTr 2.5 TSO T.E. Delay After PHI1 R.E. tRWf(F) 2.5 RD/WR L.E. Delay (Fast Cycle) After PHI1 R.E. tRWf(S) 2.6 RD/WR L.E. Delay (Peripheral Cycle) After PHI1 R.E. tRWr 2.5/6 RD/WR T.E. Delay After PHI1 R.E. 15 ns tDBf(W) 2.5/6 DBE L.E. Delay (Write Cycle) After PHI1 R.E. 25 15 ns tDBf(R) 2.5/6 DBE L.E. Delay (Read Cycle) After PHI2 R.E. 20 11 ns tDBr 2.5/6 DBE T.E. Delay After PHI2 R.E. 20 15 ns tpLZ 2.7 RD,WR Low Level to TRI-STATE After RWEN/SYNC R.E. 25 20 ns tpHZ 2.7 RD,WR High Level to TRI-STATE After RWEN/SYNC R.E. 20 15 ns tpZL 2.7 RD,WR TRI-STATE to Low Level After RWEN/SYNC F.E. 25 18 ns tpZH 2.7 RD,WR TRI-STATE to High Level After RWEN/SYNC F.E. 25 18 ns 3 3 10 ns 30 18 21 ns 25 15 ns 20 3 3 WAIT STATES & CYCLE HOLD (CWAIT, WAITn, PER & RDY) TIMING tCWs(H) 2.8 CWAIT Setup Time (Cycle Hold) Before PHI1 R.E. 30 20 tCWh(H) 2.8 CWAIT Hold Time (Cycle Hold) After PHI1 R.E. 0 0 ns tCWs(W) 2.8/9 CWAIT Setup Time (Wait States) Before PHI2 R.E. 10 6 ns tCWh(W) 2.9 CWAIT Hold Time (Wait States) After PHI2 R.E. 20 10 ns tWs 2.9 WAITn Setup Time Before PHI2 R.E. 7 6 ns tWh 2.9 WAITn Hold Time After PHI2 R.E. 15 10 ns tPs 2.10 PER Setup Time Before PHI1 R.E. 7 5 ns tPh 2.10 PER Hold Time After PHI1 R.E. 30 20 tRd 2.8/9/10 RDY Delay After PHI2 R.E. 25 ns ns 12 ns SYNCHRONIZATION (SYNC) TIMING tSys 2.11 SYNC Setup Time Before XIN R.E. 6 6 ns tSyh 2.11 SYNC Hold Time After XIN R.E. 5 5 ns tCS 2.11 CTTL/SYNC Inversion Delay CTTL (master) to RWEN/SYNC (slave) 18 10 7 ns 2.0 Device Specifications (Continued) 2.4.4 Timing Diagrams TL/EE/8524 – 21 FIGURE 2-2. Clock Signals (a) TL/EE/8524 – 22 FIGURE 2-3. Clock Signals (b) TL/EE/8524 – 23 FIGURE 2-4. Control Inputs 19 2.0 Device Specifications (Continued) TL/EE/8524 – 24 FIGURE 2-5. Control Outputs (Fast Cycle) TL/EE/8524 – 25 FIGURE 2-6. Control Outputs (Peripheral Cycle) TL/EE/8524 – 26 FIGURE 2-7. Control Outputs (TRI-STATE Timing) 20 2.0 Device Specifications (Continued) TL/EE/8524 – 27 FIGURE 2-8. Cycle Hold TL/EE/8524 – 28 FIGURE 2-9. Wait State (Fast Cycle) TL/EE/8524 – 29 FIGURE 2-10. Wait State (Peripheral Cycle) 21 2.0 Device Specifications (Continued) TL/EE/8524 – 30 FIGURE 2-11. Synchronization Timing 22 Physical Dimensions inches (millimeters) 24-Lead Cavity Dual-In-Line Ceramic Package (D) Order Number NS32C201D-6 or NS32C201D-10 NS Package Number D24C 23 NS32C201-10/NS32C201-15 Timing Control Units Physical Dimensions inches (millimeters) (Continued) Lit. Ý112350 24-Lead Dual-In-Line Molded Package (N) Order Number NS32C201N-10 NS Package Number N24A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. 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