INTEGRATED CIRCUITS 74F1763 Intelligent DRAM controller (IDC) Product specification Supersedes data of 1989 Nov 17 IC15 Data Handbook 1999 Jan 08 Philips Semiconductors Product specification Intelligent DRAM controller (IDC) 74F1763 FEATURES • DRAM signal timing generator • Automatic refresh circuitry • Selectable row address hold and RAS precharge times • Facilitates page mode accesses • Controls 1 MBit DRAMs • Intelligent burst-mode refresh after page-mode access cycles ability to select the RAS precharge time and Row-Address Hold time to fit the particular DRAMs being used. DTACK has been modified from previous family parts to become a negative true, tri-stated output. The options for latched or unlatched address are contained on a single device by the addition of an Address Latch Enable (ALE) input. Finally, a burst refresh monitor has been added to ensure complete refreshing after length page-mode access cycles. With a maximum clock frequency of 100 MHz, the F1763 is capable of controlling DRAM arrays with access times down to 40 nsec. PRODUCT DESCRIPTION The Philips Semiconductors Intelligent Dynamic RAM Controller is a 1 MBit, single-port version of the 74F1764 Dual Port Dynamic RAM Controller. It contains automatic signal timing, address multiplexing and refresh control required for interfacing with dynamic RAMs. Additional features have been added to this device to take advantage of technological advances in Dynamic RAMs. A Page-Mode access pin allows the user to assert RAS for the entire access cycle rather than the pre-defined four-clock-cycle pulse width used for normal random access cycles. In addition, the user has the TYPE fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74F1763 100 MHz 150 mA ORDERING INFORMATION PACKAGES COMMERCIAL RANGE VCC = 5V 10%; TA = 0C TO 70C 48-pin Plastic DIP N74F1763N PKG DWG # SOT240-1 INPUT AND OUTPUT LOADING FAN-OUT TABLENO TAG PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW REQ DRAM Request Input 1.0/1.0 20 A/0.6 mA CP Clock Input 1.0/1.0 20 A/0.6 mA PAGE Page Mode Select Input 1.0/1.0 20 A/0.6 mA PRECHRG RAS Precharge Select Input 1.0/1.0 20 A/0.6 mA HLDROW Row Hold Select Input 1.0/1.0 20 A/0.6 mA DTACK Data Transfer Ack. Output 50/80 35 mA/60 mA GNT Access Grant Output 50/80 35 mA/60 mA RCP Refresh Clock Input 1.0/1.0 20 A/0.6 mA RA0–9 Row Address Inputs 1.0/1.0 20 A/0.6 mA CA0–9 Column Address Inputs 1.0/1.0 20 A/0.6 mA ALE Address Latch Enable Input 1.0/1.0 20 A/0.6 mA RAS Row Address Strobe Output NA 35 mA/60 mA CAS Column Address Strobe Output NA 35 mA/60 mA MA0–9 DRAM Address Outputs NA 35 mA/60 mA NOTES: One (1.0) FAST Unit Load is defined as 20 A in the HIGH state and 0.6 mA in the LOW state. FAST Unit Loads do not correspond to DRAM Input Loads. See Functional Description for details. 1999 Jan 08 2 853–1406 20619 Philips Semiconductors Product specification Intelligent DRAM controller (IDC) 74F1763 BLOCK DIAGRAM RAS CAS PAGE CP PRECHRG HLDROW DTACK RAS, CAS, MUX, DTACK TIMING REQ REFRESH ARBITRATION GNT RCP RA0–9 BURST REFRESH MONITOR REFRESH ADDRESS COUNTER ROW ADDRESS LATCH MULTIPLEXER MA0–9 CA0–9 COLUMN ADDR. LATCH ALE SF01400 3 46 CP RAS 4 45 RCP CAS 5 44 RA0 DTACK 6 43 CA0 MA0 7 42 RA1 6 5 MA1 8 41 CA1 MA0 7 39 CA0 MA2 9 40 RA2 MA1 8 38 RA1 39 CA2 MA2 9 37 CA1 MA3 10 36 RA2 11 35 CA2 GND 12 34 VCC MA4 13 33 RA3 MA5 14 32 CA3 MA3 10 38 VCC GND RA0 44 43 42 41 40 RCP 1 PAGE 2 CP 3 33 RA4 MA7 16 30 CA4 MA6 17 32 CA4 MA8 17 29 RA5 MA7 18 31 RA5 18 19 20 21 22 23 24 25 26 27 28 MA8 19 30 CA5 MA9 20 29 RA6 ALE 21 28 CA6 CA9 22 27 RA7 RA9 23 26 CA7 CA8 24 25 RA8 CA5 31 RA4 MA5 16 RA6 MA6 15 CA6 34 CA3 RA7 MA4 15 CA7 35 RA3 RA8 GND 14 CA8 36 VCC RA9 GND 13 CA9 37 VCC ALE GND 12 SF01401 1999 Jan 08 4 MA9 GND 11 REQ PRECHRG GNT 47 PAGE HLDROW 48 REQ 2 RAS 1 PRECHRG GNT HLDROW CAS PLCC PIN CONFIGURATION DTACK DIP PIN CONFIGURATION SF01402 3 Philips Semiconductors Product specification Intelligent DRAM controller (IDC) 74F1763 PIN DESCRIPTION PINS SYMBOL DIP TYPE NAME AND FUNCTION Active Low Memory Access Request input, must be asserted for the entire DRAM access cycle. REQ is sampled on the rising edge of the CP clock. REQ 48 Input GNT 1 Output PAGE 47 Input Active Low Page-Mode Access input. Forces the IDC to keep RAS asserted for as long as the PAGE input is Low and REQ is asserted Low. HLDROW 2 Input Row Address Hold input. If Low will configure the IDC to maintain the row addresses for a full CP clock cycle after RAS is asserted. If High will program the IDC to maintain row addresses for a 1/2 CP clock cycle after RAS is asserted. PRECHRG 3 Input RAS Precharge input. A Low will program the IDC to guarantee a minimum of 4 CP clock cycles of precharge. A High will guarantee 3 clock cycles of precharge. Active High Grant output. When High indicates that a DRAM access (inactive during refresh) cycle has begun. Asserted from the rising edge of the CP clock. CP 46 Input Clock input. Used by the Controller for all timing and arbitration functions. RCP 45 Input Refresh Clock input. Divided internally by 64 to produce an internal Refresh Request. DTACK 6 Output Active Low, 3-state Data Transfer Acknowledge output. Enabled by the REQ input and asserted four clock cycles after the assertion of RAS, 3-stated when REQ goes High. RA0–9 44, 42, 40, 35, 33, 31, 29, 27, 25, 23 Inputs Row Address inputs. CA0–9 43, 41, 39, 34, 32, 30, 28, 26, 24, 22 Inputs Column Address inputs. Propagated to the MA0–9 outputs 1 CP clock cycle after RAS is asserted, if HLDROW = 0 or 1/2 clock cycle later if HLDROW is 1. RAS 4 Output Active Low Row Address Strobe. Asserted for four clock cycles during each refresh cycle regardless of the PAGE input. Also asserted for four clock cycles during processor access if the PAGE input is High. If PAGE is Low, RAS is negated upon negation of PAGE or REQ, whichever occurs first. CAS 5 Output Active Low Column Address Strobe. Always asserted 1.5 CP clock cycles after the assertion of RAS. Negated upon negation of REQ. HLDROW input pin does not affect RAS to CAS timing. MA0–9 7–10, 15–20 Output DRAM multiplexed address outputs. Row and column addresses asserted on these pins during an access cycle. Refresh counter addresses presented on these outputs during refresh cycles. ALE 21 Input Active Low Address Latch Enable input. A Low on this pin will cause the address latches to be transparent. A High level will latch the RA0–9 and CA0–9 inputs. VCC 36–38 +5V 10% Supply voltage. GND 11–14 Ground 1999 Jan 08 4 Philips Semiconductors Product specification Intelligent DRAM controller (IDC) 74F1763 FUNCTIONAL DESCRIPTION RAS precharge timing The 74F1763 1 Megabit Intelligent DRAM Controller (IDC) is a synchronous device with most signal timing being a function of the CP input clock. In order to meet the RAS precharge requirement of dynamic RAMs, the controller will hold-off a subsequent RAS signal assertion due to a processor access request or a refresh cycle for four or three full CP clock cycles from the previous negation of RAS, depending on the state of the PRECHRG input. If the PRECHRG input is Low, RAS remains High for at least 4 CP clock cycles. If the PRECHRG input is High RAS remains High for at least 3 CP clock cycles. Arbitration Once the DRAM’s RAS precharge time has been satisfied, the REQ input is sampled on each rising edge of the CP clock and an internally generated refresh request is sampled on each falling edge of the same clock. When only one of these requests is sampled as active the appropriate memory cycle will begin immediately. For a memory access cycle this will be indicated by GNT and RAS outputs both being asserted and for a refresh cycle by multiplexing refresh address to the MA0–9 outputs and subsequent assertion of RAS after 1/2CP clock cycle. If both memory access and refresh requests are active at a given time the request sampled first will begin immediately and the other request (if still asserted) will be serviced upon completion of the current cycle and it’s associated RAS precharge time. Refresh timing The refresh address counter wakes-up in an all 1’s state and is an up counter. The refresh clock (RCP) is internally divided down by 64 to produce an internal refresh request. This refresh request is recognized either immediately or at the end of a running memory access cycle. Due to the possibility that page mode access cycles may be lengthy, the controller keeps track of how many refresh requests have been missed by logging them internally (up to 128) and servicing any pending refresh requests at the end of the memory access cycle. The controller performs RAS-only refresh cycles until all pending refresh requests are depleted. Memory access Page-mode access The row (RA0–9) and column (CA0–9) address inputs are latched when ALE input is High. When ALE is Low the input addresses propagate directly to the outputs. When GNT and RAS are asserted, after a REQ has been sampled the RA0–9 address inputs will have already propagated to the MA0–9 outputs for the row address. One or one-half CP clock cycles later (depending on the state of the HLDROW input) the column address (CA0–9) inputs are propagated to the MA0–9 outputs. CAS is always asserted one and one-half CP clock cycles after RAS is asserted. If the PAGE input is High, RAS will be negated approximately four CP clock cycles after its initial assertion. At this time the DTACK output becomes valid indicating the completion of a memory access cycle. The IDC will maintain the state of all its outputs until the REQ input is negated ( see timing waveforms). Fast accesses to consecutive locations of DRAM can be realized by asserting the PAGE input as shown in the timing waveforms. In this mode, the controller does not automatically negate RAS after four CP clock cycles, but keeps it asserted throughout the access cycle. By using external gates, the CAS output can be gated on and off while changing the column address inputs to the controller, which will propagate to the MA0–MA9 address outputs and provide a new column address. This is only useful if the ALE input is Low, enabling the user to charge addresses. This mode can be used with DRAMs that support page or nibble mode addressing. Output driving characteristics Considering the transmission line characteristic of the DRAM arrays, the outputs of the IDC have been designed to provide incident-edge switching (in Dual-Inline-Packaged memory arrays), needed in high performance systems. For more information on the driving characteristics, please refer to Philips Semiconductors application note AN218. The driving characteristics of the 74F1763 are the same as those of the 74F765 shown in the application note. Row address hold times If the HLDROW input of the IDC is High the row address outputs will remain valid 1/2 CP clock cycle after RAS is asserted. If the HLDROW input is Low the row address outputs will remain valid one CP clock cycle after RAS is asserted. 1999 Jan 08 5 Philips Semiconductors Product specification Intelligent DRAM controller (IDC) 74F1763 ABSOLUTE MAXIMUM RATINGS Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range. SYMBOL RATING UNIT VCC Supply voltage PARAMETER –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to +VCC V IOUT Current applied to output in Low output state 120 mA 0 to +70 C –65 to +150 C TA TSTG Operating free-air temperature range Storage temperature RECOMMENDED OPERATION CONDITIONS SYMBOL LIMITS PARAMETER MIN NOM MAX 5.0 5.5 UNIT VCC Supply voltage 4.5 VIH High-level input voltage 2.0 V VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current1 –15 mA IOL Low-level output current1 24 mA TA Operating free-air temperature range 70 C V 0 NOTE: 1. Transient currents will exceed these values in actual operation. DC ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range unless otherwise noted. SYMBOL VOH VOL VIK PARAMETER High-level output voltage Low-level output voltage LIMITS TEST CONDITIONS1 VCC = MIN, VIL = MAX, VIH = MIN VCC = MIN, VIL = MAX, VIH = MIN IOH = –15 mA 3 IOH2 = –35 mA IOL = 24 mA 4 IOL2 = 60 mA MIN 10% VCC 2.5 5% VCC 2.7 5% VCC 2.4 TYP2 MAX UNIT V 3.4 V V 10% VCC 0.35 0.50 V 5% VCC 0.35 0.50 V 0.35 0.80 V –0.73 –1.2 V 100 mA 5% VCC Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage VCC = 0.0V, VI = 7.0V IIH High-level input current VCC = MAX, VI = 2.7V 20 mA IIL Low-level input current VCC = MAX, VI = 0.5V –0.6 mA IOS Output current5 VCC = MAX, VO = 2.25V –225 mA ICC Supply current (total) VCC = MAX 220 mA –100 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, TA = 25C. 3. IOH2 is transient current necessary to guarantee a Low to High transition in a 70W transmission line. 4. IOL2 is transient current necessary to guarantee a High to Low transition in a 70W transmission line. 5. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 1999 Jan 08 6 Philips Semiconductors Product specification Intelligent DRAM controller (IDC) 74F1763 AC ELECTRICAL CHARACTERISTICS LIMITS NO PARAMETER TA = 25C VCC = +5.0V 10% CL = 300pF RL = 70 TEST CONDITIONS MIN TYP TA = 0C to +70C VCC = +5.0V 10% CL = 300pF RL = 70 MAX MIN UNIT MAX 1 CP clock period (tcp) 10 10 ns 2 CP clock low time 5 5 ns 3 CP clock high time 5 5 ns 4 RCP clock period 100 100 ns 5 RCP clock low time 10 10 ns 6 RCP clock high time 10 10 ns 7 Setup time REQ() to CP() 4 ns 8 REQ High hold time after 9 REQ High pulse width2 10 4 CP()1 2 0 0 ns 1/2tcp + 5 1/2tcp + 5 1/2tcp + 5 1/2tcp + 5 1/2tcp + 5 ns Propagation delay CP() to GNT High 8.5 11 13.5 8.5 15.5 ns 11 Propagation delay REQ() to GNT Low 8.5 10.5 13 8.5 14 ns 12 ALE pulse width Low 4 1 4 ns 13 RA0–9, CA0–9 High or Low setup to ALE() 2 0 2 ns 14 ALE() to RA0–9, CA0–9 High or Low hold 1 0 1 ns 15 Propagation delay RA0–9, CA0–9 High or Low to MA0–93 4 7.5 11 4 14 ns 16 Propagation delay ALE() to MA0–9 5.5 8.5 13 5.5 15 ns 17 Propagation delay CP() to RAS() 8.5 10.5 12.5 8.5 14 ns 18 RAS() to MA0–9 (column address) skew HLDROW = 1 1/2tcp – 2 1/2tcp + 2 1/2tcp + 5.5 1/2tcp – 2.5 1/2tcp + 7 ns 19 RAS() to MA0–9 (column address) skew HLDROW = 0 1tcp – 2 1tcp + 2 1tcp + 5.5 1tcp – 2.5 1tcp + 7 ns 20 RAS() to RAS() skew PAGE = 1 4tcp + 1.5 4tcp + 3.5 4tcp + 6 4tcp + 1 4tcp + 6.5 ns 21 Propagation delay CP() to RAS() 12 14 16.5 12 18.5 ns 22 Propagation delay REQ() to RAS()4 14.5 17.5 20 14 24 ns 23 Propagation delay CP() to CAS() 6 8 10 6 11 ns 24 Propagation delay PAGE() to RAS()4 10 12.5 15 10 17 ns 25 RAS() to CAS() skew 1.5tcp–4.5 1.5tcp–2.5 1.5tcp–0.5 1.5tcp–5.5 1.5tcp ns 26 Propagation delay REQ() to CAS() 10 12 15 10 17 ns 27 MA0–9 (column address) to CAS() skew 1tcp – 8 1tcp – 4 1tcp – 0.5 1tcp – 9 1tcp – 0.5 ns 28 MA0–9 (column address) to CAS() skew 1/2tcp – 8 1/2tcp – 4 1/2tcp – 0.5 1/2tcp – 9 1/2tcp – 0.5 ns 29 Set-up time PAGE() to CP() 1999 Jan 08 ALE Low HLDROW = 0 2 2 7 ns Philips Semiconductors Product specification Intelligent DRAM controller (IDC) 74F1763 AC ELECTRICAL CHARACTERISTICS (Continued) LIMITS NO TA = 25C VCC = +5.0V 10% CL = 300pF RL = 70 TEST CONDITIONS PARAMETER TA = 0C TO +70C VCC = +5.0V 10% CL = 300pF RL = 70 UNIT MIN TYP MAX MIN MAX 6 8 11.5 6 12 ns 7.5 9.5 12 7.5 13 ns 9 12 13 9 15.5 ns 30 Propagation delay REQ() to DTACK() 31 Propagation delay CP() to DTACK() 32 Propagation delay REQ() to DTACK (3-state) 33 MA0–9 (refresh address) to RAS() skew 1/2tcp – 5 1/2tcp – 6.5 ns 34 RAS() to MA0–9 (refresh address) skew 1tcp – 2 1tcp – 2.5 ns 35 RAS() to RAS() skew (precharge) PRECHRG = 0 4tcp – 6 4tcp – 3.5 4tcp – 1.5 4tcp – 6.5 4tcp – 6.5 ns 36 RAS() to RAS() skew (precharge) PRECHRG = 1 3tcp – 6 3tcp – 3.5 3tcp – 1.5 3tcp + 1 3tcp – 6.5 ns NOTES: 1. REQ High hold means that, if REQ is High at the rising clock edge, it is guaranteed that the REQ input was not sampled as Low. 2. A 50% duty cycle clock is recommended. If the duty cycle of the clock is not 50%, REQ should be held high for enough time such that a falling CP clock edge samples REQ as High. This is to ensure that refresh cycles don’t get locked-up. 3. When ALE is Low, the address input latches are in the transparent mode and therefore any changes in the address inputs will be propagated to the MA0–9 outputs. Figure 2 illustrates RA0–9 inputs propagating to the MA0–9 outputs, but later in the cycle, if ALE is still Low when the CA0–9 inputs are multiplexed to the MA0–9 outputs the CA0–9 inputs will be in the transparent mode. 4. If PAGE is High and REQ is Low, RAS is automatically negated after approximately 4 CP clock cycles. If PAGE is Low and REQ is also Low, RAS will be negated when PAGE goes High. RAS will always be negated when REQ goes High regardless of the state of PAGE input. TIMING DIAGRAMS 1 3 CP 2 4 6 RCP 5 SF01403 Figure 1. Clock cycle timing 1999 Jan 08 8 Philips Semiconductors Product specification Intelligent DRAM controller (IDC) 74F1763 TIMING DIAGRAMS (Continued) CP 8 9 7 REQ 11 10 GNT ALE ÇÇÇÇ ÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇ ÇÇ 12 13 RA0–9, CA0–9 14 VALID ADDRESS NOTE 1 15 16 MA0–9 NOTE 2 HLDROW = 0 HLDROW = 1 VALID ROW ADDRESS VALID COLUMN ADDRESS 18 17 22 21 19 20 RAS 23 PAGE = 1 25 CAS ÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇ 26 28 27 29 NOTE 3 PAGE 30 DTACK 24 3-STATE 31 32 3-STATE NOTE 1: If the RA0–9 and CA0–9 address inputs are not latched, RA0–9 inputs should remain valid until row address hold time is met and CA0–9 inputs should remain valid until column address hold time is met. NOTE 2: MA0–9 outputs will contain the present row address on the RA0–RA9 inputs or the last row address latched into the device. NOTE 3: PAGE input may be asserted anytime before this rising clock edge in order to hold RAS low. SF01404 Figure 2. Memory access cycle timing 1999 Jan 08 9 Philips Semiconductors Product specification Intelligent DRAM controller (IDC) 74F1763 TIMING DIAGRAMS (Continued) CP ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ REQ NOTE 1 GNT ALE NOTE 2 RA0–9, CA0–9 NOTE 3 PRECHRG = 1 MA0–9 NOTE 4 PRECHRG = 0 REFRESH ADDR. REFRESH ADDR. 33 33 NEXT REFRESH ADDRESS 34 34 35 20 36 20 RAS PRECHRG = 1 PRECHRG = 0 PRECHRG = 1 PRECHRG = 0 CAS DTACK 3-STATE NOTE 1: REQ input is a don’t care during a memory refresh cycle. If REQ is asserted during a refresh cycle, it will be recognized at the first rising CP clock edge, following the refresh cycle and its associated RAS precharge time (see Figure 4). NOTE 2: RA0–9 and CA0–9 address inputs may be latched at anytime during a memory refresh cycle. However, a memory access cycle will not begin until after the completion of the refresh cycle. NOTE 3: RA0–9 and CA0–9 if in the transparent mode do not propogate to the MA0–9 outputs during a refresh cycle. NOTE 4: MA0–9 output will contain the present row address on the RA0–RA9 inputs or the last row address latched into the device. SF01405 Figure 3. Refresh cycle timing following a memory access cycle 1999 Jan 08 10 Philips Semiconductors Product specification Intelligent DRAM controller (IDC) 74F1763 TIMING DIAGRAMS (Continued) CP 8 9 7 REQ 11 10 GNT ALE ÇÇÇÇÇÇÇÇ ÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇ ÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ 12 14 13 RA0–9, CA0–9 VALID ADDRESS NOTE 1 15 16 MA0–9 REFRESH ADDRESS REFRESH ADDRESS PRECHRG = 0 PRECHRG = 1 HLDROW = 0 HLDROW = 1 NOTE 2 VALID ROW ADDRESS VALID COLUMN ADDRESS 18 17 22 21 19 20 RAS 23 36 35 CAS PAGE = 1 25 ÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇ 26 28 27 29 NOTE 3 PAGE 30 DTACK 24 3-STATE 31 32 3-STATE NOTE 1: If the RA0–9 and CA0–9 address inputs are not latched, RA0–9 inputs should remain valid until row address hold time is met and CA0–9 inputs should remain valid until column address hold time is met. NOTE 2: MA0–9 outputs will contain the present row address on the RA0–RA9 inputs or the last row address latched into the device. NOTE 3: PAGE input may be asserted anytime before this rising clock edge in order to hold RAS low. SF01406 Figure 4. Memory access cycle timing following a refresh cycle 1999 Jan 08 11 Philips Semiconductors Product specification Intelligent DRAM controller (IDC) 74F1763 PU 1, 7, 9, 10 33.34 MHz F160A Q0 Q2 CP 16.67 MHz CPU CLOCK CP PU D C Q D C Q RCP PRECHRG RAS HLROW CAS RAS 74F1763 DRAM CONTROLLER MEMORY SELECT (FROM ADDRESS DECODER REQ PAGE AS ALE A3 CA9 A2 RA9 A4–A12 RA0–8 A13–A21 CA0–8 MA0–MA9 MA0–MA9 CAS0 A0 CAS1 A1 PLD 10 SIZ0 CAS2 CAS3 SIZ1 STERM D Q C Q DS Q3 F164 CBACK CP MR CBREQ DSACK0 D DSACK1 Q C SF01407 Figure 5. 16.67 MHz 68030 interface with 74F1763 for cache burst mode support using 4Mbytes of 100nsec. nibble-mode DRAMs (Four 32 bit words read to or written from cache in only clock cycles 1999 Jan 08 12 Philips Semiconductors Product specification Intelligent DRAM controller (IDC) 74F1763 TEST CIRCUIT AND WAVEFORMS VCC VIN VOUT PULSE GENERATOR D.U.T. tw 90% NEGATIVE PULSE 90% VM VM 10% RL RT CL AMP (V) 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% 90% POSITIVE PULSE Test Circuit Simulating RAM Boards DEFINITIONS: RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. VM VM 10% 10% tw 0V Input Pulse Definition INPUT PULSE REQUIREMENTS Family Amplitude VM 74F 3.0V 1.5V Rep. Rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF01408 1999 Jan 08 13 Philips Semiconductors Product specification Intelligent DRAM controller (IDC) 74F1763 DIP48: plastic dual in-line package; 48 leads (600 mil) 1999 Jan 08 14 SOT240-1 Philips Semiconductors Product specification Intelligent DRAM controller (IDC) 74F1763 NOTES 1999 Jan 08 15 Philips Semiconductors Product specification Intelligent DRAM controller (IDC) 74F1763 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 02-99 Document order number: 1999 Jan 08 16 9397-750-05195