ETC SN74CBT16212ADLR

SN54CBT16212A, SN74CBT16212A
24-BIT FET BUS-EXCHANGE SWITCHES
SCDS007R – NOVEMBER 1992 – REVISED NOVEMBER 2001
D
D
D
D
D
Members of the Texas Instruments
Widebus  Family
5-Ω Switch Connection Between Two Ports
TTL-Compatible Input Levels
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
SN54CBT16212A . . . WD PACKAGE
SN74CBT16212A . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
S0
1A1
1A2
2A1
2A2
3A1
3A2
GND
4A1
4A2
5A1
5A2
6A1
6A2
7A1
7A2
VCC
8A1
GND
8A2
9A1
9A2
10A1
10A2
11A1
11A2
12A1
12A2
description
The ’CBT16212A devices provide 24 bits of
high-speed TTL-compatible bus switching or
exchanging. The low on-state resistance of the
switch allows connections to be made with
minimal propagation delay.
Each device operates as a 24-bit bus switch or a
12-bit bus exchanger that provides data
exchanging between the four signal ports via the
data-select (S0, S1, S2) terminals.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
S1
S2
1B1
1B2
2B1
2B2
3B1
GND
3B2
4B1
4B2
5B1
5B2
6B1
6B2
7B1
7B2
8B1
GND
8B2
9B1
9B2
10B1
10B2
11B1
11B2
12B1
12B2
ORDERING INFORMATION
PACKAGE†
TA
TOP-SIDE
MARKING
Tube
SN74CBT16212ADL
Tape and reel
SN74CBT16212ADLR
TVSOP – DGV
Tape and reel
SN74CBT16212ADGVR
CY212A
VFBGA – GQL
Tape and reel
SN74CBT16212AGQLR
CY212A
SSOP – DL
–40°C
40°C to 85°C
ORDERABLE
PART NUMBER
CBT16212A
–55°C to 125°C
CFP – WD
Tube
SNJ54CBT16212AWD
SNJ54CBT16212AWD
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54CBT16212A, SN74CBT16212A
24-BIT FET BUS-EXCHANGE SWITCHES
SCDS007R – NOVEMBER 1992 – REVISED NOVEMBER 2001
GQL PACKAGE
(TOP VIEW)
1
2
3
4
5
terminal assignments
6
1
2
3
4
5
6
A
A
1A2
1A1
S0
S1
S2
1B1
B
B
3A1
2A2
2A1
1B2
2B1
2B2
C
C
4A1
GND
3A2
3B1
GND
3B2
D
D
5A2
4A2
5A1
4B2
4B1
5B1
E
6A2
6A1
5B2
6B1
7B1
6B2
GND
7B2
E
F
G
H
J
F
7A1
7A2
G
GND
H
VCC
8A2
9A1
9A2
9B2
9B1
8B2
J
10A1
10A2
11A1
11B1
10B2
10B1
K
11A2
12A1
12A2
12B2
12B1
11B2
8A1
8B1
K
FUNCTION TABLE
INPUTS
2
INPUTS/OUTPUTS
FUNCTION
S2
S1
S0
A1
A2
L
L
L
Z
Z
Disconnect
L
L
H
B1 port
Z
A1 port = B1 port
L
H
L
B2 port
Z
A1 port = B2 port
L
H
H
Z
B1 port
A2 port = B1 port
H
L
L
Z
B2 port
A2 port = B2 port
H
L
H
Z
Z
Disconnect
H
H
L
B1 port
B2 port
A1 port = B1 port
A2 port = B2 port
H
H
H
B2 port
B1 port
A1 port = B2 port
A2 port = B1 port
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54CBT16212A, SN74CBT16212A
24-BIT FET BUS-EXCHANGE SWITCHES
SCDS007R – NOVEMBER 1992 – REVISED NOVEMBER 2001
logic diagram (positive logic)
1A1
1A2
12A1
2
54
3
53
1B2
27
30
28
29
12B1
12B2
12A2
S0
1B1
1
56
S1
S2
55
Pin numbers shown are for the DGG, DGV, DL, and WD packages.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54CBT16212A, SN74CBT16212A
24-BIT FET BUS-EXCHANGE SWITCHES
SCDS007R – NOVEMBER 1992 – REVISED NOVEMBER 2001
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54CBT16212A
SN74CBT16212A
MIN
MAX
MIN
MAX
5.5
4
5.5
VCC
VIH
Supply voltage
4
High-level control input voltage
2
VIL
TA
Low-level control input voltage
2
–55
125
V
V
0.8
Operating free-air temperature
UNIT
–40
0.8
V
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
II
ICC
∆ICC§
Control inputs
Ci
Control inputs
Cio(off)
SN54CBT16212A
TYP‡
MAX
TEST CONDITIONS
MIN
VCC = 4.5 V,
VCC = 0,
II = –18 mA
VI = 5.5 V
VCC = 5.5 V,
VCC = 5.5 V,
VI = 5.5 V or GND
IO = 0, VI = VCC or GND
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
VI = 3 V or 0
VO = 3 V or 0,
VCC = 4 V,
TYP at VCC = 4 V
ron¶
VCC = 4.5 V
SN74CBT16212A
TYP‡
MAX
MIN
UNIT
–1.2
–1.2
10
10
V
±1
±1
3.2
3
µA
2.5
2.5
mA
µA
2.5
2.5
pF
S0, S1, and S2 = GND
7.5
7.5
pF
VI = 2.4 V,
II = 15 mA
14
20
14
20
VI = 0
II = 64 mA
II = 30 mA
4
10
4
7
4
10
4
7
Ω
VI = 2.4 V, II = 15 mA
6
14
6
12
‡ All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
§ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
¶ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54CBT16212A, SN74CBT16212A
24-BIT FET BUS-EXCHANGE SWITCHES
SCDS007R – NOVEMBER 1992 – REVISED NOVEMBER 2001
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54CBT16212A
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
SN74CBT16212A
VCC = 4 V
VCC = 5 V
± 0.5 V
VCC = 4 V
VCC = 5 V
± 0.5 V
MIN
MAX
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
tpd†
A or B
B or A
0.8*
0.35
0.25
ns
tpd
ten
S
A or B
14
1.5
13
10
1.5
9.1
ns
S
A or B
15
1.5
13.7
10.4
1.5
9.7
ns
tdis
S
A or B
14.2
1.5
13.5
9.2
1.5
8.8
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
† The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
PARAMETER MEASUREMENT INFORMATION
7V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
3V
Output
Control
LOAD CIRCUIT
1.5 V
1.5 V
0V
tPLZ
tPZL
3V
Input
1.5 V
1.5 V
0V
tPLH
1.5 V
3.5 V
1.5 V
1.5 V
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOL + 0.3 V
VOL
tPHZ
tPZH
tPHL
VOH
Output
Output
Waveform 1
S1 at 7 V
(see Note B)
1.5 V
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
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Copyright  2001, Texas Instruments Incorporated