ETC UT52L0464


UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
REVISION HISTORY
REVISION
DESCRIPTION
DATE
Rev.1.0
Original
Rev.1.1
Revised
1. AC TIMING REQUIREMENTS
Input Pulse Levels:0.8V~2.0VB0.4V~2.4V
tIS(min):1, 1.5, 1.3, 2B2, 2.5, 2.5, 2.5ns
tIH(min):1, 0.8, 0.8, 0.8B1, 1, 1, 1ns
2. Output Load Condition
June 20, 2002
Jul. 09, 2002
Rev.1.2
Add Package Outline Dimension
Jul. 26, 2002
1. Page 1 : add access parameter into “Features”
ITEM
-6 -7
-6
-7 Unit
Rev.1.3
Rev.1.4
tCLK(Min.) CL=2 B 10 10 ns
B
6
6
ns
tAC(Max.) CL=2 B
tOH(Min.) CL=2 3
3
ns
2. Page 34,35 : add –6ns,-7ns Limits parameters
1. add Operating temperature :
Commercial : 0℃~70℃
Extended : -20℃~80℃
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
Feb. 10, 2003
Apr. 25, 2003
P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
DESCRIPTION
inputs and outputs are referenced to the rising
edge of CLK. UT52L0464, UT52L0864 and
UT52L1664 achieve very high speed data rates up
to 166MHz, and are suitable for main memories or
graphic memories in computer systems.
UT52L0464 is organized as 4-bank x 4,194,304word x 4-bit Synchronous DRAM with LVTTL
interface and UT52L0864 is organized as 4-bank x
2,097,152-word x 8-bit and UT52L1664 is
organized as 4-bank x 1,048,576-word x 16-bit. All
FEATURES
ITEM
tCLK Clock Cycle Time
CL=2
CL=3
(Min.)
tRAS Active to Precharge Command Preiod (Min.)
tRCD Row to Column Delay (Min.)
tAC Access Time from CLK
(Max.)
CL=2
CL=3
tRC Ref/Active Command Period (Min.)
Icc1 Operation Current(Single Bank) (Max.)
UT52L0464
UT52L0864
UT52L1664
Icc6 Self Refresh Current(Max.)
-6,-7,-7.5,8
UT52L0464/0864/1664
-6
-7
-7.5
-8
10ns
10ns
10ns
10ns
6ns
7ns
7.5ns
8ns
42ns
45ns
45ns
48ns
18ns
20ns
20ns
20ns
6ns
6ns
6ns
6ns
5ns
5.4ns
5.4ns
6ns
60ns
63ns
67.5ns
70ns
85mA
85mA
85mA
85mA
85mA
85mA
85mA
85mA
85mA
85mA
85mA
85mA
1mA
1mA
1mA
1mA
- Single 3.3V ±0.3V power supply
- Operating temperature :
Commercial : 0℃~70℃
Extended : -20℃~80℃
- Max. Clock frequency -6:166MHz<3-3-3>/-7:143MHz<3-3-3>/-7.5:133MHz<3-3-3>/-8:100MHz<2-2-2>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (UT52L1664)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 4096 refresh cycles /64ms
- LVTTL Interface
- Package
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
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P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
PIN CONFIGURATION(TOP VIEW)
UT52L0464
UT52L0864
UT52L1664
PIN CONFIGURATION
(TOP VIEW)
Vdd
Vdd
1
54
Vss
Vss
Vss
NC
DQ0
DQ0
2
53
DQ15
DQ7
NC
VddQ
VddQ
VddQ
3
52
VssQ
VssQ
VssQ
NC
NC
DQ1
4
51
DQ14
NC
NC
DQ0
DQ1
DQ2
5
50
DQ13
DQ6
DQ3
VssQ
6
49
VddQ
VddQ
VddQ
DQ3
7
48
DQ12
NC
NC
47
DQ11
DQ5
NC
46
VssQ
VssQ
VssQ
45
DQ10
NC
NC
44
DQ9
DQ4
DQ2
43
VddQ
VddQ
VddQ
42
DQ8
NC
NC
41
Vss
Vss
Vss
40
NC
NC
NC
39
DQMU
DQM
DQM
38
CLK
CLK
CLK
VssQ
NC
VssQ
NC
NC
DQ2
DQ4
8
VddQ
VddQ
VddQ
9
NC
NC
DQ5
10
DQ1
DQ3
DQ6
11
VssQ
VssQ
VssQ
12
DQ7
13
Vdd
14
NC
Vdd
NC
Vdd
400mil 54pin TSOP(II)
Vdd
NC
NC
DQML
15
/WE
/WE
/WE
16
/CAS
/CAS
/CAS
17
/RAS
/RAS
/RAS
18
37
CKE
CKE
CKE
/CS
/CS
/CS
19
36
NC
NC
NC
BA0(A13)
BA0(A13)
BA0(A13)
20
35
A11
A11
A11
BA1(A12)
BA1(A12)
BA1(A12)
21
34
A9
A9
A9
A10(AP)
A10(AP)
A10(AP)
22
33
A8
A8
A8
A0
A0
A0
23
32
A7
A7
A7
A1
A1
A1
24
31
A6
A6
A6
30
A5
A5
A5
A2
A2
A2
25
A3
A3
A3
26
29
A4
A4
A4
Vdd
Vdd
Vdd
27
28
Vss
Vss
Vss
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
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P90006

UT52L1664/0864/0464
UTRON
Rev. 1.4
CLK：Master Clock
CKE：Clock Enable
/CS：Chip Select
/RAS：Row Address Strobe
/CAS：Column Address Strobe
/WE：Write Enable
DQ0-15：Data I/O
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
DQM：Output Disable / Write Mask
A0-11：Address Input
BA0,1：Bank Address
Vdd：Power Supply
VddQ：Power Supply for Output
Vss：Ground
VssQ：Ground for Output
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
BLOCK DIAGRAM
DQ0-7
I/O Buffer
Memory Array
4096 X 512 X 8
Cell Array
Bank #0
Memory Array
4096 X 512 X 8
Cell Array
Bank #1
Memory Array
4096 X 512 X 8
Cell Array
Bank #2
Memory Array
4096 X 512 X 8
Cell Array
Bank #3
Mode
Register
Control Circuitry
Address Buffer
Control Signal Buffer
Clock Buffer
A0-11
BA0,1
CLK
CKE
/CS
/RAS
/CAS /WE
DQM
Note：This figure shows the UT52L0864
The UT52L0464 configuration is 4096x1024x4 of cell array and DQ0-3
The UT52L1664 configuration is 4096x256x16 of cell array and DQ0-15
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
PIN FUNCTION
Input
Master Clock:
All other inputs are referenced to the rising edge of CLK
CKE
Input
Clock Enable:
CKE controls internal clock. When CKE is low, internal clock for the
following cycle is ceased. CKE is also used to select
Auto / self-refresh.
After self-refresh mode is started, CKE becomes asynchronous input.
Self-refresh is maintained as long as CKE is low.
/CS
Input
Chip Select:
When /CS is high, any command means No Operation.
/RAS, /CAS, /WE
Input
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11
Input
A0-11 specify the Row / Column Address in conjunction with BA0,1
The Row Address is specified by A0-11.
The Column Address is specified by A0-9(x4)/A0-8(x8)/A0-7(x16).
A10 is also used to indicate precharge option. When A10 is high at a
read / write command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
BA0,1
Input
Bank Address:
BA0,1 specifies one of four banks to which a command is applied.
BA0,1 must be set with ACT, PRE , READ , WRITE commands.
DQ0-3(x4),
DQ0-7(x8),
DQ0-15(x16)
Input/Output
CLK
DQM(x4,x8),
DQMU/L(x16)
Vdd,Vss
VddQ,VssQ
Input
Data In and Data out are referenced to the rising edge of CLK.
Din Mask / Output Disable:
When DQM(U/L) is high in burst write, Din for the current cycle is
masked. When DQM(U/L) is high in burst read,
Dout is disabled at the next but one cycle.
Power Supply Power Supply for the memory array and peripheral circuitry.
Power Supply VddQ and VssQ are supplied to the Output Buffers only.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6
P90006

UT52L1664/0864/0464
UTRON
Rev. 1.4
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
BASIC FUNCTIONS
The UT52L0464,0864and 1664 provides basic
functions, bank (row) activate, burst read / write,
bank (row) precharge, and auto / self refresh.
Each command is defined by control signals of
/RAS, /CAS and /WE at CLK rising edge. In
addition to 3 signals, /CS ,CKE and A10 are used
as chip select, refresh option, and precharge
option, respectively.
To know the detailed definition of commands,
please see the command truth table.
CLK
/CS
Chip Select：L=select, H=deselect
/RAS
Command
/CAS
Command
/WE
Command
CKE
A10
define basic command
Refresh Option @ refresh command
Precharge Option @ precharge or read / write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (autoprecharge, READA).
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is
set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (autoprecharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read /
write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA ).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are generated
internally. After this command, the banks are precharged automatically.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
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P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
COMMAND TRUTH TABLE
COMMAND
Deselect
MNEMONIC
CKE CKE
/CS /RAS /CAS /WE BA0,1 A11
n-1
n
A10 A0-9
DESEL
H
X
H
X
X
X
X
X
X
X
No Operation
NOP
H
X
L
H
H
H
X
X
X
X
Row Address Entry &
Bank Active
ACT
H
X
L
L
H
H
V
V
V
V
Single Bank Precharge
PRE
H
X
L
L
H
L
V
X
L
X
PREA
H
X
L
L
H
L
X
X
H
X
WRITE
H
X
L
H
L
L
V
V
L
V
WRITEA
H
X
L
H
L
L
V
V
H
V
READ
H
X
L
H
L
H
V
V
L
V
READA
H
X
L
H
L
H
V
V
H
V
Auto-Refresh
REFA
H
H
L
L
L
H
X
X
X
X
Self-Refresh Entry
REFS
H
L
L
L
L
H
X
X
X
X
L
H
H
X
X
X
X
X
X
X
L
H
L
H
H
H
X
X
X
X
Precharge All Banks
Column Address Entry
& Write
Column Address Entry &
Write with Auto-Precharge
Column Address Entry
& Read
Column Address Entry &
Read with Auto-Precharge
Self-Refresh Exit
REFSX
Burst Terminate
TBST
H
X
L
H
H
L
X
X
X
X
Mode Register Set
MRS
H
X
L
L
L
L
L
L
L
V*1
H=High Level, L=Low Level, V=Valid, X=Don’t Care, n=CLK cycle number
NOTE: 1. A7-A9=0, A0-A6=Mode Address
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
8
P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
FUNCTION TRUTH TABLE
Current
State
/CS
IDLE
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ /
WRITE
ILLEGAL*2
L
L
H
H
BA, RA
L
L
H
L
BA, A10
L
L
L
H
X
REFA
Auto-Refresh*5
L
L
L
L
Op-Code,
Mode-Add
MRS
Mode Register Set*5
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
TBST
NOP
L
H
L
H
BA, CA, A10
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
L
L
H
L
BA, A10
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
ROW
ACTIVE
/RAS /CAS /WE
Address
Command
ACT
Action
Bank Active, Latch RA
PRE / PREA NOP*4
READ /
READA
WRITE /
WRITEA
ACT
Begin Read, Latch CA, Determine
Auto-Precharge
Begin Write, Latch CA, Determine
Auto-Precharge
Bank Active, ILLEGAL*2
PRE / PREA Precharge/ Precharge All
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
9
P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
FUNCTION TRUTH TABLE (continued)
Current
State
/CS
READ
H
X
X
X
X
DESEL
NOP(Continue Burst to END)
L
H
H
H
X
NOP
NOP(Continue Burst to END)
L
H
H
L
X
TBST
Terminate Burst
L
H
L
H
BA, CA, A10
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
L
L
H
L
BA, A10
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP(Continue Burst to END)
L
H
H
H
X
NOP
NOP(Continue Burst to END)
L
H
H
L
X
TBST
Terminate Burst, Latch CA, Begin
L
H
L
H
BA, CA, A10
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
L
L
H
L
BA, A10
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
WRITE
/RAS /CAS /WE
Address
Command
READ /
READA
WRITE /
WRITEA
ACT
Action
Terminate Burst, Latch CA, Begin
Read, Determine Auto-Precharge*3
Terminate Burst, Latch CA, Begin
Write, Determine Auto-Precharge*3
Bank Active, ILLEGAL*2
PRE / PREA Terminate Burst, Precharge
READ /
READA
WRITE /
WRITEA
ACT
Terminate Burst, Latch CA, Begin
Read, Determine Auto-Precharge*3
Terminate Burst, Latch CA, Begin
Write, Determine Auto-Precharge*3
Bank Active, ILLEGAL*2
PRE / PREA Terminate Burst, Precharge
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
10
P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
FUNCTION TRUTH TABLE (continued)
Current State
/CS
READ with
AUTO
PRECHARGE
H
X
X
X
X
DESEL
NOP(Continue Burst to END)
L
H
H
H
X
NOP
NOP(Continue Burst to END)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
H
BA, CA, A10
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
L
L
H
L
BA, A10
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP(Continue Burst to END)
L
H
H
H
X
NOP
NOP(Continue Burst to END)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
H
BA, CA, A10
L
H
L
L
BA, CA, A10
L
L
H
H
BA, RA
L
L
H
L
BA, A10
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
WRITE with
AUTO
PRECHARGE
/RAS /CAS
/WE
Address
Command
READ /
READA
WRITE /
WRITEA
ACT
Action
ILLEGAL
ILLEGAL
Bank Active / ILLEGAL*2
PRE / PREA ILLEGAL*2
READ /
READA
WRITE /
WRITEA
ACT
ILLEGAL
ILLEGAL
Bank Active / ILLEGAL*2
PRE / PREA ILLEGAL*2
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
11
P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
FUNCTION TRUTH TABLE (continued)
Current State
/CS
PRECHARGING
H
X
X
X
X
DESEL
NOP(Idle after tRP)
L
H
H
H
X
NOP
NOP(Idle after tRP)
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ /
WRITE
ILLEGAL*2
L
L
H
H
BA, RA
ACT
ILLEGAL*2
L
L
H
L
BA, A10
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP(Row Active after tRCD)
L
H
H
H
X
NOP
NOP(Row Active after tRCD)
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ /
WRITE
ILLEGAL*2
L
L
H
H
BA, RA
ACT
ILLEGAL*2
L
L
H
L
BA, A10
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
ROW
ACTIVATING
/RAS /CAS
/WE
Address
Command
Action
PRE / PREA NOP*4(Idle after tRP)
PRE / PREA ILLEGAL*2
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
12
P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
FUNCTION TRUTH TABLE (continued)
Current State
/CS
WTITE
RECOVERING
H
X
X
X
X
DESEL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
TBST
ILLEGAL*2
L
H
L
X
BA, CA, A10
READ /
WRITE
ILLEGAL*2
L
L
H
H
BA, RA
ACT
ILLEGAL*2
L
L
H
L
BA, A10
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
H
X
X
X
X
DESEL
NOP(Idle after tRC)
L
H
H
H
X
NOP
NOP(Idle after tRC)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
X
BA, CA, A10
READ /
WRITE
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
REFRESHING
/RAS /CAS
/WE
Address
Command
Action
PRE / PREA ILLEGAL*2
PRE / PREA ILLEGAL
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UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
FUNCTION TRUTH TABLE (continued)
Current State
/CS
/RAS /CAS
/WE
Address
Command
Action
MODE
REGISTER
SETTING
H
X
X
X
X
DESEL
NOP(Idle after tRSC)
L
H
H
H
X
NOP
NOP(Idle after tRSC)
L
H
H
L
X
TBST
ILLEGAL
L
H
L
X
BA, CA, A10
READ /
WRITE
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
L
L
L
H
X
REFA
ILLEGAL
L
L
L
L
Op-Code,
Mode-Add
MRS
ILLEGAL
PRE / PREA ILLEGAL
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UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
FUNCTION TRUTH TABLE for CKE
Current State
SELFREFRESH*1
POWER DOWN
ALL BANKS
IDLE*2
ANY STATE
other than
listed above
CKE
n-1
CKE
n
/CS
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit Self-Refresh (Idle after tRC)
L
H
L
H
H
H
X
Exit Self-Refresh (Idle after tRC)
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP (Maintain Self-Refresh)
H
X
X
X
X
X
X
INVALID
L
H
X
X
X
X
X
Exit Power Down to Idle
L
L
X
X
X
X
X
NOP (Maintain Power Down)
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
L
L
L
H
X
Enter Self-Refresh
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
X
X
X
ILLEGAL
L
X
X
X
X
X
X
Refer to Current State =Power Down
H
H
X
X
X
X
X
Refer to Function Truth Table
H
L
X
X
X
X
X
Begin CLK Susspend at Next Cycle*3
L
H
X
X
X
X
X
Exit CLK Susspend at Next Cycle*3
L
L
X
X
X
X
X
Maintain CLK Suspend
/RAS /CAS /WE
Add Action
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup
time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
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UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
SIMPLIFIED STATE DIAGRAM
SELF
REFRESH
REFS
REFSX
MRS
MODE
REGISTER
SET
AUTO
REFRESH
REFA
IDLE
CKEL
CKEH
ACT
CLK
SUSPEND
POWER
DOWN
CKEL
CKEH
ROW
ACTIVE
TERM
TERM
WRITE
READ
WRITEA
CKEL
WRITE
SUSPEND
READA
CKEL
WRITE
WRITE
READ
CKEH
CKEH
READ
SUSPEND
READ
READA
WRITEA
READA
WRITEA
PRE
CKEL
WRITEA
SUSPEND
CKEL
WRITEA
CKEH
CKEH
PRE
POWER
APPLIED
POWER
ON
READA
SUSPEND
READA
PRE
PRE
PRE
CHARGE
Automatic Sequence
Command Sequence
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UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
POWER ON SEQUENCE
Before starting normal operation, the following
power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to
maintain CKE high, DQM high and NOP
condition at the inputs.
2. Maintain stable power, stable clock, and NOP
input conditions for a minimum of 200µs.
3. Issue precharge commands for all banks.
(PRE or PREA)
4. After all banks become idle state (after tRP),
issue 8 or more auto-refresh commands.
5. Issue a mode register set command to
initialize the mode register.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can
be programmed by setting the mode register
(MRS). The mode register stores these data until
the next MRS command, which may be issued
when all banks are in idle state. After tRSC from a
MRS command, the SDRAM is ready for new
command.
CLK
/CS
/RAS
/CAS
After these sequence, the SDRAM is idle state
and ready for normal operation.
BA0 BA1 A11
0
0
0
Write
Mode
LATENCY
MODE
CL
000
001
010
011
100
101
110
111
A10
A9
A8
A7
0
WM
0
0
0
1
A6
/WE
BA0,1 A11-A0
A5
LTMODE
A4
A3
V
A2
BT
Burst Write
Single Write
/CAS LATENCY
R
R
2
3
R
R
R
R
A1
A0
BL
BURST
LENGTH
BL
000
001
010
011
100
101
110
111
BURST
TYPE
0
1
BT=0
1
2
4
8
R
R
R
FP
BT=1
1
2
4
8
R
R
R
R
SEQUENTIAL
INTERLEAVED
R : Reserved for Future Use
FP : Full Page
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UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
CLK
Command
Address
Read
Write
Y
Y
Q0
DQ
CL=3
BL=4
Q1
/CAS Latency
Q2
Q3
Burst Length
Initial Address BL
D0
D1
D2
D3
Burst Length
Burst Type
Column Addressing
A2
A1
A0
Sequential
Interleaved
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
8
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
-
0
0
0
1
2
3
0
1
2
3
-
0
1
1
2
3
0
1
0
3
2
4
-
1
0
2
3
0
1
2
3
0
1
-
1
1
3
0
1
2
3
2
1
0
-
-
0
0
1
0
1
1
0
1
0
2
-
-
1
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UT52L1664/0864/0464
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The SDRAM has four independent banks. Each
bank is activated by the ACT command with the
bank addresses (BA0,1). A row is indicated by the
row addresses A0-11. The minimum activation
interval between one bank and the other bank is
tRRD. Maximum 2 ACT commands are allowed
within tRC , although the number of banks which
are active concurrently is not limited.
PRECHARGE
The PRE command deactivates the bank
indicated by BA0,1. When multiple banks are
active, the precharge all command (PREA, PRE
+ A10=H) is available to deactivate them at the
same time. After tRP from the precharge, an ACT
command to the same bank can be issued.
READ
After tRCD from the bank activation, a READ
command can be issued. 1st output data is
available after the /CAS Latency from the READ,
followed by (BL -1) consecutive data when the
Burst Length is BL. The start address is specified
by A0-A9(x4), A0-8(x8), A0-7 (x16) , and the
address sequence of burst data is defined by the
Burst Type. A READ command may be applied to
any active bank, so the row precharge time (tRP)
can be hidden behind continuous output data by
interleaving the multiple banks. When A10 is high
at a READ command, the auto-precharge
(READA) is performed. Any command (READ,
WRITE, PRE, TBST, ACT) to the same bank is
inhibited till the internal precharge is complete.
The internal precharge starts at BL after READA.
(Need to keep tRAS min.) The next ACT
command can be issued after (BL + tRP) from the
previous READA.
Bank Activation and Precharge All (BL=4, CL=3)
CLK
2 ACT command / tRCmin
tRCmin
Command
ACT
ACT
A0-9
Xa
PRE
READ
tRRD
ACT
tRAS
Xb
Y
0
tRP
Xb
tRCD
A10
Xa
Xb
A11
Xa
Xb
BA0,1
00
01
1
Xb
Xb
00
01
DQ
Qa0
Qa1
Qa2
Qa3
Prevharge all
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UT52L1664/0864/0464
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
Multi Bank Interleaving READ (BL=4, CL=3)
CLK
Command
ACT
READ
ACT
READ
PRE
tRCD
A0-9
Xa
Y
Xb
Y
A10
Xa
0
Xb
0
0
A11
Xa
BA0,1
00
10
00
Qa1
Qa2
Xb
00
10
Qa0
DQ
Qa3
Qb0
Qb1
Qb2
CAS latency
Burst Length
READ with Auto-Precharge (BL=4, CL=3)
CLK
BL + tRP
Command
ACT
READ
tRCD
ACT
BL
tRP
A0-9
Xa
Y
Xa
A10
Xa
1
Xa
A11
Xa
BA0,1
00
Xa
00
00
DQ
Qa0
Qa1
Qa2
Qa3
Internal precharge start
READ Auto-Precharge Timing (BL=4)
CLK
Command
ACT
READ
BL
CL=3
DQ
CL=2
DQ
Qa0
Qa0
Qa1
Qa2
Qa1
Qa2
Qa3
Qa3
Internal precharge start Timing
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UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
interleaving the multiple banks. From the last input
data to the PRE command, the write recovery time
After tRCD from the bank activation, a WRITE
(tWR) is required. When A10 is high at a WRITE
command can be issued. 1st input data is set at
command, the autoprecharge (WRITEA) is
the same cycle as the WRITE. Following (BL -1)
performed. Any command (READ, WRITE, PRE,
data are written into the RAM, when the Burst
TBST, ACT) to the same bank is inhibited till the
Length is BL. The start address is specified by A0internal precharge is complete. The internal
A9(x4), A0-8(x8), A0-7(x16) and the address
precharge begins at tWR after the last input data
sequence of burst data is defined by the Burst
cycle. (Need to keep tRAS min.) The next ACT
Type. A WRITE command may be applied to any
command can be issued after tRP from the
active bank, so the row precharge time (tRP) can
internal precharge timing.
be hidden behind continuous input data by
.
WRITE with Auto-Precharge (BL=4)
WRITE
CLK
Command
ACT
Write
ACT
tRCD
Write
PRE
PRE
0
0
0
0
10
00
10
Db0
Db1
tRCD
A0-9
Xa
Y
Xb
A10
Xa
0
Xb
A11
Xa
BA0,1
00
Y
0
Xb
DQ
00
10
Da0
Da1
Da2
Da3
Db2
Db3
Multi Bank Interleaving WRITE (BL=4)
CLK
Command
ACT
Write
ACT
tRCD
tRP
A0-9
Xa
Y
Xa
A10
Xa
1
Xa
A11
Xa
BA0,1
00
Xa
00
00
tWR
DQ
Da0
Da1
Da2
Da3
Internal precharge starts
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UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
BURST INTERRUPTION [ Read Interrupted by Read ]
Burst read operation can be interrupted by new read of any bank. Random column access is allowed
READ to READ interval is minimum 1 CLK.
Read Interrupted by Read (BL=4, CL=3)
CLK
Command
READ
READ
READ
READ
A0-9
Yi
Yj
Yk
Yl
A10
0
0
0
0
00
00
10
01
A11
BA0,1
DQ
Qai0
Qaj0
Qaj1
Qbk0
Qbk1
Qbk2
Qal0
Qal1
Qal2
Qal3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any bank. Random column access is allowed. In this
case, the DQ should be controlled adequately by using the DQM to prevent the bus contention. The
output is disabled automatically 1 cycle after WRITE assertion.
Read Interrupted by Write (BL=4, CL=3)
CLK
Command
READ
Write
A0-9
Yi
Yj
A10
0
0
00
00
A11
BA0,1
DQM
Q
D
Qai0
Daj0
DQM contorl
Daj1
Daj2
Daj3
Write contorl
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UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge of the same bank . READ to PRE interval is
minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. As a result,
READ to PRE interval determines valid data length to be output. The figure below shows examples of
BL=4.
Read Interrupted by Precharge (BL=4)
CLK
Command
READ
PRE
DQ
Command
READ
Q0
Q1
Q0
Q1
Q2
PRE
CL=3
DQ
Command
READ
PRE
DQ
Command
Q0
READ
PRE
Q0
DQ
Command
READ
Q1
Q2
PRE
CL=2
DQ
Command
DQ
Q0
READ
Q1
PRE
Q0
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UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
[Read Interrupted by Burst Terminate]
Similarly to the precharge, a burst terminate command can interrupt the burst read operation and disable
the data output. The terminated bank remains active.
READ to TBST interval is minimum 1 CLK. A TBST command to output disable latency is equivalent to the
/CAS Latency.
Read Interrupted by Terminate (BL=4)
CLK
Command
READ
TBST
DQ
Command
READ
Q0
Q1
Q0
Q1
Q2
TBST
CL=3
DQ
Command
READ
TBST
DQ
Command
Q0
READ
TBST
Q0
DQ
Command
READ
Q1
Q2
TBST
CL=2
DQ
Command
DQ
Q0
READ
Q1
TBST
Q0
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UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any bank. Random column access is allowed.
WRITE to WRITE interval is minimum 1 CLK.
Write Interrupted by Write (CL=3,BL=4)
CLK
Command
Write
Write
Write
Write
A0-9
Yi
Yj
Yk
Yl
A10
0
0
0
0
00
00
10
00
Dai0
Daj0
A11
BA0,1
DQ
Daj1
Dbk0
Dbk1
Dbk2
Dal0
Dal1
Dal2
Dal3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank. Random column access is
allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle
is "don't care".
Write Interrupted by Read (CL=3,BL=4)
CLK
Command
Write
READ
Write
READ
A0-9
Yi
Yj
Yk
Yl
A10
0
0
0
0
00
00
10
00
A11
BA0,1
DQM
DQ
Dai0
Qaj0
Qaj1
Dbk0
Dbk1
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Qal0
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UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
[Write Interrupted by Precharge]
Burst write operation can be interrupted by precharge of the same bank.Write recovery time(tWR) is
required from the last data to PRE command. During write recovery, data inputs must be masked by DQM.
Write Interrupted by Precharge (BL=4)
CLK
Command
ACT
Write
ACT
A0-9,11
Xa
Ya
A10
0
0
0
0
BA0,1
00
00
00
00
PRE
tRP
Xa
DQM
tWR
DQ
Da0
Da1
[Write Interrupted by Burst Terminate]
Burst terminate command can terminate burst write operation.In this case, the write recovery time is not
required and the bank remains active. WRITE to TBST interval is minimum 1 CLK.
Write Interrupted by Terminate (BL=4)
CLK
Command
ACT
Write
A0-9,11
Xa
Ya
Yb
A10
0
0
0
BA0,1
00
00
00
DQ
Da0
TBST
Da1
Write
Db0
Db1
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Db2
Db3
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UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
[Write with Auto-Precharge Interrupted by Write or Read to another Bank]
Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT command
can be issued after tRP. Auto-precharge interruption by a command to the same bank is inhibited.
Write with Auto-Precharge Interrupted by WRITE to another bank (BL=4)
CLK
Command
Write
Write
ACT
A0-9,11
Ya
Yb
A10
1
0
Xa
BA0,1
00
10
00
DQ
Da0
BL
tRP
Xa
tWR
Da1
auto-precharge
Db0
Db1
Db2
Db3
interrupted
activate
Write with Auto-Precharge Interrupted by READ to another bank (CL=2,BL=4)
CLK
Command
Write
Read
ACT
A0-9,11
Ya
Yb
A10
1
0
Xa
BA0,1
00
10
00
DQ
Da0
BL
tRP
Xa
tWR
Da1
auto-precharge
Qb0
interrupted
Qb1
Qb2
Qb3
activate
UTRON TECHNOLOGY INC.
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P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
[Read with Auto-Precharge Interrupted by Read to another Bank]
Burst Read with auto-precharge can be interrupted by write or read to another bank. Next ACT command
can be issued after tRP. Auto-precharge interruption by a command to the same bank is inhibited.
Read with Auto-Precharge Interrupted by Read to another bank (CL=2,BL=4)
CLK
Command
Read
Read
ACT
A0-9,11
Ya
Yb
Xa
A10
1
0
Xa
BA0,1
00
10
00
BL
DQ
Qa0
auto-precharge
tRP
Qa1
Qb0
interrupted
Qb1
Qb2
Qb3
activate
[Full Page Burst]
Full page burst length is available for only the sequential burst type. Full page burst read or write is
repeated untill a Precharge or a Burst Terminate command is issued. In case of the full page burst, a read
or write with auto-precharge command is illegal.
[Single Write]
When single write mode is set, burst length for write is always one, independently of Burst Length defined
by (A2-0).
UTRON TECHNOLOGY INC.
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P90006

UTRON
Rev. 1.4
UT52L1664/0864/0464
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H) command.
The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 64M bit memory cells.
The auto-refresh is performed on 4 banks concurrently. Before performing an auto-refresh, all banks must
be in the idle state. Auto-refresh to auto-refresh interval is minimum tRC. Any command must not be
supplied to the device before tRC from the REFA command.
Auto-Refresh
CLK
/CS
NOP or DESELECT
/RAS
/CAS
/WE
CKE
minimum tRFC
A0-11
BA0,1
Auto Refresh on All Banks
Auto Refresh on All Banks
UTRON TECHNOLOGY INC.
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P90006

UTRON
Rev. 1.4
UT52L1664/0864/0464
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L).
Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode,
CKE is asynchronous and the only enabled input ,all other inputs including CLK are disabled and ignored,
so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable
CLK inputs, asserting DESEL or NOP command and then asserting CKE=H. After tRC from the 1st CLK
egde following CKE=H, all banks are in the idle state and a new command can be issued, but DESEL or
NOP commands must be asserted till then.
Self-Refresh
CLK
Stable CLK
NOP
/CS
/RAS
/CAS
/WE
CKE
new command
A0-11
X
BA0,1
00
Self Refresh Exit
Auto Refresh Entry
UTRON TECHNOLOGY INC.
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minimum tRFC
for recovery
P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
CLK SUSPEND
CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating
CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or
input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be
performed either when the banks are active or idle. A command at the suspended cycle is ignored.
ext.CLK
tIH
tIS
tIH
tIS
CKE
int.CLK
POWER DOWN by CKE
CLK
CKE
Command
Standby Powen Down
PRE
NOP
NOP
NOP
CKE
Command
Active Powen Down
ACT
NOP
NOP
NOP
DQ Suspend by CKE(CL=2)
CLK
CKE
Command
Write
DQ
D0
Read
D1
D2
D3
Q0
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Q1
Q2
Q3
P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
DQM CONTROL
DQM is a dual function signal defined as the data mask for writes and the output disable for reads. During
writes, DQM(U,L) masks input data word by word. DQM(U,L) to write mask latency is 0. During reads,
DQM(U,L) forces output to Hi-Z word by word. DQM(U,L) to output Hi-Z latency is 2.
DQM Function(CL=3)
CLK
Command
Read
Write
DQM
DQ
D0
D2
D3
Q0
Q1
Q3
disable by DQM(U,L)=H
masked by DQM(U,L)=H
UTRON TECHNOLOGY INC.
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P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
ABSOLUTE MAXIMUM RATINGS
Symbol
Vdd
VddQ
VI
VO
IO
Pd
Parameter
Supply Voltage
Supply Voltage for Output
Input Voltage
Output Voltage
Output Current
Power Dissipation
Topr
Operating Temperature
Tstg
Storage Temperature
Conditions
With respect to Vss
With respect to VssQ
With respect to Vss
With respect to VssQ
Ratings
-0.5-4.6
-0.5-4.6
-0.5-4.6
-0.5-4.6
50
1000
0-70
-20-80
-65-150
Ta=25℃
Commercial
Extended
Unit
V
V
V
V
mA
mW
℃
℃
℃
RECOMMENDED OPERATING CONDITIONS
Symbol
Vdd
Vss
VddQ
VssQ
1
VIH*
2
VIL*
Limits
Parameter
Supply Voltage
Supply Voltage
Supply Voltage for Output
Supply Voltage for Output
High-Level Input Voltage all inputs
Low-Level Input Voltage all inputs
Min.
Typ.
Max.
3.0
0
3.0
0
2.0
-0.3
3.3
0
3.3
0
-
3.6
3.6
0
VddQ+0.3
0.8
Unit
V
V
V
V
V
V
NOTES:
1. VIH(max)=5.5V for pulse width less than 10ns.
2. VIL(min)=-1.0V for pulse width less than 10ns.
CAPACITANCE
(Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V,unless otherwise noted)
Symbol
CI(A)
CI(C)
CI(K)
CI/O
Patameter
Input Capacitance,address pin
Input Capacitance,contorl pin
Input Capacitance, CLK pin
Input Capacitance, I/O pin
Test Condition Limits(min.)
@1MHz
1.4V bias
200mV swing
Vcc=3.3V
2.5
2.5
2.5
4.0
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Limits(max.)
-6,-7
-7.5,-8
3.8
5.0
3.8
5.0
3.5
4.0
6.5
6.5
Unit
pF
pF
pF
pF
P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
AVERAGE SUPPLY CURRENT from Vdd
(Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V,unless otherwise noted)
ITEM
Symbol
Operating current
Icc1
Test Conditions
Icc3NS
Burst current
Icc4
Unit
-7
-7.5
-8
X4
85
85
85
85
mA
X8
85
85
85
85
mA
X16
85
85
85
85
mA
X4/x8/x16
20
20
20
20
mA
X4/x8/x16
15
15
15
15
mA
X4/x8/x16
2
2
2
2
mA
X4/x8/x16
1
1
1
1
mA
CKE=/CS=VIHmin
tCLK=15ns(Note)
X4/x8/x16
30
30
30
30
mA
CKE=VIHmin
tCLK=VILmax(fixed)
X4/x8/x16
25
25
25
25
mA
X4
100
100
100
100
mA
X8
100
100
100
100
mA
X16
100
100
100
100
mA
tRC=min,tCLK=min,
BL=1,IOL=0mA
CKE=VILmax
Precharge Standby Icc2P
tCLK=15ns(Note)
current in Power
CKE=VILmax
down mode
Icc2PS
tCLK=VILmax(fixed)
Icc3N
Limits(max.)
-6
CKE=VIHmin
Precharge Standby Icc2N tCLK=15ns
current in NonPower down mode Icc2NS CKE=VIHmin
tCLK=VILmax(fixed)
Active Stnadby
current
Organization
All Bank Active
tCLK=min
BL=4,CL=3,IOL=0mA
Auto-refresh
current
Icc5
tRC=min,tCLK=min
X4/x8/x16
130
130
130
130
mA
Self-refresh current
Icc6
CKE<0.2V X4/x8/x16
6,7,7.5,8
1
1
1
1
mA
Limits
Min.
Max.
Unit
NOTE:
1. Icc(max)is specified at the output open condition.
2. Input signals are changed one time during 30ns.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V,unless otherwise noted)
Symbol
Parameter
Test Conditions
VOH(DC)
High-Level Output Voltage(DC)
IOH=-2mA
VOL(DC)
Low-Level Output Voltage(DC)
IOL=2mA
IOZ
Off-state Output Current
Q floatomg VO=0--VddQ
Ii
Input Current
VIH=0--VddQ+0.3V
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2.4
V
0.4
V
-5
5
µA
-5
5
µA
P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
AC TIMING REQUIREMENTS
(Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V,unless otherwise noted)
Input Pulse Levels:0.4V-2.4V
Input Timing Measurement Level:1.4V
Limits
Symbol
Parameter
-6
-7
-7.5
Unit
-8
Min. Max. Min. Max. Min. Max. Min. Max.
CL=2
10
10
10
10
ns
CL=3
6
7
7.5
8
ns
CLK High pulse width
2
2.5
2.5
3
ns
tCL
CLK Low pulse width
2
2.5
2.5
3
ns
tT
Transition time of CLK
1
tIS
Input Setup time (all inputs)
2
2.5
2.5
2.5
ns
tIH
Input Hold time (all inputs)
1
1
1
1
ns
tRC
Row Cycle time
60
63
67.5
70
ns
tRFC
Refersh Cycle time
60
70
75
80
ns
tRCD
Row to Column Delay
18
20
20
20
ns
tRAS
Row Active time
42
45
100K 48
tRP
Row Precharge time
18
20
20
20
ns
tWR
Write Recovery time
12
14
15
20
ns
tRRD
Act to Act Delay time
12
14
15
20
ns
tRSC
Mode Register Set Cycle time
12
14
15
20
ns
tREF
Refresh Interval time
tCLK
CLK cycle time
tCH
10
100K
1
45
64
CLK
1.4V
DQ
1.4V
10
100K
64
10
64
1
10
ns
100K
64
ns
ms
Any AC timing is referenced
to the input signal passing
throutg 1.4V
UTRON TECHNOLOGY INC.
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1
P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
SWITCHING CHARACTERISTICS
(Vdd=VddQ=3.3±0.3V,Vss=VssQ=0V,unless otherwise noted)
Limits
Parameter
Symbol
-6
-7
-7.5
Unit
-8
Note
Min. Max Min. Max Min. Max Min. Max.
tAC
tOH
Access time from CLK
Output Hold time from CLK
CL=2
6
6
6
6
ns
CL=3
5
5.4
5.4
6
ns
CL=2
3
3
3
3
ns
CL=3
2.5
2.7
3
3
ns
0
0
0
0
ns
Delay time, output low-impedance
from CLk
Delay time, output high-impedance
tOHZ
from CLK
tOLZ
2.5
5
2.7
5.4
3
5.4
3
6
*1
ns
NOTE:
1. If clock rising time is longer than 1ns,(tr/2-0.5ns) should be added to the parameter.
Output Load Condition
Vtt=+1.4 V
CLK
1.4V
50 Ω
Output
Z0=50Ω
1.4V
DQ
50PF
AC output load circuit
1.4V
CLK
tOLZ
DQ
1.4V
tRC
tOH
tOHZ
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P90006

UTRON
UT52L1664/0864/0464
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
Burst Write (single bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRC
/CS
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
tWR
tWR
/WE
CKE
DQM
A0-8
X
A10
X
X
A9,11
X
X
BA0,1
0
DQ
Y
0
D0
ACT#0
X
WRITE#0
0
D0
D0
0
D0
Y
0
D0
PRE#0
ACT#0
0
D0
WRITE#0
D0
D0
PRE#0
Italic parameter indicates minimum case
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P90006

UTRON
UT52L1664/0864/0464
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
Burst Write (multi bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRC
tRC
/CS
tRAS
tRRD
tRP
/RAS
tRCD
tRCD
tRCD
/CAS
tWR
tWR
/WE
CKE
DQM
A0-8
X
A10
X
X
X
X
A9,11
X
X
X
X
BA0,1
0
DQ
ACT#0
Y
X
0
1
D0
D0
WRITE#0
ACT#1
Y
D0
D0
X
1
0
D1
D1
PRE#0
D1
Y
0
0
D1
D0
ACT#0
WRITE#0
X
1
D0
D0
ACT#1
0
D0
PRE#0
WRITE A#1
(Auto-Precharge)
Italic parameter indicates minimum case
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P90006

UTRON
UT52L1664/0864/0464
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
Burst Read (single bank) @BL=4 CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRC
/CS
tRAS
tRP
tRAS
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
Y
X
A10
X
X
A9,11
X
X
BA0,1
0
0
0
D0
DQ
ACT#0
READ#0
D0
D0
PRE#0
0
Y
0
0
D0
D0
ACT#0
READ#0
D0
D0
D0
PRE#0
Italic parameter indicates minimum case
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P90006

UTRON
UT52L1664/0864/0464
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
Burst Read (multiple bank) @BL=4 CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRC
tRC
/CS
tRRD
tRAS
/RAS
tRCD
tRCD
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
Y
X
A10
X
X
X
X
A9,11
X
X
X
X
BA0,1
0
0
Y
1
1
Q0
DQ
ACT#0
READA#0
X
Q0
Q0
READA#1
Y
0
Q0
Q1
ACT#0
X
1
0
Q1
Q1
Q1
READ#0
Q0
ACT#1
0
Q0
Q0
Q0
PRE#0
ACT#1
Italic parameter indicates minimum case
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P90006

UTRON
UT52L1664/0864/0464
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
Write Interrupted by Write @BL=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
tRRD
/RAS
tRCD
/CAS
tWR
/WE
CKE
DQM
A0-8
X
A10
X
X
X
A9,11
X
X
X
BA0,1
0
DQ
ACT#0
Y
X
0
1
D0
D0
WRITE#0
ACT#1
Y
Y
0
D0
D0
Y
0
1
D0
D1
X
D1
WRITE#0
interrupt same bank
D1
D0
0
D0
D0
WRITE#0
interrupt other bank
1
D0
PRE#0
ACT#1
WRITE A#1
interrupt other bank
Italic parameter indicates minimum case
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P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
Read Interrupted by Read @BL=4,CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
tRRD
/RAS
tRCD
tRCD
/CAS
/WE
CKE
DQM
Y
X
A10
X
X
X
A9,11
X
X
X
BA0,1
0
0
X
Y
1
DQ
1
Q0
ACT#0
Y
X
A0-8
Q0
Y
0
1
Q0
Q1
Q1
ACT#1
Q1
Q1
READ#0
interrupt other bank
READ#1
interrupt other bank
READ#0
Q1
1
Q0
Q0
Q0
Q0
ACT#1
READ A#1
interrupt same bank
Italic parameter indicates minimum case
UTRON TECHNOLOGY INC.
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P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
Write Interrupted by Read, Read Interrupted by Write @BL=4,CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
tRRD
/RAS
tRCD
tRCD
/CAS
tWR
/WE
CKE
DQM
A0-8
X
X
A10
X
X
A9,11
X
X
BA0,1
0
1
DQ
Y
Y
Y
0
1
1
D0
ACT#0
ACT#1
D0
Q1
Q1
1
D1
D1
Write#1
READ#1
D1
D1
PRE#1
WRITE#0
Italic parameter indicates minimum case
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
43
P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
Write/Read Terminated by Precharge @BL=4,CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRC
/CS
tRP
tRAS
tRP
/RAS
tRCD
tRCD
/CAS
tWR
/WE
CKE
DQM
A0-8
X
Y
A10
X
X
X
A9,11
X
X
X
BA0,1
0
ACT#0
0
0
D0
DQ
X
WRITE#0
X
Y
0
0
0
D0
Q0
PRE#0
Terminate
ACT#0
READ#0
PRE#0
Terminate
0
Q0
ACT#0
Italic parameter indicates minimum case
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
44
P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
Write/Read Terminated by Burst Terminate @BL=4,CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
/RAS
tRCD
/CAS
tWR
/WE
CKE
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
Y
Y
Y
0
0
0
D0
DQ
ACT#0
WRITE#0
D0
Q1
TERM
Q1
TERM
D0
WRITE#0
0
D0
D0
D0
PRE#0
READ#0
Italic parameter indicates minimum case
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
45
P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
Single Write Burst Read @BL=4,CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
Y
Y
0
0
D0
DQ
ACT#0
WRITE#0
D0
D0
D0
D0
READ#0
Italic parameter indicates minimum case
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
46
P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
Power-Up Sequesce and Intialize
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
200uS
/CS
tRP
tRFC
tRFC
tRSC
/RAS
/CAS
/WE
CKE
DQM
A0-8
MA
X
A10
0
X
A9,11
0
X
BA0,1
0
0
MRS
ACT#0
DQ
NOP
Power On
PRE ALL
REFA
REFA
REFA
Minimum 8 REFA cycles
Italic parameter indicates minimum case
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
47
P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
Auto Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRFC
/CS
tRP
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
Y
0
DQ
D0
PRE ALL
PREA
ACT#0
D0
D0
D0
WRITE#0
Italic parameter indicates minimum case
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
48
P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
Self Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
tRFC
/CS
tRP
/RAS
/CAS
/WE
CKE
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
DQ
PRE ALL
Self Refresh Entry
Self Refresh Exit
ACT#0
All banks must be idle before REFS is issued
Italic parameter indicates minimum case
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
49
P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
CLK Suspension @BL=4,CL=2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
/RAS
tRCD
/CAS
/WE
CKE
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
Y
Y
0
0
D0
DQ
ACT#0
WRITE#0
D0
D0
internal
CLK suspended
D0
Q0
READ#0
Q0
Q0
Q0
internal
CLK suspended
Italic parameter indicates minimum case
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
50
P90006

UT52L1664/0864/0464
UTRON
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
Rev. 1.4
Power Down
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
/CS
/RAS
/CAS
/WE
Standby Power Down
Active Power Down
CKE
DQM
A0-8
X
A10
X
A9,11
X
BA0,1
0
DQ
PRE ALL
ACT#0
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
51
P90006

UTRON
Rev. 1.4
UT52L1664/0864/0464
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
PACKAGE OUTLINE DIMENSION
54 pin 400mil TSOP II Package Outline Dimension
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
52
P90006

UT52L1664/0864/0464
UTRON
Rev. 1.4
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
ORDERING INFORMATION
Commercial Temperature :
PART NO.
UT52L0464MC-6
UT52L0864MC-6
UT52L1664MC-6
UT52L0464MC-7
UT52L0864MC-7
UT52L1664MC-7
UT52L0464MC-7.5
UT52L0864MC-7.5
UT52L1664MC-7.5
UT52L0464MC-8
UT52L0864MC-8
UT52L1664MC-8
ACCESS TIME
PACKAGE
6ns
54 PIN TSOP II
7ns
54 PIN TSOP II
7.5ns
54 PIN TSOP II
8ns
54 PIN TSOP II
ACCESS TIME
PACKAGE
6ns
54 PIN TSOP II
7ns
54 PIN TSOP II
7.5ns
54 PIN TSOP II
8ns
54 PIN TSOP II
Extended Temperature :
PART NO.
UT52L0464MC-6E
UT52L0864MC-6E
UT52L1664MC-6E
UT52L0464MC-7E
UT52L0864MC-7E
UT52L1664MC-7E
UT52L0464MC-7.5E
UT52L0864MC-7.5E
UT52L1664MC-7.5E
UT52L0464MC-8E
UT52L0864MC-8E
UT52L1664MC-8E
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
53
P90006

UTRON
Rev. 1.4
UT52L1664/0864/0464
64M(X16-BITS / X8-BITS / X4-BITS)SDRAM
This Page Is Left Blank Intentionally.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
54
P90006