UTRON UT62L1024(I) 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 REVISION HISTORY REVISION Rev. 1.0 Rev. 1.1 DESCRIPTION Original. Add order information for lead free product UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 1 Date Mar. 27. 2003 May. 09. 2003 P80078 UTRON UT62L1024(I) 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 FEATURES GENERAL DESCRIPTION Fast access time : 55/70ns CMOS low power operation Operating current : 20/18/15mA (TYP.) Standby current : 20 uA(TYP.) L -version 2 uA(TYP.) LL-version Single 2.5V~3.6V power supply Operating temperature: Industrial : -40℃~85℃ All TTL compatible inputs and outputs Fully static operation Three state outputs Data retention voltage: 1.5V (min) Package : 32-pin 450mil SOP 32-pin 8mm x 20mm TSOP-Ⅰ 32-pin 8mm x 13.4mm STSOP 36-pin 6mm × 8mm TFBGA The UT62L1024(I) is a 1,048,576-bit low power CMOS static random access memory organized as 131,072 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology. The UT62L1024(I) is designed for very low power system applications. It is particularly well suited for battery back-up nonvolatile memory applications. It operates from a wide range of 2.5V~ 3.6V supply voltage. Easy memory expansion is provided by using two chip enable input, CE & CE2. And all inputs and three-state outputs are fully TTL compatible. FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 2048 x 512 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O Vcc Vss I/O1-I/O8 CE CE2 OE WE CONTROL CIRCUIT UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 2 P80078 UTRON UT62L1024(I) 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 PIN CONFIGURATION 1 32 Vcc 2 31 A15 A14 3 30 CE2 A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 A2 10 A1 11 UT62L1024(I) NC A16 24 OE 23 A10 22 CE A0 12 21 I/ O 8 I/ O 1 13 20 I/ O 7 I/ O 2 14 19 I/ O 6 I/ O 3 15 18 I/ O 5 Vss 16 17 I/ O 4 SOP A A0 A1 CE2 A3 A6 A8 B I/O 5 A2 WE A4 A7 I/O 1 C I/O 6 NC A5 D V ss V cc E V cc V ss F I/O 7 G I/O 8 H A9 1 I/O 2 NC NC CE A 16 A 15 I/O 4 A 10 A 11 A 12 A 13 A 14 4 5 6 OE 2 3 I/O 3 TFBGA A11 A9 A8 A13 WE CE2 A15 Vcc NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UT62L1024(I) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O8 I/O7 I/O6 I/O5 I/O4 Vss I/O3 I/O2 I/O1 A0 A1 A2 A3 TSOP-1/STSOP PIN DESCRIPTION SYMBOL A0 - A16 I/O1 - I/O8 CE ,CE2 DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Inputs WE OE VCC VSS NC Output Enable Input Power Supply Ground No Connection Write Enable Input UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 3 P80078 UTRON UT62L1024(I) 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 TRUTH TABLE MODE Standby Output Disable Read Write Note: CE2 X L H H H CE H X L L L OE X X H L X WE X X H H L I/O OPERATION SUPPLY CURRENT ISB,ISB1 ISB,ISB1 ICC,ICC1,ICC2 ICC,ICC1,ICC2 ICC,ICC1,ICC2 High - Z High - Z High - Z DOUT DIN H = VIH, L=VIL, X = Don't care. ABSOLUTE MAXIMUM RATINGS* PARAMETER Terminal Voltage with Respect to VSS Operating Temperature Industrial Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 secs) SYMBOL VTERM TA TSTG PD IOUT Tsolder RATING -0.5 to 4.6 -40 to 85 -65 to 150 1 50 260 UNIT V ℃ ℃ W mA ℃ *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = 2.5V~3.6V, TA = -40℃ to 85℃) PARAMETER Power Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage SYMBOL TEST CONDITION VCC ＊1 VIH ＊2 VIL ILI ILO VOH VOL MIN. TYP. MAX. UNIT 2.5 3.0 3.6 V 2.2 Vcc+0.3 V - 0.2 0.6 V -1 1 VSS ≦VIN ≦VCC µA -1 1 VSS ≦VI/O ≦VCC, Output Disabled µA V IOH= - 1mA (IOH= -0.5mA when Vcc<2.7V) 2.2 2.7 0.4 V IOL= 2.1mA Cycle time=Min.100% duty, ICC II/O =0mA Operating Current ICC1 ICC2 55 - 20 35 mA 70 - 18 30 mA - 4 5 mA - 8 10 mA - 0.3 20 2 0.5 80 10 mA µA µA CE =VIL and CE2 = VIH, 100%duty, II/O=0mA, CE ≦0.2V TCycle= 1µs and CE2≧Vcc-0.2V, other pins TCycle= at 0.2V or Vcc-0.2V 500ns Standby Current (TTL) ISB CE =VIH or CE2 = VIL Standby Current (CMOS) ISB1 CE =VCC-0.2V or CE2=0.2V, -L other pins at 0.2V or Vcc-0.2V -LL Notes: 1. Overshoot : Vcc+3.0v for pulse width less than 10ns. 2. Undershoot : Vss-3.0v for pulse width less than 10ns. 3. Overshoot and Undershoot are sampled, not 100% tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 4 P80078 UTRON UT62L1024(I) 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 CAPACITANCE (TA=25℃, f=1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 6 8 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS 0.1VCC to 0.9VCC 5ns 1.5V CL = 30pF+1TTL, IOH= -1mA, IOL= 2.1mA Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load AC ELECTRICAL CHARACTERISTICS (VCC = 2.5V~3.6V, TA = - 40℃ to 85℃) (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change SYMBOL tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH UT62L1024(I)-55 MIN. MAX. 55 55 55 30 10 5 20 20 10 - UT62L1024(I)-70 MIN. MAX. 70 70 70 35 10 5 25 25 10 - UNIT UT62L1024(I)-55 MIN. MAX. 55 50 50 0 45 0 25 0 5 20 UT62L1024(I)-70 MIN. MAX. 70 60 60 0 55 0 30 0 5 25 UNIT ns ns ns ns ns ns ns ns ns (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High Z SYMBOL tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* ns ns ns ns ns ns ns ns ns ns *These parameters are guaranteed by device characterization, but not production tested. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 5 P80078 UTRON UT62L1024(I) 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address t AA t OH Dout t OH Previous data valid Data Valid READ CYCLE 2 ( CE and CE2 and OE Controlled) (1,3,4,5) tRC Address t AA CE t ACE CE2 OE tCHZ tOE tC LZ t OHZ t OLZ Dout t OH High-Z Data Valid High-Z Notes : 1. WE is high for read cycle. 2.Device is continuously selected OE =low, CE =low, CE2=high. 3.Address must be valid prior to or coincident with CE =low, CE2=high; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL=5pF. Transition is measured±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 6 P80078 UTRON UT62L1024(I) 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 WRITE CYCLE 1 ( WE Controlled) (1,2,3,5,6) t WC Address tAW CE t CW CE2 t AS tWP t WR WE tWHZ Dout t OW High-Z (4) (4) t DW Din tDH Data Valid WRITE CYCLE 2 ( CE and CE2 Controlled) (1,2,5,6) t WC Address tAW CE tWR t AS tCW CE2 tWP WE tWHZ Dout High-Z (4) tDW tDH Din Data Valid Notes : 1. WE , CE must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE , high CE2, low WE . 3.During a WE controlled write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE low transition and CE2 high transition occurs simultaneously with or after WE low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 7 P80078 UTRON UT62L1024(I) 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 DATA RETENTION CHARACTERISTICS (TA = - 40℃ to 85℃) PARAMETER Vcc for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time SYMBOL VDR IDR tCDR TEST CONDITION CE ≧VCC-0.2V or CE2≦0.2V Vcc=1.5V -L CE ≧VCC-0.2V - LL or CE2≦0.2V See Data Retention Waveforms (below) tR MIN. 1.5 TYP. - MAX. 3.6 UNIT V - 10 80 µA - 1 6 µA 0 - - ns tRC* - - ns tRC* = Read Cycle Time DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) ( CE controlled) VDR ≧ 1.5V VCC Vcc(min.) Vcc(min.) tCDR CE VIH tR CE ≧ VCC-0.2V VIH Low Vcc Data Retention Waveform (2) (CE2 controlled) VDR ≧ 1.5V VCC CE2 VCC(min.) VCC(min.) tCDR tR VIL CE2 ≦ 0.2V UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 8 VIL P80078 UTRON UT62L1024(I) 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 PACKAGE OUTLINE DIMENSION 32 pin 450mil SOP Package Outline Dimension UNIT SYMBOL A A1 A2 b c D E E1 e L L1 S y Θ INCH(BASE) MM(REF) 0.118 (MAX) 0.004(MIN) 0.111(MAX) 0.016(TYP) 0.008(TYP) 0.817(MAX) 0.445 ±0.005 2.997 (MAX) 0.102(MIN) 2.82(MAX) 0.406(TYP) 0.203(TYP) 20.75(MAX) 11.303 ±0.127 14.097 ± 0.555 ±0.012 0.305 0.050(TYP) 1.270(TYP) 0.0347 ±0.008 0.881 ±0.203 0.055 ±0.008 1.397 ±0.203 0.026(MAX) 0.660 (MAX) 0.004(MAX) 0.101(MAX) o o o o 0 -10 0 -10 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 9 P80078 UTRON UT62L1024(I) 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 32 pin 8mm x 20mm TSOP-I Package Outline Dimension UNIT SYMBOL A A1 A2 b c D E e HD L L1 y Θ INCH(BASE) MM(REF) 0.047 (MAX) 0.004 ±0.002 0.039 ±0.002 0.008 + 0.002 - 0.001 0.005 (TYP) 0.724 ±0.004 0.315 ±0.004 0.020 (TYP) 0.787 ±0.008 0.0197 ±0.004 0.0315 ±0.004 0.003 (MAX) o o 0 ∼5 1.20 (MAX) 0.10 ±0.05 1.00 ±0.05 0.20 + 0.05 -0.03 0.127 (TYP) 18.40 ±0.10 8.00 ±0.10 0.50 (TYP) 20.00 ±0.20 0.50 ±0.10 0.08 ±0.10 0.076 (MAX) o o 0 ∼5 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 10 P80078 UTRON UT62L1024(I) 128K X 8 BIT LOW POWER CMOS SRAM Rev. 1.1 32 pin 8mm x 13.4mm STSOP Package Outline Dimension HD cL 12° (2x) 32 16 17 12° (2x) b E e 1 "A" Seating Plane D y 12° (2X) 16 17 0.254 A2 c A GAUGE PLANE A1 0 SEATING PLANE L 12° (2X) L1 "A" DATAIL VIEW 1 32 UNIT SYMBOL A A1 A2 b c D E e HD L L1 y Θ INCH(BASE) MM(REF) 0.049 (MAX) 1.25 (MAX) 0.005 ±0.002 0.130 ±0.05 0.039 ±0.002 1.00 ±0.05 0.008 ±0.01 0.20±0.025 0.005 (TYP) 0.127 (TYP) 0.465 ±0.004 11.80 ±0.10 0.315 ±0.004 8.00 ±0.10 0.020 (TYP) 0.50 (TYP) 0.528±0.008 13.40 ±0.20. 0.0197 ±0.004 0.50 ±0.10 0.0315 ±0.004 0.8 ±0.10 0.003 (MAX) 0.076 (MAX) o o o o 0 ∼5 0 ∼5 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 11 P80078 UTRON Rev. 1.1 UT62L1024(I) 128K X 8 BIT LOW POWER CMOS SRAM 36 pin 6mm×8mm TFBGA Package Outline Dimension UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 12 P80078 UTRON Rev. 1.1 UT62L1024(I) 128K X 8 BIT LOW POWER CMOS SRAM ORDERING INFORMATION INDUSTRIAL TEMPERATURE PART NO. ACCESS TIME (ns) UT62L1024SC-55LI 55 UT62L1024SC-55LLI 55 UT62L1024SC-70LI 70 UT62L1024SC-70LLI 70 UT62L1024LC-55LI 55 UT62L1024LC-55LLI 55 UT62L1024LC-70LI 70 UT62L1024LC-70LLI 70 UT62L1024LS-55LI 55 UT62L1024LS-55LLI 55 UT62L1024LS-70LI 70 UT62L1024LS-70LLI 70 UT62L1024BS-55LI 55 UT62L1024BS-55LLI 55 UT62L1024BS-70LI 70 UT62L1024BS-70LLI 70 STANDBY CURRENT (µA) TYP. 20 2 20 2 20 2 20 2 20 2 20 2 20 2 20 2 PACKAGE 32 PIN SOP 32 PIN SOP 32 PIN SOP 32 PIN SOP 32 PIN TSOP-I 32 PIN TSOP-I 32 PIN TSOP-I 32 PIN TSOP-I 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 36 PIN TFBGA 36 PIN TFBGA 36 PIN TFBGA 36 PIN TFBGA ORDERING INFORMATION (for lead free product) INDUSTRIAL TEMPERATURE PART NO. ACCESS TIME (ns) UT62L1024SCL-55LI 55 UT62L1024SCL-55LLI 55 UT62L1024SCL-70LI 70 UT62L1024SCL-70LLI 70 UT62L1024LCL-55LI 55 UT62L1024LCL-55LLI 55 UT62L1024LCL-70LI 70 UT62L1024LCL-70LLI 70 UT62L1024LSL-55LI 55 UT62L1024LSL-55LLI 55 UT62L1024LSL-70LI 70 UT62L1024LSL-70LLI 70 UT62L1024BSL-55LI 55 UT62L1024BSL-55LLI 55 UT62L1024BSL-70LI 70 UT62L1024BSL-70LLI 70 STANDBY CURRENT (µA) TYP. 20 2 20 2 20 2 20 2 20 2 20 2 20 2 20 2 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 13 PACKAGE 32 PIN SOP 32 PIN SOP 32 PIN SOP 32 PIN SOP 32 PIN TSOP-I 32 PIN TSOP-I 32 PIN TSOP-I 32 PIN TSOP-I 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 32 PIN STSOP 36 PIN TFBGA 36 PIN TFBGA 36 PIN TFBGA 36 PIN TFBGA P80078 UTRON Rev. 1.1 UT62L1024(I) 128K X 8 BIT LOW POWER CMOS SRAM This page is left blank intentionally. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 14 P80078