APPLICATION NOTE A V A I L A B L E AN61 X25170 16K 2K x 8 Bit SPI Serial E2PROM with Block Lock™ Protection FEATURES • 5MHz Clock Rate • SPI Modes (0,0 & 1,1) • 2K X 8 Bits —32 byte page mode • Low Power CMOS —<1µA standby current —<5mA active current • 2.5V To 5.5V Power Supply • Block Lock Protection —Protect 1/4, 1/2 or all of E2PROM array • Built-In Inadvertent Write Protection —Power-up/power-down protection circuitry —Write enable latch —Write protect pin • Self-Timed Write Cycle —5ms write cycle time (typical) • High Reliability —Endurance: 100,000 cycles —Data retention: 100 Years —ESD protection: 2000V on all pins • 8-Lead PDlP Package • 8-Lead SOIC Package • 14-Lead TSSOP Package DESCRIPTION The X25170 is a CMOS 16384-bit serial E2PROM, internally organized as 2K x 8. The X25170 features a Serial Peripheral Interface (SPI) and software protocol, allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. The X25170 also features two additional inputs that provide the end user with added flexibility. By asserting the HOLD input, the X25170 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. The WP input can be used as a hardwire input to the X25170 (disabling all write attempts to the status register), thus providing a mechanism for limiting end user capability of altering 0, 1/4, 1/2 or all of the memory. The X25170 utilizes Xicor’s proprietary Direct Write™ cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. BLOCK DIAGRAM Status Register Write Protect Logic X Decode Logic 2K Byte Array 16 SO SI SCK CS HOLD Command Decode and Control Logic 16 X 256 16 16 X 256 32 32 X 256 WP Write Control and Timing Logic 32 8 Y Decode Data Register Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc. Xicor, Inc. 2000 Patents Pending 9900-5004.9 5/26/00 EP Characteristics subject to change without notice. 1 of 15 X25170 PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS) It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. When CS is HIGH, the X25170 is deselected and the SO output pin is at high impedance; unless an internal write operation is underway, the X25170 will be in the standby power mode. CS LOW enables the X25170, placing it in the active power mode. Write Protect (WP) When WP is LOW and the nonvolatile bit WPEN is “1”, nonvolatile writes to the X25170 status register are disabled, but the part otherwise functions normally. When WP is held HIGH, all functions, including nonvolatile writes operate normally. WP going LOW while CS is still LOW will interrupt a write to the X25170 status register. If the internal write cycle has already been initiated, WP going LOW will have no effect on a write. The WP pin function is blocked when the WPEN bit in the status register is “0”. This allows the user to install the X25170 in a system with WP pin grounded and still be able to write to the status register. The WP pin functions will be enabled when the WPEN bit is set “1”. Pin Names Symbol Description CS Chip Select Input SO Serial Output SI Serial Input SCK Serial Clock Input WP Write Protect Input VSS Ground VCC Supply Voltage HOLD Hold Input NC No Connect PIN CONFIGURATION DIP/SOIC CS SO 1 2 WP VSS 3 4 X25170 8 7 6 5 VCC HOLD SCK SI TSSOP CS SO 1 2 NC 3 X25170 11 4 10 5 9 6 NC NC WP VSS 7 14 13 12 8 VCC HOLD NC NC NC SCK SI HOLD (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. Characteristics subject to change without notice. 2 of 15 X25170 PRINCIPLES OF OPERATION The X25170 is a 2K x 8 E2PROM designed to interface directly with the synchronous serial peripheral interface (SPI) of many popular microcontroller families. The X25170 contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising SCK. CS must be LOW and the HOLD and WP inputs must be HIGH during the entire operation. The WP input is “don’t care” if WPEN is set “0”. Table 1 contains a list of the instructions and their opcodes. All instructions, addresses and data are transferred MSB first. Data input is sampled on the first rising edge of SCK after CS goes LOW. SCK is static, allowing the user to stop the clock and then resume operations. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input to place the X25170 into a “PAUSE” condition. After releasing HOLD, the X25170 will resume operation from the point when HOLD was first asserted. Write Enable Latch The X25170 contains a “write enable” latch. This latch must be SET before a write operation will be completed internally. The WREN instruction will set the latch and the WRDI instruction will reset the latch. This latch is automatically reset upon a power-up condition and after the completion of a byte, page, or status register write cycle. Status Register The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is formatted as follows: 7 6 5 4 3 2 1 0 WPEN X X X BL1 BL0 WEL WIP WPEN, BP0 and BP1 are set by the WRSR instruction. WEL and WIP are read-only and automatically set by other operations. The Write-In-Process (WIP) bit indicates whether the X25170 is busy with a write operation. When set to a “1”, a write is in progress, when set to a “0”, no write is in progress. During a write, all other bits are set to “1”. The Write Enable Latch (WEL) bit indicates the status of the “write enable” latch. When set to a “1”, the latch is set, when set to a “0”, the latch is reset. The Block Protect (BP0 and BP1) bits are nonvolatile and allow the user to select one of four levels of protection. The X25170 is divided into four 4096-bit segments. One, two, or all four of the segments may be protected. That is, the user may read the segments but will be unable to alter (write) data within the selected segments. The partitioning is controlled as illustrated in the following table. Status Register Bits BP1 BP0 Array Addresses Protected 0 0 None 0 1 $0600–$07FF 1 0 $0400–$07FF 1 1 $0000–$07FF Table 1. Instruction Set Instruction Name Instruction Format* Operation WREN 0000 0110 Set the write enable latch (enable write operations) WRDI 0000 0100 Reset the write enable latch (disable write operations) RDSR 0000 0101 Read status register WRSR 0000 0001 Write status register READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address (1 to 32 Bytes) Notes: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first. Characteristics subject to change without notice. 3 of 15 X25170 Write-Protect Enable The Write-Protect-Enable (WPEN) bit is available for the X25170 as a nonvolatile enable bit for the WP pin. The Write Protect (WP) pin and the nonvolatile Write Protect Enable (WPEN) bit in the Status Register control the programmable hardware write protect feature. Hardware write protection is enabled when WP pin is LOW, and the WPEN bit is “1”. Hardware write protection is disabled when either the WP pin is HIGH or the WPEN bit is “0”. When the chip is hardware write protected, nonvolatile writes are disabled to the Status Register, including the Block Protect bits and the WPEN bit itself, as well as the block-protected sections in the memory array. Only the sections of the memory array that are not block-protected can be written. Note: Since the WPEN bit is write protected, it cannot be changed back to a “0”, as long as the WP pin is held LOW. WPEN WP WEL Protected Blocks Unprotected Blocks Status Register 0 X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 LOW 0 Protected Protected Protected 1 LOW 1 Protected Writable Protected X HIGH 0 Protected Protected Protected X HIGH 1 Protected Writable Writable Clock and Data Timing Data input on the SI line is latched on the rising edge of SCK. Data is output on the SO line by the falling edge of SCK. Read Sequence When reading from the E2PROM memory array, CS is first pulled LOW to select the device. The 8-bit READ instruction is transmitted to the X25170, followed by the 16-bit address of which the last 11 are used. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached ($07FF), the address counter rolls over to address $0000, allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS HIGH. Refer to the read E2PROM array operation sequence illustrated in Figure 1. To read the status register the CS line is first pulled LOW to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the status register are shifted out on the SO line. The read status register sequence is illustrated in Figure 2. Characteristics subject to change without notice. 4 of 15 X25170 Figure 1. Read E2PROM Array Operation Sequence CS 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 SCK Instruction 16 Bit Address SI 15 14 13 3 2 1 0 Data Out High Impedance 7 SO 6 5 4 3 2 1 0 MSB Figure 2. Read Status Register Operation Sequence CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCK Instruction SI Data Out High Impedance SO 7 6 5 4 3 2 1 0 MSB Write Sequence Prior to any attempt to write data into the X25170, the “write enable” latch must first be set by issuing the WREN instruction (See Figure 3). CS is first taken LOW, then the WREN instruction is clocked into the X25170. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. To write data to the E2PROM memory array, the user issues the WRITE instruction, followed by the address and then the data to be written. This is minimally a thirty-two clock operation. CS must go LOW and remain LOW for the duration of the operation. The host may continue to write up to 32 bytes of data to the X25170. The only restriction is the 32 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will “roll over” to the first address of the page and overwrite any data that may have been written. Characteristics subject to change without notice. 5 of 15 X25170 Figure 3. Write Enable Latch Sequence CS 0 1 2 3 4 5 6 7 SCK SI High Impedance SO For the write operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of data byte N is clocked in. If it is brought HIGH at any other time the write operation will not be completed. Refer to Figures 4 and 5 below for a detailed illustration of the write sequences and time frames in which CS going HIGH are valid. Figure 4. Byte Write Operation Sequence CS 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 16 Bit Address 15 14 13 SI 3 2 Data Byte 1 0 7 6 5 4 3 2 1 0 High Impedance SO To write to the status register, the WRSR instruction is followed by the data to be written. Data bits 0, 1, 4, 5 and 6 must be “0”. This sequence is shown in Figure 6. While the write is in progress following a status register or E2PROM write sequence, the status register may be read to check the WIP bit. During this time the WIP bit will be HIGH. Hold Operation The HOLD input should be HIGH (at VIH) under normal operation. If a data transfer is to be interrupted HOLD can be pulled LOW to suspend the transfer until it can be resumed. The only restriction is the SCK input must be LOW when HOLD is first pulled LOW, and SCK must also be LOW when HOLD is released. The HOLD input may be tied HIGH either directly to VCC or tied to VCC through a resistor. Characteristics subject to change without notice. 6 of 15 X25170 Figure 5. Page Write Operation Sequence CS 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 16 Bit Address 15 14 13 SI 3 Data Byte 1 2 1 7 0 6 5 4 3 2 1 0 CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 SI 7 6 5 4 3 2 Data Byte 3 1 0 7 6 5 Data Byte N 4 3 2 1 0 6 7 8 9 10 6 5 4 3 2 1 0 Figure 6. Write Status Register Operation Sequence CS 0 1 2 3 4 5 11 12 13 14 15 SCK Instruction SI Data Byte 7 6 5 4 3 2 1 0 High Impedance SO Operational Notes The X25170 powers-up in the following state: – The device is in the low power standby state. – A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. – SO pin is high impedance. – The “write enable” latch is reset. Data Protection The following circuitry has been included to prevent inadvertent writes: – The “write enable” latch is reset upon power-up. – A WREN instruction must be issued to set the “write enable” latch. – CS must come HIGH at the proper clock count in order to start a write cycle. Characteristics subject to change without notice. 7 of 15 X25170 ABSOLUTE MAXIMUM RATINGS COMMENT Temperature under bias ........................–65 to +135°C Storage temperature .............................–65 to +150°C Voltage on any pin with respect to VSS ....... –1V to +7V D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds).........300°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Supply Voltage Limits Commercial 0°C +70°C X25170 5V ±10% X25170-2.5 2.5V to 5.5V Industrial –40°C +85°C Military –55°C +125°C D.C. OPERATING CHARACTERISTICS(Over the recommended operating conditions unless otherwise specified.) Limits Symbol ICC Parameter Min. VCC supply current (active) Max. Units 5 mA Test Conditions SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO = Open, CS = VSS SO = Open, CS = VSS SO = Open, CS = VSS ISB VCC supply current (standby) 1 µA CS = VCC, VIN = VSS or VCC ILI Input leakage current 10 µA VIN = VSS to VCC ILO Output leakage current 10 µA VOUT = VSS to VCC VCC x 0.3 V VCC x 0.7 VCC + 0.5 V (1) Input LOW voltage (1) VIH Input HIGH voltage VOL1 Output LOW voltage VOH1 Output HIGH voltage VOL2 Output LOW voltage VOH2 Output HIGH voltage VIL –1 0.4 VCC–0.8 0.4 VCC–0.3 V VCC = 5V, IOL = 3mA V VCC = 5V, IOH = -1.6mA V VCC = 2.70V, IOL = 1.5mA V VCC = 2.70V, IOH = -0.4mA POWER-UP TIMING Symbol Parameter Min. Max. Units TPUR(3) Power-up to read operation 1 ms (3) Power-up to write operation 1 ms TPUW Characteristics subject to change without notice. 8 of 15 X25170 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol Parameter (2) COUT (2) CIN Max. Units Test Conditions Output capacitance (SO) 8 pF VOUT = 0V Input capacitance (SCK, SI, CS, WP, HOLD) 6 pF VIN = 0V Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUIT 5V 3V 1.44KΩ 1.64KΩ Output 1.95KΩ A.C. CONDITIONS OF TEST 100pF Output 4.63KΩ Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels VCC X 0.5 100pF A.C. CHARACTERISTICS (Over recommended operationg conditions, unless otherwise specified.) Data Input Timing Symbol Parameter Min. Max. Units 0 5 MHz fSCK Clock frequency tCYC Cycle time 200 ns tLEAD CS lead time 100 ns tLAG CS lag time 100 ns tWH Clock HIGH time 80 ns tWL Clock LOW time 80 ns tSU Data setup time 20 ns tH Data hold time 20 ns (4) Data in rise time 2 µs (4) tFI Data in fall time 2 µs tHD HOLD setup time 40 ns tCD HOLD hold time 40 ns tCS CS deselect time 100 tWC(5) Write cycle time tRI ns 10 ms Characteristics subject to change without notice. 9 of 15 X25170 Data Output Timing Symbol Parameter Min. Units fSCK Clock frequency 5 MHz tDIS Output disable time 100 ns Output valid from clock LOW 80 ns tV tHO 0 Max. Output hold time 0 ns (4) Output rise time 50 ns (4) Output fall time 50 ns (4) HOLD HIGH to output in low Z 50 ns (4) HOLD LOW to output in high Z 50 ns tRO tFO tLZ tHZ Notes: (4) This parameter is periodically sampled and not 100% tested. (5) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle Serial Output Timing CS tWH tCYC tLAG SCK tV SO SI tWL tHO MSB Out tDIS MSB–1 Out LSB Out ADDR LSB IN Serial Input Timing tCS CS tLEAD tLAG SCK tSU SI tH MSB IN tRI tFI LSB IN High Impedance SO Characteristics subject to change without notice. 10 of 15 X25170 Hold Timing CS tHD tCD tCD tHD SCK tHZ tLZ SO SI HOLD SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance Characteristics subject to change without notice. 11 of 15 X25170 PACKAGING INFORMATION 8-Lead Plastic Dual In-Line Package Type P 0.430 (10.92) 0.360 (9.14) 0.260 (6.60) 0.240 (6.10) Pin 1 Index Pin 1 0.300 (7.62) Ref. Half Shoulder Width On All End Pins Optional 0.145 (3.68) 0.128 (3.25) Seating Plane 0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) .073 (1.84) Max. Typ. 0.010 (0.25) 0.060 (1.52) 0.020 (0.51) 0.020 (0.51) 0.016 (0.41) 0.325 (8.25) 0.300 (7.62) 0° 15° NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH Characteristics subject to change without notice. 12 of 15 X25170 PACKAGING INFORMATION 8-Lead Plastic Small Outline Gull Wing Package Type S 0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25) 0.050 (1.27) 0.010 (0.25) X 45° 0.020 (0.50) 0.050"Typical 0.050" Typical 0° - 8° 0.0075 (0.19) 0.010 (0.25) 0.250" 0.016 (0.410) 0.037 (0.937) 0.030" Typical 8 Places FOOTPRINT NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) Characteristics subject to change without notice. 13 of 15 X25170 PACKAGING INFORMATION 14-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .193 (4.9) .200 (5.1) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15) .010 (.25) Gage Plane 0° - 8° Seating Plane .019 (.50) .029 (.75) Detail A (20X) .031 (.80) .041 (1.05) See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) Characteristics subject to change without notice. 14 of 15 X25170 Ordering Information X25170 P T -V VCC Limits Blank = 5V ±10% 2.5 = 2.5V to 5.5V Device Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C Package S8 = 8-Lead SOIC Part Mark Convention X25170 X Blank = 8-Lead SOIC X Blank = 5V ±10%, 0°C to +70°C I = 5V ±10%, –40°C to +85°C AE = 2.5V to 5.5V, 0°C to +70°C AF = 2.5V to 5.5V, –40°C to +85°C LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Characteristics subject to change without notice. 15 of 15