AMD 29K Family Technical Bulletin Arbiter Solution for Shared-Bus Systems Using the Am29030 or Am29035 EPD Systems Engineering Microprocessor September 2, 1993 Assistance is available in the U.S. from 9:00 A.M. to 6:00 P.M. central time, Monday through Friday (except major holidays). In Europe assistance is available during U.K. business hours. Contact us at one of the following numbers: Purpose The Revision D Am29030 and Am29035 ––– microprocessors inappropriately assert the REQ –––– signal after BGRT is deasserted. In doing so, they create the potential for a bus collision in shared-bus systems. This bulletin includes the PAL equations for a state machine used in an EB29030 board to prevent bus collisions. These equations may be revised to suit a particular arbiter design. To reach the U.S. From U.S. Call 1-800-2929-AMD U.K. 0-800-89-1455 Affected Parts Japan 0031-11-1163 The information in this bulletin affects the following parts: Any other location +1-512-462-4118✝ Device Revision Am29030 microprocessor Am29035 microprocessor B, D B, D ✝ Toll applies. To reach the U.K. If You Need Assistance Product support for the 29K Family processors is available from our Embedded Processor Division (EPD) Technical Support Hotlines located in the U.S. and in the U.K. From U.K. Call (0)256-811101 France 0590-8621 Germany 0130-813875 Italy 1678-77224 Any other location +44-(0)256-811101✝ ✝ Toll applies. PID No. 18012 1 of 6 Example PAL Equations for the EB29030 Board Arbiter (in PLPL) "DEFINITIONS" "030 = Am29030 or Am29035 microprocessor" "AT = PC AT" "EB29030 = Am29030 Execution Board" "NOTE" "These PAL equations were designed for a state machine used in an EB29030" "board. These equations may be revised to suit a particular arbiter" "design." "U17 performs arbitration of 030 and AT access requests to EB29030 memory," "as well as freeing memory for refresh when posted by the AT." "Rev 11 removes *BREQ from the arbitration, using *REQ and *BGRT only." "Rev 12 implements pseudo-arbitration. It relies on the 030 to relinquish" "the bus by deasserting *REQ. This is the only arbitration scheme for" "Rev D in the EB29030 board." DEVICE Arbitrat (p22v10) PIN "The PAL pin names and architectural features follow." "Input pin definitions" MEMCLK /ATACCPLT /ATACRDY /BREQ /ATACREQ /REFREQ /REFECPLT /REFOCPLT /RESET /CASODD /CASEVEN /REQ EXREFCPLT /ERLYA = = = = = = = = = = = = = = 1 (Clock) 2 (Input Combinatorial) 3 (Input Combinatorial) 4 (Input Combinatorial) 5 (Input Combinatorial) 6 (Input Combinatorial) 7 (Input Combinatorial) 8 (Input Combinatorial) 9 (Input Combinatorial) 10 (Input Combinatorial) 11 (Input Combinatorial) 13 (Input Combinatorial) 14 (Input Combinatorial) 23 (Input Combinatorial) "AT access complete" "AT access ready" "030 bus request" "AT access request" "AT refresh request" "Even bank refresh complete" "Odd bank refresh complete" "Hardware reset" "Odd bank access complete" "Even bank access complete" "030 request" "EB29030 board refresh complete" "030 early address mode" PID No. 18012 2 of 6 "Output pin definitions" /state[4] /state[5] /state[0] /state[1] /state[2] /state[3] /state[7] /state[6] = = = = = = = = 22 21 20 19 18 17 16 15 (Output (Output (Output (Output (Output (Output (Output (Output Registered Registered Registered Registered Registered Registered Registered Registered Active_low) Active_low) Active_low) Active_low) Active_low) Active_low) Active_low) Active_low); "SV4 and "SV5 and "SV0" "SV1" "SV2" "SV3" "SV7 and "SV6 and ATACGRNT" ATACACK" Begin "The logic definition and operation of the state machine is" "contained within this Begin-End construct." BGRT" REFACT" Enable(/state[7]); Enable(/state[6]); Enable(/state[5]); Enable(/state[4]); Enable(/state[3]); Enable(/state[2]); Enable(/state[1]); Enable(/state[0]); If (RESET) then Begin "BGRT = 0" /state [7:0] = 126; End; Else Case (/state [7:0]) Begin 126 ) Begin "BGRT = 0" "Let 030 have the bus upon reset or if no refresh" "nor AT Access Request is outstanding." If (REFREQ * /ERLYA) then /state [7:0] = 127; "Refresh request arrives." Else If (/REFREQ * ATACREQ * /ERLYA) then /state [7:0] = 124; "AT host access request arrives." Else /state [7:0] = 126; "Stay 126 if there is no request." End; PID No. 18012 3 of 6 127 ) Begin "BGRT = 0" "Synchronize a refresh request from the AT with" "arbitration logic in this device." If (/REFREQ) then /state [7:0] = 126; "REFREQ set-up time missed this cycle." Else If (/REQ) then /state [7:0] = 255; "Move to 255 when *REQ deasserts." Else /state [7:0] = 127; "Wait until 030 relinquishes bus." End; 255 ) Begin /state [7:0] = 243; End; " *BGRT is deasserted in this cycle." 243 ) Begin If (/REQ) then /state [7:0] = 242; Else /state [7:0] = 243; End; 242 ) Begin "Work-around for 030 bug found 8-25-91 where 030" "asserts *REQ even after *REQ deassert from *BGRT" "deassertion." If (REQ) then /state [7:0] = 243; Else /state [7:0] = 191; End; 191 ) Begin "REFACT = 0" "Refresh Active is now asserted indicating that a" "refresh can begin by each bank ras/cas/refresh PAL." "This is the holding state which we remain in until" "both halves have completed their respective refresh" "cycle." If (/REFECPLT + /REFOCPLT + /EXREFCPLT) then /state [7:0] = 191; If (REFECPLT * REFOCPLT * EXREFCPLT) then /state [7:0] = 126; End; PID No. 18012 4 of 6 124 ) Begin "BGRT = 0" "Synchronize an AT access request with the arbitration" "state machine." If (/ATACREQ) then /state [7:0] = 126; "Set-up time was satisfied." Else If (/REQ) then /state [7:0] = 252; "Move to 252 when *REQ deasserts." Else /state [7:0] = 124; "Wait until 030 relinquishes bus." End; 252 ) Begin /state [7:0] = 246; End; " *BGRT is deasserted here." 246 ) Begin If (/REQ) then /state [7:0] = 240; Else /state [7:0] = 246; End; 240 ) Begin "Work-around for 030 bug found 8-25-91 where 030" "asserts *REQ even after *BGRT is deasserted." If (REQ) then /state [7:0] = 246; Else /state [7:0] = 220; End; 220 ) Begin "ATACACK = 0" "AT Access Acknowledge is now asserted indicating that" "the AT can have the bus. We wait here until the AT" "is ready to proceed with its access." "Synchronization of its ready status is also performed" "in this and the next adjacent state." If (/ATACRDY) then /state [7:0] = 220; Else /state [7:0] = 212; End; PID No. 18012 5 of 6 212 ) Begin "ATACACK = 0" If (/ATACRDY) then /state [7:0] = 220; Else /state [7:0] = 228; End; 228 ) Begin "ATACGRNT = 0" "This arbitration logic now informs the" "simple/page-mode PAL to perform a simple access to" "the appropriate bank while waiting for the access to" "be completed." If (/CASODD * /CASEVEN) then /state [7:0] = 228; If (CASODD + CASEVEN) then /state [7:0] = 245; End; 245 ) Begin "The AT arbitration logic will inform this logic that" "its bus cycle is complete by asserting AT Access" "Complete, but synchronization is required between it" "and this PAL, i.e., different clocks." If (/ATACCPLT) then /state [7:0] = 245; Else /state [7:0] = 253; End; 253 ) Begin If (/ATACCPLT) then /state [7:0] = 245; Else /state [7:0] = 126; End; End; End. PID No. 18012 6 of 6