ETC AM29030

PRELIMINARY
Am29030 and Am29035
RISC Microprocessors with 8-Kbyte/4-Kbyte Instruction Cache
Advanced
Micro
Devices
Am29030 MICROPROCESSOR DISTINCTIVE CHARACTERISTICS
Full 32-bit architecture
8-, 16-, or 32-bit ROM interface
26 million instructions per second (MIPS)
sustained at 33 MHz
64-entry Memory Management Unit on-chip
8-Kbyte, two-way set-associative instruction
cache
On-chip timer facility
Fully pipelined
192 general-purpose registers
33- and 25-MHz operating frequencies
Three-address instruction architecture
Scalable Clocking technology
Master/slave chip/output checking
Programmable 16- or 32-bit data bus width
CMOS technology/TTL-compatible
Software compatible with Am29005 and
Am29000 microprocessors
4-Gbyte virtual address space with demand
paging
Advanced debugging support
IEEE Std 1149.1-1990 (JTAG) compliant
Standard Test Access Port and Boundary
Scan Architecture implementation
Streamlined system interface for simplified,
high-frequency operation
Burst-mode and page-mode access support
Am29035 MICROPROCESSOR DISTINCTIVE CHARACTERISTICS
The Am29035 microprocessor is similar to the Am29030 microprocessor except for the following differences:
4-Kbyte, direct-mapped instruction cache
12 million instructions per second (MIPS)
sustained at 16 MHz
16-MHz operating frequency
SIMPLIFIED BLOCK DIAGRAM
Address
Am29030 and Am29035
RISC Microprocessors
with 8Kbyte/4Kbyte
Instruction Cache
Instruction/Data
32 or 16
32
32 or 16
8, 16, or 32
Address
Instruction/
Data
ROM
Address
Instruction/
Data
RAM
Instruction/Data
32 or 16
Instruction/Data
Publication# 18150 Rev. A Amendment /0
Issue Date: August 1993. WWW: 5/4/95
AMD
ADVANCE INFORMATION
TABLE OF CONTENTS
DISTINCTIVE CHARACTERISTICS
1
Am29030 MICROPROCESSOR
1
Am29035 MICROPROCESSOR
1
SIMPLIFIED BLOCK DIAGRAM
1
GENERAL DESCRIPTION
3
29K FAMILY DEVELOPMENT SUPPORT PRODUCTS
3
RELATED AMD PRODUCTS
3
THIRD-PARTY DEVELOPMENT SUPPORT PRODUCTS
3
CONNECTION DIAGRAM
4
145-LEAD PGA PACKAGE
PGA Pin Designations by Pin Number
PGA Pin Designations by Pin Name
4
5
6
144-LEAD CERQUAD PACKAGE
Cerquad Pin Designations by Pin Number
Cerquad Pin Designations by Pin Name
7
8
9
LOGIC SYMBOL
10
ORDERING INFORMATION
11
ABSOLUTE MAXIMUM RATINGS
12
OPERATING RANGES
12
DC CHARACTERISTICS over COMMERCIAL operating ranges
12
CAPACITANCE
12
SWITCHING CHARACTERISTICS over COMMERCIAL operating range
13
PGA PACKAGE
13
CERQUAD PACKAGE
14
SWITCHING WAVEFORMS
15
CAPACITIVE OUTPUT DELAYS
16
SWITCHING TEST CIRCUIT
16
THERMAL CHARACTERISTICS
17
PHYSICAL DIMENSIONS
18
2
GQD 144—Cerquad Trimmed and Formed
18
CGY 145—Pin Grid Array—**Not currently available in this Acrobat file**
19
Am29030 and Am29035 Microprocessors
PRELIMINARY
AMD
GENERAL DESCRIPTION
The Am29030 and Am29035 RISC microprocessors
are high-performance, general-purpose, 32-bit microprocessors implemented in CMOS technology. Through
high circuit densities and a high degree of on-chip
integration, the Am29030 and Am29035 microprocessors are capable of operating at high internal frequencies while providing the designer with a simple streamlined external interface.
The Am29030 and Am29035 microprocessors were
designed to meet the common requirements of
embedded applications such as laser beam printers,
graphics processors, X terminals and servers, Application Program Interface (API) accelerators, and scanners. The Am29030 and Am29035 microprocessors are
well suited for these applications since they provide high
performance at low cost, and offer the designer complete design flexibility. Coupled with hardware and software development tools from AMD and AMD’s
Fusion29K partners, no design is ever far from the
marketplace.
The Am29030 microprocessor is available in a 145-lead
pin-grid-array (PGA) package and a 144-pin cerquad
package. The PGA has 111 signal pins, 26 power and
ground pins, 7 reserved pins, and 1 alignment/ground
pin. The cerquad has 111 signal pins, 30 power and
ground pins, and 3 reserved pins.
The Am29035 microprocessor is available in a 144-pin
cerquad package.
29K Family Development Support Products
Contact your local AMD representative for information on the complete set of development support tools.
Software development products on several hosts:
Optimizing compilers for common high-level languages
Assembler and utility packages
Source- and assembly-level software debuggers
Target-resident development monitors
Simulators
EZ-030, an Am29030 microprocessor-based evaluation board kit
RELATED AMD PRODUCTS
29K Family Devices
Device
Description
Am29000
Streamlined Instruction Microprocessor
Am29005
Low-cost Streamlined Instruction Microprocessor
Am29050
Streamlined Instruction Microprocessor with On-chip Floating Point
Am29200
RISC Microcontroller
Am29205
Low-cost RISC Microcontroller
Third-Party Development Support Products
The Fusion29K Program of Partnerships for Application Solutions provides the user with a vast array of products
designed to meet critical time-to-market needs.
Products and solutions available through AMD’s Fusion29K partners include:
Silicon products
Multiuser, kernel, and real-time operating systems
Software generation and debug tools
Graphics solutions
Hardware development tools
Networking and communications solutions
Board level products
Manufacturing support
Laser printer solutions
Custom support
Am29030 and Am29035 Microprocessors
3
PRELIMINARY
AMD
CONNECTION DIAGRAM
145-Lead PGA
Bottom View
A B C D E F G H J K L M N P Q
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin Number E-4 is defined for emulator access and is not a physical pin on the package (see the
Am29030 and Am29035 Microprocessors User’s Manual, order #15723, Signal Description section).
Note: Pinout observed from pin side of package (pins facing viewer).
4
Am29030 and Am29035 Microprocessors
PRELIMINARY
AMD
PGA PIN DESIGNATIONS
(Sorted by Pin Number)
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
A–1
ID4
C–8
GND
H–14
MEMCLK
N–12
Vcc
A–2
ID0
C–9
Vcc
H–15
DIV2
N–13
A1
A–3
TRST
C–10
GND
J–1
ID21
N–14
ERLYA
A–4
TDI
C–11
Vcc
J–2
ID22
N–15
ERR
A–5
TCK
C–12
STAT1
J–3
GND
P–1
ID31
A–6
TEST
C–13
WBC
J–13
INCLK
P–2
A30
A–7
I/D
C–14
HIT
J–14
PWRCLK
P–3
A27
A–8
IO/MEM
C–15
INTR0
J–15
BREQ
P–4
A24
A–9
BWE0
D–1
ID12
K–1
ID23
P–5
A22
A–10
BWE2
D–2
ID11
K–2
ID24
P–6
A20
A–11
SUP/US
D–3
ID9
K–3
Vcc
P–7
A18
A–12
OPT0
D–4
GND
K–13
GND
P–8
A15
A–13
OPT2
D–13
DI
K–14
REQ
P–9
A13
A–14
MPGM1
D–14
INTR1
K–15
BURST
P–10
A10
A–15
STAT2
D–15
INTR2
L–1
ID25
P–11
A8
B–1
ID7
E–1
ID14
L–2
ID26
P–12
A6
B–2
ID6
E–2
ID13
L–3
Vcc
P–13
A4
B–3
ID3
E–3
GND
L–13
Vcc
P–14
A2
B–4
ID1
E–13
GND
L–14
BGRT
P–15
A0
B–5
TDO
E–14
INTR3
L–15
PGMODE
Q–1
A31
B–6
TMS
E–15
TRAP1
M–1
ID27
Q–2
A29
B–7
R/W
F–1
ID16
M–2
ID28
Q–3
A25
B–8
WARN
F–2
ID15
M–3
NC
Q–4
A23
B–9
BWE1
F–3
NC
M–13
GND
Q–5
A21
B–10
BWE3
F–13
Vcc
M–14
RDN
Q–6
A19
B–11
LOCK
F–14
RESET
M–15
RDY
Q–7
A17
B–12
OPT1
F–15
TRAP0
N–1
ID29
Q–8
A16
B–13
MPGM0
G–1
ID18
N–2
ID30
Q–9
A14
B–14
STAT0
G–2
ID17
N–3
NC
Q–10
A12
B–15
MSERR
G–3
Vcc
N–4
A28
Q–11
A11
C–1
ID10
G–13
Vcc
N–5
A26
Q–12
A9
C–2
ID8
G–14
CNTL0
N–6
GND
Q–13
A7
C–3
NC*
G–15
CNTL1
N–7
Vcc
Q–14
A5
C–4
ID5
H–1
ID20
N–8
GND
Q–15
A3
C–5
ID2
H–2
ID19
N–9
GND
C–6
Vcc
H–3
GND
N–10
GND
C–7
GND
H–13
GND
N–11
Vcc
Notes:
*1. NC = No connection internally.
2. Pin Number D–4 is the alignment/ground pin and must be electrically connected to ground.
3. Pin Number E–4 is defined for emulator access and is not a physical pin on the package (see Am29030 and Am29035
Microprocessors User’s Manual, Signal Description section).
Am29030 and Am29035 Microprocessors
5
PRELIMINARY
AMD
PGA PIN DESIGNATION
(Sorted by Pin Name)
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
P–15
A0
B–10
BWE3
F–1
ID16
C–12
STAT1
N–13
A1
G–14
CNTL0
G–2
ID17
A–15
STAT2
P–14
A2
G–15
CNTL1
G–1
ID18
A–11
SUP/US
Q–15
A3
H–15
DIV2
H–2
ID19
A–5
TCK
P–13
A4
N–14
ERLYA
H–1
ID20
A–4
TDI
Q–14
A5
N–15
ERR
J–1
ID21
B–5
TDO
P–12
A6
C–7
GND
J–2
ID22
A–6
TEST
Q–13
A7
C–8
GND
K–1
ID23
B–6
TMS
P–11
A8
C–10
GND
K–2
ID24
F–15
TRAP0
Q–12
A9
D–4
GND
L–1
ID25
E–15
TRAP1
P–10
A10
E–3
GND
L–2
ID26
A–3
TRST
Q–11
A11
E–13
GND
M–1
ID27
C–6
Vcc
Q–10
A12
H–3
GND
M–2
ID28
C–9
Vcc
P–9
A13
H–13
GND
N–1
ID29
C–11
Vcc
Q–9
A14
J–3
GND
N–2
ID30
F–13
Vcc
P–8
A15
K–13
GND
P–1
ID31
G–3
Vcc
Q–8
A16
M–13
GND
J–13
INCLK
G–13
Vcc
Q–7
A17
N–6
GND
C–15
INTR0
K–3
Vcc
P–7
A18
N–8
GND
D–14
INTR1
L–3
Vcc
Q–6
A19
N–9
GND
D–15
INTR2
L–13
Vcc
P–6
A20
N–10
GND
E–14
INTR3
N–7
Vcc
Q–5
A21
A–7
I/D
A–8
IO/MEM
N–11
Vcc
P–5
A22
A–2
ID0
B–11
LOCK
N–12
Vcc
Q–4
A23
B–4
ID1
H–14
MEMCLK
B–8
WARN
P–4
A24
C–5
ID2
B–13
MPGM0
Q–3
A25
B–3
ID3
A–14
MPGM1
N–5
A26
A–1
ID4
B–15
MSERR
P–3
A27
C–4
ID5
A–12
OPT0
N–4
A28
B–2
ID6
B–12
OPT1
Q–2
A29
B–1
ID7
A–13
OPT2
P–2
A30
C–2
ID8
L–15
PGMODE
Q–1
A31
D–3
ID9
J–14
PWRCLK
L–14
BGRT
C–1
ID10
M–14
RDN
J–15
BREQ
D–2
ID11
M–15
RDY
K–15
BURST
D–1
ID12
F–14
RESET
A–9
BWE0
E–2
ID13
K–14
REQ
D–13
DI
B–9
A10
BWE1
BWE2
E–1
F–2
ID14
ID15
B–7
B–14
R/W
STAT0
C–14
C–13
HIT
WBC
RESERVED*
Notes:
*1. These following signals are reserved for future processor implementations. To maintain compatibility with future processor
implementations, these pins should be connected to VCC by individual pull-up resistors.
2. Pin Number D–4 is the alignment/ground pin and must be electrically connected to ground.
3. Pin Number E–4 is defined for emulator access and is not a physical pin on the package (see Am29030 andAm29035 Microprocessors User’s Manual, Signal Description section).
6
Am29030 and Am29035 Microprocessors
PRELIMINARY
AMD
CONNECTION DIAGRAM
144-Lead Cerquad
Top View
Pin 144
Pin 109
Pin 108
Pin 1
Pin 36
Pin 73
Pin 37
Pin 72
Am29030 and Am29035 Microprocessors
7
PRELIMINARY
AMD
CERQUAD PIN DESIGNATIONS
(Sorted by Pin Number)
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
VCC
37
VCC
73
VCC
109
A1
2
GND
38
GND
74
GND
110
A0
3
MSERR
39
ID5
75
A29
111
ERLYA
4
STAT2
40
ID6
76
A28
112
ERR
5
STAT1
41
ID7
77
A27
113
RDN
6
STAT0
42
ID8
78
A26
114
RDY
7
MPGM1
43
ID9
79
A25
115
BGRT
8
MPGM0
44
ID10
80
A24
116
GND
9
OPT2
45
ID11
81
A23
117
VCC
10
OPT1
46
ID12
82
A22
118
PGMODE
11
OPT0
47
ID13
83
A21
119
BURST
12
LOCK
48
ID14
84
A20
120
REQ
13
SUP/US
49
ID15
85
A19
121
BREQ
14
BWE3
50
VCC
86
A18
122
GND
15
BWE2
51
GND
87
A17
123
INCLK
16
BWE1
52
ID16
88
A16
124
VCC
17
BWE0
53
ID17
89
VCC
125
PWRCLK
18
VCC
54
ID18
90
GND
126
MEMCLK
19
GND
55
ID19
91
VCC
127
GND
20
WARN
56
ID20
92
GND
128
VCC
21
IO/MEM
57
ID21
93
A15
129
GND
22
I/D
58
ID22
94
A14
130
DIV2
23
GND
59
ID23
95
A13
131
CNTL0
24
VCC
60
GND
96
A12
132
CNTL1
25
R/W
61
VCC
97
A11
133
VCC
26
TEST
62
GND
98
A10
134
GND
27
TCK
63
ID24
99
A9
135
RESET
28
TMS
64
ID25
100
A8
136
TRAP0
29
TDI
65
ID26
101
A7
137
TRAP1
30
TDO
66
ID27
102
A6
138
INTR3
31
TRST
67
ID28
103
A5
139
INTR2
32
ID0
68
ID29
104
A4
140
INTR1
33
ID1
69
ID30
105
A3
141
INTR0
34
ID2
70
ID31
106
A2
142
DI
35
ID3
71
A31
107
GND
143
HIT
36
ID4
72
A30
108
VCC
144
WBC
8
Am29030 and Am29035 Microprocessors
PRELIMINARY
AMD
CERQUAD PIN DESIGNATIONS
(Sorted by Pin Name)
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
110
A0
16
BWE1
45
ID11
125
PWRCLK
109
A1
15
BWE2
46
ID12
113
RDN
106
A2
14
BWE3
47
ID13
114
RDY
105
A3
131
CNTL0
48
ID14
135
RESET
104
A4
132
CNTL1
49
ID15
120
REQ
103
A5
130
DIV2
52
ID16
25
R/W
102
A6
111
ERLYA
53
ID17
6
STAT0
101
A7
112
ERR
54
ID18
5
STAT1
100
A8
2
GND
55
ID19
4
STAT2
99
A9
19
GND
56
ID20
13
SUP/US
98
A10
23
GND
57
ID21
27
TCK
97
A11
38
GND
58
ID22
29
TDI
96
A12
51
GND
59
ID23
30
TDO
95
A13
60
GND
63
ID24
26
TEST
94
A14
62
GND
64
ID25
28
TMS
93
A15
74
GND
65
ID26
136
TRAP0
88
A16
90
GND
66
ID27
137
TRAP1
87
A17
92
GND
67
ID28
31
TRST
86
A18
107
GND
68
ID29
1
Vcc
85
A19
116
GND
69
ID30
18
Vcc
84
A20
122
GND
70
ID31
24
Vcc
83
A21
127
GND
123
INCLK
37
Vcc
82
A22
129
GND
141
INTR0
50
Vcc
81
A23
134
GND
140
INTR1
61
Vcc
80
A24
22
I/D
139
INTR2
73
Vcc
79
A25
32
ID0
138
INTR3
89
Vcc
78
A26
33
ID1
21
IO/MEM
91
Vcc
77
A27
34
ID2
12
LOCK
108
Vcc
76
A28
35
ID3
126
MEMCLK
117
Vcc
75
A29
36
ID4
8
MPGM0
124
Vcc
72
A30
39
ID5
7
MPGM1
128
Vcc
71
A31
40
ID6
3
MSERR
133
Vcc
115
BGRT
41
ID7
11
OPT0
20
WARN
121
BREQ
42
ID8
10
OPT1
119
BURST
43
ID9
9
OPT2
17
BWE0
44
ID10
118
PGMODE
Note:
The following signals are reserved for future processor implementations:
Pin No.
Pin Name
142
DI
143
HIT
144
WBC
To maintain compatibility with future processor implementations, these pins should be connected to VCC by
individual pull-up resistors.
Am29030 and Am29035 Microprocessors
9
PRELIMINARY
AMD
LOGIC SYMBOL
BREQ
BGRT
R/W
RDN
SUP/US
ERLYA
LOCK
RDY
MPGM1–MPGM0
ERR
REQ
2
BURST
WARN
4
2
BWE3–BWE0
MSERR
INTR3–INTR0
I/D
CNTL1–CNTL0
RESET
TEST
OPT2–OPT0
3
STAT2–STAT0
3
INCLK
2
4
PGMODE
TRAP1–TRAP0
IO/MEM
DIV2
A31–A0
TCK
TDO
TDI
TMS
TRST
PWRCLK
MEMCLK ID31–ID0
10
Am29030 and Am29035 Microprocessors
32
PRELIMINARY
AMD
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the elements below.
AM29030
–20
C
F
/W
CERQUAD LEAD FORMING
Blank = For PGA package only
/W = For Cerquad package only:
denotes leads are trimmed/formed
TEMPERATURE RANGE
C = Commercial (TC = 0°C to +85°C)
PACKAGE TYPE
F = 144-lead Cerquad (GQD144)
G = 145-lead Pin Grid Array without
Heat Sink (CGY145)
SPEED OPTION
–33 = 33 MHz
–25 = 25 MHz
–20 = 20 MHz
–16 = 16 MHz
DEVICE NUMBER/DESCRIPTION
Am29030
RISC Microprocessor with 8 Kbyte of Instruction Cache
Am29035
RISC Microprocessor with 4 Kbyte of Instruction Cache
Valid Combinations
AM29030–33
AM29030–25
GC
AM29030–20
AM29035–16
FC/W
Valid Combinations
Valid Combinations list configurations planned to
be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
Am29030 and Am29035 Microprocessors
11
PRELIMINARY
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . –65°C to +150°C
Voltage on any Pin
with Respect to GND . . . . . . . . . . . –0.5 to VCC +0.5 V
Commercial (C) Devices
Stresses above those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
Operating ranges define those limits between which the functionality of the device is guaranteed.
Case Temperature (TC) . . . . . . . . . . . . . . 0°C to +85°C
Supply Voltage (VCC) . . . . . . . . . . . . . +4.75 to +5.25 V
DC CHARACTERISTICS over COMMERCIAL operating ranges
Parameter
P
Parameter
D
Description
i i
Symbol
Preliminary
T
Test
C
Conditions
di i
Min
Max
Unit
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
2.0
VCC +0.5
V
VILINCLK
INCLK Input Low Voltage
–0.5
0.8
V
VIHINCLK
INCLK Input High Voltage
2.0
VCC +0.5
V
VILMEMCLK
MEMCLK Input Low Voltage
–0.5
0.8
V
VIHMEMCLK
MEMCLK Input High Voltage
VCC –0.8
VCC +0.5
V
VOL
Output Low Voltage for All Outputs except
MEMCLK
IOL = 3.2 mA
0.45
V
VOH
Output High Voltage for All Outputs except
MEMCLK
IOH = –400 µA
ILI
Input Leakage Current
0.45 V ≤ VIN ≤ VCC –0.45 V
±10
µA
ILO
Output Leakage Current
0.45 V ≤ VOUT ≤ VCC –0.4 V
±10
µA
ICCOP
Operating Power Supply Current
VCC = 5.25 V, Outputs
Floating; Holding RESET
active with externally supplied MEMCLK
16.7 MHz Cerquad
20 MHz Cerquad
25 MHz PGA
33.3 MHz PGA
30
30
28
27
0.6
VOLC
MEMCLK Output Low Voltage
IOLC = 20 mA
VOHC
MEMCLK Output High Voltage
IOHC = 20 mA
IOSGND
MEMCLK GND Short Circuit Current
IOSVCC
MEMCLK VCC Short Circuit Current
2.4
V
mA/MHz
V
VCC –0.6
V
VCC = 5.0 V
100
mA
VCC = 5.0 V
100
mA
CAPACITANCE
Parameter
P
Parameter
D
Description
i i
Symbol
Preliminary
T
Test
C
Conditions
di i
Min
Max
Unit
15
pF
20
pF
20
pF
CIN
Input Capacitance
CINCLK
INCLK Input Capacitance
CMEMCLK
MEMCLK Capacitance
COUT
Output Capacitance
20
pF
CI/O
I/O Pin Capacitance
20
pF
12
fC = 10 MHz
Am29030 and Am29035 Microprocessors
PRELIMINARY
AMD
SWITCHING CHARACTERISTICS over COMMERCIAL operating range (PGA)
Preliminary
No.
N
P
Parameter
Description
25 MHz
T
Test
Conditions
33 MHz
Min
Max
Min
Max
Unit
U
i
1
INCLK Period (T)
40
100
30
100
ns
2
INCLK High Time
16
84
14.4
85.6
ns
3
INCLK Low Time
16
84
14.4
85.6
ns
4
INCLK Rise Time
0
6
0
6
ns
5
INCLK Fall Time
0
6
0
6
ns
6
MEMCLK Delay From INCLK
Notes 1, 2
0
6
0
6
ns
7
Synchronous Output Valid Delay
for signals not broken out below
MEMCLK Output
MEMCLK Input
1
2
13
17
1
2
13
17
ns
7a
Synchronous Output Valid Delay
for ID31–ID0
MEMCLK Output
MEMCLK Input
1
2
13
17
1
2
13
17
ns
7b
Synchronous Output Valid Delay
for PGMODE
MEMCLK Output
MEMCLK Input
1
2
13
19
1
2
13
19
ns
8
Synchronous Output Invalid Delay
for signals not broken out below
MEMCLK Output
MEMCLK Input
1
2
13
17
1
2
13
17
ns
8a
Synchronous Output Invalid Delay
for ID31–ID0
MEMCLK Output
MEMCLK Input
1
2
13
17
1
2
13
17
ns
8b
Synchronous Output Invalid Delay
for PGMODE
MEMCLK Output
MEMCLK Input
1
2
13
19
1
2
13
19
ns
9
Synchronous Input Setup Time
for signals not broken out below
(Note 3)
MEMCLK Output
MEMCLK Input
MEMCLK = INCLK
17
17
12
17
17
12
ns
9a
Synchronous Input Setup Time
for ID31–ID0
(Note 3)
MEMCLK Output
MEMCLK Input
MEMCLK = INCLK
9
9
6
9
9
6
ns
9b
Synchronous Input Setup Time
for ERR
(Note 3)
MEMCLK Output
MEMCLK Input
MEMCLK = INCLK
11
11
7
11
11
7
ns
9c
Synchronous Input Setup Time
for RDN
(Note 3)
MEMCLK Output
MEMCLK Input
MEMCLK = INCLK
18
18
12
18
18
12
ns
10
Synchronous Input Hold Time
MEMCLK Output
MEMCLK= INCLK
0
2
0
2
11
Setup Time for Synchronous
RESET Deassertion
2
2
ns
12
Hold Time for Synchronous RESET
Deassertion
5
5
ns
13
WARN Pulse Width
14
Asynchronous Input Pulse Width
15
MEMCLK High Time
MEMCLK Period=T
MEMCLK Period=2T
16
T–3
84
T+3
14.4
T–3
85.6
T+3
ns
16
MEMCLK Low Time
MEMCLK Period=T
MEMCLK Period=2T
16
T–3
84
T+3
14.4
T–3
85.6
T+3
ns
17
MEMCLK Rise Time
0
5
0
5
ns
18
MEMCLK Fall Time
0
5
0
5
ns
4T
ns
4T
T+10
ns
T+10
ns
Notes:
1. MEMCLK as an input is always CMOS level.
2. MEMCLK can drive an external load of 150 pF.
3. The input setup times with MEMCLK used as an input are improved if MEMCLK and INCLK are tied to the same clock
input. This is possible only if the processor and bus operate at the same frequency.
4. Except where noted, measurement conditions are the same as the Am29000 microprocessor.
5. All output valid delays are measured with VOL = 1.5 V and VOH = 1.5 V.
Am29030 and Am29035 Microprocessors
13
PRELIMINARY
AMD
SWITCHING CHARACTERISTICS over COMMERCIAL operating range (Cerquad)
No.
N
P
Parameter
Description
Preliminary Information
16 MHz
20 MHz
Min
Max
Min
Max
T
Test
Conditions
Unit
U
i
1
INCLK Period (T)
60
100
50
100
ns
2
INCLK High Time
24
76
20
80
ns
3
INCLK Low Time
24
76
20
80
ns
4
INCLK Rise Time
0
6
0
6
ns
5
INCLK Fall Time
0
6
0
6
ns
6
MEMCLK Delay From INCLK
Notes 1, 2
0
6
0
6
ns
7
Synchronous Output Valid Delay
for signal not broken out below
MEMCLK Output
MEMCLK Input
1
2
20
24
1
2
18
22
ns
7a
Synchronous Output Valid Delay
for ID31–ID0
MEMCLK Output
MEMCLK Input
1
2
22
26
1
2
20
24
ns
7b
Synchronous Output Valid Delay
for PGMODE
MEMCLK Output
MEMCLK Input
1
2
22
26
1
2
20
24
ns
8
Synchronous Output Invalid Delay
for signals not broken out below
MEMCLK Output
MEMCLK Input
1
2
20
24
1
2
18
22
ns
8a
Synchronous Output Invalid Delay
for ID31–ID0
MEMCLK Output
MEMCLK Input
1
2
22
26
1
2
20
24
ns
8b
Synchronous Output Invalid Delay
for PGMODE
MEMCLK Output
MEMCLK Input
1
2
22
26
1
2
22
26
ns
9
Synchronous Input Setup Time
for signals not broken out below
(Note 3)
MEMCLK Output
MEMCLK Input
MEMCLK = INCLK
21
21
17
19
19
15
ns
9a
Synchronous Input Setup Time
for ID31–ID0
(Note 3)
MEMCLK Output
MEMCLK Input
MEMCLK = INCLK
17
17
13
15
15
11
ns
9b
Synchronous Input Setup Time
for ERR
(Note 3)
MEMCLK Output
MEMCLK Input
MEMCLK = INCLK
17
17
13
15
15
11
ns
9c
Synchronous Input Setup Time
for RDN
(Note 3)
MEMCLK Output
MEMCLK Input
MEMCLK = INCLK
21
21
17
19
19
15
ns
10
Synchronous Input Hold Time
MEMCLK Output
MEMCLK Input
2
3
2
3
11
Setup Time for Synchronous
RESET Deassertion
4
4
ns
12
7
7
ns
13
14
15
Hold Time for Synchronous RESET
Deassertion
WARN Pulse Width
Asynchronous Input Pulse Width
MEMCLK High Time
16
MEMCLK Low Time
17
18
MEMCLK Rise Time
MEMCLK Fall Time
MEMCLK Period=T
MEMCLK Period=2T
MEMCLK Period=T
MEMCLK Period=2T
4T
T+10
24
T–3
24
T–3
0
0
76
T+3
76
T+3
6
6
4T
T+10
20
T–3
20
T–3
0
0
ns
80
T+3
80
T+3
6
6
ns
ns
ns
ns
ns
ns
Notes:
1. MEMCLK as an input is always CMOS level.
2. MEMCLK can drive an external load of 150 pF.
3. The input setup times with MEMCLK used as an input are improved if MEMCLK and INCLK are tied to the same clock input. This
is possible only if the processor and bus operate at the same frequency.
4. Except where noted, measurement conditions are the same as the Am29000 microprocessor.
5. All output valid delays are measured with VOL = 1.5 V and VOH = 1.5 V.
14
Am29030 and Am29035 Microprocessors
PRELIMINARY
AMD
SWITCHING WAVEFORMS
1
2
3
5
4
2.4 V
INCLK
1.5 V
0.8 V
6
15
16
17
MEMCLK
18
VCC–1.0 V
1.5 V
0.8 V
8
7
8a 8b
7a 7b
Synchronous
Outputs
9
9a
10
9b 9c
Synchronous
Inputs
12
11
RESET
13
WARN
14
Asynchronous
Inputs
Am29030 and Am29035 Microprocessors
15
PRELIMINARY
AMD
Capacitive Output Delays
For loads greater than 80 pF
The following table describes the additional output
delays for capacitive loads greater than 80 pF. Values in
the Maximum Additional Delay column should be added
to the value listed in the Switching Characteristics table.
For loads less than or equal to 80 pF, refer to the delays
listed in the Switching Characteristics table. This table
applies to the PGA package only.
Preliminary
N
No.
7
7a
P
Parameter
t D
Description
i ti
Total External Capacitance Maximum Additional Delay
(pF)
(ns)
Synchronous MEMCLK Output Valid Delay
100 pF
150 pF
200 pF
250 pF
300 pF
+1 ns
+2 ns
+4 ns
+6 ns
+8 ns
Synchronous MEMCLK Output Valid Delay
for ID31–ID0
100 pF
150 pF
200 pF
250 pF
300 pF
+1 ns
+6 ns
+10 ns
+15 ns
+19 ns
SWITCHING TEST CIRCUIT
VL
IOL = 3.2 mA
CL
V
Am29030 or
Am29035 CPU
Pin Under Test
VREF = 1.5 V
IOH = 400 µA
VH
Note:
16
CL is guaranteed to 80 pF. For capacitive loading greater than 80 pF, refer to the Capacitive Output Delay table.
Am29030 and Am29035 Microprocessors
PRELIMINARY
AMD
THERMAL CHARACTERISTICS
Pin-Grid-Array Package
θJA
θCA
ÉÉÉÉ
θJC
θJA = θJC + θCA
Thermal Resistance – °C/Watt
Pin-Grid-Array Package
Airflow (LFPM)
0
150
300
500
θJC
Junction-to-Case
3
–
–
–
θCA
Case-to-Ambient
20
18
16
13
Cerquad Package
Airflow (LFPM)
0
150
300
500
θJC
Junction-to-Case
7.5
–
–
–
θCA
Case-to-Ambient
20.8
18.7
16.4
13.3
Am29030 and Am29035 Microprocessors
17
PRELIMINARY
AMD
PHYSICAL DIMENSIONS
GQD 144 — Cerquad Trimmed and Formed (metric unit)
31.00
31.40
27.50
22.75
REF
28.10
0.22
0.38
22.75
REF
27.50
28.10
31.00
31.40
Top View
See Detail A
3.20
3.95
Max
3.60
Side View
0.25
Min
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
0.400 Min
Cap
Seal Glass
DETAIL A
5° ± 2°
±.05
0.305 R
Base
0.127
±.05
R
±.10
0.80
18
0.13
0.23
0° ≤ θ ≤ 7°
Am29030 and Am29035 Microprocessors
20000A
CK 64
08/03/93 MH
PRELIMINARY
AMD
CGY 145 – Pin Grid Array (PGA)
**This diagram is not currently available in this Acrobat file. To order a printed document that contains this information,
please call AMD’s Facts-On-Demand fax information service at 800–222–9323, or call the literature hotline at
512–602–5651 (direct dial worldwide) or 800–292–9263 (toll-free for U.S.)**
Trademarks
AMD, Am29000 and Fusion29K are registered trademarks; and 29K, Am29005, Am29030, Am29035, Am29040, Am29050, Am29200, Am29202,
Am29205, Am29240, Am29243, Am29245, XRAY29K, MiniMON29K, and Scalable Clocking are trademarks of Advanced Micro Devices, Inc.
High C is a registered trademark of MetaWare, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
 1993 Advanced Micro Devices, Inc.
Am29030 and Am29035 Microprocessors
19