FINAL COM’L:-10 IND:-20 PALLV16V8-10 and PALLV16V8Z-20 Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS ◆ Low-voltage operation, 3.3 V JEDEC compatible ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ — VCC = +3.0 V to +3.6 V Pin and function compatible with all 20-pin PAL® devices Electrically-erasable CMOS technology provides reconfigurable logic and full testability Direct plug-in replacement for the PAL16R8 series Designed to interface with both 3.3-V and 5-V logic Outputs programmable as registered or combinatorial in any combination Programmable output polarity Programmable enable/disable control Preloadable output registers for testability Automatic register reset on power up Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages Extensive third-party software and programmer support Fully tested for 100% programming and functional yields and high reliability GENERAL DESCRIPTION The PALLV16V8 is an advanced PAL device built with low-voltage, high-speed, electrically-erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The macrocells provide a universal device architecture. The PALLV16V8 will directly replace the PAL16R8, with the exception of the PAL16C1. The PALLV16V8Z provides zero standby power and high speed. At 30-µA maximum standby current, the PALLV16V8Z allows battery powered operation for an extended period. The PALLV16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices. The equations are programmed into the device through floating-gate cells in the AND logic array that can be erased electrically. The fixed OR array allows up to eight data product terms per output for logic functions. The sum of these products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an active-high or active-low output. The output configuration is determined by two global bits and one local bit controlling four multiplexers in each macrocell. Publication# 17713 Amendment/0 Rev: E Issue Date: November 1998 BLOCK DIAGRAM I1 - I8 CLK/I0 8 Programmable AND Array 32 x 64 OE/I9 MACRO MACRO MACRO MACRO MACRO MACRO MACRO MACRO MC0 MC1 MC2 MC3 MC4 MC5 MC6 MC7 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 17713D-1 FUNCTIONAL DESCRIPTION The PALLV16V8 is a low-voltage, EE CMOS version of the PALCE16V8. The PALLV16V8Z is a low-voltage, EE CMOS version of the PALCE16V8. In addition, the PALLV16V8Z has zero standby power and an unused product term disable feature for reduced power consumption. The PALLV16V8 is a universal PAL device. It has eight independently configurable macrocells (MC0-MC7). Each macrocell can be configured as registered output, combinatorial output, combinatorial I/O or dedicated input. The programming matrix implements a programmable AND logic array, which drives a fixed OR logic array. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Pins 1 and 11 serve either as array inputs or as clock (CLK) and output enable (OE), respectively, for all flip-flops. Unused input pins should be tied directly to VCC or GND. Product terms with all bits unprogrammed (disconnected) assume the logical HIGH state and product terms with both true and complement of any input signal connected assume a logical LOW state. The programmable functions on the PALLV16V8 are automatically configured from the user’s design specification. The design specification is processed by development software to verify the design and create a programming file. This file, once downloaded to a programmer, configures the device according to the user’s desired function. 2 PALLV16V8-10 and PALLV16V8Z-20 Families The user is given two design options with the PALLV16V8. First, it can be programmed as a standard PAL device from the PAL16R8 and PAL10H8 series. The PAL programmer manufacturer will supply device codes for the standard PAL device architectures to be used with the PALLV16V8. The programmer will program the PALLV16V8 in the corresponding architecture. This allows the user to use existing standard PAL device JEDEC files without making any changes to them. Alternatively, the device can be programmed as a PALLV16V8. Here the user must use the PALLV16V8 device code. This option allows full utilization of the macrocell. OE 11 VCC 0X 10 To Adjacent Macrocell 11 10 00 01 SL0X SG1 11 0X D SL1X CLK Q I/OX 10 Q 10 11 0X *SG1 *In macrocells MC0 and MC7, SG1 is replaced by SG0 on the feedback multiplexer. SL0X From Adjacent Pin 17713D-004 Figure 1. PALLV16V8 Macrocell CONFIGURATION OPTIONS Each macrocell can be configured as one of the following: registered output, combinatorial output, combinatorial I/O, or dedicated input. In the registered output configuration, the output buffer is enabled by the OE pin. In the combinatorial configuration, the buffer is either controlled by a product term or always enabled. In the dedicated input configuration, it is always disabled. With the exception of MC0 and MC7, a macrocell configured as a dedicated input derives the input signal from an adjacent I/O. MC0 derives its input from pin 11 (OE) and MC7 from pin 1 (CLK). The macrocell configurations are controlled by the configuration control word. It contains 2 global bits (SG0 and SG1) and 16 local bits (SL00 through SL07 and SL10 through SL17). SG0 determines whether registers will be allowed. SG1 determines whether the PALLV16V8 will emulate a PAL16R8 family. Within each macrocell, SL0x, in conjunction with SG1, selects the configuration of the macrocell, and SL1x sets the output as either active low or active high for the individual macrocell. The configuration bits work by acting as control inputs for the multiplexers in the macrocell. There are four multiplexers: a product term input, an enable select, an output select, and a feedback select multiplexer. SG1 and SL0x are the control signals for all four multiplexers. In MC0 and MC7, PALLV16V8-10 and PALLV16V8Z-20 Families 3 SG0 replaces SG1 on the feedback multiplexer. This accommodates CLK being the adjacent pin for MC7 and OE the adjacent pin for MC0. Registered Output Configuration The control bit settings are SG0 = 0, SG1 = 1 and SL0x =0. There is only one registered configuration. All eight product terms are available as inputs to the OR gate. Data polarity is determined by SL1x. The flip-flop is loaded on the LOW-to-HIGH transition of CLK. The feedback path is from Q on the register. The output buffer is enabled by OE. Combinatorial Configurations The PALLV16V8 has three combinatorial output configurations: dedicated output in a nonregistered device, I/O in a non-registered device and I/O in a registered device. Dedicated Output In a Non-Registered Device The control bit settings are SG0 = 1, SG1 = 0 and SL0x =0. All eight product terms are available to the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the exception of MC3 and MC4. MC3 and MC4 do not use feedback in this mode. Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as input signals. Pin 1 will use the feedback path of MC7, and pin 11 will use the feedback path of MC0. Combinatorial I/O In a Non-Registered Device The control bit settings are SG0 = 1, SG1 = 1, and SL0x =1. Only seven product terms are available to the OR gate. The eighth product term is used to enable the output buffer. The signal at the I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used as an input. Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as inputs. Pin 1 will use the feedback path of MC7, and pin 11 will use the feedback path of MC0. Combinatorial I/O in a Registered Device The control bit settings are SG0 = 0, SG1 = 1 and SL0x =1. Only seven product terms are available to the OR gate. The eighth product term is used as the output enable. The feedback signal is the corresponding I/O signal. Dedicated Input Configuration The control bit settings are SG0 = 1, SG1 = 0 and SL0x =1. The output buffer is disabled. Except for MC0 and MC7, the feedback signal is an adjacent I/O. For MC0 and MC7, the feedback signals are pins 1 and 11. These configurations are summarized in Table 1 and illustrated in Figure 2. 4 PALLV16V8-10 and PALLV16V8Z-20 Families Table 1. Macrocell Configuration SG0 SG1 SL0X Cell Configuration Devices Emulated SG0 SG1 Device Uses Registers SL0X Cell Configuration Devices Emulated Device Uses No Registers 0 1 0 Registered Output PAL16R8, 16R6, 16R4 1 0 0 Combinatorial Output PAL10H8, 12H6, 14H4, 16H2, 10L8, 12L6, 14L4, 16L2 0 1 1 Combinatorial I/O PAL16R6, 16R4 1 0 1 Input PAL12H6, 14H4, 16H2, 12L6, 14L4, 16L2 1 1 1 Combinatorial I/O PAL16L8 Programmable Output Polarity The polarity of each macrocell can be active-high or active-low, either to match output signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. It can also save “DeMorganizing” efforts. Selection is through a programmable bit SL1x which controls an exclusive-OR gate at the output of the AND/OR logic. The output is active high if SL1x is 1 and active low if SL1x is 0. PALLV16V8-10 and PALLV16V8Z-20 Families 5 OE OE D CLK Q D CLK Q Q Q a. Registered active low b. Registered active high c. Combinatorial I/O active low d. Combinatorial I/O active high VCC VCC Note 1 e. Combinatorial output active low Note 1 f. Combinatorial output active high Notes: . Feedback is not available on pins 15 and 16 in the combinatorial output mode. . The dedicated-input configuration is not available on pins 15 and 16. Adjacent I/O pin Note 2 17713D-5 g. Dedicated input Figure 2. Macrocell Configurations 6 PALLV16V8-10 and PALLV16V8Z-20 Families Benefits of Lower Operating Voltage The PALLV16V8 has an operating voltage range of 3.0V to 3.6 V. Low voltage allows for lower operating power consumption, longer battery life, and/or smaller batteries for notebook applications. The PALLV16V8 inputs accept up to 5.5 V, so they are safe for mixed voltage design. Because power is proportional to the square of the voltage, reduction of the supply voltage from 5.0 V to 3.3 V significantly reduces power consumption. This directly translates to longer battery life for portable applications. Lower power consumption can also be used to reduce the size and weight of the battery. Thus, 3.3-V designs facilitate a reduction in the form factor. A lower operating voltage results in a reduction of I/O voltage swings. This reduces noise generation and provides a less hostile environment for board design. A lower operating voltage also reduces electromagnetic radiation noise and makes obtaining FCC approval easier. Power-Up Reset All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the PALLV16V8 will depend on whether they are selected as registered or combinatorial. If registered is selected, the output will be HIGH. If combinatorial is selected, the output will be a function of the logic. Register Preload The register on the PALLV16V8 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. The preload function is not disabled by the security bit. This allows functional testing after the security bit is programmed. Security Bit A security bit is provided on the PALLV16V8 as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. However, programming and verification are also defeated by the security bit. The bit can only be erased in conjunction with the array during an erase cycle. Electronic Signature Word An electronic signature word is provided in the PALLV16V8 device. It consists of 64 bits of programmable memory that can contain user-defined data. The signature data is always available to the user independent of the security bit. Programming and Erasing The PALLV16V8 can be programmed on standard logic programmers. It also may be erased to reset a previously configured device back to its unprogrammed state. Erasure is automatically performed by the programming hardware. No special erase operation is required. PALLV16V8-10 and PALLV16V8Z-20 Families 7 Quality and Testability The PALLV16V8 offers a very high level of built-in quality. The erasability if the device provides a direct means of verifying performance of all the AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to yield the highest programming yields and post-programming function yields in the industry. Technology The high-speed PALLV16V8Z is fabricated with Vantis’ advanced electrically-erasable (EE) CMOS process. The array connections are formed with proven EE cells. This technology provides strong input-clamp diodes and a grounded substrate for clean switching. Zero-Standby Power Mode The PALLV16V8 features a zero-standby power mode. When none of the inputs switch for an extended period (typically 50 ns), the PALLV16V8Z will go into standby mode, shutting down most of its internal circuitry. The current will go to almost zero (ICC < 30 µA). The outputs will maintain the states held before the device went into the standby mode. There is no speed penalty associated with coming out of standby mode. When any input switches, the internal circuitry is fully enabled, and power consumption returns to normal. This feature results in considerable power savings for operation at low to medium frequencies. This saving is illustrated in the ICC vs. frequency graph. The PALLV16V8Z-20 has the free-running-clock feature. This means that if one or more registers are used, switching only the CLK will not wake up the logic array or any macrocell. The device will not be in standby mode because the CLK buffer will draw some current, but dynamic ICC will typically be less than 2 mA. Product-Term Disable On a programmed PALLV16V8Z, any product terms that are not used are disabled. Power is cut off from these product terms so that they do not draw current. As shown in the ICC vs. frequency graph, product-term disabling results in considerable power savings. This saving is greater at the higher frequencies. Further hints on minimizing power consumption can be found in a separate document entitled, Minimizing Power Consumption with Zero-Power PLDs. 8 PALLV16V8-10 and PALLV16V8Z-20 Families LOGIC DIAGRAM 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 CLK/I 0 1 11 VCC 0X 10 20 VCC 11 10 00 01 SL0 7 0 SG1 11 0X D 7 Q 19 I/O7 10 Q SL1 7 10 11 0X I1 2 SG0 11 VCC 0X 10 SL0 7 11 10 00 01 SL0 6 8 SG1 11 0X D 15 Q 18 I/O6 10 Q SL16 10 11 0X I2 3 SG1 11 VCC 0X 10 SL0 6 11 10 00 01 SL0 5 16 SG1 11 0X D 23 Q 17 I/O5 10 Q SL1 5 10 11 0X I3 4 SG1 11 VCC 0X 10 SL0 5 11 10 00 01 SL0 4 24 SG1 11 0X D Q 16 I/O4 10 Q 31 SL1 4 10 11 0X I4 5 SG1 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 SL0 4 CLK OE 17713D-17 PALLV16V8-10 and PALLV16V8Z-20 Families 9 LOGIC DIAGRAM (CONTINUED) 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 CLK OE 11 10 00 01 11 VCC 0X 10 SL0 3 32 SG1 11 0X D 39 Q 15 I/O 3 10 Q SL1 3 10 11 0X I5 6 SG1 11 VCC 0X 10 SL0 3 11 10 00 01 SL0 2 40 SG1 11 0X D 47 I6 Q 14 I/O 2 10 Q SL1 2 10 11 0X 7 SG1 11 VCC 0X 10 SL0 2 11 10 00 01 SL0 1 48 SG1 11 0X D 55 Q 13 I/O1 10 Q SL1 1 10 11 0X I7 8 SG1 11 VCC 0X 10 SL0 1 11 10 00 01 SL0 0 56 SG1 11 0X D 63 SL1 0 Q 12 I/O 0 10 Q 10 11 0X I8 9 SG0 SL00 11 OE/I 9 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 GND 10 17713D-18 10 PALLV16V8-10 and PALLV16V8Z-20 Families ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55°C to +125°C Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . . . -0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +3.0 V to +3.6 V DC Input Voltage . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latch-up Current (TA = 0°C to 75°C) . . . . . . . . . . . . . . . . . . . . . 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES Parameter Symbol Parameter Description Test Conditions VIN = VIH or VIL VCC = Min Min Max Unit IOH = –2 mA 2.4 V IOH = –75 mA VCC - 0.2 V V VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage IIH IOL = 2 mA 0.4 V IOL = 100 mA 0.2 V 5.5 V Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V Input HIGH Leakage Current VIN = VCC, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –100 µA IOZH Off-State Output Leakage Current HIGH VOUT = VCC, VCC = Max, VIN = VIH or VIL (Note 2) 10 µA IOZL Off-State Output Leakage Current LOW VOUT = VCC, VCC = Max, VIN = VIH or VIL (Note 2) -100 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) -130 mA ICC Supply Current Outputs Open (IOUT = 0 mA), VCC = Max, f = 15 MHz (Note 4) 55 mA VIN = VIH or VIL VCC = Min 2.0 -50 Notes: 1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIL and IOZL). 3. Not more than one output should be shortened at a time, and the duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. This parameter is guaranteed worst case under test conditions. Refer to the ICC vs. frequency graph for typical measurements. PALLV16V8-10 (Com’l) 11 CAPACITANCE 1 Parameter Symbol Parameter Description Test Condition CIN Input Capacitance VIN = 2.0 V COUT Output Capacitance VOUT = 2.0 V Typ Unit 5 pF 8 pF VCC - 3.3 V, TA = 25°C, f = 1 MHz Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES 1 -10 Parameter Symbol Parameter Description Min Max Unit 10 ns tPD Input or Feedback to Combinatorial Output (Note 2) tS Setup Time from Input or Feedback to Clock 7 ns tH Hold Time 0 ns tCO Clock to Output tWL ns LOW 6 ns HIGH 6 ns Clock Width tWH fMAX 7 Maximum Frequency (Notes 2 and 3) External Feedback 1/(tS + tCO) 71.4 MHz Internal Feedback (fCNT 1/(tS + tCF) 83.3 MHz No Feedback 1/(tS + tH) 83.3 MHz tPZX OE to Output Enable 10 ns tPXZ OE to Output Disable 10 ns tEA Input to Output Enable Using Product Term Control 12 ns tER Input to Output Disable Using Product Term Control 12 ns Notes: 1. See “Switching Test Circuit” for test conditions. 2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 3. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS. 12 PALLV16V8-10 (Com’l) ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Industrial (I) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55°C to +125°C Ambient Temperature (TA) . . . . . . . . . . -40°C to +85°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Supply Voltage (VCC) with Respect to Ground. . . . . . . . . . . . . . . +3.0 V to +3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latch-up Current (TA = -40°C to 85°C) . . . . . . . . . . . . . . . . . . . . 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES Parameter Symbol Parameter Description Test Conditions VIN = VIH or VIL VCC = Min Min Max Unit IOH = –2 mA 2.4 V IOH = –75 µA VCC – 0.2 V V VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage IIH IOL = 2 mA 0.4 V IOL = 100 µA 0.2 V 5.5 V Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V Input HIGH Leakage Current VIN = VCC, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –10 µA IOZH Off-State Output Leakage Current HIGH VOUT = VCC, VCC = Max, VIN = VIH or VIL (Note 2) 10 µA IOZL Off-State Output Leakage Current LOW VOUT = VCC, VCC = Max, VIN = VIH or VIL (Note 2) -10 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) -75 mA 30 µA Supply Current Outputs Open (IOUT = 0 mA) VCC = Max, f = 15 MHz (Note 4) f = 0 MHz ICC f = 15 MHz 45 mA VIN = VIH or VIL VCC = Min 2.0 -15 Note: 1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. This parameter is guaranteed worst case under test conditions. Refer to the ICC vs. frequency graph for typical measurements. PALLV16V8Z-20 (Ind) 13 CAPACITANCE 1 Parameter Symbol Parameter Description Test Condition CIN Input Capacitance VIN = 2.0 V COUT Output Capacitance VOUT = 2.0 V VCC = 5.0 V, TA = 25°C, f = 1 MHz Typ Unit 5 pF 8 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES 1 -20 Parameter Symbol Parameter Description Min Max Unit 20 ns tPD Input or Feedback to Combinatorial Output (Note 2) tS Setup Time from Input or Feedback to Clock 15 ns tH Hold Time 0 ns tCO Clock to Output tWL ns LOW 8 ns HIGH 8 ns Clock Width tWH fMAX 10 Maximum Frequency (Notes 3 and 4) External Feedback 1/(tS + tCO) 40 MHz Internal Feedback (fCNT) 1/(tS + tCF) 50 MHz No Feedback 1/(tS + tH) 66.7 MHz tPZX OE to Output Enable 20 ns tPXZ OE to Output Disable 20 ns tEA Input to Output Enable Using Product Term Control 20 ns tER Input to Output Disable Using Product Term Control 20 ns Notes: 1. See “Switching Test Circuit” for test conditions. 2. This parameter is tested in Standby Mode. When the device is not in Standby Mode, the tPD will typically be about 2 ns faster. 3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) - tS. 14 PALLV16V8Z-20 (Ind) SWITCHING WAVEFORMS Input or Feedback Input or Feedback VT tS VT tPD VT tCO Clock Combinatorial Output VTO 17713D-7 tH Registered Output VTO 17713D-8 a. Combinatorial output b. Registered output VT Input tWH tER Clock VT tEA VOH - 0.5V VOL + 0.5V Output tWL VTO 17713D-10 17713D-9 d. Input to output disable/enable c. Clock width VT OE tPXZ tPZX VOH - 0.5V VOL + 0.5V Output VTO 17713D-11 e. OE to output disable/enable Notes: 1. VT = 1.5 V for input signals and VCC/2 for output signals. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns to 5 ns typical. PALLV16V8-10 and PALLV16V8Z-20 Families 15 KEY TO SWITCHING WAVEFORM WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010-PAL SWITCHING TEST CIRCUIT VCC S1 R1 Output Test Point R2 CL S2 17713D-12 Specification S1 S2 tPD, tCO Closed Closed tPZX, tEA Z → H: Open Z → L: Closed Z → H: Closed Z → L: Open tPXZ, tER H → Z: Open L → Z: Closed H → Z: Closed L → Z: Open 16 CL R1 R2 Measured Output Value VCC/2 30 pF 1.6K 1.6K 5 pF PALLV16V8-10 and PALLV16V8Z-20 Families VCC/2 H → Z: VOH – 0.5 V L → Z: VOL + 0.5 V TYPICAL ICC CHARACTERISTICS VCC = 3.3 V, TA = 25°C 150 125 100 PALLV16V8-10 ICC (mA) 75 PALLV16V8Z-20 50 25 0 0 10 20 30 40 Frequency (MHz) 50 17713D-13 ICC vs. Frequency The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and the other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector, half of the outputs were switching. By utilizing 50% of the device, a midpoint is defined for ICC. From this midpoint, a designer may scale the ICC graphs up or down to estimate the ICC requirements for a particular design. PALLV16V8-10 and PALLV16V8Z-20 Families 17 ENDURANCE CHARACTERISTICS The PALLV16V8 is manufactured using Vantis’ advanced electrically-erasable (EE) CMOS process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, devices can be erased and reprogrammed—a feature which allows 100% testing at the factory. Symbol Parameter Test Conditions tDR Min Pattern Data Retention Time N Max Reprogramming Cycles Value Unit Max Storage Temperature 10 Years Max Operating Temperature 20 Years Normal Programming Conditions 100 Cycles ROBUSTNESS FEATURES The PALLV16V8 has some unique features that make it extremely robust, especially when operating in high-speed design environments. Pull-up resistors on inputs and I/O pins cause unconnected pins to default to a known state. Input clamping circuitry limits negative overshoot, eliminating the possibility of false clocking caused by subsequent ringing. A special noise filter makes the programming circuitry completely insensitive to any positive overshoot that has a pulse width of less than about 100 ns. INPUT/OUTPUT EQUIVALENT SCHEMATICS VCC VCC > 50 kΩ ESD Protection and Clamping Programming Pins only Programming Voltage Detection Programming Circuitry Positive Overshoot Filter Typical Input 17713D-14 VCC VCC > 50 kΩ 5-V Protection Provides ESD Protection and Clamping Preload Circuitry Typical Output 18 PALLV16V8-10 and PALLV16V8Z-20 Families Feedback Input 17713D-15 POWER-UP RESET The PALLV16V8 has been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will be HIGH independent of the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are: ◆ The VCC rise must be monotonic. ◆ Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Symbol Parameter Descriptions tPR Power-Up Reset Time tS Input or Feedback Setup Time tWL Clock Width LOW Min Max Unit 1000 ns See Switching Characteristics VCC Power 2.7 V tPR Registered Output tS Clock tWL 17713D-16 Figure 3. Power-Up Reset Waveform PALLV16V8-10 and PALLV16V8Z-20 Families 19 TYPICAL THERMAL CHARACTERISTICS Measured at 25°C ambient. These parameters are not tested. Typ Parameter Symbol Parameter Description PDIP PLCC Unit θjc Thermal impedance, junction to case 20 19 °C/W θja Thermal impedance, junction to ambient 65 57 °C/W 200 lfpm air 58 41 °C/W 400 lfpm air 51 37 °C/W 600 lfpm air 47 35 °C/W 800 lfpm air 44 33 °C/W θjma Thermal impedance, junction to ambient with air flow Plastic θjc Considerations The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The heatflow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location ion the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, θjc tests on packages are performed in a constant temperature. Therefore, the measurements can only be used in a similar environment. 20 PALLV16V8-10 and PALLV16V8Z-20 Families CONNECTION DIAGRAMS (TOP VIEW) DIP/SOIC 1 20 VCC I1 2 19 I/O 7 I1 CLK/I0 VCC I2 3 18 I/O 6 3 2 1 20 19 I3 4 17 I/O 5 I4 5 16 I/O 4 I5 6 15 I/O 3 I6 7 14 I/O 2 I7 8 13 I/O 1 I8 9 12 I/O 0 GND 10 11 OE/I 9 18 I/O6 I4 5 17 I/O5 I5 6 16 I/O4 I6 7 15 I/O3 I7 8 14 I/O2 PIN DESIGNATIONS = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage I/O1 I/O0 10 11 12 13 OE/I9 9 GND 4 I8 I3 17713D-2 CLK GND I I/O NC VCC I/O7 CLK/I 0 I2 PLCC 17713D-3 Note: Pin 1 is marked for orientation. PALLV16V8-10 and PALLV16V8Z-20 Families 21 ORDERING INFORMATION Commercial and Industrial Products Vantis programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: PAL FAMILY TYPE PAL = Programmable Array Logic TECHNOLOGY LV = Low-Voltage NUMBER OF ARRAY INPUTS 16 V 8 Z -10 P C OPERATING CONDITIONS C = Commercial (0°C to +75°C) I = Industrial (–40°C to 85°C) PACKAGE TYPE P = 20-Pin Plastic DIP (PD 020) J = 20-Pin Plastic Leaded Chip Carrier (PL 020) S = 20-Pin Plastic Gull-Wing Small Outline Package (SO 020) OUTPUT TYPE V = Versatile NUMBER OF OUTPUTS Z LV = Zero Power (30 µA ICC Standby) SPEED –10 = 10 ns tPD –20 = 20 ns tPD Valid Combinations 22 PALLV16V8-10 PC, JC, SC PALLV16V8Z-20 PI, JI Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Vantis sales office to confirm availability of specific valid combinations and to check on newly released PALLV16V8-10 and PALLV16V8Z-20 Families