A
B
C
D
E
Table Of Contents
Page 1: Cover.SCH
Page 2: Inputs.SCH
Page 3: MACH.SCH
Page 4: Ports.SCH
Page 5: Displays.SCH
Page 6: Datainfo.SCH
Page 7: Ethernet.SCH
Page 8: Debug.SCH
4
4
TEST INTERFACE PORT
7,3
Schematics
3
3
REV 1.1
Sheet 2:
Sheet
Sheet
Sheet
Sheet
2
3:
5:
6:
7:
Sheet 8:
REV 1.2
Sheet 3:
Sheet 4:
Sheet 8:
© Copyright 1998 Advanced Micro Devices, Inc.
Removed 1K pull down on AEN.
Changed resistor values of R10 and R11.
Added a Schottky Barrier Rectifier
to power supply circuit.
Added TRESET net to MACH.
Changed resistor R66 form 10K to 0 ohm.
Changed resistors R84 - R91 from 10K to 1K.
Ground AVSS1 on U26.
Added 1k pull up resistor to IOCHRDY signal.
Changed SW_IRQ# nodename to MAIN_IRQ.
Replace 74HC4072 OR gate with 74HC21 AND gate.
Removed pull down resistor R15 - R18 from
shared interrupt signals.
Added a pull up resistor to the PARINT signal.
Added a pull up resistor to the PEMD signal.
while making the existing pull down resistor
an optional populate resistor.
Routed IOCHRDY and TIPFLHCS# nets to debug header
REV 1.3
Sheet 3:
1
All Rights Reserved
Advanced Micro Devices, Inc. ("AMD") reserves the right to discontinue its products,
or make changes in its products, at any time without notice.
The information in this publication is believed to be accurate at the time of publication,
but AMD makes no representations or warranties with respect to the accuracy or completeness
of the contents of this publication or the information contained herein, and reserves the
right to make changes at any time, without notice. AMD disclaims responsibility for any
consequences resulting from the use of the information included in this publication.
This publication neither states nor implies any representations or warranties of any kind,
including but not limited to, any implied warranty of merchantability or fitness for a
particular purpose. AMD’s products are not designed, intended, authorized or warranted for
use as components in systems intended for surgical implant into the body, or in other applications
intended to support or sustain life, or in any other application in which the failure of AMD’s
product could create a situation where personal injury, death, or severe property or environmental
damage may occur. AMD assumes no liability whatsoever for claims associated with the sale or use
(including the use of engineering samples) of AMD products except as provided in AMD’s
Terms and Conditions of Sale for such product.
Note: Unless otherwise stated the resistors are a 0805 package and 5% Tol.
Note: Unless otherwise stated the capacitors are a 0805 package and 10% Tol.
NOTE: An asterisk (*) in front of a resistor or capacitor value
indicates a non populated component.
Removed resistor R17.
Replaced AND gates with OR gates.
Made the spare MACH I/O pin 61 accessible for use.
1
(C) Advanced Micro Devices, Inc.
(800) 222-9323
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
Title
Test Interface Port (TIP)
Size
Document Number
Cover.SCH
Date: Friday, May 07, 1999
A
B
2
C
D
Rev
1.3
Sheet
E
1
of
8
A
B
VCC5
VCC5
C
D
C1
C2
C3
C4
C5
C6
C7
C8
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
VCC5
+ C10
10uF
C CASE, 16V
U1
TA0
TA1
TA2
TA3
TA4
TA5
TA6
TA7
TA8
TA9
TA10
TA11
TA12
TA13
TA14
TA15
4
104068-6
** NOTE **
1
Target boards should
use a pull down resistor
on pin 35 or a pull up
resistor on pin 37, for
auto detect of the TIP
being active
2
E
VCC5
TD[7:0]
TA[19:0]
A[19:0]
1
48
25
24
1OE#
2OE#
3OE#
4OE#
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
21
4
10
15
TD[7:0]
VCC
VCC
VCC
VCC
7
18
31
42
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
GND
GND
GND
GND
GND
GND
GND
GND
28
34
39
45
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
4
TI 74ACT16244DGGR
TD[7:0]
P1
R4
10K
Top View
R5
TIPSEL#
TIPSEL
1K
ENETIRQ
PARINT
SERINT1
SERINT0
IOCHRDY
SEL186
SEL186
MAIN_IRQ
HRESET#
TRESET
FLASHRD#
FLASHWR#
FLASHCS#
EXTFLHCS#
TD0
TD1
TD2
TD3
TD4
TD5
TD6
TD7
10uF
1DIR
2DIR
48
25
1G#
2G#
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
21
4
10
15
C CASE, 16V
VCC
VCC
VCC
VCC
7
18
31
42
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
GND
GND
GND
GND
GND
GND
GND
GND
28
34
39
45
A16
A17
A18
A19
AEN
RD#
WR#
S2
D0
D1
D2
D3
D4
D5
D6
D7
AEN
RD#
WR#
S2
D[7:0]
2
TI 74ACT16245DGGR
VCC5
R10
HVCC
R9
A 5V external power supply is
required to provide VCC to the
TIP board. But a host board
must be properly connected
to the TIP before the external
supply is allowed to power the
board.
3.3M
JP1
U3
HVCC
4 U3JMP
5
6
8
R11
V+
ININ+ HYST
VREF
GND OUT
1.2M
LINEAR LTC1540CMS8
R12
COMPARATOR
*0
ALTOUT
3
2
1
U4
2
D2
6
1
8
3
Vs
DS1
DS2
GND
IN1
IN2
G1
G2
COMPAROUT
7
3
2
1
U3INPOS
KYCON KLD-0202-BC
DC POWER CONN
MAIN_IRQ
10K
P2
1
2
3
SW1
HRESET#
3
1
FSM4J
VCC5
R13
TRESET
FLASHRD#
FLASHWR#
TIPFLHCS#
SW_INTRP#
10K
SW_INTRP#
4
5
2
7
VCC5
RVCC 1
EVCC
LINEAR LTC1155
MOSFET DRIVER
U5
VCC5
10K
TAEN
TRD#
TWR #
TS2
NOTE:
6
5
3
1
D2
D2
S2
S1
D1
D1
G2
G1
8
7
4
2
1
3
1
10K
TAEN
TRD#
TWR #
TS2
+
C9
Power Supply Circuit
SLEEVE
SHUNT
CENTER
R3
TA16
TA17
TA18
TA19
1
24
D1
1
2
1
2
4
2/NC
Top View
FSM4J
Title
C11
3
3
Barrel Connector
3
1
Test Interface Port (TIP)
1
3
Alcoswitch FSM4J
0.1uF
Size
BAT54
Document Number
Inputs.SCH
Date: Monday, April 26, 1999
A
B
(800) 222-9323
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
SW2
FET2
FET1
Temic Si9925DY
MOSFET (N-CHAN)
ALTOUT
(C) Advanced Micro Devices, Inc.
R14
10K
1
2
TD0
TD2
TD4
TD6
AMP 104068-6
1K
HVCC
R8
3
U2
1K
60
DB2G#
DB2DIR#
VCC5
TA10
TA12
TA14
TA16
TA18
R7
VCC5
59
DB2G#
DB2DIR#
VCC5
10K
TD1
TD3
TD5
TD7
TA0
TA2
TA4
TA6
TA8
R2
TA11
TA13
TA15
TA17
TA19
3
2
4
6
8
10
GND
14
16
18
20
22
GND
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
3
5
7
9
GND
13
15
17
19
21
GND
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
VCC
VCC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
HRESET#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
R1
TA1
TA3
TA5
TA7
TA9
C
D
Rev
1.3
Sheet
E
2
of
8
A
B
C
D
E
REV 1.3
C12
C13
C14
VCC5
VCC5
C15
C67
WARNING: The peripheral interrupt signals on the TIP are unterminated.
As a result, software must ensure that each peripheral’s interrupt is
enabled so that the interrupt input to the OR gate driving the MAIN_IRQ
signal is not floatng. Alternatively, the target board may utilize pull-down
resistors on the peripheral interrupt signals.
VCC5
0.1uF
0.1uF
0.1uF
0.1uF
14
0.1uF
ENETIRQ
PARINT
2
3
SERINT1
SERINT0
4
5
U6A
TP_IRQ
VCC5
14
7
1
U6B
9
10
4
13
4
MAIN_IRQ
7
11
12
A[19:0]
U7
2
D0
D1
D2
D3
D4
D5
D6
D7
7
18
37
43
70
71
88
98
63
13
49
54
56
4
87
24
38
68
I/O10
I1/CLK1
I/O30
I/O32
I/O49
I/O50
I/O63
I/O5
I3/CLK2
I0/CLK0
I/O38
I2
I/O41
I5
I/O62
I/O21
I/O31
I4/CLK3
1
2
16
17
29
30
40
41
51
52
66
67
79
80
90
91
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I/O36
I/O40
I/O42
I/O29
I/O51
I/O35
I/O33
I/O61
I/O55
I/O60
I/O57
I/O26
I/O24
I/O58
I/O39
I/O52
I/O34
I/O59
I/O56
I/O43
I/O44
I/O45
I/O46
I/O47
47
55
57
36
72
46
44
86
76
85
82
33
31
83
50
73
45
84
81
58
59
60
61
62
I/O8
I/O23
I/O7
I/O54
I/O53
I/O37
I/O28
I/O48
5
26
100
75
74
48
35
69
SW_IRQ
DB2G#
DB2DIR#
SERCS0#
SERCS1#
PARCS#
LCDEN
LCDRS
LCDR/W
LEDCLK
LEDOE#
HDRLTCLK
HDRLTOE#
HDRBFOE#
HEXCS0#
HEXCS1#
HEXCS2#
HEXCS3#
DIPSWOE#
IOSPARE1
IOSPARE2
IOSPARE3
IOSPARE4
3
SP1
SP2
SP3
SP4
TRESET
D[7:0]
REV 1.3
D0
D1
D2
D3
D4
D5
D6
D7
VCC5
P3
TCK
TMS
TDI
TDO
ENABLE
TRST
28
27
3
78
53
77
TCK
TMS
TDI
TDO
ENABLE
TRST
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
14
15
39
42
64
65
89
92
1
3
5
7
9
2
4
6
8
10
3M 2510-6002UB
VCC5
LOW
R19
1K
R118 1K
I/O0
I/O1
I/O2
I/O3
I/O4
I/O6
I/O9
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
I/O17
I/O18
I/O19
I/O20
I/O22
I/O25
I/O27
10K
RD#
WR#
AEN
S2
TIPFLHCS#
FLASHRD#
FLASHWR#
SEL186
SW_INTRP#
SELBIT
93
94
95
96
97
99
6
8
9
10
11
12
19
20
21
22
23
25
32
34
R117
D[7:0]
3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
2
VANTIS MACH4-128/64-12YC
MACH-4
100 99
82
81
1
80
2
79
1
78
1
14
13
12
11
10
9
8
(C) Advanced Micro Devices, Inc.
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
53
29
52
30
1
2
3
4
5
6
7
Title
51
74HC21
Test Interface Port (TIP)
Size
31
32
49
50
Document Number
MACH.SCH
Date: Friday, May 07, 1999
A
(800) 222-9323
B
C
D
Rev
1.3
Sheet
E
3
of
8
A
B
C
D
E
VCC5
Parallel
Connector
VCC5
P4
0
0
*0
R21
R18
R20
C18
C19
C20
0.1uF
0.1uF
0.1uF
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
U9
4
PARINT
PARCS#
PEMD
ENIRQ
D[7:0]
12 A1
11
10 A0
9 A2
8
7 A1
VCC5
SER_A0
SER_A1
1
1
C1 C4
2
2
1
1
C2 C3
2
2
A[19:0]
R22
10K
SW3HIGH
ASF42
1
2
3
A3 4
5
A2 6
SELBIT
SW3
14
15
16
17
18
19
20
21
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
SER_A0
SER_A1
SER_A2
35
34
33
36
37
39
4
44
A0
A1
A2
IOW#
IOR#
RESET#
CLK
BDO
60
61
42
3
INT1
RXRDY1#
TXRDY1#
CS1#
45
9
22
32
INT0
RXRDY0#
TXRDY0#
CS0#
23
64
40
VDD
VDD
VDD
SER_A2
10K
RESET#
WR#
RD#
SERINT1
SERCS1#
SERINT0
3
SERCS0#
VCC5
14
VCC5
STB#
AFD#
ERR#
INIT#
SLIN#
55
56
63
57
58
PARSTB#
PARAFD#
PARERR#
PARNIT#
PARSLIN#
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
53
52
51
50
49
48
47
46
PARPD0
PARPD1
PARPD2
PARPD3
PARPD4
PARPD5
PARPD6
PARPD7
ACK#
BUSY
PE
SLCT
68
66
67
65
PARACK#
PARBUSY
PARPE
PARSLCT
DCD1#
DTR1#
SOUT1
CTS1#
SIN1
RTS1#
DSR1#
RI1#
8
11
10
13
62
12
5
6
DCD0#
DTR0#
SOUT0
CTS0#
SIN0
RTS0#
DSR0#
RI0#
29
25
26
28
41
24
31
30
GND
GND
GND
7
27
54
TRI
PEMD
ENIRQ
INT2
CS2#
D0
D1
D2
D3
D4
D5
D6
D7
SW3L OW
R23
2
1
43
59
38
3
16
4
17
5
18
SER_DCD1#
SER_DTR1#
SER_SOUT1
SER_CTS1#
SER_SIN1
SER_RTS1#
SER_DSR1#
SER_RI1#
19
7
20
8
21
9
22
10
23
11
24
12
25
Component
side view
DCE SERIAL CONFIGURATION
With these resistors populated
the serial port is in DCE configuration.
NOTE: This is the default configuration
of the TIP board.
U10
SER_DCD0#
SER_DTR0#
SER_SOUT0
SER_CTS0#
SER_SIN0
SER_RTS0#
SER_DSR0#
SER_RI0#
8
7
6
5
26
20
22
21
19
R1OUT
T1IN
T2IN
R2OUT
R3OUT
T3IN
R4OUT
T4IN
R5OUT
17
V-
24
25
EN#
SD
SER1C1P 12
C1+
SER1VM
C21
0.1uF
2
C23
7
0.1uF SER1C1M 14
10
R1IN
T1OUT
T2OUT
R2IN
R3IN
T3OUT
R4IN
T4OUT
R5IN
9
2
3
4
27
1
23
28
18
DCD1#_T
DTR1#_T
SOUT1_T
CTS1#_T
SIN1_T
RTS1#_T
DSR1#_T
RI1#
C2+
15
SER1C2P
C22
C1GND
C2-
16
0.1uF
SER1C2M
V+
13
SER1VP
VCC
11
R24
R25
R26
R27
R28
R29
R30
R31
P5
0
0
0
0
0
0
0
0
DCD1#_C
DTR1#_C
SOUT1_C
CTS1#_C
SIN1_C
RTS1#_C
DSR1#_C
RMRESET1
R32
1
6
2
7
3
8
4
9
5
3
0
R33
VCC5
Serial Connector
AMP 747844-5
*0
1
C24
2
0.1uF
3
4
Sipex SP211CA
With these resistors populated
the serial port is in DCE configuration.
NOTE: This is the default configuration
of the TIP board.
VCC5
U12
2
Y1
VCC5
C25
1
OE
VCC
4
2
GND
OUT
3 CLK8MHZ
ECLIPTEK EC2500-8.3300M
0.1uF
SER0VM
8
7
6
5
26
20
22
21
19
R1OUT
T1IN
T2IN
R2OUT
R3OUT
T3IN
R4OUT
T4IN
R5OUT
17
V-
24
25
EN#
SD
C26
DTE SERIAL CONFIGURATION
0.1uF
SER0C1P 12
NOTE: To configure as DTE serial port, the
C28
DCE resistors must be removed then
the below resistor must me populated.
DCD1#_T
DSR1#_T
SIN1_T
RTS1#_T
SOUT1_T
CTS1#_T
DTR1#_T
EC2500ETT-8.00M
4
1
3
R44
R45
R46
R47
R48
R49
R50
4
6
AMP 747846-2
U11A
1
14
15
13
TI TL16C552FN
TRESET
1
2
*0
*0
*0
*0
*0
*0
*0
DCD1#_C
DTR1#_C
SOUT1_C
CTS1#_C
SIN1_C
RTS1#_C
DSR1#_C
0.1uF SER0C1M 14
10
R1IN
T1OUT
T2OUT
R2IN
R3IN
T3OUT
R4IN
T4OUT
R5IN
9
2
3
4
27
1
23
28
18
DCD0#_T
DTR0#_T
SOUT0_T
CTS0#_T
SIN0_T
RTS0#_T
DSR0#_T
RI0#
C2+
15
SER0C2P
C1GND
DCD0#_C
DTR0#_C
SOUT0_C
CTS0#_C
SIN0_C
RTS0#_C
DSR0#_C
RMRESET0
R42
C2-
16
SER0C2M
V+
13
SER0VP
VCC
11
7
8
9
P6
0
0
0
0
0
0
0
0
1
6
2
7
3
8
4
9
5
2
0
AMP 747844-5
C27
0.1uF
C1+
R34
R35
R36
R37
R38
R39
R40
R41
5
6
R43
VCC5
*0
C29
HRESET#
0.1uF
1
Sipex SP211CA
6
2
7
3
8
4
9
1
1
2
12
14
8
ALCO
7
DCD0#_T
DSR0#_T
SIN0_T
RTS0#_T
SOUT0_T
CTS0#_T
DTR0#_T
R51
R52
R53
R54
R55
R56
R57
*0
*0
*0
*0
*0
*0
*0
(C) Advanced Micro Devices, Inc.
DCD0#_C
DTR0#_C
SOUT0_C
CTS0#_C
SIN0_C
RTS0#_C
DSR0#_C
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
Title
Test Interface Port (TIP)
Size
1
6
7
1
ASF42
MC74ACT04
Document Number
Ports.SCH
Date: Monday, April 26, 1999
A
B
(800) 222-9323
C
D
Rev
1.3
Sheet
E
4
of
8
A
B
C
D[7:0]
D
E
D[7:0]
VCC5
U13
D4
D5
D6
D7
HEXCS0#
LDC0H
4
3
2
13
12
DA
DB
DC
DD
5
8
4
10
STRB
BLNK
LDC
RDC
R58
330
VCC
LED
14
1
NC
NC
NC
6
9
11
GND
HEXCS2#
LDC2H
3
2
13
12
DA
DB
DC
DD
HEXCS0#
5
8
4
10
STRB
BLNK
LDC
RDC
7
LDC0L
TI TIL311
3
2
13
12
DA
DB
DC
DD
VCC5
5
8
4
10
STRB
BLNK
LDC
RDC
R62
330
VCC
LED
14
1
NC
NC
NC
6
9
11
GND
VCC
LED
14
1
NC
NC
NC
6
9
11
GND
7
DA
DB
DC
DD
HEXCS2#
5
8
4
10
STRB
BLNK
LDC
RDC
7
LDC2L
DA
DB
DC
DD
5
8
4
10
STRB
BLNK
LDC
RDC
R59
330
VCC
LED
14
1
NC
NC
NC
6
9
11
GND
VCC
LED
14
1
NC
NC
NC
6
9
11
HEXCS3#
LDC3H
7
HEXCS1#
7
GND
LDC1L
DA
DB
DC
DD
5
8
4
10
STRB
BLNK
LDC
RDC
R63
330
3
2
13
12
DA
DB
DC
DD
5
8
4
10
STRB
BLNK
LDC
RDC
VCC
LED
14
1
NC
NC
NC
6
9
11
14
1
NC
NC
NC
6
9
11
GND
7
HEXCS3#
LDC3L
TI TIL311
4
VCC5
U20
D0
D1
D2
D3
7
GND
VCC
LED
TI TIL311
R61
330
VCC5
3
2
13
12
VCC5
U16
D0
D1
D2
D3
TI TIL311
U19
D4
D5
D6
D7
TI TIL311
R64
330
3
2
13
12
VCC5
3
2
13
12
TI TIL311
HEXCS1#
LDC1H
U18
D0
D1
D2
D3
VCC5
U15
D4
D5
D6
D7
TI TIL311
R60
330
U17
D4
D5
D6
D7
VCC5
U14
D0
D1
D2
D3
3
2
13
12
DA
DB
DC
DD
5
8
4
10
STRB
BLNK
LDC
RDC
VCC
LED
14
1
NC
NC
NC
6
9
11
GND
7
TI TIL311
R65
330
3
3
VCC5
ALTOUT
R66
1
14
2
13
3
12
0
C30
C31
C32
C33
0.1uF
0.1uF
0.1uF
0.1uF
4
VCC5
5
10
7
8
U19
U20
U17
U18
U15
U16
U13
C34
C35
C36
C37
0.1uF
0.1uF
0.1uF
0.1uF
L C D
U14
VCC5
TOP VIEW
TIL311
3
20K POTENTIOMETER
1
2
R67
SPARES
F L A S H
2
LCDRS
LCDR/W
LCDEN
D0
D1
D2
D3
D4
D5
D6
D7
*SP1
D[7:0]
A[19:0]
U22
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
1
TIPFLHCS#
FLASHRD#
FLASHWR#
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
22
24
31
CE
OE
WE
D0
D1
D2
D3
D4
D5
D6
D7
13
14
15
17
18
19
20
21
D0
D1
D2
D3
D4
D5
D6
D7
JP2
1
1
2
3
4
5
6
A1
A2
A3
A4
A5
A6
7
GND
VCC
14
Y6
Y5
Y4
Y3
Y2
Y1
13
12
11
10
09
08
VCCSW20
D[7:0]
3
2
4
5
6
VO
VDD
RS
R/W
E
7
8
9
10
11
12
13
14
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
1
GND
VL ELELCTRICS MDLS-20265K-LV-G
VCC5
*SPARE_14
HEADER, 1
GND
VCC5
*SP2
JP3
1
VCC5
HEADER, 1
VCC
GND
32
C39
0.1uF
GND
16
1
2
3
4
5
6
7
8
9
10
VCC
20
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
19
18
17
16
15
14
13
12
11
A1
A2
A3
A4
A5
A6
A7
A8
A9
VCCSW20
16
15
C38
0.1uF
1
MDLS-20265
(C) Advanced Micro Devices, Inc.
Top View
GND
Title
Test Interface Port (TIP)
2
1
Size
Document Number
Displays.SCH
Date: Monday, April 26, 1999
B
(800) 222-9323
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
*SPARE_20
AMD AM29F002T
A
2
U21
U21VO
VCC5
C
D
Rev
1.3
Sheet
E
5
of
8
A
B
VCC5
C
D
E
VCC5
VCC5
C40
C41
C42
C43
C44
C45
C46
C47
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
U23
VCC5
4
C48
C49
C50
C51
0.1uF
0.1uF
0.1uF
0.1uF
D0
D1
D2
D3
D4
D5
D6
D7
D7
D6
D5
D4
D3
D2
D1
D0
LEDOE#
HDRLTOE#
D[7:0]
7
18
31
42
VCC
VCC
VCC
VCC
1OE#
2OE#
3OE#
4OE#
1
48
25
24
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
28
34
39
45
GND
GND
GND
GND
GND
GND
GND
GND
21
4
10
15
OUTHDR0
OUTHDR1
OUTHDR2
OUTHDR3
OUTHDR4
OUTHDR5
OUTHDR6
OUTHDR7
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
4
OUTHDR[7:0]
LED[7:0]
TI 74ACT16244DGGR
LEDCLK
HDRLTCLK
DIPSWOE#
HDRBFOE#
SSL-LX15YGC-RP
VCC5
LED0
2
LED1
2
LED2
2
LED3
2
CR1
CR2
CR3
3 CRLN1
R68
220
3 CRLN2
R69
220
3 CRLN3
R70
220
3 CRLN4
R71
220
3 CRLN5
R80
220
3 CRLN6
R81
220
3 CRLN7
R82
220
3 CRLN8
R83
220
VCC5
3
3
R79 10K
R78 10K
R77 10K
R76 10K
R75 10K
R74 10K
VCC5
R73 10K
R72 10K
VCC5
SW4
0
|
8
7
6
5
4
3
2
1
INPDSW7
INPDSW6
INPDSW5
INPDSW4
INPDSW3
INPDSW2
INPDSW1
INPDSW0
9
10
11
12
13
14
15
16
INPHDR0
INPHDR1
INPHDR2
INPHDR3
INPHDR4
INPHDR5
INPHDR6
INPHDR7
1K
1K
1K
1K
1K
1K
1K
1K
R85
R86
R87
R88
R89
R90
R91
2
R84
AMP 3-435640-9
1
48
25
24
1OE#
2OE#
3OE#
4OE#
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
21
4
10
15
LED4
2
LED5
2
U25
U24
VCC
VCC
VCC
VCC
7
18
31
42
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
4A1
4A2
4A3
4A4
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
GND
GND
GND
GND
GND
GND
GND
GND
28
34
39
45
D7
D6
D5
D4
D3
D2
D1
D0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
TI 74ACT16244DGGR
48
25
1
24
1LE
2LE
10E#
2OE#
VCC
VCC
VCC
VCC
7
18
31
42
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
4
10
15
21
GND
GND
GND
GND
GND
GND
GND
GND
28
34
39
45
LED6
2
LED7
2
CR5
CR6
CR7
CR8
2
TI 74ACT16373DW
OUTHDR[7:0]
P7
1
3
5
7
9
11
13
15
17
19
1
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
OUTHDR0
OUTHDR1
OUTHDR2
OUTHDR3
OUTHDR4
OUTHDR5
OUTHDR6
OUTHDR7
CR4
OUTHDR0
OUTHDR1
OUTHDR2
OUTHDR3
OUTHDR4
OUTHDR5
OUTHDR6
OUTHDR7
2
4
6
8
10
12
14
16
18
20
1
(C) Advanced Micro Devices, Inc.
AMP 103308-5
SW OPS of AMP 3-435650-9
0
1
|
Top View
2
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
20
2 X 10
HEADER
16
A
SSL-LX15YGC-RP
Title
YEL
CATH
GRN
Size
3
1
Test Interface Port (TIP)
1
2
19
B
(800) 222-9323
Document Number
DataInfo.SCH
Date: Monday, April 26, 1999
C
D
Rev
1.3
Sheet
E
6
of
8
A
B
C
VCC5
X1
AUDX2
C58
C59
C66
0.1uF
0.1uF
0.1uF
33pf
VCC5
4.7
22uF
C CASE, 16
4
*0
*0
*0
0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
3
4
5
6
8
9
10
11
12
13
14
16
17
18
44
45
46
PRAB0
PRAB1
PRAB2
PRAB3
PRAB4
PRAB5
PRAB6
PRAB7
PRAB8
PRAB9
PRAB10
PRAB11
PRAB12
PRAB13
PRAB14
21
22
23
25
26
27
28
29
30
31
33
34
39
40
41
42
D0
D1
D2
D3
D4
D5
D6
D7
76
78
81
83
86
88
91
93
77
79
82
84
87
89
92
94
D[7:0]
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
PRAB0
PRAB1
PRAB2
PRAB3
PRAB4
PRAB5
PRAB6
PRAB7
PRAB8
PRAB9
PRAB10
PRAB11
PRAB12
PRAB13
PRAB14
PRAB15
[FLashWE#]
[SA19]
[DRQ3]
[DRQ7]
[DRQ6]
[DRQ5]
[DACK7#]
[DACK6#]
[DACK5#]
[LA17]
[LA18]
[LA19]
[LA20]
[LA21]
[SA22]
[SA23]
[SA16]
[SA17]
[SA18]
The main outer pin-out is for
the AM79C961A (TQFP 144)
configured in the BUS SLAVE
mode. The pin names in "[]"
are for the the device
configured in the BUS MASTER
mode.
[SA0]
[SA1]
[SA2]
[SA3]
[SA4]
[SA5]
[SA6]
[SA7]
[SA8]
[SA9]
[SA10]
[SA11]
[SA12]
[SA13]
[SA14]
[SA15]
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
[NC]
AMD AM79C961AVC
60
61
62
69
57
55
54
53
IOCHRDY
VCC5
SLEEP#
SLEEP#
IOCS16#
IOCHRDY
SHFBUSY
SRWE#
SROE#
75
58
49
135
47
65
DXCVR/EAR#
BPCS#
LED0
LED1
LED2
LED3
119
136
124
123
121
120
CI+
CIDI+
DIDO+
DO-
117
116
115
114
112
111
CI R112 40.2
CINEG
DIPOS
DI
R115 40.2
TXDTXD+
TXPDTXPD+
RXDRXD+
100
102
99
101
96
97
TXNEG
TXPOS
TXDNEG
TXDPOS
RXNEG
RXPOS
PRDB3
PRDB4
PRDB5
PRDB6
PRDB7
131
129
128
127
126
TDO
TMS
TDI
TCK
PCMCIA_MODE
139
140
138
141
71
PRDBO/EESK
PRDB1/EEDI
PRDB2/EEDO
EECS
134
133
132
137
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
35
36
37
72
73
107
108
109
143
144
IOCHRDY
SSL-LX15YGC-RP
SHFBUSY
SRWE#
SRAMOE#
R109
330
RESLED0
ENETLED0
ENETLED1
ENETLED2
ENETLED3
CINCIP
R113 40.2
C62
RESLED1
3
R111
330
RESLED2
3
R114
330
RESLED3
1
CR10
1
CR11
3
1
CR12
3
1
P8
3
1
TDXTDX+
4
2
TXPTXP+
PRDB3
PRDB4
PRDB5
PRDB6
PRDB7
14
16
RXDRXD+
PRDB0
PRDB1
PRDB2
EECS
2
3
4
1
1
2
3
4
5
6
7
8
Pulse E2003
U27
VCC
NC
NC
GND
8
7
6
5
TD+
TD-
8
6
TDPOS
TDNEG
RD+
RD-
9
11
RDPOS
RDNEG
1
2
3
4
5
6
7
8
VCC5
U28
SK
DI
DO
CS
2
NATIONAL SEMI NM93C56N
VCC5
PRDB[7:0]
VCC5
C64
C65
0.1uF
0.1uF
U29
55659-1
Top View
From component side
1
CR9
3
R110
330
0.1uF
R116 40.2
DINDIP
C63
0.1uF
AVSS2
PRAB[14:0]
R101
IRQ4
IRQ5
IRQ9
IRQ10
IRQ11
SRCS#
IRQ15
2
7
15
24
32
43
52
64
80
90
95
122
130
105
110
2
SMA#
[MASTER#]
RESET
AEN
BPAM#
IOR#
IOW#
SBHE#
MEMR#
MEMW#
REF#
SMAM# [DACK3#]
IRQ3
IRQ4
IRQ5
IRQ9
IRQ10
IRQ11
IRQ12
IRQ15
15
A[19:0]
XTAL1
XTAL2
12
BPAM#
SHBE#
MEMR#
MEMW#
REF#
SMAM#
3
70
48
59
67
68
19
51
50
63
66
15
SMA#
1K
5
RD#
WR#
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
AVSS2
AVSS1
104
106
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
AVDD
AVDD
AVDD3
AVDD2
U26
TRESET
AEN
IRQ3
20
38
56
74
85
125
142
98
113
103
118
R107
R106
R105
R104
*0
10K 10K
0
R103
*0
1K
R108
R102
*0
R100
1K 1K 1K 1K
C61
R92
1K
C60
0.1uF
5
VCC5
12
VCC5
4
ENETIRQ
R99
R119
33pf
R98
0.1uF
R97
0.1uF
R96
0.1uF
C53
R95
0.1uF
AUDX1
C52
R94
C57
R93
C56
AVSS2
C55
E
NOTE:
For anolog decoupling, the boxed in area should be
routed as shown, and the capacitors should be connected to the prescribed pins, not vias.
FILTAVDD
C54
D
L1
GND
VCC5
PRAB1
PRAB3
PRAB5
PRAB7
PRAB9
PRAB11
PRAB13
16
14
12
10
3
2
5
A1
A3
A5
A7
A9
A11
A13
PRDB0
PRDB2
PRDB4
PRDB6
18
20
23
25
I/O1
I/O3
I/O5
I/O7
6
1
27
R/W
OE#
CE#
A0
A2
A4
A6
A8
A10
A12
A14
17
15
13
11
4
28
9
8
PRAB0
PRAB2
PRAB4
PRAB6
PRAB8
PRAB10
PRAB12
PRAB14
I/O2
I/O4
I/O6
I/O8
19
22
24
26
PRDB1
PRDB3
PRDB5
PRDB7
VCC
VSS
7
21
VCC5
1
TOSHIBA TC55257DFTI-70V
Mounting Hole Layout
Front View
(C) Advanced Micro Devices, Inc.
2
8
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
SSL-LX15YGC-RP
1 2 3 4 5 6 7 8
1
7
3
ECCM63-50-20.000MTR
YEL
CATH
GRN
1
Title
Test Interface Port (TIP)
2
Size
Top View
Document Number
Ethernet.SCH
Date: Monday, April 26, 1999
A
B
(800) 222-9323
C
D
Rev
1.3
Sheet
E
7
of
8
A
B
C
D
E
P9
1
3
5
7
9
11
13
15
A18 17
A16 19
4
SERINT0
SERINT1
PARCS#
SERCS0#
SERCS1#
+5V
CLK1
D14
D12
D10
D8
D6
D4
D2
D0
CLK2
D15
D13
D11
D9
D7
D5
D3
D1
GND
2
4
6
8
10
12
14
16
18
20
4
TIPFLHCS#
IOCHRDY
PARINT
ENETIRQ
A19
A17
AMP 103308-5
HEADER, 2 X 10
P10
A14
A12
A10
A8
A6
A4
A2
A0
1
3
5
7
9
11
13
15
17
19
+5V
CLK1
D14
D12
D10
D8
D6
D4
D2
D0
CLK2
D15
D13
D11
D9
D7
D5
D3
D1
GND
2
4
6
8
10
12
14
16
18
20
A15
A13
A11
A9
A7
A5
A3
A1
AMP 103308-5
3
3
HEADER, 2 X 10
A[19:0]
P11
RD#
WR#
AEN
S2
RD#
WR#
AEN
S2
TD6
TD4
TD2
TD0
2
1
3
5
7
9
11
13
15
17
19
+5V
CLK1
D14
D12
D10
D8
D6
D4
D2
D0
CLK2
D15
D13
D11
D9
D7
D5
D3
D1
GND
2
4
6
8
10
12
14
16
18
20
FLASHRD#
FLASHWR#
HRESET#
MAIN_IRQ
TD7
TD5
TD3
TD1
2
AMP 103308-5
HEADER, 2 X 10
TD[7:0]
HP Conn.
SPARES
2
SN74ACT04PW
14
VCC5
VCC5
U11B
U11C
14
1
S1
1
S2
2
SPRB 3
4
6
5
SPRC
1
2
1
1
VCC5
U11D
S3
1
U11E
U11F
(C) Advanced Micro Devices, Inc.
14
14
14
7
VCC5
7
VCC5
S4
2SPRD 9
8
1
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
S5
2SPRE 11
10
12
13
SPRF 1
(800) 222-9323
2
Title
20
7
7
Test Interface Port (TIP)
7
19
Size
Top View
Document Number
Debug.SCH
Date: Monday, April 26, 1999
A
B
C
D
Rev
1.3
Sheet
E
8
of
8