GigaPHY(TM) -SD Device GDPHYSD_1B Eval Board Gigabit Ethernet PHY Solutions Users Manual GigaPHY-SD Gphysd_1b Gigabit Evaluation Board GigaPHY(TM) -SD Device Physical Layer 10-Bit Transceiver for Gigabit Ethernet Last Updated 11/04/97 1997 Advanced Micro Devices Trademark Information 1 of 7 GigaPHY(TM) -SD Device GDPHYSD_1B Eval Board Features • • • • • • • Evaluation System for use in studying the GigaPHY™ Am79761. Switches for Driving Control Lines. LED’s for Monitoring Control Lines. On Board Generation of 3.3V from External 5V through 12V supply. Internal or External Clock Source. 10-bit Transmit Data Provided From Switches or onboard PAL or from a Pattern Generator. 10-bit Receive Data Monitored on LED’s or Through a Logic Analyzer Pod. Block Diagram SW Shutdown 3.3 Voltage Regulator OSC INT. EXT. SMA SMA SW SEL[0] SW SEL[1] PAL Or Switch TXD[9:0] Logic Analyzer/Pattern Pod AM79761 GigaPHY™ Ethernet PHY SW EWRAP SW EN_CDET RXD[9:0] Logic Analyzer Pod Last Updated 11/04/97 1997 Advanced Micro Devices Trademark Information 2 of 7 B U F F E R S RXD[9:0] L E D S GigaPHY(TM) -SD Device GDPHYSD_1B Eval Board General Description The GigaPHY™ GPHYSD_1B Board, provides a low cost, easy-to-use tool to evaluate the Gigabit Transceiver, AM79761, with regard to signal quality and performance. It is intended that the GigaPHY™ board be a self-contained Evaluation Unit. In its simplest form, the switches on the GPHYSD_1B can be used to set the transmit data and control lines while monitoring received data and status lines with LED’s. A pre-programmed PAL in addition to the switch settings can generate simple word patterns. More in-depth evaluations can be implemented by connecting a Pattern Generator (10-bits at 125MHz) to pods on the board in order to generate transmit data and control signals. A logic analyzer can also be connected to pods on the board in order to monitor receive data and status signals. With this setup 8B/10B data can be sent to the transmitter on the Evaluation Unit to generate Gigabit data and monitored on the Logic Analyzer. Other useful features of the board include the presence of an on-board, removable oscillator with Tristate (normally at 125MHz) in a DIP, half DIP or Surface Mount form. An on-board voltage regulator is used to provide 3.3V to the board with a shutdown switch used to turn off power to all components. Scope of this Document It is intended that the AM79761 datasheet be used for reference in understanding the device function. Additionally, the following items are enclosed in this document: 1. 2. 3. 4. Schematics for the board Artwork for the board (copies of each layer) Fabrication drawing for the board Bill of materials for the board. Operation and Switch Settings HP1 HP2 LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 LED9 LED10 LED11 LED12 LED13 LED14 LED15 LED16 LED17 P1 P2 P3 TXD Logic Analyzer/Pattern input RXD Logic Analyzer RXD[0] Status RXD[1] Status RXD[2] Status RXD[3] Status RXD[4] Status RXD[5] Status RXD[6] Status RXD[7] Status RXD[8] Status RXD[9] Status COMDET Comma Character Status +5POS External Power Supply Input indicator +3.3 Power Supply Input indicator /SHDN Status for Voltage Regulator if [ON] Shutdown [OFF] Enabled SEL[0] SEL[1] EWRAP EN_CDET /SHDN [H] Voltage Regulator is [ON] Power to DUT [L] Shuts down the Voltage Regulator[OFF] No power to DUT. SEL[0] SEL[1] P4 P5 PWR1 PWR2 SMA1 EWRAP EN_CDET Ext. Lab bench +5V DC supply Ext. Wallmount +5V DC supply External 125Mhz Clock Install [0]ohm resistor R2 and W1[to Tristate Clock Crystal]. SMA2 TX[+] Output SMA3 TX[-] Output SMA4 RX[+] Output SMA5 RX[-] Output SMA6 RCLKN Output SMA7 RCLK Output SW1 Manual Setting to TXD[0:9] U1 AM79761 U2 PAL for TXD[0:9] inputs U3 Buffer to LED’s U4 Buffer to LED’s VR1 +5POS to +3.3POS Voltage Regulator with Shutdown. W1 TRI-STATE Jumper to Tri-State Clock Crystal output. X1 125 MHz Clock Crystal. ZTP1 VDDIN [+5 volt power supply]. ZTP2 +5POS going to Voltage regulator. ZTP3,5,6,7 DVSS ZTP4 DVSS Last Updated 11/04/97 1997 Advanced Micro Devices Trademark Information 3 of 7 GigaPHY(TM) -SD Device GDPHYSD_1B Eval Board Operation The GigaPHY™ eval board provides potential customers with a simple, easy-to-use evaluation tool for understanding the function and performance of the AM79761 10-bit Gigabit Transceiver. A 125MHz 3.3V crystal oscillator provides a reference clock (REFCLK) to the AM79761. The clock trace has been minimized to provide the best signal quality possible. Since REFCLK is used to latch data into the AM79761, the trace length between the REFCLK clock and the TXD[0-9] data should be kept somewhat similar (i.e. within 1”) so as to maximize the timing margin for the chip generating the transmit data. The recovered clocks, RCLK and RCLKN, can be monitored through the SMA connectors. The TEST pins of the AM79761 are tied HIGH for manual switch operation. The EN_CDET pin, which is set by a switch, allows SYNC detection and framing. When EN_CDET is enabled, the detection of COMMA will generate a COM_DET, which is monitored by an LED. In order to select loopback mode, the EWRAP must be HIGH which will cause the parallel input data TXD[0-9] be wrapped around inside the AM79761 and outputed as RXD[0-9] and the TX[+/-] outputs will be held high. The on board 125 MHz oscillator generates the transmit clock for the AM79761 (REFCLK). TXD[0-9] is latched into the AM79761 on every rising edge of this clock. The AM79761 recovers the data with the word-oriented clock (RBC-) at 62.5MHz. An on-board diagnostic path is provided to allow testing of the board. The input parallel data can be generated by a 10-bit switch or by a pre-programmed PAL. The 10-bit switch only allows a static 10 bit word pattern but the PAL can be used to generate a longer repetitious word patterns. A more sophisticated word pattern can be generated from a Pattern Generator through the pod connector. If nonloopback mode is selected, the parallel, TXD[0-9], will be serialized by the AM79761 and pumped out through the TX[+/-]. Then, the high-speed serial data is received through the RX[+/-] into the AM79761 and is deserialized to a 10-bit parallel data bus, RXD[0-9]. LED’s or a logic analyzer through the on-board pod can monitor the RXD[0-9]. For a 50 ohm environment, the AM79761 transmitters PECL outputs drive 50 ohm traces with a 182 ohm current sinking resistor and an AC-coupled 0.01uF capacitor to the 50-ohm SMA connectors labeled TX[+] (SMA1) and TX[-] (SMA2). The resistor-capacitor termination circuit are needed to supply current and decouple the 3.3V-referenced PECL outputs of the AM79761 from the PECL-levels required on the coaxial cable. The AM79761 receives differential PECL serial data from the coax cable on the 50-ohm SMA connectors labeled RX+/-. This input is immediately AC-coupled through a 0.01uF capacitor and terminated with 182-ohm pull-down resistors. The AM79761 provides internal resistors to set the DC Bias to Vdd/2. The termination resistors and AC coupling caps are located as near as possible to the input pins on the AM79761 to maximize signal quality. The Evaluation board has voltage regulator that supplies the board with 3.3Volts. The input to the voltage regulator can be from 5 volts DC to 12 volts DC from either a lab bench supply through PWR1 or from a wall mounted supply through PWR2. The voltage regulator output can be shutdown with the shutdown a switch [P1]. When LED13 is ON the regulator output is OFF. PAL and Manual Switch Pattern Generator Settings SEL[0] L SEL[1] L Undetermined Undetermined SEL[0] L SEL[1] H Pseudorandom SEL[0] H SEL[1] L 00111100xx Repeating 00111100xx SEL[0] H SEL[1] H Alternating Alternating +/- K28.5 Note; for the PAL to output the right data the Manual switch setting SW1 all have to be off. Note; for the Manual Switch to work , the PAL has to be removed. Last Updated 11/04/97 1997 Advanced Micro Devices Trademark Information 4 of 7 GigaPHY(TM) -SD Device GDPHYSD_1B Eval Board Layout Considerations The board has been designed in a simple, straightforward manner in which highest priority was given to properly routing of high-speed signals. This four layer, controlled impedance PCB contains signal layers on the top and bottom of the board with internal Power (Vdd=3.3V) and GND planes. Components are mounted on both sides of the board so that passives may be placed as close as possible to their ideal location regardless of which side of the board the part is placed. The PCB accommodates a special socket for the AM79761 so placement of passives on the topside near the pins was not possible. The 1Gb/s transmit and receive signals between the chipset and the connector were the first priority. Since they form a differential PECL pair these traces were of minimal and equal length and, in this example, have characteristic impedance of 50 ohm. The passive components should be packed as closely as possible to minimize stub lengths and maximize signal quality. On the receiver inputs, minimization of trace length between the AC Coupling Caps (C28/C29), the input pins (RX[+],RX[-]) and the 182 ohm termination resistors are very important since the terminator resistors act as the virtual end of the line. Stubs on these lines will cause degradation of signal quality into the receivers due to reflections. Diagonal corners were used so as to avoid the impedance mismatches found in right angle traces. The same considerations as other high-speed signals apply here. Transmit data jitter is generated through two main factors: Power Supply Noise and TBC jitter. Proper layout of the REFCLK traces is essential to minimize REFCLK jitter into the part. Curved traces are used to minimize reflections. Generous bypassing of the power supplies and separate isolation and decoupling for each sensitive supply type is one easy method to eliminate much of this noise. In general, common layout/placement techniques developed for lower speed PCBs apply here and should lead to first-pass success. Last Updated 11/04/97 1997 Advanced Micro Devices Trademark Information 5 of 7 GigaPHY(TM) -SD Device GDPHYSD_1B Eval Board Table 1: Bill of Materials Part Number Manufacture Reference Number 1) Item 2 Qty. Device Description Straight .1”x.1” 20 pin Low Profile Header 2520-6002UG 3M HP1-2 2) 1 Gigabit Ethernet Transceiver AM79761 AMD U1 3) 1 2 pin jumper 103240-1 AMP W1 4) 1 Shunt 15-38-1024 MOLEX W1 5) 1 Euro Terminal Block 2 PIN 5LEV-02 Augot PWR1 6) 1 Augot/Alcoswitch SW1 7) 5 10 Position Surface Mount Extended Actuator Dip ADE10S Switch Surface Mount Toggle Switch SPDT GT11MSCKE C&K P1-5 8) 7 P.C. Pin 10-8025-2-03 Concord ZTP1-7 9) 1 Power Supply Jack PJ-002 Cui/Stack Inc. PWR2 10) 1 49.9 ohm Resistor CRCW080549R9F DALE R1 11) 1 0 ohm Resistor CRCW1206000J DALE R3 12) 5 0 ohm Resistor CRCW0805000J DALE R4,R6,R31-33 13) 4 182 ohm Resistor CRCW12061820F DALE R5,R7,R34-35 14) 5 10K ohm Resistor CRCW08051002F DALE R8,R11,R14,R26,R29 15) 16 301 ohm Resistor CRCW08053010F DALE 16) 1 1K ohm Resistor CRCW08051001F DALE R9,R13,R25,R27,R30,R3646 R10 17) 1 619 ohm Resistor CRCW08056190F DALE R12 18) 10 4.75K ohm Resistor CRCW08054751F DALE R15-24 19) 1 750 ohm Resistor CRCW08057500F DALE R28 20) 3 Straight PC mount Jack Receptacle 142-0701-201 E-F-Johnson SMA1,SMA6-7 21) 4 End Launch PC mount Jack Receptacle 142-0701-801 E-F-Johnson SMA2-5 22) 1 Wound Bead 29-43-666681 Fair-Rite FB1 23) 6 0.01MF COG Ceramic Capacitor C1812C103J5GAC Kemet C6-9,C30-31 24) 1 0.1MF X7R Ceramic Capacitor C1206C104K5RAC Kemet C10 25) 1 1000pf X7R Ceramic Capacitor C0805C102J5RAC Kemet C32 26) 1 High Performance EECMOS PLD 3.3volt GAL22LV10D-4LJ Lattice U2 27) 1 28 pin PLCC SMT socket 822066-4 AMP U2 28) 10 "ULTRA Yellow" Surface Mount LED SML10Y4B-TR LEDTRONICS LED0-9 29) 7 "HI-EFF Green" Surface Mount LED SML10G4B-TR LEDTRONICS LED10-12,LED14-17 30) 1 "ULTRA Red" Surface Mount LED 'SML10R6C-TR LEDTRONICS LED13 31) 1 LT1529CT-3.3 Linear Technology VR1 32) 1 Thermalloy 4880 VR1 33) 1 .+3.3V Low Dropout Micropower Voltage Regulator 3A TO-220 Mounting Kit Heat Sink for To-220 Thermalloy 6078B VR1 34) 1 SMF Omni-Blok Fuse Block with 750MA Fuse 154750 LittleFuse F1 36) 1 H3390-125 MF Electronics X1 37) 6 125 MHz Half-size Clock Crystal 3.3Volt with TRI_STATE Mini Spring Socket 50935-1 AMP X1 38) 1 Empty do not stuff N/A N/A R2 39) 2 Low Voltage Octal Buffer/Line Driver 74LCX540WM U3-4 40) 20 0.01MF X7R Ceramic Capacitor ECU-V1H103KBG National Semiconductor Panasonic 41) 3 33MF Tantalum Chip Capacitor 16WV 293D336X9016D2T Sprague C1,C3,C22 35) Last Updated 11/04/97 1997 Advanced Micro Devices Trademark Information 6 of 7 C4-5,C11-21,C23-29 GigaPHY(TM) -SD Device GDPHYSD_1B Eval Board Item Qty. Device Description Part Number Manufacture Reference Number 42) 1 100MF Electrolytic Capacitor 518D107M016AX7S Sprague C2 43) 1 Ferrite Bead inductor TDKBC50-1206 TDK FB2 44) 6 ASMCO ZM1-6 45) 6 ASMCO ZM1-6 46) 1 NYLON Slotted Round Head Machine Screw 112508 Thread 6-32 Length 3/8” Nylon Threaded Spacer, Thread 6-32 Length ½” 1530 H – N -.500 - 1 Lab Bench Power Supply Cable 12” Hookup wire for power supply Red M16878/5-BGE-2 47) 1 12” Hookup wire for power supply Black Anixter 48) 2 Plastic tiedowns 3-3/4” 49) 1 Switching Power Supply M16878/5BGE-0 4200 Wall Power Supply DSA-0301-05 Last Updated 11/04/97 1997 Advanced Micro Devices Trademark Information 7 of 7 Anixter ASMCO DVE A B C D 1 1 Gigabit Transceiver Section REFCLK LEDS LED[10:0] REFCLK REFCLK LED[10:0] LED[10:0] SYSTEM CLK 2 2 LED.1 SYSCLK.1 Page 5 Page 6 GIGABIT.1 Pages 2 to 4 EXTERNAL POWER 3 3 SUPPLY PWRSUPLY.1 Page 7 ADVANCED MICRO DEVICES COPYRIGHT 1997 AMD SCHEMATIC DIAGRAM APPROVED BY: Gigabit Ethernet Transceiver 1000Base-X Eval. Brd. DATE 4 MODULE SHEET 1 GPHYSD_1B DRAWN BY Steve Cooper A B ENGINEER Robert Hartman C SIZE DWG. NO. D GPHYSD_1B DATE 4 BRD. NO. B GPHYSD_1B PAGE 10-23-1997_14:48 D REV 1 of 7 A C B EWRAP D HP2 HP1 LOW Normal operation. High internal loopback H.P. 100K OHM TERMINATION EN_CDET LOW Current word alignment. HIGH Enables COM_DET HIGH Enables word resynchronization. 01650-63203 01650-63203 1 D15 4 D14 5 D13 6 D12 7 D8 11 D11 8 D10 9 D9 10 D7 12 D6 13 D5 14 D4 15 D3 16 D2 17 D1 18 D0 19 CLK1 3 CLK2 2 +5V 1 GND 20 D15 4 D14 5 D13 6 D12 7 D8 11 D11 8 D10 9 D9 10 D7 12 D6 13 D5 14 D4 15 D3 16 D2 17 D1 18 D0 19 CLK1 3 CLK2 2 +5V 1 GND 20 1 ADAPTER (OUTPUT) (OUTPUT) LOW disables COM_DET 20PSHEAD 20PHEAD H.P. 100K OHM TERMINATION ADAPTER 20PSHEAD 20PHEAD DVSS 4 TXD[3] TXD[3] 6 TXD[4] TXD[4] 7 TXD[5] TXD[5] 8 TXD[6] TXD[6] TXD[7] TXD[7] 11 TXD[8] TXD[8] 12 TXD[9] TXD[9] 13 9 2 REFCLK EWRAP 22 EWRAP 19 EN_CDET 24 1 3 REFCLK TXD[1] RXD[1] TXD[2] RXD[2] TXD[3] RXD[3] RXD[4] TXD[4] RXD[9] RXD[8] RXD[7] RXD[6] RXD[5] RXD[4] RXD[3] RXD[2] RXD[1] RXD[0] EN_CDET EWRAP COM_DET RXD[0] RXD[0] 44 RXD[1] RXD[1] 43 RXD[2] RXD[2] 41 RXD[3] RXD[3] 40 RXD[4] RXD[4] 39 RXD[5] RXD[5] TXD[5] RXD[5] TXD[6] RXD[6] 38 RXD[6] RXD[6] TXD[7] RXD[7] 36 RXD[7] RXD[7] 35 RXD[8] RXD[8] 34 RXD[9] RXD[9] TXD[8] RXD[8] TXD[9] RXD[9] REFCLK RCLK EWRAP RCLKN EN_CDET COM_DET 30 RCLKN 47 COM_DET 1 3 23 26 DVDD 2 DVSS SMA7 TEST[1] TEST[2] TX[+] SMA_STR SMA_STR TEST[4] TX[-] DVSS RX[+] R32 RC0805 0.01MF 61 TX[-] 54 RX[+] 52 RX[-] DVSS SMA6 DVDD RCLKN 1 SMA_STR 2 SMA_STR R33 RX[-] DVSS DVSS 1 of 2 0R RC0805 DVSS 1 AM79761 R31 C14 RCLK TX[+] 62 TEST[3] 2 20 EN_CDET 2 COM_DET 2 18 RXD[9:0] RCLK 31 DVSS P5 SPDT SPDT A1 IN 5 3 TXD[2] 45 4 TXD[1] TXD[2] RXD[0] 3 TXD[1] TXD[0] 5 LED16 2 2 4 R29 10K RC0805 R26 10K RC0805 1 LED17 GRN_LED LED1206 1 GRN_LED LED1206 TXD[0] 2 P4 SPDT SPDT RCLK RCLKN TXD[9] TXD[8] TXD[7] TXD[6] U1 TXD[0] 3 R27 301 RC0805 R30 301 RC0805 A1 IN TXD[5] TXD[9:0] TXD[4] DVDD TXD[3] DVDD TXD[2] DVDD TXD[1] REFCLK DVDD TXD[0] DVSS AM79761A NC=16,17,27,48,49,64 OZ64PQFP 3 3 AM79761 4 5 DVSS SMA3 1 SMA_JEL SMA_JEL DVSS DVSS DVSS R7 R5 182 RC0805 182 RC0805 R35 182 RC0805 R34 182 RC0805 DVSS 5 0R RC0805 5 4 2 R6 SMA_JEL 3 C5 0.01MF RC0805 TX[-] SMA_JEL 2 SMA_JEL DVSS SMA5 DVSS SMA_JEL DVSS 1 RX[-] 1 0R RC0805 5 4 3 2 DVSS SMA2 TX[+] SMA_JEL 3 SMA_JEL 4 1 C29 0.01MF RC0805 C4 0.01MF RC0805 R4 3 RX[+] SMA4 2 C28 0.01MF RC0805 DVSS ADVANCED MICRO DEVICES COPYRIGHT 1997 AMD 4 C24 RC0805 0.01MF C18 RC0805 0.01MF DVSS SCHEMATIC DIAGRAM APPROVED BY: DATE Gigabit Ethernet Transceiver 1000Base-X Eval. Brd. DVSS MODULE SHEET SIZE GIGABIT 1 D DRAWN BY Steve Cooper A 4 B C ENGINEER Robert Hartman DWG. NO. BRD. NO. QPHYSD_1B QPHYSD_1B DATE PAGE 2 of 7 10-21-1997_9:52 D REV B A C B D U3 74LCX540 From 10-bit receive outputs. RXD[9:0] A1 IN 1 20PSOLIC DVDD;20 DVSS;10 A2 RXD[0] RXD[0] 2 A3 RXD[1] RXD[1] 3 A4 RXD[2] RXD[2] 4 A5 RXD[3] RXD[3] 5 A6 RXD[4] RXD[4] 6 A7 RXD[5] RXD[5] 7 A8 RXD[6] RXD[6] 8 A9 RXD[7] RXD[7] 9 A1 Y1 A2 Y2 A3 Y3 A4 Y4 A5 Y5 A6 Y6 A7 Y7 A8 1G Y8 LED[10:0] A1 IN 18 LED[0] LED[0] A2 17 LED[1] LED[1] A3 16 LED[2] LED[2] A4 15 LED[3] LED[3] A5 14 LED[4] LED[4] A6 13 LED[5] LED[5] A7 12 LED[6] LED[6] A8 11 LED[7] LED[7] A9 18 LED[8] LED[8] A2 17 LED[9] LED[9] A3 16 LED[10] LED[10] A4 To LED Block 1 2G 1 19 DVSS U4 74LCX540 A1 IN 20PSOLIC DVDD;20 DVSS;10 A2 RXD[8] RXD[8] 2 A3 RXD[9] RXD[9] 3 COM_DET 4 DVDD A1 5 6 7 DVDD 8 R9 301 RC0805 2 9 DVDD DVDD Y1 A2 Y2 A3 Y3 A4 Y4 A5 Y5 A6 Y6 A7 Y7 A8 1G Y8 A1 IN 15 14 13 2 12 11 2G DVDD R11 R8 4 3 REFCLK SEL[0],SEL[1]=[1,0]....Repeating 00111100xx 2 SEL[0],SEL[1]=[0,0]....Not definded R24 2 6 5 SEL[0],SEL[1]=[0,1]....Pseudo-random R23 1 3 9 SEL[0],SEL[1]=[1,1]....Alternating +/- K28.5 R22 10 DVSS R21 2 2 11 SEL[1] To 10-bit transmitt inputs. I10 12 P3 SPDT SPDT R20 I11 R19 13 R18 16 SEL[1] 1 3 LED15 SEL[0] R17 SEL[0] DVSS R16 2 1 GRN_LED LED1206 4.75K RC0805 U2 GAL22LV10 R15 10K RC0805 10K RC0805 LED14 P2 SPDT SPDT 7 3 19 DVSS 1 GRN_LED LED1206 R13 301 RC0805 1 I9 IO9 I8 IO8 I7 IO7 I6 IO6 I5 IO5 I4 IO4 I3 IO3 I2 IO2 I1 IO1 CLK/IO IO0 27 TXD[0] TXD[0] 26 TXD[1] TXD[1] 25 TXD[2] TXD[2] 24 TXD[3] TXD[3] 23 TXD[4] TXD[4] 21 TXD[5] TXD[5] 20 TXD[6] TXD[6] 19 TXD[7] TXD[7] 18 TXD[8] TXD[8] 17 TXD[9] TXD[9] TXD[9:0] 3 GAL22LV10 AMP28PLCC NC=1,8,15,22 DVSS;14 DVDD;28 SW1 DIP SWITCH 1 2 3 4 5 20 TXD[0] TXD[0] A2 B2 19 TXD[1] TXD[1] A3 B3 18 TXD[2] TXD[2] A4 B4 17 TXD[3] TXD[3] B5 16 TXD[4] TXD[4] TXD[5] TXD[5] A5 A6 B6 15 7 A7 B7 14 TXD[6] TXD[6] B8 13 TXD[7] TXD[7] B9 12 TXD[8] TXD[8] B10 11 TXD[9] TXD[9] 9 DVDD B1 A1 6 8 DVDD A1 IN A8 A9 10 A10 DVSS DVDD A1 IN ADVANCED MICRO DEVICES COPYRIGHT 1997 AMD 4 ADE10S ADE10S C30 C7 RC1812 0.01MF RC1812 0.01MF RC1812 0.01MF DVSS C31 DVSS Manual Transmitt inputs. SCHEMATIC DIAGRAM APPROVED BY: DATE Gigabit Ethernet Transceiver 1000Base-X Eval. Brd. DVSS MODULE BOARD DRAWN BY Steve Cooper A B 4 C SHEET SIZE 2 D ENGINEER Robert Hartman DWG. NO. BRD. NO. QPHYSD_1B QPHYSD_1B DATE PAGE 10-15-1997_13:36 D 3 of 7 REV B A B C D 1 1 DVDD DVDD DVDD DVDD DVDD DVDD DVDD U1 5 10 28 50 C12 0.01MF RC0805 55 C25 0.01MF RC0805 59 C19 0.01MF RC0805 2 15 21 25 51 56 DVSS VDDD[4] VDDD[5] VSSA 2 SM_BEAD RC1206 C17 0.01MF RC0805 VDDD[3] 58 VDDD[6] DVSS VDDP[1] 14 DVSS 1 57 VDDD[2] C16 0.01MF RC0805 1 DVSS VDDA DVDD C20 0.01MF RC0805 C11 0.01MF RC0805 FB2 VDDD[1] DVSS DVSS DVSS VSSD[1] VDDP[2] VSSD[2] VDDP[3] VSSD[3] VDDT[1] VSSD[4] VDDT[2] VSSD[5] VDDT[3] DVDD 2 of 2 VSST[3] DVDD 63 2 29 37 42 C26 0.01MF RC0805 C27 0.01MF RC0805 VSST[1] DVDD 60 VSSD[7] VSST[2] DVDD 53 VSSD[6] AM79761 Power DVDD C23 0.01MF RC0805 C13 0.01MF RC0805 C15 0.01MF RC0805 C21 0.01MF RC0805 32 33 46 DVSS AM79761B DVSS DVSS DVSS DVSS DVSS NC=16,17,27,48,49,64 OZ64PQFP AM79761 DVDD 3 3 1 + 2 C22 33MF [D]7343 DVSS ADVANCED MICRO DEVICES COPYRIGHT 1997 AMD SCHEMATIC DIAGRAM APPROVED BY: Gigabit Ethernet Transceiver 1000Base-X Eval. Brd. DATE 4 MODULE SHEET BOARD DRAWN BY Steve Cooper A B 3 ENGINEER Robert Hartman C SIZE DWG. NO. D GPHYSD_1B DATE 4 BRD. NO. GPHYSD_1B PAGE 10-6-1997_14:03 D 4 of 7 REV B A B DVDD C DVDD DVDD DVDD DVDD D DVDD DVDD DVDD DVDD DVDD DVDD 1 1 R46 301 RC0805 R45 301 RC0805 R44 301 RC0805 R43 301 RC0805 R42 301 RC0805 R41 301 RC0805 R40 301 RC0805 R39 301 RC0805 R38 301 RC0805 R37 301 RC0805 R36 301 RC0805 1 LED10 LED9 GRN_LED LED1206 1 LED8 YEL_LED LED1206 1 LED7 YEL_LED LED1206 1 LED6 LED5 YEL_LED LED1206 1 YEL_LED LED1206 1 LED4 YEL_LED LED1206 1 LED3 YEL_LED LED1206 1 LED2 YEL_LED LED1206 1 LED1 YEL_LED LED1206 1 LED0 YEL_LED LED1206 1 YEL_LED LED1206 2 2 2 2 2 2 2 2 2 2 2 2 2 LED[10:0] A1 IN A1 IN 3 A2 LED[0] A3 LED[1] A4 LED[2] A5 LED[3] A6 LED[4] A7 LED[5] A8 LED[6] A9 LED[7] A2 LED[8] A3 LED[9] A4 LED[10] R[0] R[1] R[2] R[3] R[4] R[5] R[6] R[7] R[8] 3 R[9] COM_DET ADVANCED MICRO DEVICES COPYRIGHT 1997 AMD SCHEMATIC DIAGRAM APPROVED BY: Gigabit Ethernet Transceiver 1000Base-X Eval. Brd. DATE 4 MODULE LEDS DRAWN BY Steve Cooper A B SHEET 1 ENGINEER Robert Hartman C SIZE DWG. NO. D GPHYSD_1B DATE 10-22-1997_10:48 4 BRD. NO. GPHYSD_1B PAGE D 5 of 7 REV B A B C D 1 1 DVDD DVDD R10 C6 1K RC0805 0.01MF RC1812 C32 DVSS 1000pF RC0805 P8 +3.3V ENABLES CLK OUTPUT DVDD P8 DVSS DISABLE CLK OUTPUT X1 2 2 W1 1 1 DVSS TRI 14 VCC 4 HDR2 JUMPER2 2 11 R3 7 DVSS GND 8 CLK 125_OSC_CLKA REFCLK REFCLK 0R RC1206 125MHZ_TR XSTAL_XX EMPTY RC1206 R2 SMA1 SMA_STR 1 125_EXT_CLK SMA_STR 49R9 RC0805 DVSS 2 3 DVSS 4 5 3 R1 3 DVSS ADVANCED MICRO DEVICES COPYRIGHT 1997 AMD SCHEMATIC DIAGRAM APPROVED BY: Gigabit Ethernet Transceiver 1000Base-X Eval. Brd. DATE 4 MODULE SHEET 1 SYSCLK DRAWN BY Steve Cooper A B ENGINEER Robert Hartman C SIZE DWG. NO. D GPHYSD_1B DATE 4 BRD. NO. B GPHYSD_1B PAGE 10-15-1997_13:38 D REV 6 of 7 A B C D From +5Volt Regulated External Power Supply ZTP1 PWR2 1 3 VDDIN 1 5POS 5.5V External 2 VDDIN_A 750MA EXTPWR PJ002 ZTP2 FB1 F1 2 1 SMF154 1 3 2 4 1 C9 0.01MF RC1812 FB3 W_BEAD + C10 0.1MF RC1206 C2 100MF AECAP-D DVSS PWR1 SYSGND 1 +V_IN 2 -V_IN PWRCON2 2POS_PWR SYSGND 5POS 5POS DVDD 2 R28 C3 33MF [D]7343 1 [ON] Output OFF 2 2 DVSS + 1529CT33 TO220-5 ZTP4 2 5 IN OUT 1 1 3 SD SENSE GND1 3 2 DVSS DVSS DVSS ZTP7 C1 33MF [D]7343 + 4 3.3V Internal ZTP3 1 2 2 Supply Indicator ZTP6 ZTP5 DVDD 3.3V Internal DVSS GND2 6 C8 RC1812 0.01MF 3 +5POS External VR1 1 P1 SPDT SPDT 2 DVSS 10K RC0805 LED12 URED_LED ULED1206 [OFF] Output ON LED13 1 GRN_LED LED1206 5POS R14 GRN_LED LED1206 1 R25 301 RC0805 R12 619 RC0805 LED11 750 RC0805 2 DVSS 3 DVSS DVSS 3.3V Internal Shutdown Switch [LOW] The Output is turned off. DVSS DVSS DVSS [HIGH] The Output is turned on. DVSS ADVANCED MICRO DEVICES COPYRIGHT 1997 AMD ZM3 ZM1 TP1 MBMT ZM6 TP1 MBMT ZM4 ZM5 TP1 MBMT ZM2 TP1 MBMT TP1 MBMT TP1 MBMT SCHEMATIC DIAGRAM APPROVED BY: Gigabit Ethernet Transceiver 1000Base-X Eval. Brd. DATE 4 ZZ3 FIDUCIAL ZZ2 FIDUCIAL ZZ1 FIDUCIAL 1 1 1 T3 T3 T3 MODULE Steve Cooper B 1 PWRSUPL DRAWN BY A SHEET ENGINEER Robert Hartman C SIZE DWG. NO. D GPHYSD_1B DATE 10-23-1997_14:32 4 BRD. NO. B GPHYSD_1B PAGE D REV 7 of 7