ETC UFORCE

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Table of Contents
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A
1:
2:
3:
4:
5:
6:
7:
8:
9:
10:
11:
12:
13:
14:
15:
uforCE.SCH
E4.SCH
CLK.SCH
MEMORY.SCH
PCMCIA.SCH
MISC.SCH
LCD.SCH
AUDIC.SCH
AUDPORT.SCH
VCC3.SCH
VCC5.SCH
P12V.SCH
LCDVEE.SCH
BATTCHRG.SCH
VCCSWTCH.SCH
A
uforCE
Elan SC400 - Windows CE
Demonstration Board Schematic
B
B
C
C
Rev
Sh.
Sh.
Sh.
Sh.
2.0:
2
3
5
6
Sh. 7
Sh. 8
Sh. 10
Rev 1.0:
Original design
D
Rev 1.1:
Sh. 3
Sh. 4
Sh. 5
Sh. 7
Sh. 10
Sh. 11
Sh. 14
Sh. 15
Sh. 11
Removed "no populate" designator from JP1.
Added TP to ROMCS0#.
Removed "no populate" designator from U6
Added RSTA A2 errata work-around.
Swapped nets TABXNEG & TABYPOS at J1.
Swapped nets LCDD0-LCDD3 at J2.
Changed P/N for J1 & J2.
Changed value of R43 (DISP_ON) & connected to LVEE
Added 2M resistor from U21 pin 19 to VSOURCE.
Added 2M resistor from U23 pin 19 to VSOURCE.
Corrected BATTEMP circuit.
Changed values of R118-R120 for FSTCHRG#.
Changed comparator bias voltage for VCC switch to Vbias
Sh. 12
Sh. 13
Sh. 14
Sh. 15
E
Removed BATTEMP signal from GPIO-CS3 pin
JP1 changed to 2mm spacing
JP2 added for PCMCIA booting
TC7SH32FU added to level shift SIRIN signal
U38D added to unused gates
Added GND to U14-9 and U14-10
Added circuit to slow turn-on of LCD
TC7SH32FU added to level shift PEN_OFF signal
R56 changed to 3.3K pull-up
R144 added to pull-up IOCHRDY signal
Filter circuit added to SPKR signal for noise supression
LDO regulator circuit changed to 2.85V nominal
Changed control of U21 PWM* mode
U21-9 connected to Vsource
U21 output capacitor increased; added bypass capacitor
Changed control of U23 PWM* mode
U23-9 connected to Vsource
Added bypass capacitor to U23
Changed D5 to no-populate
Changed enable for U24 to PCMVPP2A signal
Changed U24-8 to no-connect to cut output current
Slow-start circuit added to slow ramp-up of P12VOLT
Increased L8; decreased C146 on U25 output
Slow-start circuit added to slow ramp-up of LCDVEE
Changed U25-8 to no-connect to cut output current
U27 changed to MIC4576 for increased output currrent
Charger circuit changed to use MC33340 controller chip
for Fast/Trickle charge control and battery overtemperature
shutoff
Added LED to indicate charge mode
Charge currents changed to 1.25A/25mA nominal
Changed software controls for charger circuitry to
FASTCHG# and CHARGE# signals
Changed Vbatt/12VDC switch circuit to use SI4435DY
and power U37 from Vsource
Added current limit circuit to 12VDC
Modified Vbatt/12VDC switch circuit to work with MC33340
Adjusted BLx# sensors for 4.6V, 4.8V, 5.0V nominal
Removed BATTEMP circuit
R124 reduced to 1M for increased hysteresis
R128, R129, R137 increased to 5.1M for reduced hysteresis
D
LPD - Logic Products Division
(C) Advanced Micro Devices, Inc.
2
3
E
Title
AMD
uforCE Demo Board
Size
Document Number
uforCE.SCH
Date: Tuesday, October 14, 1997
1
(800) 222-9323
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
4
Rev
2.0
Sheet
5
1
of
15
1
2
VCC3
VCC3
4
5
AVCC
133
141
149
157
124
132
140
148
156
164
172
21
18
36
13
8
24
81
115
105
137
209
252
194
158
143
117
101
85
225
223
169
237
222
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
VCC3 VCCCPU
3
VCCCPU
C1
C2
C3
C4
C5
0.001uF
0.01uF
0.1uF
0.1uF
0.1uF
U1
A
A
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
176
159
168
150
160
151
152
142
144
135
134
136
128
127
120
126
125
119
112
118
111
104
103
110
96
109
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
B
SA[0..25]
C
D[0..15]
SD[0..15]
TP32
REV. 2.0
TP18
D
1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
FSTCHRG#
1
PEN_OFF
30
10
49
29
9
28
48
7
27
6
47
26
5
46
25
4
99
90
107
98
89
106
97
114
123
122
113
121
129
130
145
131
44
77
58
PCMB-VCC#_GPIO16
PCMB-VPP1_GPIO17
PCMB-VPP2_GPIO18
PPDWE#_GPIO21
PPOEN#_GPIO22
SLCT_WP-B_GPIO23
BUSY_BVD2-B_GPIO24
ACK#_BVD1-B_GPIO25
PE_RDY-B#_GPIO26
ERROR#_CD-B#_GPIO27
INIT#_REG-B#_GPIO28
SLCTIN#_RST-B_GPIO29
AFDT#_MCEH-B#_GPIO30
STRB#_MCEL-B#_GPIO31
211
231
250
199
171
180
179
178
218
200
238
219
217
198
PCMVCCB#
ElanSC400
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
KBDCOL0_[XTDATA]
KBDCOL1_[XTCLK]
KBDCOL2_PIRQ3
KBDCOL3_PIRQ4
KBDCOL4_PIRQ5
KBDCOL5_PIRQ6
KBDCOL6_PIRQ7
KBDCOL7
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
KBDROW0_CASL2#
KBDROW1_CASL3#
KBDROW2_CASH2#
KBDROW3_CASH3#
KBDROW4_RAS2#
KBDROW5_RAS3#
KBDROW6_MA12
KBDROW7_PDACK1#
KBDROW8_PDRQ1
KBDROW9_PIRQ2
KBDROW10_BALE
KBDROW11_SBHE#
KBDROW12_MCS16#
KBDROW13_R32BFOE#
KBDROW14_SUSRES
[SD0]
[SD1]
[SD2]
[SD3]
[SD4]
[SD5]
[SD6]
[SD7]
[SD8]
[SD9]
[SD10]
[SD11]
[SD12]
[SD13]
[SD14]
[SD15]
DBUFOE#_GPIO-CS4
DBUFRDH_GPIO-CS3
DBUFRDL_GPIO-CS2
ROMRD#
ROMWR#
ROMCS0#
1
216
195
166
175
ROMRD#
ROMWR#
ROMCS0#
ROMCS1#
ACIN
BL0#
BL1#
BL2#
LBL2#
228
230
249
229
210
ACIN
BL0#_CLKIO
BL1#
BL2#
LBL2#_GPIO19
BBATSEN
202
BBATSEN
SPKR
203
SPKR
1
247
BNDSCNEN
X32IN
X32OUT
242
240
32KXTAL1
32KXTAL2
LFHS
LFLS
LFVID
LFINT
201
220
221
239
LFHS
LFLS
LFVID
LFINT
39
76
57
38
75
56
37
63
42
83
62
41
91
3
248
KBDROW0
KBDROW1
KBDROW2
KBDROW3
KBDROW4
KBDROW5
KBDROW6
KBDROW7
KBDROW8
KBDROW9
KBDROW10
KBDROW11
KBDROW12
KBDROW13
40
59
78
60
79
86
93
80
94
88
95
87
20
19
CASH0#
CASL0#
CASH1#
CASL1#
RAS0#
RAS1#
MWE#
73
35
17
54
55
74
11
MA0_{CFG0}
MA1_{CFG1}
MA2_{CFG2}
MA3_{CFG3}
MA4_{CFG4}
MA5
MA6
MA7
MA8
MA9
MA10
MA11
50
31
12
32
51
14
33
52
15
34
53
16
R1
1
1
1
1
1
1
1
TP5
TP6
TP7
TP8
TP9
TP10
TP11
1
TP12
RSTB
MCEHB#
MCELB#
KBDCOL0
KBDCOL1
KBDCOL2
KBDCOL3
KBDCOL4
KBDCOL5
KBDCOL6
1
VCC3
AVCC
RDYB#
CDB#
82
61
2
23
43
1
22
45
LCDDO_VL-RST#
LCDD1_VL-ADS#
LCDD2_VL-W/R#
LCDD3_VL-M/IO#
LCDD4_VL-LRDY#
LCDD5_VL-D/C#
LCDD6_VL-LDEV#
LCDD7_VL-BE3#
M_VL-BE2#
LC_VL-BE1#
SCK_VL-BE0#
FRM_VL-LCLK
LVEE#_VL-BRDY#
LVDD#_VL-BLAST
TP1
C6
C7
C8
0.001uF
0.01uF
0.1uF
10
C9
+ 10uF
10V
A CASE
VCC3
VCC3
C10
C11
C12
C13
0.001uF
0.01uF
0.1uF
0.1uF
B
VCC3
VCC3
TP13
KBDCOL[0..7]
C14
C15
C16
C17
0.1uF
0.1uF
0.1uF
0.1uF
VCC3
VCC3
C18
C19
C20
C21
0.1uF
0.1uF
0.1uF
0.1uF
KBDROW[0..13]
SUSRES
LCDD0
LCDD1
LCDD2
LCDD3
1
1
1
1
M
LC
SCK
FRM
LVEE#
LVDD#
C
TP14
TP15
TP16
TP17
CASH0#
CASL0#
CASH1#
CASL1#
RAS0#
RAS1#
MWE#
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
VCC5
D
C22
0.1uF
VCC5
MA[0..11]
DTR#
DCD#
RTS#
CTS#
SOUT
SIN
DSR#
RIN#
244
205
224
206
246
227
226
207
SIRIN
SIROUT
SDA_GPIO-CS0
SCL_GPIO-CS1
245
204
215
256
DTR#
DCD#
RTS#
CTS#
SOUT
SIN
DSR#
RIN#
SIRIN
SIROUT
SUSPDIS#
DIG_CS#
U2A
1
SUSPDIS
2
74ACT04
SUSPDIS#
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
165
173
188
189
190
191
192
193
64
65
66
67
68
69
70
71
72
84
92
100
108
116
181
182
183
184
185
186
187
241
TP19
CHARGE#
IOCHRDY
PIRQ1
PIRQ0
1
PCMWE#
PCMOE#
CDA1#
RDYA#
BVD1A
BVD2A
WPA
WAIT#
RSTA
REGA#
MCEHA#
MCELA#
PCMVCCA#
PCMVPP1A
PCMVPP2A
CDA2#
14
TP4
1
1
139
146
153
162
155
197
163
170
177
161
138
147
154
212
232
251
102
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSANALOG
TP2
TP3
ICDIR
WE#
OE#
CD-A#
RDY-A#
BVD1-A
BVD2-A
WP-A
WAIT-AB#
RST-A_BNDSCN-TDI
REG-A#_BNDSCN_TDO
MCEH-A#_BNDSCN_TMS
MCEL-A#_BNDSCN_TCK
PCMA-VCC#_GPIOCS13
PCMA-VPP1_GPIOCS14
PCMA-VPP2_GPIO15
CDA2#_STATIC-CLK_GPIO20
VCC
VCC
VCC
VCC
VCCCPU
VCCCPU
VCCCPU
VCCCPU
VCCCPU
VCCCPU
VCCCPU
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCMEM
VCCBUS
VCCBUS
VCCBUS
VCCBUS
VCCSYS
VCCSYS
VCCSYS
VCCSYS
VCCSYS
VCCSYS
VCCLCD
VCCLCD
VCCSER
VCCRTC
VCCPCM
VCCPCM2
VCCANALOG
RESET#
RSTDRV
IOR#
IOW#
MEMR#
MEMW#
IOCS16#_GPIO-CS5
IOCHRDY_GPIO-CS6
PIRQ1_GPIO-CS7
PIRQ0_GPIO-CS8
TC_GPIO-CS9
AEN_GPIO-CS10
PDACK0#_GPIO-CS11
PDRQ0_GPIO-CS12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AEN
PDACK0#
PDRQ0
243
208
196
167
236
174
235
214
255
234
254
213
233
253
RESET#
RSTDRV
IOR#
IOW#
E
E
(C) Advanced Micro Devices, Inc.
(800) 222-9323
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
Title
uforCE Demo Board
Note: Unless otherwise stated the resistors are 0603 package 5% Tol.
Note: Unless otherwise stated the capacitors are 0603 package 10% Tol.
Size
Document Number
E4.SCH
Rev
2.0
Date: Thursday, February 05, 1998
1
2
3
4
Sheet
5
2
of
15
1
2
3
4
5
VCC3
X32IN
1
2
3
3
4
4
32.768 KHz CRYSTAL
ECLIPTEK ECPSM29T
2
X1
1
A
Put jumper on JP1 to enable
routing of ROMCS0# to PCMCIA
socket A.
REV. 2.0
JP1
X32OUT
ECLIPTEK ECPSM29T
MA2
R2
10K
R3
10K
A
1
2
2mm 1x2
CFG2
MA1
AVCC
CFG1
MA[0..11]
B
C28
470pF
470pF
C29
33pF
22pf
R4
R5
4.7K
4.7K
C26
LFLSR
15pF
LFHSR
330pF
C27
C25
C30
0.001uF
R6
4.7K
LFINTR
C24
LFVIDR
C23
H2 PIN STRAP OPTIONS
0.01uF
CFG1
0
1
1
R7
4.7K
CFG0
0
0
1
Configuration
x8 ROMCS0# ROM Interface
x16 ROMCS0# ROM Interface
x32 ROMCS0# ROM Interface
B
CFG2 Configuration
0
Enable ROMCS0# decode on the ROMCS0# pin.
1
Enable ROMCS0# decode to access PCMCIA socket A.
LFHS
LFVID
LFLS
LFINT
VCCSUSP
Video PLL
High Speed PLL
C
1
Low Speed PLL
Intermediate PLL
2
BAT54
VCC3
10K
R8
SD1
10K
R9
SD2
10K
R10
SD3
10K
R11
SD4
10K
R12
SD5
10K
R13
SD6
10K
R14
SD7
10K
R15
SD8
10K
R16
SD9
10K
R17
SD10
10K
R18
SD11
10K
R19
SD12
10K
R20
SD13
10K
R21
SD14
10K
R22
SD15
10K
R23
3
3
SD0
D1
R24
BAT54
1
Reset Switch
2
150K
SW1
C
3
RESET#
PBNO
C&K KT11P2SM
C31
+ 10uF
10V
A CASE
SD[0..15]
D
D
4
3
2
1
VCC3
R25
C&K SWITCH
BBATSEN
VCC3
150K
+ C32
10uF
10V
A CASE
R26
100K
SW2
Suspend/Resume Switch
1
3
PBNO
C&K KT11P2SM
E
SUSRES
C33
(C) Advanced Micro Devices, Inc.
0.1uF
(800) 222-9323
E
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
Title
uforCE Demo Board
Note: Unless otherwise stated the resistors are 0603 package 5% Tol.
Size
Note: Unless otherwise stated the capacitors are 0603 package 10% Tol.
Document Number
CLK.SCH
Date: Thursday, February 05, 1998
1
2
3
4
Rev
2.0
Sheet
5
3
of
15
1
2
3
4
5
SD[0..15]
SA[0..25]
A
A
U3
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
RSTDRV#
VCC5
14
VCC5
R27
10K
U2B
RSTDRV
B
3
4
74ACT04
ROMCS0#
ROMRD#
ROMWR#
30
29
28
27
22
21
20
19
18
17
16
15
10
9
8
7
6
5
4
3
46
U4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
RY/BY#
RSTDRV#
42
14
RY/BY#
RESET#
ROMCS0#
ROMRD#
ROMWR#
11
43
44
CE#
OE#
WE#
D0
D1
D2
D3
D4
D5
D6
D7
31
32
33
34
38
39
40
41
VCC
VCC
12
37
VCC5
C34
C35
0.1uF
0.1uF
35
36
GND
GND
30
29
28
27
22
21
20
19
18
17
16
15
10
9
8
7
6
5
4
3
46
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
1
31
32
33
34
38
39
40
41
VCC
VCC
12
37
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
VCC5
42
RY/BY#
RSTDRV# 14
RY/BY#
RESET#
ROMCS0# 11
ROMRD# 43
ROMWR# 44
CE#
OE#
WE#
29F016
2Mx8
AM29F016EC-120
D0
D1
D2
D3
D4
D5
D6
D7
C36
C37
0.1uF
0.1uF
B
35
36
GND
GND
29F016
2Mx8
AM29F016EC-120
TP31
C
C
2 BANKS 1Mx16
2 BANKS4Mx16
D[0..15]
MA[0..11]
RAS1#
CASH0#
CASH1#
MWE#
*TC51V18160AFTS
11
15
16
NC
NC
NC
18
35
34
17
33
RAS
CASL
CASH
WE
OE
2
3
4
5
7
8
9
10
41
42
43
44
46
47
48
49
NC
NC
40
36
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
RAS0#
CASL0#
CASL1#
MWE#
19
20
21
22
23
24
27
28
29
30
31
32
33
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
NC/A12
11
15
16
NC
NC
NC
14
38
37
13
36
RAS
CASL
CASH
WE
OE
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
2
3
4
5
7
8
9
10
41
42
43
44
46
47
48
49
NC
NC
NC
NC
NC
40
35
34
18
17
U8
1
6
12
25
U7
1
6
12
25
U6
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
RAS1#
CASH0#
CASH1#
MWE#
19
20
21
22
23
24
27
28
29
30
31
32
33
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
NC/A12
11
15
16
NC
NC
NC
14
38
37
13
36
RAS
CASL
CASH
WE
OE
VCC
VCC
VCC
VCC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
NC/A10
NC/A11
VCC
VCC
VCC
VCC
21
22
23
24
27
28
29
30
31
32
20
19
VCC
VCC
VCC
NC
NC
40
36
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
VCC3
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
2
3
4
5
7
8
9
10
41
42
43
44
46
47
48
49
NC
NC
NC
NC
NC
40
35
34
18
17
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D
26
39
45
50
*TC51V18160AFTS
4Mx16
4Mx16
26
39
45
50
RAS
CASL
CASH
WE
OE
26
45
50
18
35
34
17
33
2
3
4
5
7
8
9
10
41
42
43
44
46
47
48
49
VSS
VSS
VSS
NC
NC
NC
VCC
VCC
VCC
11
15
16
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
26
45
50
RAS0#
CASL0#
CASL1#
MWE#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
NC/A10
NC/A11
1
6
25
U5
1
6
25
D
21
22
23
24
27
28
29
30
31
32
20
19
VSS
VSS
VSS
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
VCC3
VSS
VSS
VSS
VSS
VCC3
VSS
VSS
VSS
VSS
VCC3
VCC3
(C) Advanced Micro Devices, Inc.
E
C38
0.33uf
0805
(800) 222-9323
E
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
C39
0.33uf
0805
Title
uforCE Demo Board
Note: Unless otherwise stated the resistors are 0603 package 5% Tol.
Size
Document Number
MEMORY.SCH
Rev
2.0
Note: Unless otherwise stated the capacitors are 0603 package 10% Tol.
Date: Thursday, February 05, 1998
1
2
3
4
Sheet
5
4
of
15
1
2
3
4
5
SD[0..15]
SA[0..25]
VCC3
A
VPPPCMA
VCCPCMA5
VCCPCMA5
A
VPPPCMA
VCC5
R28
100K
U9
2
4
6
8
11
13
15
17
IOR#
IOW#
PCMOE#
PCMWE#
1
19
PCMVCCA#
PCMVCCB#
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
18
16
14
12
9
7
5
3
1G
VCC
2G
GND
74ACT244
20
10
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
IORA#
IOWA#
PCMOEA#
PCMWEA#
SD3
SD4
SD5
SD6
SD7
MCELA#
PCMOEB#
PCMWEB#
SA10
PCMOEA#
SA11
SA9
SA8
SA13
SA14
VCC5
PCMWEA#
RDYA#
B
C40
SA16
SA15
SA12
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
0.1uF
VCCPCMA5
VPPPCMA
CDA1#
P1
SD0
SD1
SD2
VCCPCMB5
C41
C42
C43
0.1uF
0.1uF
0.1uF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GND
D3
D4
D5
D6
D7
CE1
A10
OE
A11
A9
A8
A13
A14
WE
RDY/IREQ
VCC
VPP1
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
WP/IOIS
GND
WPA
GND
CD1
D11
D12
D13
D14
D15
CE2
RFSH
NIOR
NIOW
A17
A18
A19
A20
A21
VCC
VPP2
A22
A23
A24
A25
NC
RESET
WAIT
INPACK
REG
BVD2/SPK
BVD1/STS
D8
D9
D10
CD2
GND
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Populate JP2
to fetch
startup code
from FLASH
SD11
SD12
SD13
SD14
SD15
MCEHA#
IORA#
IOWA#
SA17
SA18
SA19
SA20
SA21
R140
RSTA
470
JP2
VCCPCMA5
1
2
SA22
SA23
SA24
SA25
2mm 1x2
B
R29
REV. 2.0
1M
RSTA_E
WAIT#
REGA#
BVD2A
BVD1A
SD8
SD9
SD10
VCC3
R30
PCMCIA CONN.
100K
CDA2#
C
C
VCC3
VCC5
RSTB
PCMVCCA#
PCMA3EN#
PCMVPP1A
PCMVPP2A
PCMVCCB#
PCMB3EN#
PCMBEN0
PCMBEN1
5
6
7
8
19
20
21
22
VCCPCMB5
SA19
SA17
SA15
VPPPCMA
VCCPCMA5
AVCC5EN#
AVCC3EN#
AEN0
AEN1
AVCCOUT
AVCCOUT
AVCCOUT
AVPPOUT
2
26
28
24
BVCC5EN#
BVCC3EN#
BEN0
BEN1
BVCCOUT
BVCCOUT
BVCCOUT
BVPPOUT
12
14
16
10
SA12
SA10
SA9
SA7
SA6
SA4
SA3
SA1
SA25
SA24
SA23
D
18
4
GND
GND
SD15
SD13
SD12
SD10
SD9
SD0
SD2
SD4
VCC3
VCC5
C45
+ 1uF
16V
A CASE
P12VOLT
C46
+ 1uF
16V
A CASE
C47
+ 1uF
16V
A CASE
SD7
VCCPCMB5
1
2
3
1
4
TP20
MCEHB# 5
6
7
8
9
10
11
12
13
1
14
TP22
15
16
17
18
PCMOEB#
19
20
21
22
23
24
25
26
1
27
TP27
28
1
29
TP28
1
30
TP30
61
A18
A16
A14
VCCR
CEH
A11
A9
A8
A6
A5
A3
A2
A0
RAS
A24
A23
A22
OE
D15
D13
D12
D10
D9
D0
D2
D4
RSVD
D7
SDA
SCL
VCC
VCC5
A19
A17
A15
A13
A12
RESET
A10
VS1
A7
BS8
A4
CEL
A1
CASL
CASH
CD
A21
BUSY
WE
D14
RSVD
D11
VS2
D8
D1
D3
D5
D6
RSVD
A20
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
CINS
GND
62
63
SA20
SA18
SA16
SA14
SA13
1
PCMCIA PWR
MICREL MIC2563A-1
AVPPIN
BVPPIN
AVCC3IN
BVCC3IN
AVCC5IN
AVCC5IN
BVCC5IN
BVCC5IN
R34
R33
R32
R31
23
9
27
13
1
3
15
17
1M
1M
1M
1M
P2
U10
VCCPCMB5
R35
14
P12VOLT
VCC5
100K
RSTB#
3
2
SA11
1
TP21
R36
SA8
BS8#
10K
SA5
U11A
74ACT125
VCC5
MCELB#
SA2
1
1
CDB#
C44
TP23
TP24
0.1uF
SA22
RDYB#
PCMWEB#
D
SD14
1
TP25
1
TP26
1
TP29
SD11
VCCPCMB5
SD8
SD1
SD3
SD5
SD6
R37
100K
SA21
BS8#
R38
CDB#
*0
MINI CARD
XVCC5EN#
0
0
0
0
E
XVCC3EN#
1
1
1
1
XEN1
0
0
1
1
XEN0
0
1
0
1
XVCCOUT
XVPPOUT
5V
5V
5V
5V
0V
5V
12V
OFF
The mini-card requires an active low reset
which, if using just an inverted state of RSTB,
the mini-card would be left in an active state
during suspend since RSTB is low during this
time.
During normal power on, this implementation
will cause RSTB# to be low until RSTB goes
inactive, then RSTB# will follow the state of
VCCPCMB5. When entering suspend, RSTB will be
inactive, still allowing RSTB# to follow the
state of VCCPCMB5.
Note: Unless otherwise stated the resistors are a 0603 package and 5% Tol.
Note: Unless otherwise stated the capacitors are a 0603 package and 10% Tol.
Note: A * denotes the part is not installed at this time.
1
2
3
4
(C) Advanced Micro Devices, Inc.
(800) 222-9323
E
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
Title
uforCE Demo Board
Size
Document Number
PCMCIA.SCH
Date: Thursday, February 05, 1998
Rev
2.0
Sheet
5
5
of
15
1
2
3
VCC3
U12
A
SUSPDIS#
VCCSUSP
3
2
15
14
4
AVCCINS AVCCOUT
AVCCIN1 AVCCOUT
AVCCIN2
AVCCIN3
AEN
1
16
11
10
7
6
12
BVCCINS BVCCOUT
BVCCIN1 BVCCOUT
BVCCIN2
BVCCIN3
BEN
GND
GND
8
9
14
VCC5
U2C
5
5
VCC5
SUSPDIS# is normally high &
will go low when SUSPEND is
entered.
LVDD#
4
VCC5
VCC3
VCCSUSP
A
VCCLCD3
VCCLCD3
C48
C49
0.1uF
0.1uF
C50
1uF
16V
A CASE
+
C51
1uF
16V
A CASE
+
5
13
LTC1478CS
6
74ACT04
B
B
TOP SIDE VIEW
8
7
6
VCC5
VCC5
5
9
R39
R40
R41
47
10
10
C52
0.1uF
U13
10
2
1
3
8
4
C53
6.8uF
10V
A CASE
TFDS6000
C
+
SIROUT
TC7SH32FU
VCCLEDA LEDC
4
GND
7
2
TXD
RXD
REV 2.0
GP1
GP2
9
10
C55
5
4
SIRIN
SD
NC
5
4
1
2
C57
C1V+
VCC
SD is normally low to
enable transceiver & goes
high to enter standby
mode.
3
(Top View)
REV 2.0
9
8
10
7
11
6
5
12
C2+
27
DCDP#
DSRP#
SINP
RTSP#
SOUTP
CTSP#
DTRP#
RINP#
P3
DCDP#
SOUTP
1
3
5
7
9
RTSP#
RINP#
SINP
DTRP#
DSRP#
CTSP#
2
4
6
8
10
HEADER 5X2
SERC2P
C
C2VGND
26
28
17
0.1uF
SERC2M
SERVM
1
3
5
7
9
C58
RS232-3V
LTC1327CG
0.1uF
2
SSOP5-P-A
TC7SH32FU
RI3
RI2
RI4
DO2
DO3
RI1
DO1
RI5
C56
SERC1M
SERVP
U14
TFDS6000
1
RO3
RO2
RO4
DI2
DI3
RO1
DI1
RO5
ON/OFF
C1+
0.1uF
5
6
U43
21
22
20
23
19
24
25
18
13
3
SERC1P
VCC3
321
4
1
3
C54
0.1uF
DCD#
DSR#
SIN
RTS#
SOUT
CTS#
DTR#
RIN#
SUSPDIS#
2
4
6
8
10
0.1uF
TOP SIDE VIEW
VCC3
SUSPDIS
P4
VCC5
D
14
11
3
U2E
10
11
74ACT04
10
1
6
3
2
VCC5
U15A
74ACT00
-
13
TLC3704C
14
U11B
74ACT125
+
U38D
12
5
CON14
KBDROW[0..13]
VCC3
14
VCC5
4
D
VCC5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
14
KBDROW0
KBDROW1
KBDROW2
KBDROW3
KBDROW4
KBDROW5
KBDROW6
KBDROW7
KBDROW8
KBDROW9
KBDROW10
KBDROW11
KBDROW12
KBDROW13
12
7
1
11
VCC5
14
1
13
VCC5
P5
E
CON7
KBDCOL[0..7]
U15D
74ACT00
14
10
14
3mm
7
6
5
4
3
2
1
1
KBDCOL0
KBDCOL1
KBDCOL2
KBDCOL3
KBDCOL4
KBDCOL5
KBDCOL6
REV 2.0
4
9
1
8
6
5
Molex 39-51-3074
U11C
74ACT125
Molex 39-51-3144
(C) Advanced Micro Devices, Inc.
U15B
74ACT00
(800) 222-9323
Title
Edge of Board
uforCE Demo Board
Note: Unless otherwise stated the resistors are a 0603 package and 5% Tol.
Size
Document Number
MISC.SCH
Rev
2.0
Note: Unless otherwise stated the capacitors are a 0603 package and 10% Tol.
Date: Thursday, February 05, 1998
1
2
E
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
3
4
Sheet
5
6
of
15
1
2
3
4
VCC5
5
VCCADIG
DIGITIZER INTERFACE
L1
SD[0..15]
* Keep analog traces
X-, X+, Y-, and Y+
short and isolated
INDUCTOR
U16
TABXPOS
TXD
AVG
24
25
26
27
X+
XY+
Y-
TABXNEG
TABYNEG
3
4
SA0
SA1
18
SA[0..25]
C60
22pf
CABLE (PINS FACE DOWN)
B
8
1
15
16
DIGXIN
DIGXOUT
SUSPDIS
X2
1
22
17
BHE
X_SELECT
VDD
5
VSS
12
XTALIN
XTALOUT
AVD
28
VREF
AVS
23
PD_RST
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
VCC5
VCC3
U2D
9
DIGIRQ#
C59
+ 1uF
16V
A CASE
+ C62
1uF
16V
A CASE
EDGE OF BOARD
DIGITIZER
TRI-TECH TR88802CS
8
PIRQ1
74ACT04
U42
1
4
PEN_OFF
2
C61
+ 1uF
16V
A CASE
1.8432MHz
C63
22pf
1
NEW_DATA
PEN_OFF
TABYPOS
CON8
AMP 487952-8
4
21
20
19
14
13
10
9
8
14
1
2
3
4
5
6
7
8
A
D<0>
D<1>
D<2>
D<3>
D<4>
D<5>
D<6>
D<7>
COEN
7
11
5
6
DIG_CS#
J1
TC7SH32FU
3
A
REV. 2.0
TC7SH32FU
321
B
4
AMP 487952-8
(CONTACTS FACE UP)
5
SSOP5-P-A
(Top View)
PIN 1 INDICATOR
VCCLCD3
LCD INTERFACE
3
FRM
LC
M
SCK
LCDD3
LCDD2
LCDD1
LCDD0
2
C
REV. 2.0
D15
RB400D
C
R43
LCDVEE
LVEE
1K
C139
0.1uF
C64
LCDVEE
R44
0.1uF
J2
4
1K
3
-
U17A
LCDV5
LCDV2
LCDVEE
VCCLCD3
FRM
GND
LC
GND
M
DISP_ON
SCK
LCDV4
LCDV3
LCDD3
LCDD2
LCDD1
LCDD0
1
MC33174
+
11
2
+
LCDVEE
R45
4
1K
C65
3.3uF
35V
C CASE
5
D
+
-
U17B
7
C66
+ 3.3uF
35V
C CASE
MC33174
11
6
R46
LCDVEE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
D
CABLE (PINS FACE UP)
CON18
AMP 1-487951-8
13K
18
1
4
EDGE OF BOARD
10
RB400D
1 2
AMP 1-487951-8
(CONTACTS FACE DOWN)
8
-
C67
+ 3.3uF
35V
C CASE
MC33174
11
9
U17C
+
LCDVEE
R47
3
1K
4
(Top View)
12
E
+
-
1K
11
13
R48
U17D
(C) Advanced Micro Devices, Inc.
14
MC33174
+
(800) 222-9323
Title
uforCE Demo Board
Note: Unless otherwise stated the resistors are a 0603 package and 5% Tol.
Size
Document Number
LCD.SCH
Rev
2.0
Note: Unless otherwise stated the capacitors are a 0603 package and 10% Tol.
Date: Thursday, February 05, 1998
1
2
3
E
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
C68
3.3uF
35V
C CASE
4
Sheet
5
7
of
15
1
2
3
VCC5
4
5
+5VA
L2
Y1
C69
10uf
10V
A CASE
A
VCC5
+
C70
C71
0.1uf
22pf
C72
16.9mhz
22pf
A
L3
C73
C74
C75
C76
0.1uf
0.1uf
0.1uf
0.1uf
VCC5
REV. 2.0
AUDVCC
R144
4.7K
C
0.1uf
9
8
RSTDRV#
10
MUTE
SCS/UP
XCTL1/SINT/DOWN
XCTL0/XA2
95
9
16
12
RLINE
LLINE
RAUX2
LAUX2
CMAUX2
MIC R
MIC L
RAUX1
LAUX1
ROUT
LOUT
MONO IN
MONO OUT
86
87
84
85
96
82
83
74
75
72
73
88
89
70
69
68
67
59
64
63
62
61
60
78
79
JAB1
JBB1/FSYNC
JACX
JBCX/SDOUT
MIDI IN
JBCY/SDIN
JACY
JBB2/SCLK
JAB2
MIDI OUT
VREF
REFFLT
RFILT
76
77
46
18
66
97
53
71
80
10K
C80
0805
1000pF
CS 4236B
C81
0805
1000pF
R59
15
R58
BRESET
R53
R54
R55
10K
VCC5
10K
14
13
8
7
6
5
4
3
2
1
10
11
LFILT
DGND1
SGND1
SGND2
SGND3
SGND4
TEST
AGND
R62
During normal operation,
LBL2# be high & go low
during critical suspend.
The audio chip needs an
active high to hold the
part in reset & low power
mode.
100
99
B
XA0/SCL
XA1
SDA/XD0
XD1/SCLK
XD2/SDIN
XD3/SDOUT
XD4/FSYNC
XD5/MCLK
XD6/LRCLK
XD7/SDATA
XIOR
XIOW
VCC5
U15C
74ACT00
10K
RESDRV
14
LBL2#
R52
90
PDACK0#
D
10K
DRQA(DRQ0)
DRQB(DRQ1)
DRQC(DRQ3)
DACKA(DACK0)
DACKB(DACK1)
DACKC(DACK3)
PDRQ0
VCC5
R51
55
51
52
58
56
57
C77
10K
(INT5)IRQA
(INT7)IRQB
(INT9)IRQC
(INT11)IRQD
(INT12)IRQE
(INT15)IRQF
VCC5
R50
24
23
22
21
20
19
PIRQ0
10K
IOCHRDY
R49
40
IOCHRDY
10K
AEN
IOR
IOW
R56
39
37
38
AEN
IOR#
IOW#
10K
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
3.3K
41
42
43
44
47
48
49
50
XTAL_IN
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
XTAL_OUT
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
R57
VCC3
25
26
27
28
29
30
31
32
33
34
35
36
94
93
92
91
10K
REV 2.0
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
U18
10K
B
VDF1
VDF2
VDF3
VDF4
VA
SD[0..15]
VD1
45
SA[0..25]
17
65
98
54
81
Pull up on XD1-7 reduces idle current
Pull up required on XD0
NOTE : To control noise the resistors
R145 and R146 are no longer populated.
The Capicator C141 has been replaced
with a 47K Resistor.
AUDVREF
C
VCC3
R145
*4.7K
RMICIN
LMICIN
RLINE
LLINE
RDACOUT
LDACOUT
MONOIN
C140
SPKRR
MIX_OUT
SPKR
*47K
0805
0.1uf
VCC5
R146
C141
47K
0805
R60
10K
R61
D
REV 2.0
10K
AUDVREF
REFFLT
C78
+
1uf
16V
A CASE
C79
10uf +
10V
A CASE
C82
C83
0.1uf
0.1uf
(C) Advanced Micro Devices, Inc.
(800) 222-9323
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
E
E
Title
uforCE Demo Board
Note: Unless otherwise stated the resistors are a 0603 package and 5% Tol.
Size
Document Number
AUDIC.SCH
Rev
2.0
Note: Unless otherwise stated the capacitors are a 0603 package and 10% Tol.
Date: Thursday, February 05, 1998
1
2
3
4
8
Sheet
5
of
15
1
2
3
4
5
VCCSUSPA
VCCSUSPA
X3
4.7K
R64
2.2K
C86
+
10uf
10V
A CASE
C87
R65
6.8K
0805
L4
A
C84
+
10uf
10V
A CASE
MICROPHONE
PANASONIC WM-54BT
0.33uf
0805
MICROPHONE P/N
WM-60AY
WM-60AT
WM-65A103
0805
RMICIN
C89
LMICIN
68pf
0805
R67
1.0uf
R66
1
2
3
4
HDR 4X1
CD IN
0805
1206
C91
1.0uf
LLINE
6.8K
R68
6.8K
0805
1206
R69
6.8K
0805
R70
6.8K
0805
HIGH PASS
Fc=1/6.28*65*47uf
Fc=170hz
VCCSUSPA
B
RDACOUT
AUDVREF
8
C90
RLINE
39K
0805
J3
U19A
R71
C93
C94
1000pF
0805
1.0uf
33K
R73 0805 27K
2
+
3
-
0805
1206
1
C95
P6
C92
10V
47uf
C CASE
TDA1308
4
B
C85
0.1uf
0.33uf
C88
ALTERNATE
PANASONIC
PANASONIC
PANASONIC
VCCSUSP
1
2
+
R63
A
R72
33
3
R74 0805 33
0805
2
1
PHONEJACK STEREO
0.1uf
VCCSUSPA
VCCSUSPA
C
C
10MS
C96
U19B
C98 1.0uf
VCC5
5
R77 27K
U11D
12
11
74ACT125
22K
R80
0805
C100 2700pF
D
R81
10K
0805
MIX_OUT
VCCSUSPA
R83
C102
1.0uF
22K
0805
U20
4
-
5
3
+
8
0.1uF
1
2
Speaker Out
CON2
2
7
LM4861M
C103
VCCSUSPA
C104
0.1uF
E
1206
C99
1000pF
0805
7
-
0805
C97
10V
47uf
C CASE
TDA1308
R78
47K
0805
R79
47K
0805
39K
R82
0805
C101
68pf
0805
D
J4
6
1
1206
The audio amp will be
shutdown (active high) when
in suspend. To achieve
this, VCCSUSPA is used to
provide power to the amp &
to control shutdown the of
amp. During normal power on
& resume functions, the
shutdown will be active
until the RC on the gate of
the 125 reaches a level to
tri-state the output, then
the P.D. will force the
shutdown pin low.
+
4
14
0.1uF
R76
10K
13
6
+
100K
8
LDACOUT
R75
SPEAKER P/N
PANASONIC EAS-3P123A
PANASONIC EAS-3P128A
PANASONIC EAS-2P106C
PANASONIC EAS-2P20A
LZR 20R04
LZR 28R04
LZR 23RPC01
(C) Advanced Micro Devices, Inc.
(800) 222-9323
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
E
Title
uforCE Demo Board
Note: Unless otherwise stated the resistors are a 0603 package and 5% Tol.
Size
Document Number
AUDPORT.SCH
Rev
2.0
Note: Unless otherwise stated the capacitors are a 0603 package and 10% Tol.
Date: Thursday, February 05, 1998
1
2
3
4
9
Sheet
5
of
15
A
B
C
VSOURCE
D
E
REV. 2.0
4
4
C142
R84
R85
10K
20K
C106
11
0
C108
0.1uF
3
R88
10.0K
1%
1206
FLAG
3
8
F1
L5
1
2
47uH
1
SW
SW
D3
10
PWM
13
COMP
FB
12
18
SYNC
BIAS
19
MBRS130LT3
PGND
PGND
PGND
PGND
SGND
SGND
SGND
SGND
R87
EN
MIC2178BWM
2
20
REV. 2.0
VIN
VIN
VIN
U21
9
1
2
VCC3
0.01uF
SUSPDIS
0.1uF
REV. 2.0
4
5
6
7
14
15
16
17
C105
+ 22uF
35V
E CASE
low ESR
C107
+ 100uF
10V
D CASE
low ESR
R86
33.2K
1%
1206
1.5A
VSOURCE
C109
3
R89
20.0K
1%
1206
R142
2M
C110
0.01uF
6800pF
0805
REV. 2.0
VCCCPU
U22
2
C111
0.01uF
2
1
INPUT
EN
3
GROUND
2
OUTPUT
4
ADJUST
5
MIC29152BU
R90
118K
1%
1206
R92
90.9K
1%
1206
REV. 2.0
C112
+ 100uF
10V
E CASE
low ESR
(C) Advanced Micro Devices, Inc.
1
(800) 222-9323
1
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
Title
uforCE Demo Board
Note: Unless otherwise stated the resistors are a 0603 package and 5% Tol.
Size
Note: Unless otherwise stated the capacitors are a 0603 package and 10% Tol.
Document Number
VCC3.SCH
Date: Thursday, February 05, 1998
A
B
C
D
Rev
2.0
10
Sheet
E
of
15
1
2
3
4
5
A
A
VSOURCE
REV. 2.0
REV. 2.0
REV. 2.0
C113
+ 22uF
35V
E CASE
low ESR
R93
20K
100K
0.1uF
C144
1.0uF
1206
FLAG
10
PWM
13
18
2
COMP
FB
12
SYNC
BIAS
19
C117
6800pF
0805
R96
60.4K
1%
1206
1.0A
2
47uH
D4
MBRS130LT3
C114
+ 100uF
10V
D CASE
low ESR
VSOURCE
R143
2M
4
5
6
7
14
15
16
17
0.1uF
R99
10.0K
1%
1206
F2
L6
1
C116
VCC5
1
3
8
1
11
MIC2178BWM
SW
SW
VIN
VIN
VIN
EN
2
0
20
9
1
2
U23
SUSPDIS
C115
B
REV. 2.0
D5
*MBRS130LT3
R98
C
VCC3
REV. 2.0
PGND
PGND
PGND
PGND
SGND
SGND
SGND
SGND
B
C143
R94
C
R100
20.0K
1%
1206
0.01uF
D
D
(C) Advanced Micro Devices, Inc.
(800) 222-9323
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
E
Note: Unless otherwise stated the resistors are a 0603 package and 5% Tol.
E
Title
Note: Unless otherwise stated the capacitors are a 0603 package and 10% Tol.
uforCE Demo Board
Note: A * denotes the part is not installed at this time.
Size
Document Number
VCC5.SCH
Date: Thursday, February 05, 1998
1
2
3
4
Rev
2.0
11
Sheet
5
of
15
1
2
3
4
5
A
A
B
B
VSOURCE
P12VOLT
D6
L7
1
2
F3
1
MBRS130LT3
U24
PCMVPP2A
R102
4.75K
1%
1206
EN
VIN
5
2
COMP
VSW
7
1
8
6
S GND
P GND 1
P GND 2
FB
3
R101
13.0K
1%
1206
0.5A
C145
1.0uf
1206
D16
3
2
C119
+ 33uF
25V
D CASE
low ESR
C
REV. 2.0 MIC3172BM
RB400D
C120
0805
1000pF
3
C121
4
R103
1.50K
1%
1206
0.01uF
2
C118
+
68uF
20V
E CASE
low ESR
C
2
47uH
REV. 2.0
D17
RB400D
REV. 2.0
D
D
RB400D
1 2
3
(Top View)
(C) Advanced Micro Devices, Inc.
(800) 222-9323
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
E
Note: Unless otherwise stated the resistors are a 0603 package and 5% Tol.
E
Title
uforCE Demo Board
Note: Unless otherwise stated the capacitors are a 0603 package and 10% Tol.
Size
Note: A * denotes the part is not installed at this time.
Document Number
P12V.SCH
Date: Thursday, February 05, 1998
1
2
3
4
Rev
2.0
12
Sheet
5
of
15
1
2
3
4
5
A
A
14
VCC5
LOW=ON
U2F
13
LVEE#
HIGH=ON
LVEE
LVEE
12
74ACT04
VSOURCE
D7
2
2
SS26
R105
100K
1%
1206
REV 2.0
U25
+
REV. 2.0
VIN
5
COMP
VSW
7
1
8
6
S GND
P GND 1
P GND 2
FB
3
C146
1.0uf
1206
3
R107
2K POT
2
R104
10K
REV 2.0
D18
MIC3172BM
C124
0805
1000pF
C125
RB400D
2
D19
RB400D
C
LCDVEE
0.5A
2
R108
4.53K
1%
1206
F4
Q2
2N7002
1
3
0.01uF
Q1
TPO610T
1
R147
20K
2
1
C
EN
2
REV 2.0
C122
+ 22uF
35V
E CASE
low ESR
3
R106
4.75K
1%
1206
4
3
C123
22uF
35V
E CASE
low ESR
B
28VOUT
1
100uH
2
1
3
L8
B
REV. 2.0
D
D
2N7002
TP0610T
(N-Channel)
2 1
(P-Channel)
2 1
S
S
G
RB400D
1 2
G
D
D
3
3
SOT-23
(Top View)
3
SOT-23
(Top View)
(Top View)
(C) Advanced Micro Devices, Inc.
(800) 222-9323
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
E
Note: Unless otherwise stated the resistors are a 0603 package and 5% Tol.
E
Title
uforCE Demo Board
Note: Unless otherwise stated the capacitors are a 0603 package and 10% Tol.
Size
Note: A * denotes the part is not installed at this time.
Document Number
LCDVEE.SCH
Date: Thursday, February 05, 1998
1
2
3
4
Rev
2.0
13
Sheet
5
of
15
A
B
C
D
E
12VDC
R148
330
1
REV. 2.0
4
REV. 2.0
4.8V-1300mAH
NiMH BATT
D20
REV. 2.0
2
3
2
1
2
1
3
+
VIN
GND
FB
MIC4576BU
68uH
4
C128
5
U28
R114
3.01K
+
1
1%
0805
-
2.0A
CON3
12VDC
12VDC
R149
10K
R116
4
10.0K
Q9
1%
0805
C130
1
5%
0805
0.01uF
12VDC
1
2N7002
+
3
-
4
12VDC
12VDC
2
MIC6211
REV. 2.0
C147
MIC6211
R153
1.00K
1%
0805
3
R121
34.0K
1%
0805
RB400D
1 2
321
R154
10K
U39
2
2
5
3
0.01uF
3
VCC
8
VIN
T3/REFL
T2/SEN
T1/REFH
1
5
6
7
GND
4
VOUT
Q11
1
4
2N7002
U29
5
0.01uF
Q3
1
2
R115
1.00K
1%
0805
3
1
D10
13V
GLL4743
Q10
1
R152
*0
C132
3
(Top View)
2
2N7002
10K
2
SLM-13MW
1 2
3
SHDN
R151
CHARGE#
C129
1000pF
R150
10K
3
2
MIC6211
2
1
3
1
SS24
C126
+ 68uF
20V
E CASE
low ESR
R113
100
1%
0805
0.01uF
F5
2
SS24
REV. 2.0
3
0.1
1%
2010
12VDC
D9
2
C127
68uF
20V
E CASE
low ESR
R112
3
SW
1
SHDN
J5
D8
2
5
VBATT
RB400D
L9
3
U27
3
2
SHDN
12VDC
4
TMIST
D24
GREEN
____
TRKL
2N7002
SOT-23-5
MC33340
(Top View)
(Top View)
REV. 2.0
R156
6.34K
0805
1%
2N7002
Q12
S
G
D
1
R155
20.0K
1%
0805
FSTCHRG#
1
2N7002
2
2
2
3
(N-Channel)
2 1
LM4041CIM3-1.2
3
TRICKLE#
VSEN
TMIST
3
SOT-23
(Top View)
SOT-23 (M3)
(Top View)
(C) Advanced Micro Devices, Inc.
1
(800) 222-9323
1
REV. 2.0
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
Note: Unless otherwise stated the resistors are a 0603 package and 5% Tol.
Title
Note: Unless otherwise stated the capacitors are a 0603 package and 10% Tol.
uforCE Demo Board
Note: A * denotes the part is not installed at this time.
Size
Document Number
BATTCHRG.SCH
Date: Thursday, February 05, 1998
A
B
C
D
Rev
2.0
14
Sheet
E
of
15
1
2
3
4
VBATT
12VDC
J6
2
3
1
1
2
3
4
C148
2.0A
S
S
S
G
0.1uF
PWR3
D12
D
D
D
D
8
7
6
5
2
D21
1K
1
SS24
R159
10K
SI9435DY
R157
U41
R122
10K
3
A
Vsource
U40
F6
5
1
2
3
4
C133
+ 100uF
16V
E CASE
low ESR
S
S
S
G
8
7
6
5
D
D
D
D
A
SI4435DY
REV. 2.0
R158
20K
2
RB400D
REV. 2.0
VCC3
VCC3
R123
B
12VDC
Vsource
1
R126
10K
REV. 2.0
2
R165
110K
1%
0805
3
+
4
-
U37
1
LMC7221
C
5
C149
0805
6800pF
VBATT
R128
Vsource
R136
VREF
2
R137
D13
C136
R134
60.4K
1%
0805
5.1M
VBATT
LM4041CIM3-1.2
VCC3
3
0.01uF
3
+
6
-
1
5.1M
R132
196K
1%
0805
VCC3
TLC3704C
150K
RB400D
1 2
7
U38A
3
REV. 2.0
R129
VCC3
12
R127
47K
0805
VBATT
5.1M
R131
182K
1%
0805
REV. 2.0
3
R138
169K
1%
0805
+
4
-
U38B
2
R135
60.4K
1%
0805
D
0.01uF
TP0610T
BL1#
(N-Channel)
2 1
(P-Channel)
2 1
S
S
G
E
G
D
D
C138
1000pF
0805
R139
60.4K
1%
0805
U38C
9
+
8
-
14
BL2#
TLC3704C
12
2N7002
(C) Advanced Micro Devices, Inc.
3
SOT-23
(Top View)
3
SOT-23
(Top View)
BL0#
TLC3704C
3
(Top View)
C137
5
12
150K
0805
1%
D
2N7002
0.01uF
VSEN
0.01uF
ACIN
Q5
C134
R164
C150
1M
3
R162
11.0K
1%
0805
R163
301K
1%
0805
C
Q6
TPO610T
1
32.4K
0805
1%
RB400D
2
R124
R161
3
VBATT
2
2
3
D22
REV. 2.0
B
100K
(800) 222-9323
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
E
Title
uforCE Demo Board
Note: Unless otherwise stated the resistors are a 0603 package and 5% Tol.
Size
Document Number
VCCSWTCH.SCH
Rev
2.0
Note: Unless otherwise stated the capacitors are a 0603 package and 10% Tol.
Date: Thursday, February 05, 1998
1
2
3
4
15
Sheet
5
of
15