Incompatibilities Between the AMD-762™ System Controller and the Via Technologies, Inc. VT82C686B “Super South” Southbridge Application Note Publication # 24919 Rev: B Issue Date: June 2001 © 2001 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD logo, and combinations thereof, AMD-761, and AMD-762 are trademarks of Advanced Micro Devices, Inc. Microsoft and Windows are registered trademarks of Microsoft Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 24919B—June 2001 Incompatibilities Between the AMD-762™ System Controller and the Via Technologies, Inc. VT82C686B “Super South” Southbridge Revision History Date Rev Description April 2001 A Initial Release June 2001 B Converted from Tech Note to App Note, disclaimer about AMD-761TM system controller solution added. Revision History iii Confidential - Advance Information Incompatibilities Between the AMD-762™ System Controller and the Via Technologies, Inc. VT82C686B “Super South” Southbridge 24919B—June iv Revision History 24919B—June 2001 Incompatibilities Between the AMD-762™ System Controller and the Via Technologies, Inc. VT82C686B “Super South” Southbridge Application Note Incompatibilities Between the AMD-762™ System Controller and the Via Technologies, Inc. VT82C686B “Super South” Southbridge Purpose This paper describes two system-level incompatibilities that occur when creating a system with the AMD-762™ System Controller (Northbridge) and the Via Technologies, Inc. VT82C686B (Southbridge): 1. Inability to support the IOAPIC in the Southbridge due to incompatibilities in the Write Snoop Complete (WSC#) protocol. This prevents compliance with the Microsoft’s PC-2001 specification. 2. Potential data corruption when switching into the ACPI S3 power management state (Suspend to RAM) in systems that use registered DDR DIMMs due to incompatible sequencing of the PCIRESET# pin. 1 Confidential - Advance Information Incompatibilities Between the AMD-762TM System Controller and the Via Technologies, Inc. VT82C686B “Super South” Southbridge 24919B—June 2001 Write Snoop Protocol Incompatibilty The Microsoft® “Windows® Logo Program Requirements 2.0 v.0.9” requires that all desktop systems must be Advanced Programmable Interrupt Controller (APIC) enabled (SYS001.3). This requires that all hardware interrupts be connected to the IOAPIC, and that the IOAPIC be connected to the processor’s local APIC. The communication between the IOAPIC and the local APIC occurs over a separate sideband bus. A comparison of this configuration to the traditional PIC configuration is shown in Figure 1 on page 3. Operation with the IOAPIC and the local APIC requires all of the Northbridge’s posted write-buffers to be properly flushed to coherent memory before the IOAPIC sends an interrupt message to the processor. This is required to prevent potential data coherency problems that may result when the processor receives an interrupt and reads stale data because the data most recently written by the PCI Bus master still resides in a posted write-buffer in the Northbridge. Non-APIC implementations do not have the potential for this problem because the processor’s interrupt acknowledge cycle that traverses the PCI Bus is serializing in nature, thus all postedwrite buffers are flushed before the processor reads memory in the interrupt service routine. Note: The solution using a POP/NOPOP resistor for single processor configurations published in the 24952A application note, Interfacing the AMD-761TM system controller and the Via Technologies VT62C686B Southbridge, does not apply to multiprocessor solutions using the AMD-762 system controller. 2 Confidential - Advance Information 24919B—June 2001 Incompatibilities Between the AMD-762™ System Controller and the Via Technologies, Inc. VT82C686B “Super South” Southbridge CPU CPU Northbridge Snoop Posted Writes Interrupt Acknowledge Cycle on PCI Bus 3 IOAPIC INTR IOAPIC System Configuration 2. 3. 4. Peripheral interrupt request occurs, IOAPIC must send interrupt message to the processor. WSC# protocol forces Northbridge and CPU to snoop all posted writes, and provide a status indicator to the Southbridge Southbridge/IOAPIC is now free to issue message to CPU on the interrupt bus Processor reads of memory are coherent. Figure 1. PIC Southbridge Southbridge 1. Posted Writes Snoop WSC# Interrupt Message Bus Northbridge PIC System Configuration 1. 2. 3. 4. Peripheral interrupt request occurs, PIC sends interrupt request to the processor on the INTR pin. Processor responds with interrupt acknowledge cycle Interrupt acknowledge cycle forces Northbridge to flush all posted writes Processor reads of memory are coherent. IOAPIC vs. Traditional PIC System Configuration The mechanism typically employed in chipsets to flush the posted write-buffers is a simple protocol between the Northbridge and the Southbridge that signals the completion of processor snooping of all posted write-buffers, indicating that an interrupt message may be safely sent from the IOAPIC to the local APIC. This mechanism is known as “Write Snoop Complete” and is implemented with a pin called “WSC#. The WSC# pin is supported on both the AMD-762 system controller and the VT82C686B Southbridge, but the implementations are functionally incompatible as follows: ■ The AMD-762 system controller implements WSC# as a bidirectional pin that is first asserted by the Southbridge to request that the posted write-buffers be snooped by the processor, and subsequently asserted by the Northbridge to 3 Confidential - Advance Information 24919B—June 2001 Incompatibilities Between the AMD-762TM System Controller and the Via Technologies, Inc. VT82C686B “Super South” Southbridge ■ indicate that the Southbridge’s IOAPIC can issue an interrupt message to the local APIC. The AMD-762 system controller will not assert the WSC# pin low unless it first receives a request on this pin. The VT82C686B implements WSC# as a unidirectional pin that is only driven by the Northbridge and must be asserted low unless the Northbridge has outstanding PCI to DRAM posted writes that have not been snooped by the processor. When the VT82C686B is connected to an AMD-762 system controller the WSC# pin will never be asserted because the VT82C686B does not first assert WSC# to request posted writes to be snooped, and thus the system will not be able to send interrupt messages to the processor. ACPI S3 Incompatibility with Registered DDR DIMMs Systems employing registered DDR DIMMs and the AMD-762 system controller/VT82C686B combination may experience data corruption when entering or exiting the ACPI S3 (Suspend t o R A M ) p owe r m a n a g e m e n t s t a t e . Thi s i s d u e t o a n incompatibility in the sequencing of the PCIRESET# signal between the Northbridge and the Southbridge. CLK AMD-762TM System Controller DCSTOP# CPU STPCLK# Figure 2. 4 Registered DDR DIMMs PCIRESET# Southbridge DDR DIMM Reset Connection in AMD-762™ System Controller System Confidential - Advance Information 24919B—June 2001 Incompatibilities Between the AMD-762™ System Controller and the Via Technologies, Inc. VT82C686B “Super South” Southbridge The AMD-762 system controller supports the ACPI S3 state by specific sequencing on the DCSTOP# and PCIRESET# pins. When entering the S3 state the DCSTOP# pin must be asserted followed by the assertion of the PCIRESET# pin one RTC clock later (~30 mS). The PCIRESET# assertion is used by the AMD-762 system controller to gate off its I/O pad ring since the pad ring will be powered off while the core remains powered (the DDR I/O pad ring remains powered). Approximately four clocks later the DDR clocks will be disabled. Since registered DIMMs incorporate PLLs and registers on the module, they require a separate reset pin that must be asserted before its clocks are removed to guarantee stable operation. As shown in Figure 2 on page 4, the reset pin on the DDR DIMMs is connected to the Southbridge’s PCIRESET# pin in a AMD-762 system controller based system. When entering the Suspend to RAM state, the AMD-762 system controller will continue to drive the DDR clocks for at least four clocks after the PCIRST# pin is asserted to meet the DIMM requirements. ■ The VT82C686B does not follow the DCSTOP# and PCIRESET# sequencing listed above. The VT82C686B does not assert the PCIRESET# pin low until after the power supply is turned off (PWRGOOD de-asserted). This means that the system clock generator is powered off by the time the AMD-762 system controller detects the assertion of PCIRESET#. This potentially results in DDR memory failures since the DIMM was not properly shut down. 5 Confidential - Advance Information Incompatibilities Between the AMD-762TM System Controller and the Via Technologies, Inc. VT82C686B “Super South” Southbridge 6 24919B—June 2001